1 /* $NetBSD: ixgbe_api.c,v 1.22 2018/12/06 13:25:02 msaitoh Exp $ */ 2 3 /****************************************************************************** 4 SPDX-License-Identifier: BSD-3-Clause 5 6 Copyright (c) 2001-2017, Intel Corporation 7 All rights reserved. 8 9 Redistribution and use in source and binary forms, with or without 10 modification, are permitted provided that the following conditions are met: 11 12 1. Redistributions of source code must retain the above copyright notice, 13 this list of conditions and the following disclaimer. 14 15 2. Redistributions in binary form must reproduce the above copyright 16 notice, this list of conditions and the following disclaimer in the 17 documentation and/or other materials provided with the distribution. 18 19 3. Neither the name of the Intel Corporation nor the names of its 20 contributors may be used to endorse or promote products derived from 21 this software without specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 27 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 POSSIBILITY OF SUCH DAMAGE. 34 35 ******************************************************************************/ 36 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_api.c 331224 2018-03-19 20:55:05Z erj $*/ 37 38 #include "ixgbe_api.h" 39 #include "ixgbe_common.h" 40 41 #define IXGBE_EMPTY_PARAM 42 43 static const u32 ixgbe_mvals_base[IXGBE_MVALS_IDX_LIMIT] = { 44 IXGBE_MVALS_INIT(IXGBE_EMPTY_PARAM) 45 }; 46 47 static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = { 48 IXGBE_MVALS_INIT(_X540) 49 }; 50 51 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = { 52 IXGBE_MVALS_INIT(_X550) 53 }; 54 55 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = { 56 IXGBE_MVALS_INIT(_X550EM_x) 57 }; 58 59 static const u32 ixgbe_mvals_X550EM_a[IXGBE_MVALS_IDX_LIMIT] = { 60 IXGBE_MVALS_INIT(_X550EM_a) 61 }; 62 63 /** 64 * ixgbe_dcb_get_rtrup2tc - read rtrup2tc reg 65 * @hw: pointer to hardware structure 66 * @map: pointer to u8 arr for returning map 67 * 68 * Read the rtrup2tc HW register and resolve its content into map 69 **/ 70 void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map) 71 { 72 if (hw->mac.ops.get_rtrup2tc) 73 hw->mac.ops.get_rtrup2tc(hw, map); 74 } 75 76 /** 77 * ixgbe_init_shared_code - Initialize the shared code 78 * @hw: pointer to hardware structure 79 * 80 * This will assign function pointers and assign the MAC type and PHY code. 81 * Does not touch the hardware. This function must be called prior to any 82 * other function in the shared code. The ixgbe_hw structure should be 83 * memset to 0 prior to calling this function. The following fields in 84 * hw structure should be filled in prior to calling this function: 85 * back, device_id, vendor_id, subsystem_device_id, 86 * subsystem_vendor_id, and revision_id 87 **/ 88 s32 ixgbe_init_shared_code(struct ixgbe_hw *hw) 89 { 90 s32 status; 91 92 DEBUGFUNC("ixgbe_init_shared_code"); 93 94 /* 95 * Set the mac type 96 */ 97 ixgbe_set_mac_type(hw); 98 99 switch (hw->mac.type) { 100 case ixgbe_mac_82598EB: 101 status = ixgbe_init_ops_82598(hw); 102 break; 103 case ixgbe_mac_82599EB: 104 status = ixgbe_init_ops_82599(hw); 105 break; 106 case ixgbe_mac_X540: 107 status = ixgbe_init_ops_X540(hw); 108 break; 109 case ixgbe_mac_X550: 110 status = ixgbe_init_ops_X550(hw); 111 break; 112 case ixgbe_mac_X550EM_x: 113 status = ixgbe_init_ops_X550EM_x(hw); 114 break; 115 case ixgbe_mac_X550EM_a: 116 status = ixgbe_init_ops_X550EM_a(hw); 117 break; 118 default: 119 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 120 break; 121 } 122 hw->mac.max_link_up_time = IXGBE_LINK_UP_TIME; 123 124 return status; 125 } 126 127 /** 128 * ixgbe_set_mac_type - Sets MAC type 129 * @hw: pointer to the HW structure 130 * 131 * This function sets the mac type of the adapter based on the 132 * vendor ID and device ID stored in the hw structure. 133 **/ 134 s32 ixgbe_set_mac_type(struct ixgbe_hw *hw) 135 { 136 s32 ret_val = IXGBE_SUCCESS; 137 138 DEBUGFUNC("ixgbe_set_mac_type\n"); 139 140 if (hw->vendor_id != IXGBE_INTEL_VENDOR_ID) { 141 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 142 "Unsupported vendor id: %x", hw->vendor_id); 143 return IXGBE_ERR_DEVICE_NOT_SUPPORTED; 144 } 145 146 hw->mvals = ixgbe_mvals_base; 147 148 switch (hw->device_id) { 149 case IXGBE_DEV_ID_82598: 150 case IXGBE_DEV_ID_82598_BX: 151 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 152 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 153 case IXGBE_DEV_ID_82598AT: 154 case IXGBE_DEV_ID_82598AT2: 155 case IXGBE_DEV_ID_82598EB_CX4: 156 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 157 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 158 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 159 case IXGBE_DEV_ID_82598EB_XF_LR: 160 case IXGBE_DEV_ID_82598EB_SFP_LOM: 161 hw->mac.type = ixgbe_mac_82598EB; 162 break; 163 case IXGBE_DEV_ID_82599_KX4: 164 case IXGBE_DEV_ID_82599_KX4_MEZZ: 165 case IXGBE_DEV_ID_82599_XAUI_LOM: 166 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 167 case IXGBE_DEV_ID_82599_KR: 168 case IXGBE_DEV_ID_82599_SFP: 169 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 170 case IXGBE_DEV_ID_82599_SFP_FCOE: 171 case IXGBE_DEV_ID_82599_SFP_EM: 172 case IXGBE_DEV_ID_82599_SFP_SF2: 173 case IXGBE_DEV_ID_82599_SFP_SF_QP: 174 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 175 case IXGBE_DEV_ID_82599EN_SFP: 176 case IXGBE_DEV_ID_82599_CX4: 177 case IXGBE_DEV_ID_82599_BYPASS: 178 case IXGBE_DEV_ID_82599_T3_LOM: 179 hw->mac.type = ixgbe_mac_82599EB; 180 break; 181 case IXGBE_DEV_ID_X540T: 182 case IXGBE_DEV_ID_X540T1: 183 case IXGBE_DEV_ID_X540_BYPASS: 184 hw->mac.type = ixgbe_mac_X540; 185 hw->mvals = ixgbe_mvals_X540; 186 break; 187 case IXGBE_DEV_ID_X550T: 188 case IXGBE_DEV_ID_X550T1: 189 hw->mac.type = ixgbe_mac_X550; 190 hw->mvals = ixgbe_mvals_X550; 191 break; 192 case IXGBE_DEV_ID_X550EM_X_KX4: 193 case IXGBE_DEV_ID_X550EM_X_KR: 194 case IXGBE_DEV_ID_X550EM_X_10G_T: 195 case IXGBE_DEV_ID_X550EM_X_1G_T: 196 case IXGBE_DEV_ID_X550EM_X_SFP: 197 case IXGBE_DEV_ID_X550EM_X_XFI: 198 hw->mac.type = ixgbe_mac_X550EM_x; 199 hw->mvals = ixgbe_mvals_X550EM_x; 200 break; 201 case IXGBE_DEV_ID_X550EM_A_KR: 202 case IXGBE_DEV_ID_X550EM_A_KR_L: 203 case IXGBE_DEV_ID_X550EM_A_SFP_N: 204 case IXGBE_DEV_ID_X550EM_A_SGMII: 205 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 206 case IXGBE_DEV_ID_X550EM_A_1G_T: 207 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 208 case IXGBE_DEV_ID_X550EM_A_10G_T: 209 case IXGBE_DEV_ID_X550EM_A_QSFP: 210 case IXGBE_DEV_ID_X550EM_A_QSFP_N: 211 case IXGBE_DEV_ID_X550EM_A_SFP: 212 hw->mac.type = ixgbe_mac_X550EM_a; 213 hw->mvals = ixgbe_mvals_X550EM_a; 214 break; 215 default: 216 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 217 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 218 "Unsupported device id: %x", 219 hw->device_id); 220 break; 221 } 222 223 DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n", 224 hw->mac.type, ret_val); 225 return ret_val; 226 } 227 228 /** 229 * ixgbe_init_hw - Initialize the hardware 230 * @hw: pointer to hardware structure 231 * 232 * Initialize the hardware by resetting and then starting the hardware 233 **/ 234 s32 ixgbe_init_hw(struct ixgbe_hw *hw) 235 { 236 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw), 237 IXGBE_NOT_IMPLEMENTED); 238 } 239 240 /** 241 * ixgbe_reset_hw - Performs a hardware reset 242 * @hw: pointer to hardware structure 243 * 244 * Resets the hardware by resetting the transmit and receive units, masks and 245 * clears all interrupts, performs a PHY reset, and performs a MAC reset 246 **/ 247 s32 ixgbe_reset_hw(struct ixgbe_hw *hw) 248 { 249 return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw), 250 IXGBE_NOT_IMPLEMENTED); 251 } 252 253 /** 254 * ixgbe_start_hw - Prepares hardware for Rx/Tx 255 * @hw: pointer to hardware structure 256 * 257 * Starts the hardware by filling the bus info structure and media type, 258 * clears all on chip counters, initializes receive address registers, 259 * multicast table, VLAN filter table, calls routine to setup link and 260 * flow control settings, and leaves transmit and receive units disabled 261 * and uninitialized. 262 **/ 263 s32 ixgbe_start_hw(struct ixgbe_hw *hw) 264 { 265 return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw), 266 IXGBE_NOT_IMPLEMENTED); 267 } 268 269 /** 270 * ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering, 271 * which is disabled by default in ixgbe_start_hw(); 272 * 273 * @hw: pointer to hardware structure 274 * 275 * Enable relaxed ordering; 276 **/ 277 void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw) 278 { 279 if (hw->mac.ops.enable_relaxed_ordering) 280 hw->mac.ops.enable_relaxed_ordering(hw); 281 } 282 283 /** 284 * ixgbe_clear_hw_cntrs - Clear hardware counters 285 * @hw: pointer to hardware structure 286 * 287 * Clears all hardware statistics counters by reading them from the hardware 288 * Statistics counters are clear on read. 289 **/ 290 s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw) 291 { 292 return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw), 293 IXGBE_NOT_IMPLEMENTED); 294 } 295 296 /** 297 * ixgbe_get_media_type - Get media type 298 * @hw: pointer to hardware structure 299 * 300 * Returns the media type (fiber, copper, backplane) 301 **/ 302 enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw) 303 { 304 return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw), 305 ixgbe_media_type_unknown); 306 } 307 308 /** 309 * ixgbe_get_mac_addr - Get MAC address 310 * @hw: pointer to hardware structure 311 * @mac_addr: Adapter MAC address 312 * 313 * Reads the adapter's MAC address from the first Receive Address Register 314 * (RAR0) A reset of the adapter must have been performed prior to calling 315 * this function in order for the MAC address to have been loaded from the 316 * EEPROM into RAR0 317 **/ 318 s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr) 319 { 320 return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr, 321 (hw, mac_addr), IXGBE_NOT_IMPLEMENTED); 322 } 323 324 /** 325 * ixgbe_get_san_mac_addr - Get SAN MAC address 326 * @hw: pointer to hardware structure 327 * @san_mac_addr: SAN MAC address 328 * 329 * Reads the SAN MAC address from the EEPROM, if it's available. This is 330 * per-port, so set_lan_id() must be called before reading the addresses. 331 **/ 332 s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 333 { 334 return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr, 335 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 336 } 337 338 /** 339 * ixgbe_set_san_mac_addr - Write a SAN MAC address 340 * @hw: pointer to hardware structure 341 * @san_mac_addr: SAN MAC address 342 * 343 * Writes A SAN MAC address to the EEPROM. 344 **/ 345 s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 346 { 347 return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr, 348 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 349 } 350 351 /** 352 * ixgbe_get_device_caps - Get additional device capabilities 353 * @hw: pointer to hardware structure 354 * @device_caps: the EEPROM word for device capabilities 355 * 356 * Reads the extra device capabilities from the EEPROM 357 **/ 358 s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps) 359 { 360 return ixgbe_call_func(hw, hw->mac.ops.get_device_caps, 361 (hw, device_caps), IXGBE_NOT_IMPLEMENTED); 362 } 363 364 /** 365 * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM 366 * @hw: pointer to hardware structure 367 * @wwnn_prefix: the alternative WWNN prefix 368 * @wwpn_prefix: the alternative WWPN prefix 369 * 370 * This function will read the EEPROM from the alternative SAN MAC address 371 * block to check the support for the alternative WWNN/WWPN prefix support. 372 **/ 373 s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix, 374 u16 *wwpn_prefix) 375 { 376 return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix, 377 (hw, wwnn_prefix, wwpn_prefix), 378 IXGBE_NOT_IMPLEMENTED); 379 } 380 381 /** 382 * ixgbe_get_fcoe_boot_status - Get FCOE boot status from EEPROM 383 * @hw: pointer to hardware structure 384 * @bs: the fcoe boot status 385 * 386 * This function will read the FCOE boot status from the iSCSI FCOE block 387 **/ 388 s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs) 389 { 390 return ixgbe_call_func(hw, hw->mac.ops.get_fcoe_boot_status, 391 (hw, bs), 392 IXGBE_NOT_IMPLEMENTED); 393 } 394 395 /** 396 * ixgbe_get_bus_info - Set PCI bus info 397 * @hw: pointer to hardware structure 398 * 399 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 400 **/ 401 s32 ixgbe_get_bus_info(struct ixgbe_hw *hw) 402 { 403 return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw), 404 IXGBE_NOT_IMPLEMENTED); 405 } 406 407 /** 408 * ixgbe_get_num_of_tx_queues - Get Tx queues 409 * @hw: pointer to hardware structure 410 * 411 * Returns the number of transmit queues for the given adapter. 412 **/ 413 u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw) 414 { 415 return hw->mac.max_tx_queues; 416 } 417 418 /** 419 * ixgbe_get_num_of_rx_queues - Get Rx queues 420 * @hw: pointer to hardware structure 421 * 422 * Returns the number of receive queues for the given adapter. 423 **/ 424 u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw) 425 { 426 return hw->mac.max_rx_queues; 427 } 428 429 /** 430 * ixgbe_stop_adapter - Disable Rx/Tx units 431 * @hw: pointer to hardware structure 432 * 433 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 434 * disables transmit and receive units. The adapter_stopped flag is used by 435 * the shared code and drivers to determine if the adapter is in a stopped 436 * state and should not touch the hardware. 437 **/ 438 s32 ixgbe_stop_adapter(struct ixgbe_hw *hw) 439 { 440 return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw), 441 IXGBE_NOT_IMPLEMENTED); 442 } 443 444 /** 445 * ixgbe_read_pba_string - Reads part number string from EEPROM 446 * @hw: pointer to hardware structure 447 * @pba_num: stores the part number string from the EEPROM 448 * @pba_num_size: part number string buffer length 449 * 450 * Reads the part number string from the EEPROM. 451 **/ 452 s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size) 453 { 454 return ixgbe_read_pba_string_generic(hw, pba_num, pba_num_size); 455 } 456 457 /** 458 * ixgbe_read_pba_num - Reads part number from EEPROM 459 * @hw: pointer to hardware structure 460 * @pba_num: stores the part number from the EEPROM 461 * 462 * Reads the part number from the EEPROM. 463 **/ 464 s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num) 465 { 466 return ixgbe_read_pba_num_generic(hw, pba_num); 467 } 468 469 /** 470 * ixgbe_identify_phy - Get PHY type 471 * @hw: pointer to hardware structure 472 * 473 * Determines the physical layer module found on the current adapter. 474 **/ 475 s32 ixgbe_identify_phy(struct ixgbe_hw *hw) 476 { 477 s32 status = IXGBE_SUCCESS; 478 479 if (hw->phy.type == ixgbe_phy_unknown) { 480 status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw), 481 IXGBE_NOT_IMPLEMENTED); 482 } 483 484 return status; 485 } 486 487 /** 488 * ixgbe_reset_phy - Perform a PHY reset 489 * @hw: pointer to hardware structure 490 **/ 491 s32 ixgbe_reset_phy(struct ixgbe_hw *hw) 492 { 493 s32 status = IXGBE_SUCCESS; 494 495 if (hw->phy.type == ixgbe_phy_unknown) { 496 if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS) 497 status = IXGBE_ERR_PHY; 498 } 499 500 if (status == IXGBE_SUCCESS) { 501 status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw), 502 IXGBE_NOT_IMPLEMENTED); 503 } 504 return status; 505 } 506 507 /** 508 * ixgbe_get_phy_firmware_version - 509 * @hw: pointer to hardware structure 510 * @firmware_version: pointer to firmware version 511 **/ 512 s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version) 513 { 514 s32 status = IXGBE_SUCCESS; 515 516 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version, 517 (hw, firmware_version), 518 IXGBE_NOT_IMPLEMENTED); 519 return status; 520 } 521 522 /** 523 * ixgbe_read_phy_reg - Read PHY register 524 * @hw: pointer to hardware structure 525 * @reg_addr: 32 bit address of PHY register to read 526 * @device_type: type of device you want to communicate with 527 * @phy_data: Pointer to read data from PHY register 528 * 529 * Reads a value from a specified PHY register 530 **/ 531 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 532 u16 *phy_data) 533 { 534 if (hw->phy.id == 0) 535 ixgbe_identify_phy(hw); 536 537 return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr, 538 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 539 } 540 541 /** 542 * ixgbe_write_phy_reg - Write PHY register 543 * @hw: pointer to hardware structure 544 * @reg_addr: 32 bit PHY register to write 545 * @device_type: type of device you want to communicate with 546 * @phy_data: Data to write to the PHY register 547 * 548 * Writes a value to specified PHY register 549 **/ 550 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 551 u16 phy_data) 552 { 553 if (hw->phy.id == 0) 554 ixgbe_identify_phy(hw); 555 556 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr, 557 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 558 } 559 560 /** 561 * ixgbe_setup_phy_link - Restart PHY autoneg 562 * @hw: pointer to hardware structure 563 * 564 * Restart autonegotiation and PHY and waits for completion. 565 **/ 566 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw) 567 { 568 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw), 569 IXGBE_NOT_IMPLEMENTED); 570 } 571 572 /** 573 * ixgbe_setup_internal_phy - Configure integrated PHY 574 * @hw: pointer to hardware structure 575 * 576 * Reconfigure the integrated PHY in order to enable talk to the external PHY. 577 * Returns success if not implemented, since nothing needs to be done in this 578 * case. 579 */ 580 s32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw) 581 { 582 return ixgbe_call_func(hw, hw->phy.ops.setup_internal_link, (hw), 583 IXGBE_SUCCESS); 584 } 585 586 /** 587 * ixgbe_check_phy_link - Determine link and speed status 588 * @hw: pointer to hardware structure 589 * @speed: link speed 590 * @link_up: TRUE when link is up 591 * 592 * Reads a PHY register to determine if link is up and the current speed for 593 * the PHY. 594 **/ 595 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 596 bool *link_up) 597 { 598 return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed, 599 link_up), IXGBE_NOT_IMPLEMENTED); 600 } 601 602 /** 603 * ixgbe_setup_phy_link_speed - Set auto advertise 604 * @hw: pointer to hardware structure 605 * @speed: new link speed 606 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 607 * 608 * Sets the auto advertised capabilities 609 **/ 610 s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed, 611 bool autoneg_wait_to_complete) 612 { 613 return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed, 614 autoneg_wait_to_complete), 615 IXGBE_NOT_IMPLEMENTED); 616 } 617 618 /** 619 * ixgbe_set_phy_power - Control the phy power state 620 * @hw: pointer to hardware structure 621 * @on: TRUE for on, FALSE for off 622 */ 623 s32 ixgbe_set_phy_power(struct ixgbe_hw *hw, bool on) 624 { 625 return ixgbe_call_func(hw, hw->phy.ops.set_phy_power, (hw, on), 626 IXGBE_NOT_IMPLEMENTED); 627 } 628 629 /** 630 * ixgbe_check_link - Get link and speed status 631 * @hw: pointer to hardware structure 632 * @speed: pointer to link speed 633 * @link_up: TRUE when link is up 634 * @link_up_wait_to_complete: bool used to wait for link up or not 635 * 636 * Reads the links register to determine if link is up and the current speed 637 **/ 638 s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 639 bool *link_up, bool link_up_wait_to_complete) 640 { 641 return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed, 642 link_up, link_up_wait_to_complete), 643 IXGBE_NOT_IMPLEMENTED); 644 } 645 646 /** 647 * ixgbe_disable_tx_laser - Disable Tx laser 648 * @hw: pointer to hardware structure 649 * 650 * If the driver needs to disable the laser on SFI optics. 651 **/ 652 void ixgbe_disable_tx_laser(struct ixgbe_hw *hw) 653 { 654 if (hw->mac.ops.disable_tx_laser) 655 hw->mac.ops.disable_tx_laser(hw); 656 } 657 658 /** 659 * ixgbe_enable_tx_laser - Enable Tx laser 660 * @hw: pointer to hardware structure 661 * 662 * If the driver needs to enable the laser on SFI optics. 663 **/ 664 void ixgbe_enable_tx_laser(struct ixgbe_hw *hw) 665 { 666 if (hw->mac.ops.enable_tx_laser) 667 hw->mac.ops.enable_tx_laser(hw); 668 } 669 670 /** 671 * ixgbe_flap_tx_laser - flap Tx laser to start autotry process 672 * @hw: pointer to hardware structure 673 * 674 * When the driver changes the link speeds that it can support then 675 * flap the tx laser to alert the link partner to start autotry 676 * process on its end. 677 **/ 678 void ixgbe_flap_tx_laser(struct ixgbe_hw *hw) 679 { 680 if (hw->mac.ops.flap_tx_laser) 681 hw->mac.ops.flap_tx_laser(hw); 682 } 683 684 /** 685 * ixgbe_setup_link - Set link speed 686 * @hw: pointer to hardware structure 687 * @speed: new link speed 688 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 689 * 690 * Configures link settings. Restarts the link. 691 * Performs autonegotiation if needed. 692 **/ 693 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 694 bool autoneg_wait_to_complete) 695 { 696 return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed, 697 autoneg_wait_to_complete), 698 IXGBE_NOT_IMPLEMENTED); 699 } 700 701 /** 702 * ixgbe_setup_mac_link - Set link speed 703 * @hw: pointer to hardware structure 704 * @speed: new link speed 705 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 706 * 707 * Configures link settings. Restarts the link. 708 * Performs autonegotiation if needed. 709 **/ 710 s32 ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 711 bool autoneg_wait_to_complete) 712 { 713 return ixgbe_call_func(hw, hw->mac.ops.setup_mac_link, (hw, speed, 714 autoneg_wait_to_complete), 715 IXGBE_NOT_IMPLEMENTED); 716 } 717 718 /** 719 * ixgbe_get_link_capabilities - Returns link capabilities 720 * @hw: pointer to hardware structure 721 * @speed: link speed capabilities 722 * @autoneg: TRUE when autoneg or autotry is enabled 723 * 724 * Determines the link capabilities of the current configuration. 725 **/ 726 s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 727 bool *autoneg) 728 { 729 return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw, 730 speed, autoneg), IXGBE_NOT_IMPLEMENTED); 731 } 732 733 /** 734 * ixgbe_led_on - Turn on LEDs 735 * @hw: pointer to hardware structure 736 * @index: led number to turn on 737 * 738 * Turns on the software controllable LEDs. 739 **/ 740 s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index) 741 { 742 return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index), 743 IXGBE_NOT_IMPLEMENTED); 744 } 745 746 /** 747 * ixgbe_led_off - Turn off LEDs 748 * @hw: pointer to hardware structure 749 * @index: led number to turn off 750 * 751 * Turns off the software controllable LEDs. 752 **/ 753 s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index) 754 { 755 return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index), 756 IXGBE_NOT_IMPLEMENTED); 757 } 758 759 /** 760 * ixgbe_blink_led_start - Blink LEDs 761 * @hw: pointer to hardware structure 762 * @index: led number to blink 763 * 764 * Blink LED based on index. 765 **/ 766 s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index) 767 { 768 return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index), 769 IXGBE_NOT_IMPLEMENTED); 770 } 771 772 /** 773 * ixgbe_blink_led_stop - Stop blinking LEDs 774 * @hw: pointer to hardware structure 775 * @index: led number to stop 776 * 777 * Stop blinking LED based on index. 778 **/ 779 s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index) 780 { 781 return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index), 782 IXGBE_NOT_IMPLEMENTED); 783 } 784 785 /** 786 * ixgbe_init_eeprom_params - Initialize EEPROM parameters 787 * @hw: pointer to hardware structure 788 * 789 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 790 * ixgbe_hw struct in order to set up EEPROM access. 791 **/ 792 s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw) 793 { 794 return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw), 795 IXGBE_NOT_IMPLEMENTED); 796 } 797 798 799 /** 800 * ixgbe_write_eeprom - Write word to EEPROM 801 * @hw: pointer to hardware structure 802 * @offset: offset within the EEPROM to be written to 803 * @data: 16 bit word to be written to the EEPROM 804 * 805 * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not 806 * called after this function, the EEPROM will most likely contain an 807 * invalid checksum. 808 **/ 809 s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data) 810 { 811 return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data), 812 IXGBE_NOT_IMPLEMENTED); 813 } 814 815 /** 816 * ixgbe_write_eeprom_buffer - Write word(s) to EEPROM 817 * @hw: pointer to hardware structure 818 * @offset: offset within the EEPROM to be written to 819 * @data: 16 bit word(s) to be written to the EEPROM 820 * @words: number of words 821 * 822 * Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not 823 * called after this function, the EEPROM will most likely contain an 824 * invalid checksum. 825 **/ 826 s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, u16 words, 827 u16 *data) 828 { 829 return ixgbe_call_func(hw, hw->eeprom.ops.write_buffer, 830 (hw, offset, words, data), 831 IXGBE_NOT_IMPLEMENTED); 832 } 833 834 /** 835 * ixgbe_read_eeprom - Read word from EEPROM 836 * @hw: pointer to hardware structure 837 * @offset: offset within the EEPROM to be read 838 * @data: read 16 bit value from EEPROM 839 * 840 * Reads 16 bit value from EEPROM 841 **/ 842 s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data) 843 { 844 return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data), 845 IXGBE_NOT_IMPLEMENTED); 846 } 847 848 /** 849 * ixgbe_read_eeprom_buffer - Read word(s) from EEPROM 850 * @hw: pointer to hardware structure 851 * @offset: offset within the EEPROM to be read 852 * @data: read 16 bit word(s) from EEPROM 853 * @words: number of words 854 * 855 * Reads 16 bit word(s) from EEPROM 856 **/ 857 s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, 858 u16 words, u16 *data) 859 { 860 return ixgbe_call_func(hw, hw->eeprom.ops.read_buffer, 861 (hw, offset, words, data), 862 IXGBE_NOT_IMPLEMENTED); 863 } 864 865 /** 866 * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum 867 * @hw: pointer to hardware structure 868 * @checksum_val: calculated checksum 869 * 870 * Performs checksum calculation and validates the EEPROM checksum 871 **/ 872 s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val) 873 { 874 return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum, 875 (hw, checksum_val), IXGBE_NOT_IMPLEMENTED); 876 } 877 878 /** 879 * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum 880 * @hw: pointer to hardware structure 881 **/ 882 s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw) 883 { 884 return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw), 885 IXGBE_NOT_IMPLEMENTED); 886 } 887 888 /** 889 * ixgbe_insert_mac_addr - Find a RAR for this mac address 890 * @hw: pointer to hardware structure 891 * @addr: Address to put into receive address register 892 * @vmdq: VMDq pool to assign 893 * 894 * Puts an ethernet address into a receive address register, or 895 * finds the rar that it is already in; adds to the pool list 896 **/ 897 s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 898 { 899 return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr, 900 (hw, addr, vmdq), 901 IXGBE_NOT_IMPLEMENTED); 902 } 903 904 /** 905 * ixgbe_set_rar - Set Rx address register 906 * @hw: pointer to hardware structure 907 * @index: Receive address register to write 908 * @addr: Address to put into receive address register 909 * @vmdq: VMDq "set" 910 * @enable_addr: set flag that address is active 911 * 912 * Puts an ethernet address into a receive address register. 913 **/ 914 s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 915 u32 enable_addr) 916 { 917 return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq, 918 enable_addr), IXGBE_NOT_IMPLEMENTED); 919 } 920 921 /** 922 * ixgbe_clear_rar - Clear Rx address register 923 * @hw: pointer to hardware structure 924 * @index: Receive address register to write 925 * 926 * Puts an ethernet address into a receive address register. 927 **/ 928 s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index) 929 { 930 return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index), 931 IXGBE_NOT_IMPLEMENTED); 932 } 933 934 /** 935 * ixgbe_set_vmdq - Associate a VMDq index with a receive address 936 * @hw: pointer to hardware structure 937 * @rar: receive address register index to associate with VMDq index 938 * @vmdq: VMDq set or pool index 939 **/ 940 s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 941 { 942 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq), 943 IXGBE_NOT_IMPLEMENTED); 944 945 } 946 947 /** 948 * ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address 949 * @hw: pointer to hardware structure 950 * @vmdq: VMDq default pool index 951 **/ 952 s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq) 953 { 954 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq_san_mac, 955 (hw, vmdq), IXGBE_NOT_IMPLEMENTED); 956 } 957 958 /** 959 * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address 960 * @hw: pointer to hardware structure 961 * @rar: receive address register index to disassociate with VMDq index 962 * @vmdq: VMDq set or pool index 963 **/ 964 s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 965 { 966 return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq), 967 IXGBE_NOT_IMPLEMENTED); 968 } 969 970 /** 971 * ixgbe_init_rx_addrs - Initializes receive address filters. 972 * @hw: pointer to hardware structure 973 * 974 * Places the MAC address in receive address register 0 and clears the rest 975 * of the receive address registers. Clears the multicast table. Assumes 976 * the receiver is in reset when the routine is called. 977 **/ 978 s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw) 979 { 980 return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw), 981 IXGBE_NOT_IMPLEMENTED); 982 } 983 984 /** 985 * ixgbe_get_num_rx_addrs - Returns the number of RAR entries. 986 * @hw: pointer to hardware structure 987 **/ 988 u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw) 989 { 990 return hw->mac.num_rar_entries; 991 } 992 993 /** 994 * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses 995 * @hw: pointer to hardware structure 996 * @addr_list: the list of new multicast addresses 997 * @addr_count: number of addresses 998 * @func: iterator function to walk the multicast address list 999 * 1000 * The given list replaces any existing list. Clears the secondary addrs from 1001 * receive address registers. Uses unused receive address registers for the 1002 * first secondary addresses, and falls back to promiscuous mode as needed. 1003 **/ 1004 s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, 1005 u32 addr_count, ixgbe_mc_addr_itr func) 1006 { 1007 return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw, 1008 addr_list, addr_count, func), 1009 IXGBE_NOT_IMPLEMENTED); 1010 } 1011 1012 /** 1013 * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses 1014 * @hw: pointer to hardware structure 1015 * @mc_addr_list: the list of new multicast addresses 1016 * @mc_addr_count: number of addresses 1017 * @func: iterator function to walk the multicast address list 1018 * @clear: flag, when set clears the table beforehand 1019 * 1020 * The given list replaces any existing list. Clears the MC addrs from receive 1021 * address registers and the multicast table. Uses unused receive address 1022 * registers for the first multicast addresses, and hashes the rest into the 1023 * multicast table. 1024 **/ 1025 s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, 1026 u32 mc_addr_count, ixgbe_mc_addr_itr func, 1027 bool clear) 1028 { 1029 return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw, 1030 mc_addr_list, mc_addr_count, func, clear), 1031 IXGBE_NOT_IMPLEMENTED); 1032 } 1033 1034 /** 1035 * ixgbe_enable_mc - Enable multicast address in RAR 1036 * @hw: pointer to hardware structure 1037 * 1038 * Enables multicast address in RAR and the use of the multicast hash table. 1039 **/ 1040 s32 ixgbe_enable_mc(struct ixgbe_hw *hw) 1041 { 1042 return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw), 1043 IXGBE_NOT_IMPLEMENTED); 1044 } 1045 1046 /** 1047 * ixgbe_disable_mc - Disable multicast address in RAR 1048 * @hw: pointer to hardware structure 1049 * 1050 * Disables multicast address in RAR and the use of the multicast hash table. 1051 **/ 1052 s32 ixgbe_disable_mc(struct ixgbe_hw *hw) 1053 { 1054 return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw), 1055 IXGBE_NOT_IMPLEMENTED); 1056 } 1057 1058 /** 1059 * ixgbe_clear_vfta - Clear VLAN filter table 1060 * @hw: pointer to hardware structure 1061 * 1062 * Clears the VLAN filer table, and the VMDq index associated with the filter 1063 **/ 1064 s32 ixgbe_clear_vfta(struct ixgbe_hw *hw) 1065 { 1066 return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw), 1067 IXGBE_NOT_IMPLEMENTED); 1068 } 1069 1070 /** 1071 * ixgbe_set_vfta - Set VLAN filter table 1072 * @hw: pointer to hardware structure 1073 * @vlan: VLAN id to write to VLAN filter 1074 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 1075 * @vlan_on: boolean flag to turn on/off VLAN 1076 * @vlvf_bypass: boolean flag indicating updating the default pool is okay 1077 * 1078 * Turn on/off specified VLAN in the VLAN filter table. 1079 **/ 1080 s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, 1081 bool vlvf_bypass) 1082 { 1083 return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind, 1084 vlan_on, vlvf_bypass), IXGBE_NOT_IMPLEMENTED); 1085 } 1086 1087 /** 1088 * ixgbe_set_vlvf - Set VLAN Pool Filter 1089 * @hw: pointer to hardware structure 1090 * @vlan: VLAN id to write to VLAN filter 1091 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 1092 * @vlan_on: boolean flag to turn on/off VLAN in VLVF 1093 * @vfta_delta: pointer to the difference between the current value of VFTA 1094 * and the desired value 1095 * @vfta: the desired value of the VFTA 1096 * @vlvf_bypass: boolean flag indicating updating the default pool is okay 1097 * 1098 * Turn on/off specified bit in VLVF table. 1099 **/ 1100 s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, 1101 u32 *vfta_delta, u32 vfta, bool vlvf_bypass) 1102 { 1103 return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind, 1104 vlan_on, vfta_delta, vfta, vlvf_bypass), 1105 IXGBE_NOT_IMPLEMENTED); 1106 } 1107 1108 /** 1109 * ixgbe_fc_enable - Enable flow control 1110 * @hw: pointer to hardware structure 1111 * 1112 * Configures the flow control settings based on SW configuration. 1113 **/ 1114 s32 ixgbe_fc_enable(struct ixgbe_hw *hw) 1115 { 1116 return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw), 1117 IXGBE_NOT_IMPLEMENTED); 1118 } 1119 1120 /** 1121 * ixgbe_setup_fc - Set up flow control 1122 * @hw: pointer to hardware structure 1123 * 1124 * Called at init time to set up flow control. 1125 **/ 1126 s32 ixgbe_setup_fc(struct ixgbe_hw *hw) 1127 { 1128 return ixgbe_call_func(hw, hw->mac.ops.setup_fc, (hw), 1129 IXGBE_NOT_IMPLEMENTED); 1130 } 1131 1132 /** 1133 * ixgbe_set_fw_drv_ver - Try to send the driver version number FW 1134 * @hw: pointer to hardware structure 1135 * @maj: driver major number to be sent to firmware 1136 * @minr: driver minor number to be sent to firmware 1137 * @build: driver build number to be sent to firmware 1138 * @ver: driver version number to be sent to firmware 1139 * @len: length of driver_ver string 1140 * @driver_ver: driver string 1141 **/ 1142 s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 minr, u8 build, 1143 u8 ver, u16 len, char *driver_ver) 1144 { 1145 return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, minr, 1146 build, ver, len, driver_ver), 1147 IXGBE_NOT_IMPLEMENTED); 1148 } 1149 1150 1151 1152 /** 1153 * ixgbe_dmac_config - Configure DMA Coalescing registers. 1154 * @hw: pointer to hardware structure 1155 * 1156 * Configure DMA coalescing. If enabling dmac, dmac is activated. 1157 * When disabling dmac, dmac enable dmac bit is cleared. 1158 **/ 1159 s32 ixgbe_dmac_config(struct ixgbe_hw *hw) 1160 { 1161 return ixgbe_call_func(hw, hw->mac.ops.dmac_config, (hw), 1162 IXGBE_NOT_IMPLEMENTED); 1163 } 1164 1165 /** 1166 * ixgbe_dmac_update_tcs - Configure DMA Coalescing registers. 1167 * @hw: pointer to hardware structure 1168 * 1169 * Disables dmac, updates per TC settings, and then enable dmac. 1170 **/ 1171 s32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw) 1172 { 1173 return ixgbe_call_func(hw, hw->mac.ops.dmac_update_tcs, (hw), 1174 IXGBE_NOT_IMPLEMENTED); 1175 } 1176 1177 /** 1178 * ixgbe_dmac_config_tcs - Configure DMA Coalescing registers. 1179 * @hw: pointer to hardware structure 1180 * 1181 * Configure DMA coalescing threshold per TC and set high priority bit for 1182 * FCOE TC. The dmac enable bit must be cleared before configuring. 1183 **/ 1184 s32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw) 1185 { 1186 return ixgbe_call_func(hw, hw->mac.ops.dmac_config_tcs, (hw), 1187 IXGBE_NOT_IMPLEMENTED); 1188 } 1189 1190 /** 1191 * ixgbe_setup_eee - Enable/disable EEE support 1192 * @hw: pointer to the HW structure 1193 * @enable_eee: boolean flag to enable EEE 1194 * 1195 * Enable/disable EEE based on enable_ee flag. 1196 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C 1197 * are modified. 1198 * 1199 **/ 1200 s32 ixgbe_setup_eee(struct ixgbe_hw *hw, bool enable_eee) 1201 { 1202 return ixgbe_call_func(hw, hw->mac.ops.setup_eee, (hw, enable_eee), 1203 IXGBE_NOT_IMPLEMENTED); 1204 } 1205 1206 /** 1207 * ixgbe_set_source_address_pruning - Enable/Disable source address pruning 1208 * @hw: pointer to hardware structure 1209 * @enable: enable or disable source address pruning 1210 * @pool: Rx pool - Rx pool to toggle source address pruning 1211 **/ 1212 void ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable, 1213 unsigned int pool) 1214 { 1215 if (hw->mac.ops.set_source_address_pruning) 1216 hw->mac.ops.set_source_address_pruning(hw, enable, pool); 1217 } 1218 1219 /** 1220 * ixgbe_set_ethertype_anti_spoofing - Enable/Disable Ethertype anti-spoofing 1221 * @hw: pointer to hardware structure 1222 * @enable: enable or disable switch for Ethertype anti-spoofing 1223 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 1224 * 1225 **/ 1226 void ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 1227 { 1228 if (hw->mac.ops.set_ethertype_anti_spoofing) 1229 hw->mac.ops.set_ethertype_anti_spoofing(hw, enable, vf); 1230 } 1231 1232 /** 1233 * ixgbe_read_iosf_sb_reg - Read 32 bit PHY register 1234 * @hw: pointer to hardware structure 1235 * @reg_addr: 32 bit address of PHY register to read 1236 * @device_type: type of device you want to communicate with 1237 * @phy_data: Pointer to read data from PHY register 1238 * 1239 * Reads a value from a specified PHY register 1240 **/ 1241 s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1242 u32 device_type, u32 *phy_data) 1243 { 1244 return ixgbe_call_func(hw, hw->mac.ops.read_iosf_sb_reg, (hw, reg_addr, 1245 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1246 } 1247 1248 /** 1249 * ixgbe_write_iosf_sb_reg - Write 32 bit register through IOSF Sideband 1250 * @hw: pointer to hardware structure 1251 * @reg_addr: 32 bit PHY register to write 1252 * @device_type: type of device you want to communicate with 1253 * @phy_data: Data to write to the PHY register 1254 * 1255 * Writes a value to specified PHY register 1256 **/ 1257 s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1258 u32 device_type, u32 phy_data) 1259 { 1260 return ixgbe_call_func(hw, hw->mac.ops.write_iosf_sb_reg, (hw, reg_addr, 1261 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1262 } 1263 1264 /** 1265 * ixgbe_disable_mdd - Disable malicious driver detection 1266 * @hw: pointer to hardware structure 1267 * 1268 **/ 1269 void ixgbe_disable_mdd(struct ixgbe_hw *hw) 1270 { 1271 if (hw->mac.ops.disable_mdd) 1272 hw->mac.ops.disable_mdd(hw); 1273 } 1274 1275 /** 1276 * ixgbe_enable_mdd - Enable malicious driver detection 1277 * @hw: pointer to hardware structure 1278 * 1279 **/ 1280 void ixgbe_enable_mdd(struct ixgbe_hw *hw) 1281 { 1282 if (hw->mac.ops.enable_mdd) 1283 hw->mac.ops.enable_mdd(hw); 1284 } 1285 1286 /** 1287 * ixgbe_mdd_event - Handle malicious driver detection event 1288 * @hw: pointer to hardware structure 1289 * @vf_bitmap: vf bitmap of malicious vfs 1290 * 1291 **/ 1292 void ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap) 1293 { 1294 if (hw->mac.ops.mdd_event) 1295 hw->mac.ops.mdd_event(hw, vf_bitmap); 1296 } 1297 1298 /** 1299 * ixgbe_restore_mdd_vf - Restore VF that was disabled during malicious driver 1300 * detection event 1301 * @hw: pointer to hardware structure 1302 * @vf: vf index 1303 * 1304 **/ 1305 void ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf) 1306 { 1307 if (hw->mac.ops.restore_mdd_vf) 1308 hw->mac.ops.restore_mdd_vf(hw, vf); 1309 } 1310 1311 /** 1312 * ixgbe_fw_recovery_mode - Check if in FW NVM recovery mode 1313 * @hw: pointer to hardware structure 1314 * 1315 **/ 1316 bool ixgbe_fw_recovery_mode(struct ixgbe_hw *hw) 1317 { 1318 if (hw->mac.ops.fw_recovery_mode) 1319 return hw->mac.ops.fw_recovery_mode(hw); 1320 return FALSE; 1321 } 1322 1323 /** 1324 * ixgbe_enter_lplu - Transition to low power states 1325 * @hw: pointer to hardware structure 1326 * 1327 * Configures Low Power Link Up on transition to low power states 1328 * (from D0 to non-D0). 1329 **/ 1330 s32 ixgbe_enter_lplu(struct ixgbe_hw *hw) 1331 { 1332 return ixgbe_call_func(hw, hw->phy.ops.enter_lplu, (hw), 1333 IXGBE_NOT_IMPLEMENTED); 1334 } 1335 1336 /** 1337 * ixgbe_handle_lasi - Handle external Base T PHY interrupt 1338 * @hw: pointer to hardware structure 1339 * 1340 * Handle external Base T PHY interrupt. If high temperature 1341 * failure alarm then return error, else if link status change 1342 * then setup internal/external PHY link 1343 * 1344 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 1345 * failure alarm, else return PHY access status. 1346 */ 1347 s32 ixgbe_handle_lasi(struct ixgbe_hw *hw) 1348 { 1349 return ixgbe_call_func(hw, hw->phy.ops.handle_lasi, (hw), 1350 IXGBE_NOT_IMPLEMENTED); 1351 } 1352 1353 /** 1354 * ixgbe_bypass_rw - Bit bang data into by_pass FW 1355 * @hw: pointer to hardware structure 1356 * @cmd: Command we send to the FW 1357 * @status: The reply from the FW 1358 * 1359 * Bit-bangs the cmd to the by_pass FW status points to what is returned. 1360 **/ 1361 s32 ixgbe_bypass_rw(struct ixgbe_hw *hw, u32 cmd, u32 *status) 1362 { 1363 return ixgbe_call_func(hw, hw->mac.ops.bypass_rw, (hw, cmd, status), 1364 IXGBE_NOT_IMPLEMENTED); 1365 } 1366 1367 /** 1368 * ixgbe_bypass_valid_rd - Verify valid return from bit-bang. 1369 * 1370 * If we send a write we can't be sure it took until we can read back 1371 * that same register. It can be a problem as some of the feilds may 1372 * for valid reasons change inbetween the time wrote the register and 1373 * we read it again to verify. So this function check everything we 1374 * can check and then assumes it worked. 1375 * 1376 * @u32 in_reg - The register cmd for the bit-bang read. 1377 * @u32 out_reg - The register returned from a bit-bang read. 1378 **/ 1379 bool ixgbe_bypass_valid_rd(struct ixgbe_hw *hw, u32 in_reg, u32 out_reg) 1380 { 1381 return ixgbe_call_func(hw, hw->mac.ops.bypass_valid_rd, 1382 (in_reg, out_reg), IXGBE_NOT_IMPLEMENTED); 1383 } 1384 1385 /** 1386 * ixgbe_bypass_set - Set a bypass field in the FW CTRL Regiter. 1387 * @hw: pointer to hardware structure 1388 * @cmd: The control word we are setting. 1389 * @event: The event we are setting in the FW. This also happens to 1390 * be the mask for the event we are setting (handy) 1391 * @action: The action we set the event to in the FW. This is in a 1392 * bit field that happens to be what we want to put in 1393 * the event spot (also handy) 1394 * 1395 * Writes to the cmd control the bits in actions. 1396 **/ 1397 s32 ixgbe_bypass_set(struct ixgbe_hw *hw, u32 cmd, u32 event, u32 action) 1398 { 1399 return ixgbe_call_func(hw, hw->mac.ops.bypass_set, 1400 (hw, cmd, event, action), 1401 IXGBE_NOT_IMPLEMENTED); 1402 } 1403 1404 /** 1405 * ixgbe_bypass_rd_eep - Read the bypass FW eeprom address 1406 * @hw: pointer to hardware structure 1407 * @addr: The bypass eeprom address to read. 1408 * @value: The 8b of data at the address above. 1409 **/ 1410 s32 ixgbe_bypass_rd_eep(struct ixgbe_hw *hw, u32 addr, u8 *value) 1411 { 1412 return ixgbe_call_func(hw, hw->mac.ops.bypass_rd_eep, 1413 (hw, addr, value), IXGBE_NOT_IMPLEMENTED); 1414 } 1415 1416 /** 1417 * ixgbe_read_analog_reg8 - Reads 8 bit analog register 1418 * @hw: pointer to hardware structure 1419 * @reg: analog register to read 1420 * @val: read value 1421 * 1422 * Performs write operation to analog register specified. 1423 **/ 1424 s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val) 1425 { 1426 return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg, 1427 val), IXGBE_NOT_IMPLEMENTED); 1428 } 1429 1430 /** 1431 * ixgbe_write_analog_reg8 - Writes 8 bit analog register 1432 * @hw: pointer to hardware structure 1433 * @reg: analog register to write 1434 * @val: value to write 1435 * 1436 * Performs write operation to Atlas analog register specified. 1437 **/ 1438 s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val) 1439 { 1440 return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg, 1441 val), IXGBE_NOT_IMPLEMENTED); 1442 } 1443 1444 /** 1445 * ixgbe_init_uta_tables - Initializes Unicast Table Arrays. 1446 * @hw: pointer to hardware structure 1447 * 1448 * Initializes the Unicast Table Arrays to zero on device load. This 1449 * is part of the Rx init addr execution path. 1450 **/ 1451 s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw) 1452 { 1453 return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw), 1454 IXGBE_NOT_IMPLEMENTED); 1455 } 1456 1457 /** 1458 * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address 1459 * @hw: pointer to hardware structure 1460 * @byte_offset: byte offset to read 1461 * @dev_addr: I2C bus address to read from 1462 * @data: value read 1463 * 1464 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1465 **/ 1466 s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1467 u8 *data) 1468 { 1469 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset, 1470 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1471 } 1472 1473 /** 1474 * ixgbe_read_i2c_byte_unlocked - Reads 8 bit word via I2C from device address 1475 * @hw: pointer to hardware structure 1476 * @byte_offset: byte offset to read 1477 * @dev_addr: I2C bus address to read from 1478 * @data: value read 1479 * 1480 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1481 **/ 1482 s32 ixgbe_read_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1483 u8 dev_addr, u8 *data) 1484 { 1485 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte_unlocked, 1486 (hw, byte_offset, dev_addr, data), 1487 IXGBE_NOT_IMPLEMENTED); 1488 } 1489 1490 /** 1491 * ixgbe_read_link - Perform read operation on link device 1492 * @hw: pointer to the hardware structure 1493 * @addr: bus address to read from 1494 * @reg: device register to read from 1495 * @val: pointer to location to receive read value 1496 * 1497 * Returns an error code on error. 1498 */ 1499 s32 ixgbe_read_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) 1500 { 1501 return ixgbe_call_func(hw, hw->link.ops.read_link, (hw, addr, 1502 reg, val), IXGBE_NOT_IMPLEMENTED); 1503 } 1504 1505 /** 1506 * ixgbe_read_link_unlocked - Perform read operation on link device 1507 * @hw: pointer to the hardware structure 1508 * @addr: bus address to read from 1509 * @reg: device register to read from 1510 * @val: pointer to location to receive read value 1511 * 1512 * Returns an error code on error. 1513 **/ 1514 s32 ixgbe_read_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) 1515 { 1516 return ixgbe_call_func(hw, hw->link.ops.read_link_unlocked, 1517 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1518 } 1519 1520 /** 1521 * ixgbe_write_i2c_byte - Writes 8 bit word over I2C 1522 * @hw: pointer to hardware structure 1523 * @byte_offset: byte offset to write 1524 * @dev_addr: I2C bus address to write to 1525 * @data: value to write 1526 * 1527 * Performs byte write operation to SFP module's EEPROM over I2C interface 1528 * at a specified device address. 1529 **/ 1530 s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1531 u8 data) 1532 { 1533 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset, 1534 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1535 } 1536 1537 /** 1538 * ixgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C 1539 * @hw: pointer to hardware structure 1540 * @byte_offset: byte offset to write 1541 * @dev_addr: I2C bus address to write to 1542 * @data: value to write 1543 * 1544 * Performs byte write operation to SFP module's EEPROM over I2C interface 1545 * at a specified device address. 1546 **/ 1547 s32 ixgbe_write_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1548 u8 dev_addr, u8 data) 1549 { 1550 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte_unlocked, 1551 (hw, byte_offset, dev_addr, data), 1552 IXGBE_NOT_IMPLEMENTED); 1553 } 1554 1555 /** 1556 * ixgbe_write_link - Perform write operation on link device 1557 * @hw: pointer to the hardware structure 1558 * @addr: bus address to write to 1559 * @reg: device register to write to 1560 * @val: value to write 1561 * 1562 * Returns an error code on error. 1563 */ 1564 s32 ixgbe_write_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) 1565 { 1566 return ixgbe_call_func(hw, hw->link.ops.write_link, 1567 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1568 } 1569 1570 /** 1571 * ixgbe_write_link_unlocked - Perform write operation on link device 1572 * @hw: pointer to the hardware structure 1573 * @addr: bus address to write to 1574 * @reg: device register to write to 1575 * @val: value to write 1576 * 1577 * Returns an error code on error. 1578 **/ 1579 s32 ixgbe_write_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) 1580 { 1581 return ixgbe_call_func(hw, hw->link.ops.write_link_unlocked, 1582 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1583 } 1584 1585 /** 1586 * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface 1587 * @hw: pointer to hardware structure 1588 * @byte_offset: EEPROM byte offset to write 1589 * @eeprom_data: value to write 1590 * 1591 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1592 **/ 1593 s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, 1594 u8 byte_offset, u8 eeprom_data) 1595 { 1596 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom, 1597 (hw, byte_offset, eeprom_data), 1598 IXGBE_NOT_IMPLEMENTED); 1599 } 1600 1601 /** 1602 * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface 1603 * @hw: pointer to hardware structure 1604 * @byte_offset: EEPROM byte offset to read 1605 * @eeprom_data: value read 1606 * 1607 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1608 **/ 1609 s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data) 1610 { 1611 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom, 1612 (hw, byte_offset, eeprom_data), 1613 IXGBE_NOT_IMPLEMENTED); 1614 } 1615 1616 /** 1617 * ixgbe_get_supported_physical_layer - Returns physical layer type 1618 * @hw: pointer to hardware structure 1619 * 1620 * Determines physical layer capabilities of the current configuration. 1621 **/ 1622 u64 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw) 1623 { 1624 return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer, 1625 (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN); 1626 } 1627 1628 /** 1629 * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics 1630 * @hw: pointer to hardware structure 1631 * @regval: bitfield to write to the Rx DMA register 1632 * 1633 * Enables the Rx DMA unit of the device. 1634 **/ 1635 s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval) 1636 { 1637 return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma, 1638 (hw, regval), IXGBE_NOT_IMPLEMENTED); 1639 } 1640 1641 /** 1642 * ixgbe_disable_sec_rx_path - Stops the receive data path 1643 * @hw: pointer to hardware structure 1644 * 1645 * Stops the receive data path. 1646 **/ 1647 s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw) 1648 { 1649 return ixgbe_call_func(hw, hw->mac.ops.disable_sec_rx_path, 1650 (hw), IXGBE_NOT_IMPLEMENTED); 1651 } 1652 1653 /** 1654 * ixgbe_enable_sec_rx_path - Enables the receive data path 1655 * @hw: pointer to hardware structure 1656 * 1657 * Enables the receive data path. 1658 **/ 1659 s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw) 1660 { 1661 return ixgbe_call_func(hw, hw->mac.ops.enable_sec_rx_path, 1662 (hw), IXGBE_NOT_IMPLEMENTED); 1663 } 1664 1665 /** 1666 * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore 1667 * @hw: pointer to hardware structure 1668 * @mask: Mask to specify which semaphore to acquire 1669 * 1670 * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified 1671 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1672 **/ 1673 s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1674 { 1675 return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync, 1676 (hw, mask), IXGBE_NOT_IMPLEMENTED); 1677 } 1678 1679 /** 1680 * ixgbe_release_swfw_semaphore - Release SWFW semaphore 1681 * @hw: pointer to hardware structure 1682 * @mask: Mask to specify which semaphore to release 1683 * 1684 * Releases the SWFW semaphore through SW_FW_SYNC register for the specified 1685 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1686 **/ 1687 void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1688 { 1689 if (hw->mac.ops.release_swfw_sync) 1690 hw->mac.ops.release_swfw_sync(hw, mask); 1691 } 1692 1693 /** 1694 * ixgbe_init_swfw_semaphore - Clean up SWFW semaphore 1695 * @hw: pointer to hardware structure 1696 * 1697 * Attempts to acquire the SWFW semaphore through SW_FW_SYNC register. 1698 * Regardless of whether is succeeds or not it then release the semaphore. 1699 * This is function is called to recover from catastrophic failures that 1700 * may have left the semaphore locked. 1701 **/ 1702 void ixgbe_init_swfw_semaphore(struct ixgbe_hw *hw) 1703 { 1704 if (hw->mac.ops.init_swfw_sync) 1705 hw->mac.ops.init_swfw_sync(hw); 1706 } 1707 1708 1709 void ixgbe_disable_rx(struct ixgbe_hw *hw) 1710 { 1711 if (hw->mac.ops.disable_rx) 1712 hw->mac.ops.disable_rx(hw); 1713 } 1714 1715 void ixgbe_enable_rx(struct ixgbe_hw *hw) 1716 { 1717 if (hw->mac.ops.enable_rx) 1718 hw->mac.ops.enable_rx(hw); 1719 } 1720 1721 /** 1722 * ixgbe_set_rate_select_speed - Set module link speed 1723 * @hw: pointer to hardware structure 1724 * @speed: link speed to set 1725 * 1726 * Set module link speed via the rate select. 1727 */ 1728 void ixgbe_set_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed) 1729 { 1730 if (hw->mac.ops.set_rate_select_speed) 1731 hw->mac.ops.set_rate_select_speed(hw, speed); 1732 } 1733