1 /****************************************************************************** 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_api.c 299200 2016-05-06 22:54:56Z pfg $*/ 34 /*$NetBSD: ixgbe_api.c,v 1.15 2016/12/05 08:50:29 msaitoh Exp $*/ 35 36 #include "ixgbe_api.h" 37 #include "ixgbe_common.h" 38 39 static const u32 ixgbe_mvals_base[IXGBE_MVALS_IDX_LIMIT] = { 40 IXGBE_MVALS_INIT() 41 }; 42 43 static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = { 44 IXGBE_MVALS_INIT(_X540) 45 }; 46 47 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = { 48 IXGBE_MVALS_INIT(_X550) 49 }; 50 51 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = { 52 IXGBE_MVALS_INIT(_X550EM_x) 53 }; 54 55 /** 56 * ixgbe_dcb_get_rtrup2tc - read rtrup2tc reg 57 * @hw: pointer to hardware structure 58 * @map: pointer to u8 arr for returning map 59 * 60 * Read the rtrup2tc HW register and resolve its content into map 61 **/ 62 void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map) 63 { 64 if (hw->mac.ops.get_rtrup2tc) 65 hw->mac.ops.get_rtrup2tc(hw, map); 66 } 67 68 /** 69 * ixgbe_init_shared_code - Initialize the shared code 70 * @hw: pointer to hardware structure 71 * 72 * This will assign function pointers and assign the MAC type and PHY code. 73 * Does not touch the hardware. This function must be called prior to any 74 * other function in the shared code. The ixgbe_hw structure should be 75 * memset to 0 prior to calling this function. The following fields in 76 * hw structure should be filled in prior to calling this function: 77 * back, device_id, vendor_id, subsystem_device_id, 78 * subsystem_vendor_id, and revision_id 79 **/ 80 s32 ixgbe_init_shared_code(struct ixgbe_hw *hw) 81 { 82 s32 status; 83 84 DEBUGFUNC("ixgbe_init_shared_code"); 85 86 /* 87 * Set the mac type 88 */ 89 ixgbe_set_mac_type(hw); 90 91 switch (hw->mac.type) { 92 case ixgbe_mac_82598EB: 93 status = ixgbe_init_ops_82598(hw); 94 break; 95 case ixgbe_mac_82599EB: 96 status = ixgbe_init_ops_82599(hw); 97 break; 98 case ixgbe_mac_X540: 99 status = ixgbe_init_ops_X540(hw); 100 break; 101 case ixgbe_mac_X550: 102 status = ixgbe_init_ops_X550(hw); 103 break; 104 case ixgbe_mac_X550EM_x: 105 status = ixgbe_init_ops_X550EM(hw); 106 break; 107 case ixgbe_mac_82599_vf: 108 case ixgbe_mac_X540_vf: 109 case ixgbe_mac_X550_vf: 110 case ixgbe_mac_X550EM_x_vf: 111 status = ixgbe_init_ops_vf(hw); 112 break; 113 default: 114 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 115 break; 116 } 117 hw->mac.max_link_up_time = IXGBE_LINK_UP_TIME; 118 119 return status; 120 } 121 122 /** 123 * ixgbe_set_mac_type - Sets MAC type 124 * @hw: pointer to the HW structure 125 * 126 * This function sets the mac type of the adapter based on the 127 * vendor ID and device ID stored in the hw structure. 128 **/ 129 s32 ixgbe_set_mac_type(struct ixgbe_hw *hw) 130 { 131 s32 ret_val = IXGBE_SUCCESS; 132 133 DEBUGFUNC("ixgbe_set_mac_type\n"); 134 135 if (hw->vendor_id != IXGBE_INTEL_VENDOR_ID) { 136 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 137 "Unsupported vendor id: %x", hw->vendor_id); 138 return IXGBE_ERR_DEVICE_NOT_SUPPORTED; 139 } 140 141 hw->mvals = ixgbe_mvals_base; 142 143 switch (hw->device_id) { 144 case IXGBE_DEV_ID_82598: 145 case IXGBE_DEV_ID_82598_BX: 146 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 147 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 148 case IXGBE_DEV_ID_82598AT: 149 case IXGBE_DEV_ID_82598AT2: 150 case IXGBE_DEV_ID_82598EB_CX4: 151 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 152 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 153 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 154 case IXGBE_DEV_ID_82598EB_XF_LR: 155 case IXGBE_DEV_ID_82598EB_SFP_LOM: 156 hw->mac.type = ixgbe_mac_82598EB; 157 break; 158 case IXGBE_DEV_ID_82599_KX4: 159 case IXGBE_DEV_ID_82599_KX4_MEZZ: 160 case IXGBE_DEV_ID_82599_XAUI_LOM: 161 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 162 case IXGBE_DEV_ID_82599_KR: 163 case IXGBE_DEV_ID_82599_SFP: 164 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 165 case IXGBE_DEV_ID_82599_SFP_FCOE: 166 case IXGBE_DEV_ID_82599_SFP_EM: 167 case IXGBE_DEV_ID_82599_SFP_SF2: 168 case IXGBE_DEV_ID_82599_SFP_SF_QP: 169 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 170 case IXGBE_DEV_ID_82599EN_SFP: 171 case IXGBE_DEV_ID_82599_CX4: 172 case IXGBE_DEV_ID_82599_BYPASS: 173 case IXGBE_DEV_ID_82599_T3_LOM: 174 hw->mac.type = ixgbe_mac_82599EB; 175 break; 176 case IXGBE_DEV_ID_82599_VF: 177 case IXGBE_DEV_ID_82599_VF_HV: 178 hw->mac.type = ixgbe_mac_82599_vf; 179 break; 180 case IXGBE_DEV_ID_X540_VF: 181 case IXGBE_DEV_ID_X540_VF_HV: 182 hw->mac.type = ixgbe_mac_X540_vf; 183 hw->mvals = ixgbe_mvals_X540; 184 break; 185 case IXGBE_DEV_ID_X540T: 186 case IXGBE_DEV_ID_X540T1: 187 case IXGBE_DEV_ID_X540_BYPASS: 188 hw->mac.type = ixgbe_mac_X540; 189 hw->mvals = ixgbe_mvals_X540; 190 break; 191 case IXGBE_DEV_ID_X550T: 192 case IXGBE_DEV_ID_X550T1: 193 hw->mac.type = ixgbe_mac_X550; 194 hw->mvals = ixgbe_mvals_X550; 195 break; 196 case IXGBE_DEV_ID_X550EM_X_KX4: 197 case IXGBE_DEV_ID_X550EM_X_KR: 198 case IXGBE_DEV_ID_X550EM_X_10G_T: 199 case IXGBE_DEV_ID_X550EM_X_1G_T: 200 case IXGBE_DEV_ID_X550EM_X_SFP: 201 hw->mac.type = ixgbe_mac_X550EM_x; 202 hw->mvals = ixgbe_mvals_X550EM_x; 203 break; 204 case IXGBE_DEV_ID_X550_VF: 205 case IXGBE_DEV_ID_X550_VF_HV: 206 hw->mac.type = ixgbe_mac_X550_vf; 207 hw->mvals = ixgbe_mvals_X550; 208 break; 209 case IXGBE_DEV_ID_X550EM_X_VF: 210 case IXGBE_DEV_ID_X550EM_X_VF_HV: 211 hw->mac.type = ixgbe_mac_X550EM_x_vf; 212 hw->mvals = ixgbe_mvals_X550EM_x; 213 break; 214 default: 215 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 216 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 217 "Unsupported device id: %x", 218 hw->device_id); 219 break; 220 } 221 222 DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n", 223 hw->mac.type, ret_val); 224 return ret_val; 225 } 226 227 /** 228 * ixgbe_init_hw - Initialize the hardware 229 * @hw: pointer to hardware structure 230 * 231 * Initialize the hardware by resetting and then starting the hardware 232 **/ 233 s32 ixgbe_init_hw(struct ixgbe_hw *hw) 234 { 235 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw), 236 IXGBE_NOT_IMPLEMENTED); 237 } 238 239 /** 240 * ixgbe_reset_hw - Performs a hardware reset 241 * @hw: pointer to hardware structure 242 * 243 * Resets the hardware by resetting the transmit and receive units, masks and 244 * clears all interrupts, performs a PHY reset, and performs a MAC reset 245 **/ 246 s32 ixgbe_reset_hw(struct ixgbe_hw *hw) 247 { 248 return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw), 249 IXGBE_NOT_IMPLEMENTED); 250 } 251 252 /** 253 * ixgbe_start_hw - Prepares hardware for Rx/Tx 254 * @hw: pointer to hardware structure 255 * 256 * Starts the hardware by filling the bus info structure and media type, 257 * clears all on chip counters, initializes receive address registers, 258 * multicast table, VLAN filter table, calls routine to setup link and 259 * flow control settings, and leaves transmit and receive units disabled 260 * and uninitialized. 261 **/ 262 s32 ixgbe_start_hw(struct ixgbe_hw *hw) 263 { 264 return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw), 265 IXGBE_NOT_IMPLEMENTED); 266 } 267 268 /** 269 * ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering, 270 * which is disabled by default in ixgbe_start_hw(); 271 * 272 * @hw: pointer to hardware structure 273 * 274 * Enable relaxed ordering; 275 **/ 276 void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw) 277 { 278 if (hw->mac.ops.enable_relaxed_ordering) 279 hw->mac.ops.enable_relaxed_ordering(hw); 280 } 281 282 /** 283 * ixgbe_clear_hw_cntrs - Clear hardware counters 284 * @hw: pointer to hardware structure 285 * 286 * Clears all hardware statistics counters by reading them from the hardware 287 * Statistics counters are clear on read. 288 **/ 289 s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw) 290 { 291 return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw), 292 IXGBE_NOT_IMPLEMENTED); 293 } 294 295 /** 296 * ixgbe_get_media_type - Get media type 297 * @hw: pointer to hardware structure 298 * 299 * Returns the media type (fiber, copper, backplane) 300 **/ 301 enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw) 302 { 303 return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw), 304 ixgbe_media_type_unknown); 305 } 306 307 /** 308 * ixgbe_get_mac_addr - Get MAC address 309 * @hw: pointer to hardware structure 310 * @mac_addr: Adapter MAC address 311 * 312 * Reads the adapter's MAC address from the first Receive Address Register 313 * (RAR0) A reset of the adapter must have been performed prior to calling 314 * this function in order for the MAC address to have been loaded from the 315 * EEPROM into RAR0 316 **/ 317 s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr) 318 { 319 return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr, 320 (hw, mac_addr), IXGBE_NOT_IMPLEMENTED); 321 } 322 323 /** 324 * ixgbe_get_san_mac_addr - Get SAN MAC address 325 * @hw: pointer to hardware structure 326 * @san_mac_addr: SAN MAC address 327 * 328 * Reads the SAN MAC address from the EEPROM, if it's available. This is 329 * per-port, so set_lan_id() must be called before reading the addresses. 330 **/ 331 s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 332 { 333 return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr, 334 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 335 } 336 337 /** 338 * ixgbe_set_san_mac_addr - Write a SAN MAC address 339 * @hw: pointer to hardware structure 340 * @san_mac_addr: SAN MAC address 341 * 342 * Writes A SAN MAC address to the EEPROM. 343 **/ 344 s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 345 { 346 return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr, 347 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 348 } 349 350 /** 351 * ixgbe_get_device_caps - Get additional device capabilities 352 * @hw: pointer to hardware structure 353 * @device_caps: the EEPROM word for device capabilities 354 * 355 * Reads the extra device capabilities from the EEPROM 356 **/ 357 s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps) 358 { 359 return ixgbe_call_func(hw, hw->mac.ops.get_device_caps, 360 (hw, device_caps), IXGBE_NOT_IMPLEMENTED); 361 } 362 363 /** 364 * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM 365 * @hw: pointer to hardware structure 366 * @wwnn_prefix: the alternative WWNN prefix 367 * @wwpn_prefix: the alternative WWPN prefix 368 * 369 * This function will read the EEPROM from the alternative SAN MAC address 370 * block to check the support for the alternative WWNN/WWPN prefix support. 371 **/ 372 s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix, 373 u16 *wwpn_prefix) 374 { 375 return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix, 376 (hw, wwnn_prefix, wwpn_prefix), 377 IXGBE_NOT_IMPLEMENTED); 378 } 379 380 /** 381 * ixgbe_get_fcoe_boot_status - Get FCOE boot status from EEPROM 382 * @hw: pointer to hardware structure 383 * @bs: the fcoe boot status 384 * 385 * This function will read the FCOE boot status from the iSCSI FCOE block 386 **/ 387 s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs) 388 { 389 return ixgbe_call_func(hw, hw->mac.ops.get_fcoe_boot_status, 390 (hw, bs), 391 IXGBE_NOT_IMPLEMENTED); 392 } 393 394 /** 395 * ixgbe_get_bus_info - Set PCI bus info 396 * @hw: pointer to hardware structure 397 * 398 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 399 **/ 400 s32 ixgbe_get_bus_info(struct ixgbe_hw *hw) 401 { 402 return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw), 403 IXGBE_NOT_IMPLEMENTED); 404 } 405 406 /** 407 * ixgbe_get_num_of_tx_queues - Get Tx queues 408 * @hw: pointer to hardware structure 409 * 410 * Returns the number of transmit queues for the given adapter. 411 **/ 412 u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw) 413 { 414 return hw->mac.max_tx_queues; 415 } 416 417 /** 418 * ixgbe_get_num_of_rx_queues - Get Rx queues 419 * @hw: pointer to hardware structure 420 * 421 * Returns the number of receive queues for the given adapter. 422 **/ 423 u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw) 424 { 425 return hw->mac.max_rx_queues; 426 } 427 428 /** 429 * ixgbe_stop_adapter - Disable Rx/Tx units 430 * @hw: pointer to hardware structure 431 * 432 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 433 * disables transmit and receive units. The adapter_stopped flag is used by 434 * the shared code and drivers to determine if the adapter is in a stopped 435 * state and should not touch the hardware. 436 **/ 437 s32 ixgbe_stop_adapter(struct ixgbe_hw *hw) 438 { 439 return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw), 440 IXGBE_NOT_IMPLEMENTED); 441 } 442 443 /** 444 * ixgbe_read_pba_string - Reads part number string from EEPROM 445 * @hw: pointer to hardware structure 446 * @pba_num: stores the part number string from the EEPROM 447 * @pba_num_size: part number string buffer length 448 * 449 * Reads the part number string from the EEPROM. 450 **/ 451 s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size) 452 { 453 return ixgbe_read_pba_string_generic(hw, pba_num, pba_num_size); 454 } 455 456 /** 457 * ixgbe_read_pba_num - Reads part number from EEPROM 458 * @hw: pointer to hardware structure 459 * @pba_num: stores the part number from the EEPROM 460 * 461 * Reads the part number from the EEPROM. 462 **/ 463 s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num) 464 { 465 return ixgbe_read_pba_num_generic(hw, pba_num); 466 } 467 468 /** 469 * ixgbe_identify_phy - Get PHY type 470 * @hw: pointer to hardware structure 471 * 472 * Determines the physical layer module found on the current adapter. 473 **/ 474 s32 ixgbe_identify_phy(struct ixgbe_hw *hw) 475 { 476 s32 status = IXGBE_SUCCESS; 477 478 if (hw->phy.type == ixgbe_phy_unknown) { 479 status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw), 480 IXGBE_NOT_IMPLEMENTED); 481 } 482 483 return status; 484 } 485 486 /** 487 * ixgbe_reset_phy - Perform a PHY reset 488 * @hw: pointer to hardware structure 489 **/ 490 s32 ixgbe_reset_phy(struct ixgbe_hw *hw) 491 { 492 s32 status = IXGBE_SUCCESS; 493 494 if (hw->phy.type == ixgbe_phy_unknown) { 495 if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS) 496 status = IXGBE_ERR_PHY; 497 } 498 499 if (status == IXGBE_SUCCESS) { 500 status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw), 501 IXGBE_NOT_IMPLEMENTED); 502 } 503 return status; 504 } 505 506 /** 507 * ixgbe_get_phy_firmware_version - 508 * @hw: pointer to hardware structure 509 * @firmware_version: pointer to firmware version 510 **/ 511 s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version) 512 { 513 s32 status = IXGBE_SUCCESS; 514 515 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version, 516 (hw, firmware_version), 517 IXGBE_NOT_IMPLEMENTED); 518 return status; 519 } 520 521 /** 522 * ixgbe_read_phy_reg - Read PHY register 523 * @hw: pointer to hardware structure 524 * @reg_addr: 32 bit address of PHY register to read 525 * @phy_data: Pointer to read data from PHY register 526 * 527 * Reads a value from a specified PHY register 528 **/ 529 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 530 u16 *phy_data) 531 { 532 if (hw->phy.id == 0) 533 ixgbe_identify_phy(hw); 534 535 return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr, 536 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 537 } 538 539 /** 540 * ixgbe_write_phy_reg - Write PHY register 541 * @hw: pointer to hardware structure 542 * @reg_addr: 32 bit PHY register to write 543 * @phy_data: Data to write to the PHY register 544 * 545 * Writes a value to specified PHY register 546 **/ 547 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 548 u16 phy_data) 549 { 550 if (hw->phy.id == 0) 551 ixgbe_identify_phy(hw); 552 553 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr, 554 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 555 } 556 557 /** 558 * ixgbe_setup_phy_link - Restart PHY autoneg 559 * @hw: pointer to hardware structure 560 * 561 * Restart autonegotiation and PHY and waits for completion. 562 **/ 563 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw) 564 { 565 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw), 566 IXGBE_NOT_IMPLEMENTED); 567 } 568 569 /** 570 * ixgbe_setup_internal_phy - Configure integrated PHY 571 * @hw: pointer to hardware structure 572 * 573 * Reconfigure the integrated PHY in order to enable talk to the external PHY. 574 * Returns success if not implemented, since nothing needs to be done in this 575 * case. 576 */ 577 s32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw) 578 { 579 return ixgbe_call_func(hw, hw->phy.ops.setup_internal_link, (hw), 580 IXGBE_SUCCESS); 581 } 582 583 /** 584 * ixgbe_check_phy_link - Determine link and speed status 585 * @hw: pointer to hardware structure 586 * 587 * Reads a PHY register to determine if link is up and the current speed for 588 * the PHY. 589 **/ 590 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 591 bool *link_up) 592 { 593 return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed, 594 link_up), IXGBE_NOT_IMPLEMENTED); 595 } 596 597 /** 598 * ixgbe_setup_phy_link_speed - Set auto advertise 599 * @hw: pointer to hardware structure 600 * @speed: new link speed 601 * 602 * Sets the auto advertised capabilities 603 **/ 604 s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed, 605 bool autoneg_wait_to_complete) 606 { 607 return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed, 608 autoneg_wait_to_complete), 609 IXGBE_NOT_IMPLEMENTED); 610 } 611 612 /** 613 * ixgbe_set_phy_power - Control the phy power state 614 * @hw: pointer to hardware structure 615 * @on: TRUE for on, FALSE for off 616 */ 617 s32 ixgbe_set_phy_power(struct ixgbe_hw *hw, bool on) 618 { 619 return ixgbe_call_func(hw, hw->phy.ops.set_phy_power, (hw, on), 620 IXGBE_NOT_IMPLEMENTED); 621 } 622 623 /** 624 * ixgbe_check_link - Get link and speed status 625 * @hw: pointer to hardware structure 626 * 627 * Reads the links register to determine if link is up and the current speed 628 **/ 629 s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 630 bool *link_up, bool link_up_wait_to_complete) 631 { 632 return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed, 633 link_up, link_up_wait_to_complete), 634 IXGBE_NOT_IMPLEMENTED); 635 } 636 637 /** 638 * ixgbe_disable_tx_laser - Disable Tx laser 639 * @hw: pointer to hardware structure 640 * 641 * If the driver needs to disable the laser on SFI optics. 642 **/ 643 void ixgbe_disable_tx_laser(struct ixgbe_hw *hw) 644 { 645 if (hw->mac.ops.disable_tx_laser) 646 hw->mac.ops.disable_tx_laser(hw); 647 } 648 649 /** 650 * ixgbe_enable_tx_laser - Enable Tx laser 651 * @hw: pointer to hardware structure 652 * 653 * If the driver needs to enable the laser on SFI optics. 654 **/ 655 void ixgbe_enable_tx_laser(struct ixgbe_hw *hw) 656 { 657 if (hw->mac.ops.enable_tx_laser) 658 hw->mac.ops.enable_tx_laser(hw); 659 } 660 661 /** 662 * ixgbe_flap_tx_laser - flap Tx laser to start autotry process 663 * @hw: pointer to hardware structure 664 * 665 * When the driver changes the link speeds that it can support then 666 * flap the tx laser to alert the link partner to start autotry 667 * process on its end. 668 **/ 669 void ixgbe_flap_tx_laser(struct ixgbe_hw *hw) 670 { 671 if (hw->mac.ops.flap_tx_laser) 672 hw->mac.ops.flap_tx_laser(hw); 673 } 674 675 /** 676 * ixgbe_setup_link - Set link speed 677 * @hw: pointer to hardware structure 678 * @speed: new link speed 679 * 680 * Configures link settings. Restarts the link. 681 * Performs autonegotiation if needed. 682 **/ 683 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 684 bool autoneg_wait_to_complete) 685 { 686 return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed, 687 autoneg_wait_to_complete), 688 IXGBE_NOT_IMPLEMENTED); 689 } 690 691 /** 692 * ixgbe_setup_mac_link - Set link speed 693 * @hw: pointer to hardware structure 694 * @speed: new link speed 695 * 696 * Configures link settings. Restarts the link. 697 * Performs autonegotiation if needed. 698 **/ 699 s32 ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 700 bool autoneg_wait_to_complete) 701 { 702 return ixgbe_call_func(hw, hw->mac.ops.setup_mac_link, (hw, speed, 703 autoneg_wait_to_complete), 704 IXGBE_NOT_IMPLEMENTED); 705 } 706 707 /** 708 * ixgbe_get_link_capabilities - Returns link capabilities 709 * @hw: pointer to hardware structure 710 * 711 * Determines the link capabilities of the current configuration. 712 **/ 713 s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 714 bool *autoneg) 715 { 716 return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw, 717 speed, autoneg), IXGBE_NOT_IMPLEMENTED); 718 } 719 720 /** 721 * ixgbe_led_on - Turn on LEDs 722 * @hw: pointer to hardware structure 723 * @index: led number to turn on 724 * 725 * Turns on the software controllable LEDs. 726 **/ 727 s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index) 728 { 729 return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index), 730 IXGBE_NOT_IMPLEMENTED); 731 } 732 733 /** 734 * ixgbe_led_off - Turn off LEDs 735 * @hw: pointer to hardware structure 736 * @index: led number to turn off 737 * 738 * Turns off the software controllable LEDs. 739 **/ 740 s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index) 741 { 742 return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index), 743 IXGBE_NOT_IMPLEMENTED); 744 } 745 746 /** 747 * ixgbe_blink_led_start - Blink LEDs 748 * @hw: pointer to hardware structure 749 * @index: led number to blink 750 * 751 * Blink LED based on index. 752 **/ 753 s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index) 754 { 755 return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index), 756 IXGBE_NOT_IMPLEMENTED); 757 } 758 759 /** 760 * ixgbe_blink_led_stop - Stop blinking LEDs 761 * @hw: pointer to hardware structure 762 * 763 * Stop blinking LED based on index. 764 **/ 765 s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index) 766 { 767 return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index), 768 IXGBE_NOT_IMPLEMENTED); 769 } 770 771 /** 772 * ixgbe_init_eeprom_params - Initialize EEPROM parameters 773 * @hw: pointer to hardware structure 774 * 775 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 776 * ixgbe_hw struct in order to set up EEPROM access. 777 **/ 778 s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw) 779 { 780 return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw), 781 IXGBE_NOT_IMPLEMENTED); 782 } 783 784 785 /** 786 * ixgbe_write_eeprom - Write word to EEPROM 787 * @hw: pointer to hardware structure 788 * @offset: offset within the EEPROM to be written to 789 * @data: 16 bit word to be written to the EEPROM 790 * 791 * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not 792 * called after this function, the EEPROM will most likely contain an 793 * invalid checksum. 794 **/ 795 s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data) 796 { 797 return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data), 798 IXGBE_NOT_IMPLEMENTED); 799 } 800 801 /** 802 * ixgbe_write_eeprom_buffer - Write word(s) to EEPROM 803 * @hw: pointer to hardware structure 804 * @offset: offset within the EEPROM to be written to 805 * @data: 16 bit word(s) to be written to the EEPROM 806 * @words: number of words 807 * 808 * Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not 809 * called after this function, the EEPROM will most likely contain an 810 * invalid checksum. 811 **/ 812 s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, u16 words, 813 u16 *data) 814 { 815 return ixgbe_call_func(hw, hw->eeprom.ops.write_buffer, 816 (hw, offset, words, data), 817 IXGBE_NOT_IMPLEMENTED); 818 } 819 820 /** 821 * ixgbe_read_eeprom - Read word from EEPROM 822 * @hw: pointer to hardware structure 823 * @offset: offset within the EEPROM to be read 824 * @data: read 16 bit value from EEPROM 825 * 826 * Reads 16 bit value from EEPROM 827 **/ 828 s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data) 829 { 830 return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data), 831 IXGBE_NOT_IMPLEMENTED); 832 } 833 834 /** 835 * ixgbe_read_eeprom_buffer - Read word(s) from EEPROM 836 * @hw: pointer to hardware structure 837 * @offset: offset within the EEPROM to be read 838 * @data: read 16 bit word(s) from EEPROM 839 * @words: number of words 840 * 841 * Reads 16 bit word(s) from EEPROM 842 **/ 843 s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, 844 u16 words, u16 *data) 845 { 846 return ixgbe_call_func(hw, hw->eeprom.ops.read_buffer, 847 (hw, offset, words, data), 848 IXGBE_NOT_IMPLEMENTED); 849 } 850 851 /** 852 * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum 853 * @hw: pointer to hardware structure 854 * @checksum_val: calculated checksum 855 * 856 * Performs checksum calculation and validates the EEPROM checksum 857 **/ 858 s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val) 859 { 860 return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum, 861 (hw, checksum_val), IXGBE_NOT_IMPLEMENTED); 862 } 863 864 /** 865 * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum 866 * @hw: pointer to hardware structure 867 **/ 868 s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw) 869 { 870 return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw), 871 IXGBE_NOT_IMPLEMENTED); 872 } 873 874 /** 875 * ixgbe_insert_mac_addr - Find a RAR for this mac address 876 * @hw: pointer to hardware structure 877 * @addr: Address to put into receive address register 878 * @vmdq: VMDq pool to assign 879 * 880 * Puts an ethernet address into a receive address register, or 881 * finds the rar that it is already in; adds to the pool list 882 **/ 883 s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 884 { 885 return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr, 886 (hw, addr, vmdq), 887 IXGBE_NOT_IMPLEMENTED); 888 } 889 890 /** 891 * ixgbe_set_rar - Set Rx address register 892 * @hw: pointer to hardware structure 893 * @index: Receive address register to write 894 * @addr: Address to put into receive address register 895 * @vmdq: VMDq "set" 896 * @enable_addr: set flag that address is active 897 * 898 * Puts an ethernet address into a receive address register. 899 **/ 900 s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 901 u32 enable_addr) 902 { 903 return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq, 904 enable_addr), IXGBE_NOT_IMPLEMENTED); 905 } 906 907 /** 908 * ixgbe_clear_rar - Clear Rx address register 909 * @hw: pointer to hardware structure 910 * @index: Receive address register to write 911 * 912 * Puts an ethernet address into a receive address register. 913 **/ 914 s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index) 915 { 916 return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index), 917 IXGBE_NOT_IMPLEMENTED); 918 } 919 920 /** 921 * ixgbe_set_vmdq - Associate a VMDq index with a receive address 922 * @hw: pointer to hardware structure 923 * @rar: receive address register index to associate with VMDq index 924 * @vmdq: VMDq set or pool index 925 **/ 926 s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 927 { 928 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq), 929 IXGBE_NOT_IMPLEMENTED); 930 931 } 932 933 /** 934 * ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address 935 * @hw: pointer to hardware structure 936 * @vmdq: VMDq default pool index 937 **/ 938 s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq) 939 { 940 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq_san_mac, 941 (hw, vmdq), IXGBE_NOT_IMPLEMENTED); 942 } 943 944 /** 945 * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address 946 * @hw: pointer to hardware structure 947 * @rar: receive address register index to disassociate with VMDq index 948 * @vmdq: VMDq set or pool index 949 **/ 950 s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 951 { 952 return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq), 953 IXGBE_NOT_IMPLEMENTED); 954 } 955 956 /** 957 * ixgbe_init_rx_addrs - Initializes receive address filters. 958 * @hw: pointer to hardware structure 959 * 960 * Places the MAC address in receive address register 0 and clears the rest 961 * of the receive address registers. Clears the multicast table. Assumes 962 * the receiver is in reset when the routine is called. 963 **/ 964 s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw) 965 { 966 return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw), 967 IXGBE_NOT_IMPLEMENTED); 968 } 969 970 /** 971 * ixgbe_get_num_rx_addrs - Returns the number of RAR entries. 972 * @hw: pointer to hardware structure 973 **/ 974 u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw) 975 { 976 return hw->mac.num_rar_entries; 977 } 978 979 /** 980 * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses 981 * @hw: pointer to hardware structure 982 * @addr_list: the list of new multicast addresses 983 * @addr_count: number of addresses 984 * @func: iterator function to walk the multicast address list 985 * 986 * The given list replaces any existing list. Clears the secondary addrs from 987 * receive address registers. Uses unused receive address registers for the 988 * first secondary addresses, and falls back to promiscuous mode as needed. 989 **/ 990 s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, 991 u32 addr_count, ixgbe_mc_addr_itr func) 992 { 993 return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw, 994 addr_list, addr_count, func), 995 IXGBE_NOT_IMPLEMENTED); 996 } 997 998 /** 999 * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses 1000 * @hw: pointer to hardware structure 1001 * @mc_addr_list: the list of new multicast addresses 1002 * @mc_addr_count: number of addresses 1003 * @func: iterator function to walk the multicast address list 1004 * 1005 * The given list replaces any existing list. Clears the MC addrs from receive 1006 * address registers and the multicast table. Uses unused receive address 1007 * registers for the first multicast addresses, and hashes the rest into the 1008 * multicast table. 1009 **/ 1010 s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, 1011 u32 mc_addr_count, ixgbe_mc_addr_itr func, 1012 bool clear) 1013 { 1014 return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw, 1015 mc_addr_list, mc_addr_count, func, clear), 1016 IXGBE_NOT_IMPLEMENTED); 1017 } 1018 1019 /** 1020 * ixgbe_enable_mc - Enable multicast address in RAR 1021 * @hw: pointer to hardware structure 1022 * 1023 * Enables multicast address in RAR and the use of the multicast hash table. 1024 **/ 1025 s32 ixgbe_enable_mc(struct ixgbe_hw *hw) 1026 { 1027 return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw), 1028 IXGBE_NOT_IMPLEMENTED); 1029 } 1030 1031 /** 1032 * ixgbe_disable_mc - Disable multicast address in RAR 1033 * @hw: pointer to hardware structure 1034 * 1035 * Disables multicast address in RAR and the use of the multicast hash table. 1036 **/ 1037 s32 ixgbe_disable_mc(struct ixgbe_hw *hw) 1038 { 1039 return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw), 1040 IXGBE_NOT_IMPLEMENTED); 1041 } 1042 1043 /** 1044 * ixgbe_clear_vfta - Clear VLAN filter table 1045 * @hw: pointer to hardware structure 1046 * 1047 * Clears the VLAN filer table, and the VMDq index associated with the filter 1048 **/ 1049 s32 ixgbe_clear_vfta(struct ixgbe_hw *hw) 1050 { 1051 return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw), 1052 IXGBE_NOT_IMPLEMENTED); 1053 } 1054 1055 /** 1056 * ixgbe_set_vfta - Set VLAN filter table 1057 * @hw: pointer to hardware structure 1058 * @vlan: VLAN id to write to VLAN filter 1059 * @vind: VMDq output index that maps queue to VLAN id in VFTA 1060 * @vlan_on: boolean flag to turn on/off VLAN in VFTA 1061 * 1062 * Turn on/off specified VLAN in the VLAN filter table. 1063 **/ 1064 s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on) 1065 { 1066 return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind, 1067 vlan_on), IXGBE_NOT_IMPLEMENTED); 1068 } 1069 1070 /** 1071 * ixgbe_set_vlvf - Set VLAN Pool Filter 1072 * @hw: pointer to hardware structure 1073 * @vlan: VLAN id to write to VLAN filter 1074 * @vind: VMDq output index that maps queue to VLAN id in VFVFB 1075 * @vlan_on: boolean flag to turn on/off VLAN in VFVF 1076 * @vfta_changed: pointer to boolean flag which indicates whether VFTA 1077 * should be changed 1078 * 1079 * Turn on/off specified bit in VLVF table. 1080 **/ 1081 s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, 1082 bool *vfta_changed) 1083 { 1084 return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind, 1085 vlan_on, vfta_changed), IXGBE_NOT_IMPLEMENTED); 1086 } 1087 1088 /** 1089 * ixgbe_fc_enable - Enable flow control 1090 * @hw: pointer to hardware structure 1091 * 1092 * Configures the flow control settings based on SW configuration. 1093 **/ 1094 s32 ixgbe_fc_enable(struct ixgbe_hw *hw) 1095 { 1096 return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw), 1097 IXGBE_NOT_IMPLEMENTED); 1098 } 1099 1100 /** 1101 * ixgbe_setup_fc - Set up flow control 1102 * @hw: pointer to hardware structure 1103 * 1104 * Called at init time to set up flow control. 1105 **/ 1106 s32 ixgbe_setup_fc(struct ixgbe_hw *hw) 1107 { 1108 return ixgbe_call_func(hw, hw->mac.ops.setup_fc, (hw), 1109 IXGBE_NOT_IMPLEMENTED); 1110 } 1111 1112 /** 1113 * ixgbe_set_fw_drv_ver - Try to send the driver version number FW 1114 * @hw: pointer to hardware structure 1115 * @maj: driver major number to be sent to firmware 1116 * @minr: driver minor number to be sent to firmware 1117 * @build: driver build number to be sent to firmware 1118 * @ver: driver version number to be sent to firmware 1119 **/ 1120 s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 minr, u8 build, 1121 u8 ver) 1122 { 1123 return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, minr, 1124 build, ver), IXGBE_NOT_IMPLEMENTED); 1125 } 1126 1127 1128 1129 /** 1130 * ixgbe_dmac_config - Configure DMA Coalescing registers. 1131 * @hw: pointer to hardware structure 1132 * 1133 * Configure DMA coalescing. If enabling dmac, dmac is activated. 1134 * When disabling dmac, dmac enable dmac bit is cleared. 1135 **/ 1136 s32 ixgbe_dmac_config(struct ixgbe_hw *hw) 1137 { 1138 return ixgbe_call_func(hw, hw->mac.ops.dmac_config, (hw), 1139 IXGBE_NOT_IMPLEMENTED); 1140 } 1141 1142 /** 1143 * ixgbe_dmac_update_tcs - Configure DMA Coalescing registers. 1144 * @hw: pointer to hardware structure 1145 * 1146 * Disables dmac, updates per TC settings, and then enable dmac. 1147 **/ 1148 s32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw) 1149 { 1150 return ixgbe_call_func(hw, hw->mac.ops.dmac_update_tcs, (hw), 1151 IXGBE_NOT_IMPLEMENTED); 1152 } 1153 1154 /** 1155 * ixgbe_dmac_config_tcs - Configure DMA Coalescing registers. 1156 * @hw: pointer to hardware structure 1157 * 1158 * Configure DMA coalescing threshold per TC and set high priority bit for 1159 * FCOE TC. The dmac enable bit must be cleared before configuring. 1160 **/ 1161 s32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw) 1162 { 1163 return ixgbe_call_func(hw, hw->mac.ops.dmac_config_tcs, (hw), 1164 IXGBE_NOT_IMPLEMENTED); 1165 } 1166 1167 /** 1168 * ixgbe_setup_eee - Enable/disable EEE support 1169 * @hw: pointer to the HW structure 1170 * @enable_eee: boolean flag to enable EEE 1171 * 1172 * Enable/disable EEE based on enable_ee flag. 1173 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C 1174 * are modified. 1175 * 1176 **/ 1177 s32 ixgbe_setup_eee(struct ixgbe_hw *hw, bool enable_eee) 1178 { 1179 return ixgbe_call_func(hw, hw->mac.ops.setup_eee, (hw, enable_eee), 1180 IXGBE_NOT_IMPLEMENTED); 1181 } 1182 1183 /** 1184 * ixgbe_set_source_address_pruning - Enable/Disable source address pruning 1185 * @hw: pointer to hardware structure 1186 * @enbale: enable or disable source address pruning 1187 * @pool: Rx pool - Rx pool to toggle source address pruning 1188 **/ 1189 void ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable, 1190 unsigned int pool) 1191 { 1192 if (hw->mac.ops.set_source_address_pruning) 1193 hw->mac.ops.set_source_address_pruning(hw, enable, pool); 1194 } 1195 1196 /** 1197 * ixgbe_set_ethertype_anti_spoofing - Enable/Disable Ethertype anti-spoofing 1198 * @hw: pointer to hardware structure 1199 * @enable: enable or disable switch for Ethertype anti-spoofing 1200 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 1201 * 1202 **/ 1203 void ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 1204 { 1205 if (hw->mac.ops.set_ethertype_anti_spoofing) 1206 hw->mac.ops.set_ethertype_anti_spoofing(hw, enable, vf); 1207 } 1208 1209 /** 1210 * ixgbe_read_iosf_sb_reg - Read 32 bit PHY register 1211 * @hw: pointer to hardware structure 1212 * @reg_addr: 32 bit address of PHY register to read 1213 * @device_type: type of device you want to communicate with 1214 * @phy_data: Pointer to read data from PHY register 1215 * 1216 * Reads a value from a specified PHY register 1217 **/ 1218 s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1219 u32 device_type, u32 *phy_data) 1220 { 1221 return ixgbe_call_func(hw, hw->mac.ops.read_iosf_sb_reg, (hw, reg_addr, 1222 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1223 } 1224 1225 /** 1226 * ixgbe_write_iosf_sb_reg - Write 32 bit register through IOSF Sideband 1227 * @hw: pointer to hardware structure 1228 * @reg_addr: 32 bit PHY register to write 1229 * @device_type: type of device you want to communicate with 1230 * @phy_data: Data to write to the PHY register 1231 * 1232 * Writes a value to specified PHY register 1233 **/ 1234 s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1235 u32 device_type, u32 phy_data) 1236 { 1237 return ixgbe_call_func(hw, hw->mac.ops.write_iosf_sb_reg, (hw, reg_addr, 1238 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1239 } 1240 1241 /** 1242 * ixgbe_disable_mdd - Disable malicious driver detection 1243 * @hw: pointer to hardware structure 1244 * 1245 **/ 1246 void ixgbe_disable_mdd(struct ixgbe_hw *hw) 1247 { 1248 if (hw->mac.ops.disable_mdd) 1249 hw->mac.ops.disable_mdd(hw); 1250 } 1251 1252 /** 1253 * ixgbe_enable_mdd - Enable malicious driver detection 1254 * @hw: pointer to hardware structure 1255 * 1256 **/ 1257 void ixgbe_enable_mdd(struct ixgbe_hw *hw) 1258 { 1259 if (hw->mac.ops.enable_mdd) 1260 hw->mac.ops.enable_mdd(hw); 1261 } 1262 1263 /** 1264 * ixgbe_mdd_event - Handle malicious driver detection event 1265 * @hw: pointer to hardware structure 1266 * @vf_bitmap: vf bitmap of malicious vfs 1267 * 1268 **/ 1269 void ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap) 1270 { 1271 if (hw->mac.ops.mdd_event) 1272 hw->mac.ops.mdd_event(hw, vf_bitmap); 1273 } 1274 1275 /** 1276 * ixgbe_restore_mdd_vf - Restore VF that was disabled during malicious driver 1277 * detection event 1278 * @hw: pointer to hardware structure 1279 * @vf: vf index 1280 * 1281 **/ 1282 void ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf) 1283 { 1284 if (hw->mac.ops.restore_mdd_vf) 1285 hw->mac.ops.restore_mdd_vf(hw, vf); 1286 } 1287 1288 /** 1289 * ixgbe_enter_lplu - Transition to low power states 1290 * @hw: pointer to hardware structure 1291 * 1292 * Configures Low Power Link Up on transition to low power states 1293 * (from D0 to non-D0). 1294 **/ 1295 s32 ixgbe_enter_lplu(struct ixgbe_hw *hw) 1296 { 1297 return ixgbe_call_func(hw, hw->phy.ops.enter_lplu, (hw), 1298 IXGBE_NOT_IMPLEMENTED); 1299 } 1300 1301 /** 1302 * ixgbe_handle_lasi - Handle external Base T PHY interrupt 1303 * @hw: pointer to hardware structure 1304 * 1305 * Handle external Base T PHY interrupt. If high temperature 1306 * failure alarm then return error, else if link status change 1307 * then setup internal/external PHY link 1308 * 1309 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 1310 * failure alarm, else return PHY access status. 1311 */ 1312 s32 ixgbe_handle_lasi(struct ixgbe_hw *hw) 1313 { 1314 return ixgbe_call_func(hw, hw->phy.ops.handle_lasi, (hw), 1315 IXGBE_NOT_IMPLEMENTED); 1316 } 1317 1318 /** 1319 * ixgbe_read_analog_reg8 - Reads 8 bit analog register 1320 * @hw: pointer to hardware structure 1321 * @reg: analog register to read 1322 * @val: read value 1323 * 1324 * Performs write operation to analog register specified. 1325 **/ 1326 s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val) 1327 { 1328 return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg, 1329 val), IXGBE_NOT_IMPLEMENTED); 1330 } 1331 1332 /** 1333 * ixgbe_write_analog_reg8 - Writes 8 bit analog register 1334 * @hw: pointer to hardware structure 1335 * @reg: analog register to write 1336 * @val: value to write 1337 * 1338 * Performs write operation to Atlas analog register specified. 1339 **/ 1340 s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val) 1341 { 1342 return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg, 1343 val), IXGBE_NOT_IMPLEMENTED); 1344 } 1345 1346 /** 1347 * ixgbe_init_uta_tables - Initializes Unicast Table Arrays. 1348 * @hw: pointer to hardware structure 1349 * 1350 * Initializes the Unicast Table Arrays to zero on device load. This 1351 * is part of the Rx init addr execution path. 1352 **/ 1353 s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw) 1354 { 1355 return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw), 1356 IXGBE_NOT_IMPLEMENTED); 1357 } 1358 1359 /** 1360 * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address 1361 * @hw: pointer to hardware structure 1362 * @byte_offset: byte offset to read 1363 * @dev_addr: I2C bus address to read from 1364 * @data: value read 1365 * 1366 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1367 **/ 1368 s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1369 u8 *data) 1370 { 1371 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset, 1372 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1373 } 1374 1375 /** 1376 * ixgbe_read_i2c_byte_unlocked - Reads 8 bit word via I2C from device address 1377 * @hw: pointer to hardware structure 1378 * @byte_offset: byte offset to read 1379 * @dev_addr: I2C bus address to read from 1380 * @data: value read 1381 * 1382 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1383 **/ 1384 s32 ixgbe_read_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1385 u8 dev_addr, u8 *data) 1386 { 1387 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte_unlocked, 1388 (hw, byte_offset, dev_addr, data), 1389 IXGBE_NOT_IMPLEMENTED); 1390 } 1391 1392 /** 1393 * ixgbe_read_i2c_combined - Perform I2C read combined operation 1394 * @hw: pointer to the hardware structure 1395 * @addr: I2C bus address to read from 1396 * @reg: I2C device register to read from 1397 * @val: pointer to location to receive read value 1398 * 1399 * Returns an error code on error. 1400 */ 1401 s32 ixgbe_read_i2c_combined(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) 1402 { 1403 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_combined, (hw, addr, 1404 reg, val), IXGBE_NOT_IMPLEMENTED); 1405 } 1406 1407 /** 1408 * ixgbe_read_i2c_combined_unlocked - Perform I2C read combined operation 1409 * @hw: pointer to the hardware structure 1410 * @addr: I2C bus address to read from 1411 * @reg: I2C device register to read from 1412 * @val: pointer to location to receive read value 1413 * 1414 * Returns an error code on error. 1415 **/ 1416 s32 ixgbe_read_i2c_combined_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, 1417 u16 *val) 1418 { 1419 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_combined_unlocked, 1420 (hw, addr, reg, val), 1421 IXGBE_NOT_IMPLEMENTED); 1422 } 1423 1424 /** 1425 * ixgbe_write_i2c_byte - Writes 8 bit word over I2C 1426 * @hw: pointer to hardware structure 1427 * @byte_offset: byte offset to write 1428 * @dev_addr: I2C bus address to write to 1429 * @data: value to write 1430 * 1431 * Performs byte write operation to SFP module's EEPROM over I2C interface 1432 * at a specified device address. 1433 **/ 1434 s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1435 u8 data) 1436 { 1437 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset, 1438 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1439 } 1440 1441 /** 1442 * ixgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C 1443 * @hw: pointer to hardware structure 1444 * @byte_offset: byte offset to write 1445 * @dev_addr: I2C bus address to write to 1446 * @data: value to write 1447 * 1448 * Performs byte write operation to SFP module's EEPROM over I2C interface 1449 * at a specified device address. 1450 **/ 1451 s32 ixgbe_write_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1452 u8 dev_addr, u8 data) 1453 { 1454 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte_unlocked, 1455 (hw, byte_offset, dev_addr, data), 1456 IXGBE_NOT_IMPLEMENTED); 1457 } 1458 1459 /** 1460 * ixgbe_write_i2c_combined - Perform I2C write combined operation 1461 * @hw: pointer to the hardware structure 1462 * @addr: I2C bus address to write to 1463 * @reg: I2C device register to write to 1464 * @val: value to write 1465 * 1466 * Returns an error code on error. 1467 */ 1468 s32 ixgbe_write_i2c_combined(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) 1469 { 1470 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_combined, (hw, addr, 1471 reg, val), IXGBE_NOT_IMPLEMENTED); 1472 } 1473 1474 /** 1475 * ixgbe_write_i2c_combined_unlocked - Perform I2C write combined operation 1476 * @hw: pointer to the hardware structure 1477 * @addr: I2C bus address to write to 1478 * @reg: I2C device register to write to 1479 * @val: value to write 1480 * 1481 * Returns an error code on error. 1482 **/ 1483 s32 ixgbe_write_i2c_combined_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, 1484 u16 val) 1485 { 1486 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_combined_unlocked, 1487 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1488 } 1489 1490 /** 1491 * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface 1492 * @hw: pointer to hardware structure 1493 * @byte_offset: EEPROM byte offset to write 1494 * @eeprom_data: value to write 1495 * 1496 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1497 **/ 1498 s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, 1499 u8 byte_offset, u8 eeprom_data) 1500 { 1501 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom, 1502 (hw, byte_offset, eeprom_data), 1503 IXGBE_NOT_IMPLEMENTED); 1504 } 1505 1506 /** 1507 * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface 1508 * @hw: pointer to hardware structure 1509 * @byte_offset: EEPROM byte offset to read 1510 * @eeprom_data: value read 1511 * 1512 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1513 **/ 1514 s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data) 1515 { 1516 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom, 1517 (hw, byte_offset, eeprom_data), 1518 IXGBE_NOT_IMPLEMENTED); 1519 } 1520 1521 /** 1522 * ixgbe_get_supported_physical_layer - Returns physical layer type 1523 * @hw: pointer to hardware structure 1524 * 1525 * Determines physical layer capabilities of the current configuration. 1526 **/ 1527 u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw) 1528 { 1529 return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer, 1530 (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN); 1531 } 1532 1533 /** 1534 * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics 1535 * @hw: pointer to hardware structure 1536 * @regval: bitfield to write to the Rx DMA register 1537 * 1538 * Enables the Rx DMA unit of the device. 1539 **/ 1540 s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval) 1541 { 1542 return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma, 1543 (hw, regval), IXGBE_NOT_IMPLEMENTED); 1544 } 1545 1546 /** 1547 * ixgbe_disable_sec_rx_path - Stops the receive data path 1548 * @hw: pointer to hardware structure 1549 * 1550 * Stops the receive data path. 1551 **/ 1552 s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw) 1553 { 1554 return ixgbe_call_func(hw, hw->mac.ops.disable_sec_rx_path, 1555 (hw), IXGBE_NOT_IMPLEMENTED); 1556 } 1557 1558 /** 1559 * ixgbe_enable_sec_rx_path - Enables the receive data path 1560 * @hw: pointer to hardware structure 1561 * 1562 * Enables the receive data path. 1563 **/ 1564 s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw) 1565 { 1566 return ixgbe_call_func(hw, hw->mac.ops.enable_sec_rx_path, 1567 (hw), IXGBE_NOT_IMPLEMENTED); 1568 } 1569 1570 /** 1571 * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore 1572 * @hw: pointer to hardware structure 1573 * @mask: Mask to specify which semaphore to acquire 1574 * 1575 * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified 1576 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1577 **/ 1578 s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1579 { 1580 return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync, 1581 (hw, mask), IXGBE_NOT_IMPLEMENTED); 1582 } 1583 1584 /** 1585 * ixgbe_release_swfw_semaphore - Release SWFW semaphore 1586 * @hw: pointer to hardware structure 1587 * @mask: Mask to specify which semaphore to release 1588 * 1589 * Releases the SWFW semaphore through SW_FW_SYNC register for the specified 1590 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1591 **/ 1592 void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1593 { 1594 if (hw->mac.ops.release_swfw_sync) 1595 hw->mac.ops.release_swfw_sync(hw, mask); 1596 } 1597 1598 1599 void ixgbe_disable_rx(struct ixgbe_hw *hw) 1600 { 1601 if (hw->mac.ops.disable_rx) 1602 hw->mac.ops.disable_rx(hw); 1603 } 1604 1605 void ixgbe_enable_rx(struct ixgbe_hw *hw) 1606 { 1607 if (hw->mac.ops.enable_rx) 1608 hw->mac.ops.enable_rx(hw); 1609 } 1610 1611 /** 1612 * ixgbe_set_rate_select_speed - Set module link speed 1613 * @hw: pointer to hardware structure 1614 * @speed: link speed to set 1615 * 1616 * Set module link speed via the rate select. 1617 */ 1618 void ixgbe_set_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed) 1619 { 1620 if (hw->mac.ops.set_rate_select_speed) 1621 hw->mac.ops.set_rate_select_speed(hw, speed); 1622 } 1623