1 /* $NetBSD: ixgbe_api.c,v 1.21 2018/06/11 10:34:18 msaitoh Exp $ */ 2 3 /****************************************************************************** 4 SPDX-License-Identifier: BSD-3-Clause 5 6 Copyright (c) 2001-2017, Intel Corporation 7 All rights reserved. 8 9 Redistribution and use in source and binary forms, with or without 10 modification, are permitted provided that the following conditions are met: 11 12 1. Redistributions of source code must retain the above copyright notice, 13 this list of conditions and the following disclaimer. 14 15 2. Redistributions in binary form must reproduce the above copyright 16 notice, this list of conditions and the following disclaimer in the 17 documentation and/or other materials provided with the distribution. 18 19 3. Neither the name of the Intel Corporation nor the names of its 20 contributors may be used to endorse or promote products derived from 21 this software without specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 27 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 POSSIBILITY OF SUCH DAMAGE. 34 35 ******************************************************************************/ 36 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_api.c 331224 2018-03-19 20:55:05Z erj $*/ 37 38 #include "ixgbe_api.h" 39 #include "ixgbe_common.h" 40 41 #define IXGBE_EMPTY_PARAM 42 43 static const u32 ixgbe_mvals_base[IXGBE_MVALS_IDX_LIMIT] = { 44 IXGBE_MVALS_INIT(IXGBE_EMPTY_PARAM) 45 }; 46 47 static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = { 48 IXGBE_MVALS_INIT(_X540) 49 }; 50 51 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = { 52 IXGBE_MVALS_INIT(_X550) 53 }; 54 55 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = { 56 IXGBE_MVALS_INIT(_X550EM_x) 57 }; 58 59 static const u32 ixgbe_mvals_X550EM_a[IXGBE_MVALS_IDX_LIMIT] = { 60 IXGBE_MVALS_INIT(_X550EM_a) 61 }; 62 63 /** 64 * ixgbe_dcb_get_rtrup2tc - read rtrup2tc reg 65 * @hw: pointer to hardware structure 66 * @map: pointer to u8 arr for returning map 67 * 68 * Read the rtrup2tc HW register and resolve its content into map 69 **/ 70 void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map) 71 { 72 if (hw->mac.ops.get_rtrup2tc) 73 hw->mac.ops.get_rtrup2tc(hw, map); 74 } 75 76 /** 77 * ixgbe_init_shared_code - Initialize the shared code 78 * @hw: pointer to hardware structure 79 * 80 * This will assign function pointers and assign the MAC type and PHY code. 81 * Does not touch the hardware. This function must be called prior to any 82 * other function in the shared code. The ixgbe_hw structure should be 83 * memset to 0 prior to calling this function. The following fields in 84 * hw structure should be filled in prior to calling this function: 85 * back, device_id, vendor_id, subsystem_device_id, 86 * subsystem_vendor_id, and revision_id 87 **/ 88 s32 ixgbe_init_shared_code(struct ixgbe_hw *hw) 89 { 90 s32 status; 91 92 DEBUGFUNC("ixgbe_init_shared_code"); 93 94 /* 95 * Set the mac type 96 */ 97 ixgbe_set_mac_type(hw); 98 99 switch (hw->mac.type) { 100 case ixgbe_mac_82598EB: 101 status = ixgbe_init_ops_82598(hw); 102 break; 103 case ixgbe_mac_82599EB: 104 status = ixgbe_init_ops_82599(hw); 105 break; 106 case ixgbe_mac_X540: 107 status = ixgbe_init_ops_X540(hw); 108 break; 109 case ixgbe_mac_X550: 110 status = ixgbe_init_ops_X550(hw); 111 break; 112 case ixgbe_mac_X550EM_x: 113 status = ixgbe_init_ops_X550EM_x(hw); 114 break; 115 case ixgbe_mac_X550EM_a: 116 status = ixgbe_init_ops_X550EM_a(hw); 117 break; 118 default: 119 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 120 break; 121 } 122 hw->mac.max_link_up_time = IXGBE_LINK_UP_TIME; 123 124 return status; 125 } 126 127 /** 128 * ixgbe_set_mac_type - Sets MAC type 129 * @hw: pointer to the HW structure 130 * 131 * This function sets the mac type of the adapter based on the 132 * vendor ID and device ID stored in the hw structure. 133 **/ 134 s32 ixgbe_set_mac_type(struct ixgbe_hw *hw) 135 { 136 s32 ret_val = IXGBE_SUCCESS; 137 138 DEBUGFUNC("ixgbe_set_mac_type\n"); 139 140 if (hw->vendor_id != IXGBE_INTEL_VENDOR_ID) { 141 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 142 "Unsupported vendor id: %x", hw->vendor_id); 143 return IXGBE_ERR_DEVICE_NOT_SUPPORTED; 144 } 145 146 hw->mvals = ixgbe_mvals_base; 147 148 switch (hw->device_id) { 149 case IXGBE_DEV_ID_82598: 150 case IXGBE_DEV_ID_82598_BX: 151 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 152 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 153 case IXGBE_DEV_ID_82598AT: 154 case IXGBE_DEV_ID_82598AT2: 155 case IXGBE_DEV_ID_82598EB_CX4: 156 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 157 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 158 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 159 case IXGBE_DEV_ID_82598EB_XF_LR: 160 case IXGBE_DEV_ID_82598EB_SFP_LOM: 161 hw->mac.type = ixgbe_mac_82598EB; 162 break; 163 case IXGBE_DEV_ID_82599_KX4: 164 case IXGBE_DEV_ID_82599_KX4_MEZZ: 165 case IXGBE_DEV_ID_82599_XAUI_LOM: 166 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 167 case IXGBE_DEV_ID_82599_KR: 168 case IXGBE_DEV_ID_82599_SFP: 169 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 170 case IXGBE_DEV_ID_82599_SFP_FCOE: 171 case IXGBE_DEV_ID_82599_SFP_EM: 172 case IXGBE_DEV_ID_82599_SFP_SF2: 173 case IXGBE_DEV_ID_82599_SFP_SF_QP: 174 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 175 case IXGBE_DEV_ID_82599EN_SFP: 176 case IXGBE_DEV_ID_82599_LS: 177 case IXGBE_DEV_ID_82599_CX4: 178 case IXGBE_DEV_ID_82599_BYPASS: 179 case IXGBE_DEV_ID_82599_T3_LOM: 180 hw->mac.type = ixgbe_mac_82599EB; 181 break; 182 case IXGBE_DEV_ID_X540T: 183 case IXGBE_DEV_ID_X540T1: 184 case IXGBE_DEV_ID_X540_BYPASS: 185 hw->mac.type = ixgbe_mac_X540; 186 hw->mvals = ixgbe_mvals_X540; 187 break; 188 case IXGBE_DEV_ID_X550T: 189 case IXGBE_DEV_ID_X550T1: 190 hw->mac.type = ixgbe_mac_X550; 191 hw->mvals = ixgbe_mvals_X550; 192 break; 193 case IXGBE_DEV_ID_X550EM_X_KX4: 194 case IXGBE_DEV_ID_X550EM_X_KR: 195 case IXGBE_DEV_ID_X550EM_X_10G_T: 196 case IXGBE_DEV_ID_X550EM_X_1G_T: 197 case IXGBE_DEV_ID_X550EM_X_SFP: 198 case IXGBE_DEV_ID_X550EM_X_XFI: 199 hw->mac.type = ixgbe_mac_X550EM_x; 200 hw->mvals = ixgbe_mvals_X550EM_x; 201 break; 202 case IXGBE_DEV_ID_X550EM_A_KR: 203 case IXGBE_DEV_ID_X550EM_A_KR_L: 204 case IXGBE_DEV_ID_X550EM_A_SFP_N: 205 case IXGBE_DEV_ID_X550EM_A_SGMII: 206 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 207 case IXGBE_DEV_ID_X550EM_A_1G_T: 208 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 209 case IXGBE_DEV_ID_X550EM_A_10G_T: 210 case IXGBE_DEV_ID_X550EM_A_QSFP: 211 case IXGBE_DEV_ID_X550EM_A_QSFP_N: 212 case IXGBE_DEV_ID_X550EM_A_SFP: 213 hw->mac.type = ixgbe_mac_X550EM_a; 214 hw->mvals = ixgbe_mvals_X550EM_a; 215 break; 216 default: 217 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 218 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 219 "Unsupported device id: %x", 220 hw->device_id); 221 break; 222 } 223 224 DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n", 225 hw->mac.type, ret_val); 226 return ret_val; 227 } 228 229 /** 230 * ixgbe_init_hw - Initialize the hardware 231 * @hw: pointer to hardware structure 232 * 233 * Initialize the hardware by resetting and then starting the hardware 234 **/ 235 s32 ixgbe_init_hw(struct ixgbe_hw *hw) 236 { 237 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw), 238 IXGBE_NOT_IMPLEMENTED); 239 } 240 241 /** 242 * ixgbe_reset_hw - Performs a hardware reset 243 * @hw: pointer to hardware structure 244 * 245 * Resets the hardware by resetting the transmit and receive units, masks and 246 * clears all interrupts, performs a PHY reset, and performs a MAC reset 247 **/ 248 s32 ixgbe_reset_hw(struct ixgbe_hw *hw) 249 { 250 return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw), 251 IXGBE_NOT_IMPLEMENTED); 252 } 253 254 /** 255 * ixgbe_start_hw - Prepares hardware for Rx/Tx 256 * @hw: pointer to hardware structure 257 * 258 * Starts the hardware by filling the bus info structure and media type, 259 * clears all on chip counters, initializes receive address registers, 260 * multicast table, VLAN filter table, calls routine to setup link and 261 * flow control settings, and leaves transmit and receive units disabled 262 * and uninitialized. 263 **/ 264 s32 ixgbe_start_hw(struct ixgbe_hw *hw) 265 { 266 return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw), 267 IXGBE_NOT_IMPLEMENTED); 268 } 269 270 /** 271 * ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering, 272 * which is disabled by default in ixgbe_start_hw(); 273 * 274 * @hw: pointer to hardware structure 275 * 276 * Enable relaxed ordering; 277 **/ 278 void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw) 279 { 280 if (hw->mac.ops.enable_relaxed_ordering) 281 hw->mac.ops.enable_relaxed_ordering(hw); 282 } 283 284 /** 285 * ixgbe_clear_hw_cntrs - Clear hardware counters 286 * @hw: pointer to hardware structure 287 * 288 * Clears all hardware statistics counters by reading them from the hardware 289 * Statistics counters are clear on read. 290 **/ 291 s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw) 292 { 293 return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw), 294 IXGBE_NOT_IMPLEMENTED); 295 } 296 297 /** 298 * ixgbe_get_media_type - Get media type 299 * @hw: pointer to hardware structure 300 * 301 * Returns the media type (fiber, copper, backplane) 302 **/ 303 enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw) 304 { 305 return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw), 306 ixgbe_media_type_unknown); 307 } 308 309 /** 310 * ixgbe_get_mac_addr - Get MAC address 311 * @hw: pointer to hardware structure 312 * @mac_addr: Adapter MAC address 313 * 314 * Reads the adapter's MAC address from the first Receive Address Register 315 * (RAR0) A reset of the adapter must have been performed prior to calling 316 * this function in order for the MAC address to have been loaded from the 317 * EEPROM into RAR0 318 **/ 319 s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr) 320 { 321 return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr, 322 (hw, mac_addr), IXGBE_NOT_IMPLEMENTED); 323 } 324 325 /** 326 * ixgbe_get_san_mac_addr - Get SAN MAC address 327 * @hw: pointer to hardware structure 328 * @san_mac_addr: SAN MAC address 329 * 330 * Reads the SAN MAC address from the EEPROM, if it's available. This is 331 * per-port, so set_lan_id() must be called before reading the addresses. 332 **/ 333 s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 334 { 335 return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr, 336 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 337 } 338 339 /** 340 * ixgbe_set_san_mac_addr - Write a SAN MAC address 341 * @hw: pointer to hardware structure 342 * @san_mac_addr: SAN MAC address 343 * 344 * Writes A SAN MAC address to the EEPROM. 345 **/ 346 s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 347 { 348 return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr, 349 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 350 } 351 352 /** 353 * ixgbe_get_device_caps - Get additional device capabilities 354 * @hw: pointer to hardware structure 355 * @device_caps: the EEPROM word for device capabilities 356 * 357 * Reads the extra device capabilities from the EEPROM 358 **/ 359 s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps) 360 { 361 return ixgbe_call_func(hw, hw->mac.ops.get_device_caps, 362 (hw, device_caps), IXGBE_NOT_IMPLEMENTED); 363 } 364 365 /** 366 * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM 367 * @hw: pointer to hardware structure 368 * @wwnn_prefix: the alternative WWNN prefix 369 * @wwpn_prefix: the alternative WWPN prefix 370 * 371 * This function will read the EEPROM from the alternative SAN MAC address 372 * block to check the support for the alternative WWNN/WWPN prefix support. 373 **/ 374 s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix, 375 u16 *wwpn_prefix) 376 { 377 return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix, 378 (hw, wwnn_prefix, wwpn_prefix), 379 IXGBE_NOT_IMPLEMENTED); 380 } 381 382 /** 383 * ixgbe_get_fcoe_boot_status - Get FCOE boot status from EEPROM 384 * @hw: pointer to hardware structure 385 * @bs: the fcoe boot status 386 * 387 * This function will read the FCOE boot status from the iSCSI FCOE block 388 **/ 389 s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs) 390 { 391 return ixgbe_call_func(hw, hw->mac.ops.get_fcoe_boot_status, 392 (hw, bs), 393 IXGBE_NOT_IMPLEMENTED); 394 } 395 396 /** 397 * ixgbe_get_bus_info - Set PCI bus info 398 * @hw: pointer to hardware structure 399 * 400 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 401 **/ 402 s32 ixgbe_get_bus_info(struct ixgbe_hw *hw) 403 { 404 return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw), 405 IXGBE_NOT_IMPLEMENTED); 406 } 407 408 /** 409 * ixgbe_get_num_of_tx_queues - Get Tx queues 410 * @hw: pointer to hardware structure 411 * 412 * Returns the number of transmit queues for the given adapter. 413 **/ 414 u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw) 415 { 416 return hw->mac.max_tx_queues; 417 } 418 419 /** 420 * ixgbe_get_num_of_rx_queues - Get Rx queues 421 * @hw: pointer to hardware structure 422 * 423 * Returns the number of receive queues for the given adapter. 424 **/ 425 u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw) 426 { 427 return hw->mac.max_rx_queues; 428 } 429 430 /** 431 * ixgbe_stop_adapter - Disable Rx/Tx units 432 * @hw: pointer to hardware structure 433 * 434 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 435 * disables transmit and receive units. The adapter_stopped flag is used by 436 * the shared code and drivers to determine if the adapter is in a stopped 437 * state and should not touch the hardware. 438 **/ 439 s32 ixgbe_stop_adapter(struct ixgbe_hw *hw) 440 { 441 return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw), 442 IXGBE_NOT_IMPLEMENTED); 443 } 444 445 /** 446 * ixgbe_read_pba_string - Reads part number string from EEPROM 447 * @hw: pointer to hardware structure 448 * @pba_num: stores the part number string from the EEPROM 449 * @pba_num_size: part number string buffer length 450 * 451 * Reads the part number string from the EEPROM. 452 **/ 453 s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size) 454 { 455 return ixgbe_read_pba_string_generic(hw, pba_num, pba_num_size); 456 } 457 458 /** 459 * ixgbe_read_pba_num - Reads part number from EEPROM 460 * @hw: pointer to hardware structure 461 * @pba_num: stores the part number from the EEPROM 462 * 463 * Reads the part number from the EEPROM. 464 **/ 465 s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num) 466 { 467 return ixgbe_read_pba_num_generic(hw, pba_num); 468 } 469 470 /** 471 * ixgbe_identify_phy - Get PHY type 472 * @hw: pointer to hardware structure 473 * 474 * Determines the physical layer module found on the current adapter. 475 **/ 476 s32 ixgbe_identify_phy(struct ixgbe_hw *hw) 477 { 478 s32 status = IXGBE_SUCCESS; 479 480 if (hw->phy.type == ixgbe_phy_unknown) { 481 status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw), 482 IXGBE_NOT_IMPLEMENTED); 483 } 484 485 return status; 486 } 487 488 /** 489 * ixgbe_reset_phy - Perform a PHY reset 490 * @hw: pointer to hardware structure 491 **/ 492 s32 ixgbe_reset_phy(struct ixgbe_hw *hw) 493 { 494 s32 status = IXGBE_SUCCESS; 495 496 if (hw->phy.type == ixgbe_phy_unknown) { 497 if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS) 498 status = IXGBE_ERR_PHY; 499 } 500 501 if (status == IXGBE_SUCCESS) { 502 status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw), 503 IXGBE_NOT_IMPLEMENTED); 504 } 505 return status; 506 } 507 508 /** 509 * ixgbe_get_phy_firmware_version - 510 * @hw: pointer to hardware structure 511 * @firmware_version: pointer to firmware version 512 **/ 513 s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version) 514 { 515 s32 status = IXGBE_SUCCESS; 516 517 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version, 518 (hw, firmware_version), 519 IXGBE_NOT_IMPLEMENTED); 520 return status; 521 } 522 523 /** 524 * ixgbe_read_phy_reg - Read PHY register 525 * @hw: pointer to hardware structure 526 * @reg_addr: 32 bit address of PHY register to read 527 * @device_type: type of device you want to communicate with 528 * @phy_data: Pointer to read data from PHY register 529 * 530 * Reads a value from a specified PHY register 531 **/ 532 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 533 u16 *phy_data) 534 { 535 if (hw->phy.id == 0) 536 ixgbe_identify_phy(hw); 537 538 return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr, 539 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 540 } 541 542 /** 543 * ixgbe_write_phy_reg - Write PHY register 544 * @hw: pointer to hardware structure 545 * @reg_addr: 32 bit PHY register to write 546 * @device_type: type of device you want to communicate with 547 * @phy_data: Data to write to the PHY register 548 * 549 * Writes a value to specified PHY register 550 **/ 551 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 552 u16 phy_data) 553 { 554 if (hw->phy.id == 0) 555 ixgbe_identify_phy(hw); 556 557 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr, 558 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 559 } 560 561 /** 562 * ixgbe_setup_phy_link - Restart PHY autoneg 563 * @hw: pointer to hardware structure 564 * 565 * Restart autonegotiation and PHY and waits for completion. 566 **/ 567 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw) 568 { 569 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw), 570 IXGBE_NOT_IMPLEMENTED); 571 } 572 573 /** 574 * ixgbe_setup_internal_phy - Configure integrated PHY 575 * @hw: pointer to hardware structure 576 * 577 * Reconfigure the integrated PHY in order to enable talk to the external PHY. 578 * Returns success if not implemented, since nothing needs to be done in this 579 * case. 580 */ 581 s32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw) 582 { 583 return ixgbe_call_func(hw, hw->phy.ops.setup_internal_link, (hw), 584 IXGBE_SUCCESS); 585 } 586 587 /** 588 * ixgbe_check_phy_link - Determine link and speed status 589 * @hw: pointer to hardware structure 590 * @speed: link speed 591 * @link_up: TRUE when link is up 592 * 593 * Reads a PHY register to determine if link is up and the current speed for 594 * the PHY. 595 **/ 596 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 597 bool *link_up) 598 { 599 return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed, 600 link_up), IXGBE_NOT_IMPLEMENTED); 601 } 602 603 /** 604 * ixgbe_setup_phy_link_speed - Set auto advertise 605 * @hw: pointer to hardware structure 606 * @speed: new link speed 607 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 608 * 609 * Sets the auto advertised capabilities 610 **/ 611 s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed, 612 bool autoneg_wait_to_complete) 613 { 614 return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed, 615 autoneg_wait_to_complete), 616 IXGBE_NOT_IMPLEMENTED); 617 } 618 619 /** 620 * ixgbe_set_phy_power - Control the phy power state 621 * @hw: pointer to hardware structure 622 * @on: TRUE for on, FALSE for off 623 */ 624 s32 ixgbe_set_phy_power(struct ixgbe_hw *hw, bool on) 625 { 626 return ixgbe_call_func(hw, hw->phy.ops.set_phy_power, (hw, on), 627 IXGBE_NOT_IMPLEMENTED); 628 } 629 630 /** 631 * ixgbe_check_link - Get link and speed status 632 * @hw: pointer to hardware structure 633 * @speed: pointer to link speed 634 * @link_up: TRUE when link is up 635 * @link_up_wait_to_complete: bool used to wait for link up or not 636 * 637 * Reads the links register to determine if link is up and the current speed 638 **/ 639 s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 640 bool *link_up, bool link_up_wait_to_complete) 641 { 642 return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed, 643 link_up, link_up_wait_to_complete), 644 IXGBE_NOT_IMPLEMENTED); 645 } 646 647 /** 648 * ixgbe_disable_tx_laser - Disable Tx laser 649 * @hw: pointer to hardware structure 650 * 651 * If the driver needs to disable the laser on SFI optics. 652 **/ 653 void ixgbe_disable_tx_laser(struct ixgbe_hw *hw) 654 { 655 if (hw->mac.ops.disable_tx_laser) 656 hw->mac.ops.disable_tx_laser(hw); 657 } 658 659 /** 660 * ixgbe_enable_tx_laser - Enable Tx laser 661 * @hw: pointer to hardware structure 662 * 663 * If the driver needs to enable the laser on SFI optics. 664 **/ 665 void ixgbe_enable_tx_laser(struct ixgbe_hw *hw) 666 { 667 if (hw->mac.ops.enable_tx_laser) 668 hw->mac.ops.enable_tx_laser(hw); 669 } 670 671 /** 672 * ixgbe_flap_tx_laser - flap Tx laser to start autotry process 673 * @hw: pointer to hardware structure 674 * 675 * When the driver changes the link speeds that it can support then 676 * flap the tx laser to alert the link partner to start autotry 677 * process on its end. 678 **/ 679 void ixgbe_flap_tx_laser(struct ixgbe_hw *hw) 680 { 681 if (hw->mac.ops.flap_tx_laser) 682 hw->mac.ops.flap_tx_laser(hw); 683 } 684 685 /** 686 * ixgbe_setup_link - Set link speed 687 * @hw: pointer to hardware structure 688 * @speed: new link speed 689 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 690 * 691 * Configures link settings. Restarts the link. 692 * Performs autonegotiation if needed. 693 **/ 694 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 695 bool autoneg_wait_to_complete) 696 { 697 return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed, 698 autoneg_wait_to_complete), 699 IXGBE_NOT_IMPLEMENTED); 700 } 701 702 /** 703 * ixgbe_setup_mac_link - Set link speed 704 * @hw: pointer to hardware structure 705 * @speed: new link speed 706 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 707 * 708 * Configures link settings. Restarts the link. 709 * Performs autonegotiation if needed. 710 **/ 711 s32 ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 712 bool autoneg_wait_to_complete) 713 { 714 return ixgbe_call_func(hw, hw->mac.ops.setup_mac_link, (hw, speed, 715 autoneg_wait_to_complete), 716 IXGBE_NOT_IMPLEMENTED); 717 } 718 719 /** 720 * ixgbe_get_link_capabilities - Returns link capabilities 721 * @hw: pointer to hardware structure 722 * @speed: link speed capabilities 723 * @autoneg: TRUE when autoneg or autotry is enabled 724 * 725 * Determines the link capabilities of the current configuration. 726 **/ 727 s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 728 bool *autoneg) 729 { 730 return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw, 731 speed, autoneg), IXGBE_NOT_IMPLEMENTED); 732 } 733 734 /** 735 * ixgbe_led_on - Turn on LEDs 736 * @hw: pointer to hardware structure 737 * @index: led number to turn on 738 * 739 * Turns on the software controllable LEDs. 740 **/ 741 s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index) 742 { 743 return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index), 744 IXGBE_NOT_IMPLEMENTED); 745 } 746 747 /** 748 * ixgbe_led_off - Turn off LEDs 749 * @hw: pointer to hardware structure 750 * @index: led number to turn off 751 * 752 * Turns off the software controllable LEDs. 753 **/ 754 s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index) 755 { 756 return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index), 757 IXGBE_NOT_IMPLEMENTED); 758 } 759 760 /** 761 * ixgbe_blink_led_start - Blink LEDs 762 * @hw: pointer to hardware structure 763 * @index: led number to blink 764 * 765 * Blink LED based on index. 766 **/ 767 s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index) 768 { 769 return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index), 770 IXGBE_NOT_IMPLEMENTED); 771 } 772 773 /** 774 * ixgbe_blink_led_stop - Stop blinking LEDs 775 * @hw: pointer to hardware structure 776 * @index: led number to stop 777 * 778 * Stop blinking LED based on index. 779 **/ 780 s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index) 781 { 782 return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index), 783 IXGBE_NOT_IMPLEMENTED); 784 } 785 786 /** 787 * ixgbe_init_eeprom_params - Initialize EEPROM parameters 788 * @hw: pointer to hardware structure 789 * 790 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 791 * ixgbe_hw struct in order to set up EEPROM access. 792 **/ 793 s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw) 794 { 795 return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw), 796 IXGBE_NOT_IMPLEMENTED); 797 } 798 799 800 /** 801 * ixgbe_write_eeprom - Write word to EEPROM 802 * @hw: pointer to hardware structure 803 * @offset: offset within the EEPROM to be written to 804 * @data: 16 bit word to be written to the EEPROM 805 * 806 * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not 807 * called after this function, the EEPROM will most likely contain an 808 * invalid checksum. 809 **/ 810 s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data) 811 { 812 return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data), 813 IXGBE_NOT_IMPLEMENTED); 814 } 815 816 /** 817 * ixgbe_write_eeprom_buffer - Write word(s) to EEPROM 818 * @hw: pointer to hardware structure 819 * @offset: offset within the EEPROM to be written to 820 * @data: 16 bit word(s) to be written to the EEPROM 821 * @words: number of words 822 * 823 * Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not 824 * called after this function, the EEPROM will most likely contain an 825 * invalid checksum. 826 **/ 827 s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, u16 words, 828 u16 *data) 829 { 830 return ixgbe_call_func(hw, hw->eeprom.ops.write_buffer, 831 (hw, offset, words, data), 832 IXGBE_NOT_IMPLEMENTED); 833 } 834 835 /** 836 * ixgbe_read_eeprom - Read word from EEPROM 837 * @hw: pointer to hardware structure 838 * @offset: offset within the EEPROM to be read 839 * @data: read 16 bit value from EEPROM 840 * 841 * Reads 16 bit value from EEPROM 842 **/ 843 s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data) 844 { 845 return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data), 846 IXGBE_NOT_IMPLEMENTED); 847 } 848 849 /** 850 * ixgbe_read_eeprom_buffer - Read word(s) from EEPROM 851 * @hw: pointer to hardware structure 852 * @offset: offset within the EEPROM to be read 853 * @data: read 16 bit word(s) from EEPROM 854 * @words: number of words 855 * 856 * Reads 16 bit word(s) from EEPROM 857 **/ 858 s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, 859 u16 words, u16 *data) 860 { 861 return ixgbe_call_func(hw, hw->eeprom.ops.read_buffer, 862 (hw, offset, words, data), 863 IXGBE_NOT_IMPLEMENTED); 864 } 865 866 /** 867 * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum 868 * @hw: pointer to hardware structure 869 * @checksum_val: calculated checksum 870 * 871 * Performs checksum calculation and validates the EEPROM checksum 872 **/ 873 s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val) 874 { 875 return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum, 876 (hw, checksum_val), IXGBE_NOT_IMPLEMENTED); 877 } 878 879 /** 880 * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum 881 * @hw: pointer to hardware structure 882 **/ 883 s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw) 884 { 885 return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw), 886 IXGBE_NOT_IMPLEMENTED); 887 } 888 889 /** 890 * ixgbe_insert_mac_addr - Find a RAR for this mac address 891 * @hw: pointer to hardware structure 892 * @addr: Address to put into receive address register 893 * @vmdq: VMDq pool to assign 894 * 895 * Puts an ethernet address into a receive address register, or 896 * finds the rar that it is already in; adds to the pool list 897 **/ 898 s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 899 { 900 return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr, 901 (hw, addr, vmdq), 902 IXGBE_NOT_IMPLEMENTED); 903 } 904 905 /** 906 * ixgbe_set_rar - Set Rx address register 907 * @hw: pointer to hardware structure 908 * @index: Receive address register to write 909 * @addr: Address to put into receive address register 910 * @vmdq: VMDq "set" 911 * @enable_addr: set flag that address is active 912 * 913 * Puts an ethernet address into a receive address register. 914 **/ 915 s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 916 u32 enable_addr) 917 { 918 return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq, 919 enable_addr), IXGBE_NOT_IMPLEMENTED); 920 } 921 922 /** 923 * ixgbe_clear_rar - Clear Rx address register 924 * @hw: pointer to hardware structure 925 * @index: Receive address register to write 926 * 927 * Puts an ethernet address into a receive address register. 928 **/ 929 s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index) 930 { 931 return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index), 932 IXGBE_NOT_IMPLEMENTED); 933 } 934 935 /** 936 * ixgbe_set_vmdq - Associate a VMDq index with a receive address 937 * @hw: pointer to hardware structure 938 * @rar: receive address register index to associate with VMDq index 939 * @vmdq: VMDq set or pool index 940 **/ 941 s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 942 { 943 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq), 944 IXGBE_NOT_IMPLEMENTED); 945 946 } 947 948 /** 949 * ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address 950 * @hw: pointer to hardware structure 951 * @vmdq: VMDq default pool index 952 **/ 953 s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq) 954 { 955 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq_san_mac, 956 (hw, vmdq), IXGBE_NOT_IMPLEMENTED); 957 } 958 959 /** 960 * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address 961 * @hw: pointer to hardware structure 962 * @rar: receive address register index to disassociate with VMDq index 963 * @vmdq: VMDq set or pool index 964 **/ 965 s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 966 { 967 return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq), 968 IXGBE_NOT_IMPLEMENTED); 969 } 970 971 /** 972 * ixgbe_init_rx_addrs - Initializes receive address filters. 973 * @hw: pointer to hardware structure 974 * 975 * Places the MAC address in receive address register 0 and clears the rest 976 * of the receive address registers. Clears the multicast table. Assumes 977 * the receiver is in reset when the routine is called. 978 **/ 979 s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw) 980 { 981 return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw), 982 IXGBE_NOT_IMPLEMENTED); 983 } 984 985 /** 986 * ixgbe_get_num_rx_addrs - Returns the number of RAR entries. 987 * @hw: pointer to hardware structure 988 **/ 989 u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw) 990 { 991 return hw->mac.num_rar_entries; 992 } 993 994 /** 995 * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses 996 * @hw: pointer to hardware structure 997 * @addr_list: the list of new multicast addresses 998 * @addr_count: number of addresses 999 * @func: iterator function to walk the multicast address list 1000 * 1001 * The given list replaces any existing list. Clears the secondary addrs from 1002 * receive address registers. Uses unused receive address registers for the 1003 * first secondary addresses, and falls back to promiscuous mode as needed. 1004 **/ 1005 s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, 1006 u32 addr_count, ixgbe_mc_addr_itr func) 1007 { 1008 return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw, 1009 addr_list, addr_count, func), 1010 IXGBE_NOT_IMPLEMENTED); 1011 } 1012 1013 /** 1014 * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses 1015 * @hw: pointer to hardware structure 1016 * @mc_addr_list: the list of new multicast addresses 1017 * @mc_addr_count: number of addresses 1018 * @func: iterator function to walk the multicast address list 1019 * @clear: flag, when set clears the table beforehand 1020 * 1021 * The given list replaces any existing list. Clears the MC addrs from receive 1022 * address registers and the multicast table. Uses unused receive address 1023 * registers for the first multicast addresses, and hashes the rest into the 1024 * multicast table. 1025 **/ 1026 s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, 1027 u32 mc_addr_count, ixgbe_mc_addr_itr func, 1028 bool clear) 1029 { 1030 return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw, 1031 mc_addr_list, mc_addr_count, func, clear), 1032 IXGBE_NOT_IMPLEMENTED); 1033 } 1034 1035 /** 1036 * ixgbe_enable_mc - Enable multicast address in RAR 1037 * @hw: pointer to hardware structure 1038 * 1039 * Enables multicast address in RAR and the use of the multicast hash table. 1040 **/ 1041 s32 ixgbe_enable_mc(struct ixgbe_hw *hw) 1042 { 1043 return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw), 1044 IXGBE_NOT_IMPLEMENTED); 1045 } 1046 1047 /** 1048 * ixgbe_disable_mc - Disable multicast address in RAR 1049 * @hw: pointer to hardware structure 1050 * 1051 * Disables multicast address in RAR and the use of the multicast hash table. 1052 **/ 1053 s32 ixgbe_disable_mc(struct ixgbe_hw *hw) 1054 { 1055 return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw), 1056 IXGBE_NOT_IMPLEMENTED); 1057 } 1058 1059 /** 1060 * ixgbe_clear_vfta - Clear VLAN filter table 1061 * @hw: pointer to hardware structure 1062 * 1063 * Clears the VLAN filer table, and the VMDq index associated with the filter 1064 **/ 1065 s32 ixgbe_clear_vfta(struct ixgbe_hw *hw) 1066 { 1067 return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw), 1068 IXGBE_NOT_IMPLEMENTED); 1069 } 1070 1071 /** 1072 * ixgbe_set_vfta - Set VLAN filter table 1073 * @hw: pointer to hardware structure 1074 * @vlan: VLAN id to write to VLAN filter 1075 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 1076 * @vlan_on: boolean flag to turn on/off VLAN 1077 * @vlvf_bypass: boolean flag indicating updating the default pool is okay 1078 * 1079 * Turn on/off specified VLAN in the VLAN filter table. 1080 **/ 1081 s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, 1082 bool vlvf_bypass) 1083 { 1084 return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind, 1085 vlan_on, vlvf_bypass), IXGBE_NOT_IMPLEMENTED); 1086 } 1087 1088 /** 1089 * ixgbe_set_vlvf - Set VLAN Pool Filter 1090 * @hw: pointer to hardware structure 1091 * @vlan: VLAN id to write to VLAN filter 1092 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 1093 * @vlan_on: boolean flag to turn on/off VLAN in VLVF 1094 * @vfta_delta: pointer to the difference between the current value of VFTA 1095 * and the desired value 1096 * @vfta: the desired value of the VFTA 1097 * @vlvf_bypass: boolean flag indicating updating the default pool is okay 1098 * 1099 * Turn on/off specified bit in VLVF table. 1100 **/ 1101 s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, 1102 u32 *vfta_delta, u32 vfta, bool vlvf_bypass) 1103 { 1104 return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind, 1105 vlan_on, vfta_delta, vfta, vlvf_bypass), 1106 IXGBE_NOT_IMPLEMENTED); 1107 } 1108 1109 /** 1110 * ixgbe_fc_enable - Enable flow control 1111 * @hw: pointer to hardware structure 1112 * 1113 * Configures the flow control settings based on SW configuration. 1114 **/ 1115 s32 ixgbe_fc_enable(struct ixgbe_hw *hw) 1116 { 1117 return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw), 1118 IXGBE_NOT_IMPLEMENTED); 1119 } 1120 1121 /** 1122 * ixgbe_setup_fc - Set up flow control 1123 * @hw: pointer to hardware structure 1124 * 1125 * Called at init time to set up flow control. 1126 **/ 1127 s32 ixgbe_setup_fc(struct ixgbe_hw *hw) 1128 { 1129 return ixgbe_call_func(hw, hw->mac.ops.setup_fc, (hw), 1130 IXGBE_NOT_IMPLEMENTED); 1131 } 1132 1133 /** 1134 * ixgbe_set_fw_drv_ver - Try to send the driver version number FW 1135 * @hw: pointer to hardware structure 1136 * @maj: driver major number to be sent to firmware 1137 * @minr: driver minor number to be sent to firmware 1138 * @build: driver build number to be sent to firmware 1139 * @ver: driver version number to be sent to firmware 1140 * @len: length of driver_ver string 1141 * @driver_ver: driver string 1142 **/ 1143 s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 minr, u8 build, 1144 u8 ver, u16 len, char *driver_ver) 1145 { 1146 return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, minr, 1147 build, ver, len, driver_ver), 1148 IXGBE_NOT_IMPLEMENTED); 1149 } 1150 1151 1152 1153 /** 1154 * ixgbe_dmac_config - Configure DMA Coalescing registers. 1155 * @hw: pointer to hardware structure 1156 * 1157 * Configure DMA coalescing. If enabling dmac, dmac is activated. 1158 * When disabling dmac, dmac enable dmac bit is cleared. 1159 **/ 1160 s32 ixgbe_dmac_config(struct ixgbe_hw *hw) 1161 { 1162 return ixgbe_call_func(hw, hw->mac.ops.dmac_config, (hw), 1163 IXGBE_NOT_IMPLEMENTED); 1164 } 1165 1166 /** 1167 * ixgbe_dmac_update_tcs - Configure DMA Coalescing registers. 1168 * @hw: pointer to hardware structure 1169 * 1170 * Disables dmac, updates per TC settings, and then enable dmac. 1171 **/ 1172 s32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw) 1173 { 1174 return ixgbe_call_func(hw, hw->mac.ops.dmac_update_tcs, (hw), 1175 IXGBE_NOT_IMPLEMENTED); 1176 } 1177 1178 /** 1179 * ixgbe_dmac_config_tcs - Configure DMA Coalescing registers. 1180 * @hw: pointer to hardware structure 1181 * 1182 * Configure DMA coalescing threshold per TC and set high priority bit for 1183 * FCOE TC. The dmac enable bit must be cleared before configuring. 1184 **/ 1185 s32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw) 1186 { 1187 return ixgbe_call_func(hw, hw->mac.ops.dmac_config_tcs, (hw), 1188 IXGBE_NOT_IMPLEMENTED); 1189 } 1190 1191 /** 1192 * ixgbe_setup_eee - Enable/disable EEE support 1193 * @hw: pointer to the HW structure 1194 * @enable_eee: boolean flag to enable EEE 1195 * 1196 * Enable/disable EEE based on enable_ee flag. 1197 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C 1198 * are modified. 1199 * 1200 **/ 1201 s32 ixgbe_setup_eee(struct ixgbe_hw *hw, bool enable_eee) 1202 { 1203 return ixgbe_call_func(hw, hw->mac.ops.setup_eee, (hw, enable_eee), 1204 IXGBE_NOT_IMPLEMENTED); 1205 } 1206 1207 /** 1208 * ixgbe_set_source_address_pruning - Enable/Disable source address pruning 1209 * @hw: pointer to hardware structure 1210 * @enable: enable or disable source address pruning 1211 * @pool: Rx pool - Rx pool to toggle source address pruning 1212 **/ 1213 void ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable, 1214 unsigned int pool) 1215 { 1216 if (hw->mac.ops.set_source_address_pruning) 1217 hw->mac.ops.set_source_address_pruning(hw, enable, pool); 1218 } 1219 1220 /** 1221 * ixgbe_set_ethertype_anti_spoofing - Enable/Disable Ethertype anti-spoofing 1222 * @hw: pointer to hardware structure 1223 * @enable: enable or disable switch for Ethertype anti-spoofing 1224 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 1225 * 1226 **/ 1227 void ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 1228 { 1229 if (hw->mac.ops.set_ethertype_anti_spoofing) 1230 hw->mac.ops.set_ethertype_anti_spoofing(hw, enable, vf); 1231 } 1232 1233 /** 1234 * ixgbe_read_iosf_sb_reg - Read 32 bit PHY register 1235 * @hw: pointer to hardware structure 1236 * @reg_addr: 32 bit address of PHY register to read 1237 * @device_type: type of device you want to communicate with 1238 * @phy_data: Pointer to read data from PHY register 1239 * 1240 * Reads a value from a specified PHY register 1241 **/ 1242 s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1243 u32 device_type, u32 *phy_data) 1244 { 1245 return ixgbe_call_func(hw, hw->mac.ops.read_iosf_sb_reg, (hw, reg_addr, 1246 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1247 } 1248 1249 /** 1250 * ixgbe_write_iosf_sb_reg - Write 32 bit register through IOSF Sideband 1251 * @hw: pointer to hardware structure 1252 * @reg_addr: 32 bit PHY register to write 1253 * @device_type: type of device you want to communicate with 1254 * @phy_data: Data to write to the PHY register 1255 * 1256 * Writes a value to specified PHY register 1257 **/ 1258 s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1259 u32 device_type, u32 phy_data) 1260 { 1261 return ixgbe_call_func(hw, hw->mac.ops.write_iosf_sb_reg, (hw, reg_addr, 1262 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1263 } 1264 1265 /** 1266 * ixgbe_disable_mdd - Disable malicious driver detection 1267 * @hw: pointer to hardware structure 1268 * 1269 **/ 1270 void ixgbe_disable_mdd(struct ixgbe_hw *hw) 1271 { 1272 if (hw->mac.ops.disable_mdd) 1273 hw->mac.ops.disable_mdd(hw); 1274 } 1275 1276 /** 1277 * ixgbe_enable_mdd - Enable malicious driver detection 1278 * @hw: pointer to hardware structure 1279 * 1280 **/ 1281 void ixgbe_enable_mdd(struct ixgbe_hw *hw) 1282 { 1283 if (hw->mac.ops.enable_mdd) 1284 hw->mac.ops.enable_mdd(hw); 1285 } 1286 1287 /** 1288 * ixgbe_mdd_event - Handle malicious driver detection event 1289 * @hw: pointer to hardware structure 1290 * @vf_bitmap: vf bitmap of malicious vfs 1291 * 1292 **/ 1293 void ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap) 1294 { 1295 if (hw->mac.ops.mdd_event) 1296 hw->mac.ops.mdd_event(hw, vf_bitmap); 1297 } 1298 1299 /** 1300 * ixgbe_restore_mdd_vf - Restore VF that was disabled during malicious driver 1301 * detection event 1302 * @hw: pointer to hardware structure 1303 * @vf: vf index 1304 * 1305 **/ 1306 void ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf) 1307 { 1308 if (hw->mac.ops.restore_mdd_vf) 1309 hw->mac.ops.restore_mdd_vf(hw, vf); 1310 } 1311 1312 /** 1313 * ixgbe_enter_lplu - Transition to low power states 1314 * @hw: pointer to hardware structure 1315 * 1316 * Configures Low Power Link Up on transition to low power states 1317 * (from D0 to non-D0). 1318 **/ 1319 s32 ixgbe_enter_lplu(struct ixgbe_hw *hw) 1320 { 1321 return ixgbe_call_func(hw, hw->phy.ops.enter_lplu, (hw), 1322 IXGBE_NOT_IMPLEMENTED); 1323 } 1324 1325 /** 1326 * ixgbe_handle_lasi - Handle external Base T PHY interrupt 1327 * @hw: pointer to hardware structure 1328 * 1329 * Handle external Base T PHY interrupt. If high temperature 1330 * failure alarm then return error, else if link status change 1331 * then setup internal/external PHY link 1332 * 1333 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 1334 * failure alarm, else return PHY access status. 1335 */ 1336 s32 ixgbe_handle_lasi(struct ixgbe_hw *hw) 1337 { 1338 return ixgbe_call_func(hw, hw->phy.ops.handle_lasi, (hw), 1339 IXGBE_NOT_IMPLEMENTED); 1340 } 1341 1342 /** 1343 * ixgbe_bypass_rw - Bit bang data into by_pass FW 1344 * @hw: pointer to hardware structure 1345 * @cmd: Command we send to the FW 1346 * @status: The reply from the FW 1347 * 1348 * Bit-bangs the cmd to the by_pass FW status points to what is returned. 1349 **/ 1350 s32 ixgbe_bypass_rw(struct ixgbe_hw *hw, u32 cmd, u32 *status) 1351 { 1352 return ixgbe_call_func(hw, hw->mac.ops.bypass_rw, (hw, cmd, status), 1353 IXGBE_NOT_IMPLEMENTED); 1354 } 1355 1356 /** 1357 * ixgbe_bypass_valid_rd - Verify valid return from bit-bang. 1358 * 1359 * If we send a write we can't be sure it took until we can read back 1360 * that same register. It can be a problem as some of the feilds may 1361 * for valid reasons change inbetween the time wrote the register and 1362 * we read it again to verify. So this function check everything we 1363 * can check and then assumes it worked. 1364 * 1365 * @u32 in_reg - The register cmd for the bit-bang read. 1366 * @u32 out_reg - The register returned from a bit-bang read. 1367 **/ 1368 bool ixgbe_bypass_valid_rd(struct ixgbe_hw *hw, u32 in_reg, u32 out_reg) 1369 { 1370 return ixgbe_call_func(hw, hw->mac.ops.bypass_valid_rd, 1371 (in_reg, out_reg), IXGBE_NOT_IMPLEMENTED); 1372 } 1373 1374 /** 1375 * ixgbe_bypass_set - Set a bypass field in the FW CTRL Regiter. 1376 * @hw: pointer to hardware structure 1377 * @cmd: The control word we are setting. 1378 * @event: The event we are setting in the FW. This also happens to 1379 * be the mask for the event we are setting (handy) 1380 * @action: The action we set the event to in the FW. This is in a 1381 * bit field that happens to be what we want to put in 1382 * the event spot (also handy) 1383 * 1384 * Writes to the cmd control the bits in actions. 1385 **/ 1386 s32 ixgbe_bypass_set(struct ixgbe_hw *hw, u32 cmd, u32 event, u32 action) 1387 { 1388 return ixgbe_call_func(hw, hw->mac.ops.bypass_set, 1389 (hw, cmd, event, action), 1390 IXGBE_NOT_IMPLEMENTED); 1391 } 1392 1393 /** 1394 * ixgbe_bypass_rd_eep - Read the bypass FW eeprom address 1395 * @hw: pointer to hardware structure 1396 * @addr: The bypass eeprom address to read. 1397 * @value: The 8b of data at the address above. 1398 **/ 1399 s32 ixgbe_bypass_rd_eep(struct ixgbe_hw *hw, u32 addr, u8 *value) 1400 { 1401 return ixgbe_call_func(hw, hw->mac.ops.bypass_rd_eep, 1402 (hw, addr, value), IXGBE_NOT_IMPLEMENTED); 1403 } 1404 1405 /** 1406 * ixgbe_read_analog_reg8 - Reads 8 bit analog register 1407 * @hw: pointer to hardware structure 1408 * @reg: analog register to read 1409 * @val: read value 1410 * 1411 * Performs write operation to analog register specified. 1412 **/ 1413 s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val) 1414 { 1415 return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg, 1416 val), IXGBE_NOT_IMPLEMENTED); 1417 } 1418 1419 /** 1420 * ixgbe_write_analog_reg8 - Writes 8 bit analog register 1421 * @hw: pointer to hardware structure 1422 * @reg: analog register to write 1423 * @val: value to write 1424 * 1425 * Performs write operation to Atlas analog register specified. 1426 **/ 1427 s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val) 1428 { 1429 return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg, 1430 val), IXGBE_NOT_IMPLEMENTED); 1431 } 1432 1433 /** 1434 * ixgbe_init_uta_tables - Initializes Unicast Table Arrays. 1435 * @hw: pointer to hardware structure 1436 * 1437 * Initializes the Unicast Table Arrays to zero on device load. This 1438 * is part of the Rx init addr execution path. 1439 **/ 1440 s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw) 1441 { 1442 return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw), 1443 IXGBE_NOT_IMPLEMENTED); 1444 } 1445 1446 /** 1447 * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address 1448 * @hw: pointer to hardware structure 1449 * @byte_offset: byte offset to read 1450 * @dev_addr: I2C bus address to read from 1451 * @data: value read 1452 * 1453 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1454 **/ 1455 s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1456 u8 *data) 1457 { 1458 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset, 1459 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1460 } 1461 1462 /** 1463 * ixgbe_read_i2c_byte_unlocked - Reads 8 bit word via I2C from device address 1464 * @hw: pointer to hardware structure 1465 * @byte_offset: byte offset to read 1466 * @dev_addr: I2C bus address to read from 1467 * @data: value read 1468 * 1469 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1470 **/ 1471 s32 ixgbe_read_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1472 u8 dev_addr, u8 *data) 1473 { 1474 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte_unlocked, 1475 (hw, byte_offset, dev_addr, data), 1476 IXGBE_NOT_IMPLEMENTED); 1477 } 1478 1479 /** 1480 * ixgbe_read_link - Perform read operation on link device 1481 * @hw: pointer to the hardware structure 1482 * @addr: bus address to read from 1483 * @reg: device register to read from 1484 * @val: pointer to location to receive read value 1485 * 1486 * Returns an error code on error. 1487 */ 1488 s32 ixgbe_read_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) 1489 { 1490 return ixgbe_call_func(hw, hw->link.ops.read_link, (hw, addr, 1491 reg, val), IXGBE_NOT_IMPLEMENTED); 1492 } 1493 1494 /** 1495 * ixgbe_read_link_unlocked - Perform read operation on link device 1496 * @hw: pointer to the hardware structure 1497 * @addr: bus address to read from 1498 * @reg: device register to read from 1499 * @val: pointer to location to receive read value 1500 * 1501 * Returns an error code on error. 1502 **/ 1503 s32 ixgbe_read_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) 1504 { 1505 return ixgbe_call_func(hw, hw->link.ops.read_link_unlocked, 1506 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1507 } 1508 1509 /** 1510 * ixgbe_write_i2c_byte - Writes 8 bit word over I2C 1511 * @hw: pointer to hardware structure 1512 * @byte_offset: byte offset to write 1513 * @dev_addr: I2C bus address to write to 1514 * @data: value to write 1515 * 1516 * Performs byte write operation to SFP module's EEPROM over I2C interface 1517 * at a specified device address. 1518 **/ 1519 s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1520 u8 data) 1521 { 1522 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset, 1523 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1524 } 1525 1526 /** 1527 * ixgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C 1528 * @hw: pointer to hardware structure 1529 * @byte_offset: byte offset to write 1530 * @dev_addr: I2C bus address to write to 1531 * @data: value to write 1532 * 1533 * Performs byte write operation to SFP module's EEPROM over I2C interface 1534 * at a specified device address. 1535 **/ 1536 s32 ixgbe_write_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1537 u8 dev_addr, u8 data) 1538 { 1539 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte_unlocked, 1540 (hw, byte_offset, dev_addr, data), 1541 IXGBE_NOT_IMPLEMENTED); 1542 } 1543 1544 /** 1545 * ixgbe_write_link - Perform write operation on link device 1546 * @hw: pointer to the hardware structure 1547 * @addr: bus address to write to 1548 * @reg: device register to write to 1549 * @val: value to write 1550 * 1551 * Returns an error code on error. 1552 */ 1553 s32 ixgbe_write_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) 1554 { 1555 return ixgbe_call_func(hw, hw->link.ops.write_link, 1556 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1557 } 1558 1559 /** 1560 * ixgbe_write_link_unlocked - Perform write operation on link device 1561 * @hw: pointer to the hardware structure 1562 * @addr: bus address to write to 1563 * @reg: device register to write to 1564 * @val: value to write 1565 * 1566 * Returns an error code on error. 1567 **/ 1568 s32 ixgbe_write_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) 1569 { 1570 return ixgbe_call_func(hw, hw->link.ops.write_link_unlocked, 1571 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1572 } 1573 1574 /** 1575 * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface 1576 * @hw: pointer to hardware structure 1577 * @byte_offset: EEPROM byte offset to write 1578 * @eeprom_data: value to write 1579 * 1580 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1581 **/ 1582 s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, 1583 u8 byte_offset, u8 eeprom_data) 1584 { 1585 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom, 1586 (hw, byte_offset, eeprom_data), 1587 IXGBE_NOT_IMPLEMENTED); 1588 } 1589 1590 /** 1591 * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface 1592 * @hw: pointer to hardware structure 1593 * @byte_offset: EEPROM byte offset to read 1594 * @eeprom_data: value read 1595 * 1596 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1597 **/ 1598 s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data) 1599 { 1600 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom, 1601 (hw, byte_offset, eeprom_data), 1602 IXGBE_NOT_IMPLEMENTED); 1603 } 1604 1605 /** 1606 * ixgbe_get_supported_physical_layer - Returns physical layer type 1607 * @hw: pointer to hardware structure 1608 * 1609 * Determines physical layer capabilities of the current configuration. 1610 **/ 1611 u64 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw) 1612 { 1613 return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer, 1614 (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN); 1615 } 1616 1617 /** 1618 * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics 1619 * @hw: pointer to hardware structure 1620 * @regval: bitfield to write to the Rx DMA register 1621 * 1622 * Enables the Rx DMA unit of the device. 1623 **/ 1624 s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval) 1625 { 1626 return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma, 1627 (hw, regval), IXGBE_NOT_IMPLEMENTED); 1628 } 1629 1630 /** 1631 * ixgbe_disable_sec_rx_path - Stops the receive data path 1632 * @hw: pointer to hardware structure 1633 * 1634 * Stops the receive data path. 1635 **/ 1636 s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw) 1637 { 1638 return ixgbe_call_func(hw, hw->mac.ops.disable_sec_rx_path, 1639 (hw), IXGBE_NOT_IMPLEMENTED); 1640 } 1641 1642 /** 1643 * ixgbe_enable_sec_rx_path - Enables the receive data path 1644 * @hw: pointer to hardware structure 1645 * 1646 * Enables the receive data path. 1647 **/ 1648 s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw) 1649 { 1650 return ixgbe_call_func(hw, hw->mac.ops.enable_sec_rx_path, 1651 (hw), IXGBE_NOT_IMPLEMENTED); 1652 } 1653 1654 /** 1655 * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore 1656 * @hw: pointer to hardware structure 1657 * @mask: Mask to specify which semaphore to acquire 1658 * 1659 * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified 1660 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1661 **/ 1662 s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1663 { 1664 return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync, 1665 (hw, mask), IXGBE_NOT_IMPLEMENTED); 1666 } 1667 1668 /** 1669 * ixgbe_release_swfw_semaphore - Release SWFW semaphore 1670 * @hw: pointer to hardware structure 1671 * @mask: Mask to specify which semaphore to release 1672 * 1673 * Releases the SWFW semaphore through SW_FW_SYNC register for the specified 1674 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1675 **/ 1676 void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1677 { 1678 if (hw->mac.ops.release_swfw_sync) 1679 hw->mac.ops.release_swfw_sync(hw, mask); 1680 } 1681 1682 /** 1683 * ixgbe_init_swfw_semaphore - Clean up SWFW semaphore 1684 * @hw: pointer to hardware structure 1685 * 1686 * Attempts to acquire the SWFW semaphore through SW_FW_SYNC register. 1687 * Regardless of whether is succeeds or not it then release the semaphore. 1688 * This is function is called to recover from catastrophic failures that 1689 * may have left the semaphore locked. 1690 **/ 1691 void ixgbe_init_swfw_semaphore(struct ixgbe_hw *hw) 1692 { 1693 if (hw->mac.ops.init_swfw_sync) 1694 hw->mac.ops.init_swfw_sync(hw); 1695 } 1696 1697 1698 void ixgbe_disable_rx(struct ixgbe_hw *hw) 1699 { 1700 if (hw->mac.ops.disable_rx) 1701 hw->mac.ops.disable_rx(hw); 1702 } 1703 1704 void ixgbe_enable_rx(struct ixgbe_hw *hw) 1705 { 1706 if (hw->mac.ops.enable_rx) 1707 hw->mac.ops.enable_rx(hw); 1708 } 1709 1710 /** 1711 * ixgbe_set_rate_select_speed - Set module link speed 1712 * @hw: pointer to hardware structure 1713 * @speed: link speed to set 1714 * 1715 * Set module link speed via the rate select. 1716 */ 1717 void ixgbe_set_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed) 1718 { 1719 if (hw->mac.ops.set_rate_select_speed) 1720 hw->mac.ops.set_rate_select_speed(hw, speed); 1721 } 1722