1 /* $NetBSD: ixgbe_api.c,v 1.28 2022/06/06 02:16:37 msaitoh Exp $ */ 2 3 /****************************************************************************** 4 SPDX-License-Identifier: BSD-3-Clause 5 6 Copyright (c) 2001-2020, Intel Corporation 7 All rights reserved. 8 9 Redistribution and use in source and binary forms, with or without 10 modification, are permitted provided that the following conditions are met: 11 12 1. Redistributions of source code must retain the above copyright notice, 13 this list of conditions and the following disclaimer. 14 15 2. Redistributions in binary form must reproduce the above copyright 16 notice, this list of conditions and the following disclaimer in the 17 documentation and/or other materials provided with the distribution. 18 19 3. Neither the name of the Intel Corporation nor the names of its 20 contributors may be used to endorse or promote products derived from 21 this software without specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 27 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 POSSIBILITY OF SUCH DAMAGE. 34 35 ******************************************************************************/ 36 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_api.c 331224 2018-03-19 20:55:05Z erj $*/ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: ixgbe_api.c,v 1.28 2022/06/06 02:16:37 msaitoh Exp $"); 40 41 #include "ixgbe_api.h" 42 #include "ixgbe_common.h" 43 44 #define IXGBE_EMPTY_PARAM 45 46 static const u32 ixgbe_mvals_base[IXGBE_MVALS_IDX_LIMIT] = { 47 IXGBE_MVALS_INIT(IXGBE_EMPTY_PARAM) 48 }; 49 50 static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = { 51 IXGBE_MVALS_INIT(_X540) 52 }; 53 54 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = { 55 IXGBE_MVALS_INIT(_X550) 56 }; 57 58 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = { 59 IXGBE_MVALS_INIT(_X550EM_x) 60 }; 61 62 static const u32 ixgbe_mvals_X550EM_a[IXGBE_MVALS_IDX_LIMIT] = { 63 IXGBE_MVALS_INIT(_X550EM_a) 64 }; 65 66 /** 67 * ixgbe_dcb_get_rtrup2tc - read rtrup2tc reg 68 * @hw: pointer to hardware structure 69 * @map: pointer to u8 arr for returning map 70 * 71 * Read the rtrup2tc HW register and resolve its content into map 72 **/ 73 void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map) 74 { 75 if (hw->mac.ops.get_rtrup2tc) 76 hw->mac.ops.get_rtrup2tc(hw, map); 77 } 78 79 /** 80 * ixgbe_init_shared_code - Initialize the shared code 81 * @hw: pointer to hardware structure 82 * 83 * This will assign function pointers and assign the MAC type and PHY code. 84 * Does not touch the hardware. This function must be called prior to any 85 * other function in the shared code. The ixgbe_hw structure should be 86 * memset to 0 prior to calling this function. The following fields in 87 * hw structure should be filled in prior to calling this function: 88 * back, device_id, vendor_id, subsystem_device_id, 89 * subsystem_vendor_id, and revision_id 90 **/ 91 s32 ixgbe_init_shared_code(struct ixgbe_hw *hw) 92 { 93 s32 status; 94 95 DEBUGFUNC("ixgbe_init_shared_code"); 96 97 /* 98 * Set the mac type 99 */ 100 ixgbe_set_mac_type(hw); 101 102 switch (hw->mac.type) { 103 case ixgbe_mac_82598EB: 104 status = ixgbe_init_ops_82598(hw); 105 break; 106 case ixgbe_mac_82599EB: 107 status = ixgbe_init_ops_82599(hw); 108 break; 109 case ixgbe_mac_X540: 110 status = ixgbe_init_ops_X540(hw); 111 break; 112 case ixgbe_mac_X550: 113 status = ixgbe_init_ops_X550(hw); 114 break; 115 case ixgbe_mac_X550EM_x: 116 status = ixgbe_init_ops_X550EM_x(hw); 117 break; 118 case ixgbe_mac_X550EM_a: 119 status = ixgbe_init_ops_X550EM_a(hw); 120 break; 121 default: 122 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 123 break; 124 } 125 hw->mac.max_link_up_time = IXGBE_LINK_UP_TIME; 126 127 return status; 128 } 129 130 /** 131 * ixgbe_set_mac_type - Sets MAC type 132 * @hw: pointer to the HW structure 133 * 134 * This function sets the mac type of the adapter based on the 135 * vendor ID and device ID stored in the hw structure. 136 **/ 137 s32 ixgbe_set_mac_type(struct ixgbe_hw *hw) 138 { 139 s32 ret_val = IXGBE_SUCCESS; 140 141 DEBUGFUNC("ixgbe_set_mac_type\n"); 142 143 if (hw->vendor_id != IXGBE_INTEL_VENDOR_ID) { 144 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 145 "Unsupported vendor id: %x", hw->vendor_id); 146 return IXGBE_ERR_DEVICE_NOT_SUPPORTED; 147 } 148 149 hw->mvals = ixgbe_mvals_base; 150 151 switch (hw->device_id) { 152 case IXGBE_DEV_ID_82598: 153 case IXGBE_DEV_ID_82598_BX: 154 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 155 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 156 case IXGBE_DEV_ID_82598AT: 157 case IXGBE_DEV_ID_82598AT2: 158 case IXGBE_DEV_ID_82598EB_CX4: 159 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 160 case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 161 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 162 case IXGBE_DEV_ID_82598EB_XF_LR: 163 case IXGBE_DEV_ID_82598EB_SFP_LOM: 164 hw->mac.type = ixgbe_mac_82598EB; 165 break; 166 case IXGBE_DEV_ID_82599_KX4: 167 case IXGBE_DEV_ID_82599_KX4_MEZZ: 168 case IXGBE_DEV_ID_82599_XAUI_LOM: 169 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 170 case IXGBE_DEV_ID_82599_KR: 171 case IXGBE_DEV_ID_82599_SFP: 172 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 173 case IXGBE_DEV_ID_82599_SFP_FCOE: 174 case IXGBE_DEV_ID_82599_SFP_EM: 175 case IXGBE_DEV_ID_82599_SFP_SF2: 176 case IXGBE_DEV_ID_82599_SFP_SF_QP: 177 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 178 case IXGBE_DEV_ID_82599EN_SFP: 179 case IXGBE_DEV_ID_82599_CX4: 180 case IXGBE_DEV_ID_82599_BYPASS: 181 case IXGBE_DEV_ID_82599_T3_LOM: 182 hw->mac.type = ixgbe_mac_82599EB; 183 break; 184 case IXGBE_DEV_ID_X540T: 185 case IXGBE_DEV_ID_X540T1: 186 case IXGBE_DEV_ID_X540_BYPASS: 187 hw->mac.type = ixgbe_mac_X540; 188 hw->mvals = ixgbe_mvals_X540; 189 break; 190 case IXGBE_DEV_ID_X550T: 191 case IXGBE_DEV_ID_X550T1: 192 hw->mac.type = ixgbe_mac_X550; 193 hw->mvals = ixgbe_mvals_X550; 194 break; 195 case IXGBE_DEV_ID_X550EM_X_KX4: 196 case IXGBE_DEV_ID_X550EM_X_KR: 197 case IXGBE_DEV_ID_X550EM_X_10G_T: 198 case IXGBE_DEV_ID_X550EM_X_1G_T: 199 case IXGBE_DEV_ID_X550EM_X_SFP: 200 case IXGBE_DEV_ID_X550EM_X_XFI: 201 hw->mac.type = ixgbe_mac_X550EM_x; 202 hw->mvals = ixgbe_mvals_X550EM_x; 203 break; 204 case IXGBE_DEV_ID_X550EM_A_KR: 205 case IXGBE_DEV_ID_X550EM_A_KR_L: 206 case IXGBE_DEV_ID_X550EM_A_SFP_N: 207 case IXGBE_DEV_ID_X550EM_A_SGMII: 208 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 209 case IXGBE_DEV_ID_X550EM_A_1G_T: 210 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 211 case IXGBE_DEV_ID_X550EM_A_10G_T: 212 case IXGBE_DEV_ID_X550EM_A_QSFP: 213 case IXGBE_DEV_ID_X550EM_A_QSFP_N: 214 case IXGBE_DEV_ID_X550EM_A_SFP: 215 hw->mac.type = ixgbe_mac_X550EM_a; 216 hw->mvals = ixgbe_mvals_X550EM_a; 217 break; 218 default: 219 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 220 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 221 "Unsupported device id: %x", 222 hw->device_id); 223 break; 224 } 225 226 DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n", 227 hw->mac.type, ret_val); 228 return ret_val; 229 } 230 231 /** 232 * ixgbe_init_hw - Initialize the hardware 233 * @hw: pointer to hardware structure 234 * 235 * Initialize the hardware by resetting and then starting the hardware 236 **/ 237 s32 ixgbe_init_hw(struct ixgbe_hw *hw) 238 { 239 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw), 240 IXGBE_NOT_IMPLEMENTED); 241 } 242 243 /** 244 * ixgbe_reset_hw - Performs a hardware reset 245 * @hw: pointer to hardware structure 246 * 247 * Resets the hardware by resetting the transmit and receive units, masks and 248 * clears all interrupts, performs a PHY reset, and performs a MAC reset 249 **/ 250 s32 ixgbe_reset_hw(struct ixgbe_hw *hw) 251 { 252 return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw), 253 IXGBE_NOT_IMPLEMENTED); 254 } 255 256 /** 257 * ixgbe_start_hw - Prepares hardware for Rx/Tx 258 * @hw: pointer to hardware structure 259 * 260 * Starts the hardware by filling the bus info structure and media type, 261 * clears all on chip counters, initializes receive address registers, 262 * multicast table, VLAN filter table, calls routine to setup link and 263 * flow control settings, and leaves transmit and receive units disabled 264 * and uninitialized. 265 **/ 266 s32 ixgbe_start_hw(struct ixgbe_hw *hw) 267 { 268 return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw), 269 IXGBE_NOT_IMPLEMENTED); 270 } 271 272 /** 273 * ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering, 274 * which is disabled by default in ixgbe_start_hw(); 275 * 276 * @hw: pointer to hardware structure 277 * 278 * Enable relaxed ordering; 279 **/ 280 void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw) 281 { 282 if (hw->mac.ops.enable_relaxed_ordering) 283 hw->mac.ops.enable_relaxed_ordering(hw); 284 } 285 286 /** 287 * ixgbe_clear_hw_cntrs - Clear hardware counters 288 * @hw: pointer to hardware structure 289 * 290 * Clears all hardware statistics counters by reading them from the hardware 291 * Statistics counters are clear on read. 292 **/ 293 s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw) 294 { 295 return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw), 296 IXGBE_NOT_IMPLEMENTED); 297 } 298 299 /** 300 * ixgbe_get_media_type - Get media type 301 * @hw: pointer to hardware structure 302 * 303 * Returns the media type (fiber, copper, backplane) 304 **/ 305 enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw) 306 { 307 return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw), 308 ixgbe_media_type_unknown); 309 } 310 311 /** 312 * ixgbe_get_mac_addr - Get MAC address 313 * @hw: pointer to hardware structure 314 * @mac_addr: Adapter MAC address 315 * 316 * Reads the adapter's MAC address from the first Receive Address Register 317 * (RAR0) A reset of the adapter must have been performed prior to calling 318 * this function in order for the MAC address to have been loaded from the 319 * EEPROM into RAR0 320 **/ 321 s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr) 322 { 323 return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr, 324 (hw, mac_addr), IXGBE_NOT_IMPLEMENTED); 325 } 326 327 /** 328 * ixgbe_get_san_mac_addr - Get SAN MAC address 329 * @hw: pointer to hardware structure 330 * @san_mac_addr: SAN MAC address 331 * 332 * Reads the SAN MAC address from the EEPROM, if it's available. This is 333 * per-port, so set_lan_id() must be called before reading the addresses. 334 **/ 335 s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 336 { 337 return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr, 338 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 339 } 340 341 /** 342 * ixgbe_set_san_mac_addr - Write a SAN MAC address 343 * @hw: pointer to hardware structure 344 * @san_mac_addr: SAN MAC address 345 * 346 * Writes A SAN MAC address to the EEPROM. 347 **/ 348 s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 349 { 350 return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr, 351 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 352 } 353 354 /** 355 * ixgbe_get_device_caps - Get additional device capabilities 356 * @hw: pointer to hardware structure 357 * @device_caps: the EEPROM word for device capabilities 358 * 359 * Reads the extra device capabilities from the EEPROM 360 **/ 361 s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps) 362 { 363 return ixgbe_call_func(hw, hw->mac.ops.get_device_caps, 364 (hw, device_caps), IXGBE_NOT_IMPLEMENTED); 365 } 366 367 /** 368 * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM 369 * @hw: pointer to hardware structure 370 * @wwnn_prefix: the alternative WWNN prefix 371 * @wwpn_prefix: the alternative WWPN prefix 372 * 373 * This function will read the EEPROM from the alternative SAN MAC address 374 * block to check the support for the alternative WWNN/WWPN prefix support. 375 **/ 376 s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix, 377 u16 *wwpn_prefix) 378 { 379 return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix, 380 (hw, wwnn_prefix, wwpn_prefix), 381 IXGBE_NOT_IMPLEMENTED); 382 } 383 384 /** 385 * ixgbe_get_fcoe_boot_status - Get FCOE boot status from EEPROM 386 * @hw: pointer to hardware structure 387 * @bs: the fcoe boot status 388 * 389 * This function will read the FCOE boot status from the iSCSI FCOE block 390 **/ 391 s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs) 392 { 393 return ixgbe_call_func(hw, hw->mac.ops.get_fcoe_boot_status, 394 (hw, bs), 395 IXGBE_NOT_IMPLEMENTED); 396 } 397 398 /** 399 * ixgbe_get_bus_info - Set PCI bus info 400 * @hw: pointer to hardware structure 401 * 402 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 403 **/ 404 s32 ixgbe_get_bus_info(struct ixgbe_hw *hw) 405 { 406 return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw), 407 IXGBE_NOT_IMPLEMENTED); 408 } 409 410 /** 411 * ixgbe_get_num_of_tx_queues - Get Tx queues 412 * @hw: pointer to hardware structure 413 * 414 * Returns the number of transmit queues for the given adapter. 415 **/ 416 u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw) 417 { 418 return hw->mac.max_tx_queues; 419 } 420 421 /** 422 * ixgbe_get_num_of_rx_queues - Get Rx queues 423 * @hw: pointer to hardware structure 424 * 425 * Returns the number of receive queues for the given adapter. 426 **/ 427 u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw) 428 { 429 return hw->mac.max_rx_queues; 430 } 431 432 /** 433 * ixgbe_stop_adapter - Disable Rx/Tx units 434 * @hw: pointer to hardware structure 435 * 436 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 437 * disables transmit and receive units. The adapter_stopped flag is used by 438 * the shared code and drivers to determine if the adapter is in a stopped 439 * state and should not touch the hardware. 440 **/ 441 s32 ixgbe_stop_adapter(struct ixgbe_hw *hw) 442 { 443 return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw), 444 IXGBE_NOT_IMPLEMENTED); 445 } 446 447 /** 448 * ixgbe_read_pba_string - Reads part number string from EEPROM 449 * @hw: pointer to hardware structure 450 * @pba_num: stores the part number string from the EEPROM 451 * @pba_num_size: part number string buffer length 452 * 453 * Reads the part number string from the EEPROM. 454 **/ 455 s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size) 456 { 457 return ixgbe_read_pba_string_generic(hw, pba_num, pba_num_size); 458 } 459 460 /** 461 * ixgbe_read_pba_num - Reads part number from EEPROM 462 * @hw: pointer to hardware structure 463 * @pba_num: stores the part number from the EEPROM 464 * 465 * Reads the part number from the EEPROM. 466 **/ 467 s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num) 468 { 469 return ixgbe_read_pba_num_generic(hw, pba_num); 470 } 471 472 /** 473 * ixgbe_identify_phy - Get PHY type 474 * @hw: pointer to hardware structure 475 * 476 * Determines the physical layer module found on the current adapter. 477 **/ 478 s32 ixgbe_identify_phy(struct ixgbe_hw *hw) 479 { 480 s32 status = IXGBE_SUCCESS; 481 482 if (hw->phy.type == ixgbe_phy_unknown) { 483 status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw), 484 IXGBE_NOT_IMPLEMENTED); 485 } 486 487 return status; 488 } 489 490 /** 491 * ixgbe_reset_phy - Perform a PHY reset 492 * @hw: pointer to hardware structure 493 **/ 494 s32 ixgbe_reset_phy(struct ixgbe_hw *hw) 495 { 496 s32 status = IXGBE_SUCCESS; 497 498 if (hw->phy.type == ixgbe_phy_unknown) { 499 if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS) 500 status = IXGBE_ERR_PHY; 501 } 502 503 if (status == IXGBE_SUCCESS) { 504 status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw), 505 IXGBE_NOT_IMPLEMENTED); 506 } 507 return status; 508 } 509 510 /** 511 * ixgbe_get_phy_firmware_version - 512 * @hw: pointer to hardware structure 513 * @firmware_version: pointer to firmware version 514 **/ 515 s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version) 516 { 517 s32 status = IXGBE_SUCCESS; 518 519 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version, 520 (hw, firmware_version), 521 IXGBE_NOT_IMPLEMENTED); 522 return status; 523 } 524 525 /** 526 * ixgbe_read_phy_reg - Read PHY register 527 * @hw: pointer to hardware structure 528 * @reg_addr: 32 bit address of PHY register to read 529 * @device_type: type of device you want to communicate with 530 * @phy_data: Pointer to read data from PHY register 531 * 532 * Reads a value from a specified PHY register 533 **/ 534 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 535 u16 *phy_data) 536 { 537 if (hw->phy.id == 0) 538 ixgbe_identify_phy(hw); 539 540 return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr, 541 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 542 } 543 544 /** 545 * ixgbe_write_phy_reg - Write PHY register 546 * @hw: pointer to hardware structure 547 * @reg_addr: 32 bit PHY register to write 548 * @device_type: type of device you want to communicate with 549 * @phy_data: Data to write to the PHY register 550 * 551 * Writes a value to specified PHY register 552 **/ 553 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 554 u16 phy_data) 555 { 556 if (hw->phy.id == 0) 557 ixgbe_identify_phy(hw); 558 559 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr, 560 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 561 } 562 563 /** 564 * ixgbe_setup_phy_link - Restart PHY autoneg 565 * @hw: pointer to hardware structure 566 * 567 * Restart autonegotiation and PHY and waits for completion. 568 **/ 569 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw) 570 { 571 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw), 572 IXGBE_NOT_IMPLEMENTED); 573 } 574 575 /** 576 * ixgbe_setup_internal_phy - Configure integrated PHY 577 * @hw: pointer to hardware structure 578 * 579 * Reconfigure the integrated PHY in order to enable talk to the external PHY. 580 * Returns success if not implemented, since nothing needs to be done in this 581 * case. 582 */ 583 s32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw) 584 { 585 return ixgbe_call_func(hw, hw->phy.ops.setup_internal_link, (hw), 586 IXGBE_SUCCESS); 587 } 588 589 /** 590 * ixgbe_check_phy_link - Determine link and speed status 591 * @hw: pointer to hardware structure 592 * @speed: link speed 593 * @link_up: TRUE when link is up 594 * 595 * Reads a PHY register to determine if link is up and the current speed for 596 * the PHY. 597 **/ 598 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 599 bool *link_up) 600 { 601 return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed, 602 link_up), IXGBE_NOT_IMPLEMENTED); 603 } 604 605 /** 606 * ixgbe_setup_phy_link_speed - Set auto advertise 607 * @hw: pointer to hardware structure 608 * @speed: new link speed 609 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 610 * 611 * Sets the auto advertised capabilities 612 **/ 613 s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed, 614 bool autoneg_wait_to_complete) 615 { 616 return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed, 617 autoneg_wait_to_complete), 618 IXGBE_NOT_IMPLEMENTED); 619 } 620 621 /** 622 * ixgbe_set_phy_power - Control the phy power state 623 * @hw: pointer to hardware structure 624 * @on: TRUE for on, FALSE for off 625 */ 626 s32 ixgbe_set_phy_power(struct ixgbe_hw *hw, bool on) 627 { 628 return ixgbe_call_func(hw, hw->phy.ops.set_phy_power, (hw, on), 629 IXGBE_NOT_IMPLEMENTED); 630 } 631 632 /** 633 * ixgbe_check_link - Get link and speed status 634 * @hw: pointer to hardware structure 635 * @speed: pointer to link speed 636 * @link_up: TRUE when link is up 637 * @link_up_wait_to_complete: bool used to wait for link up or not 638 * 639 * Reads the links register to determine if link is up and the current speed 640 **/ 641 s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 642 bool *link_up, bool link_up_wait_to_complete) 643 { 644 return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed, 645 link_up, link_up_wait_to_complete), 646 IXGBE_NOT_IMPLEMENTED); 647 } 648 649 /** 650 * ixgbe_disable_tx_laser - Disable Tx laser 651 * @hw: pointer to hardware structure 652 * 653 * If the driver needs to disable the laser on SFI optics. 654 **/ 655 void ixgbe_disable_tx_laser(struct ixgbe_hw *hw) 656 { 657 if (hw->mac.ops.disable_tx_laser) 658 hw->mac.ops.disable_tx_laser(hw); 659 } 660 661 /** 662 * ixgbe_enable_tx_laser - Enable Tx laser 663 * @hw: pointer to hardware structure 664 * 665 * If the driver needs to enable the laser on SFI optics. 666 **/ 667 void ixgbe_enable_tx_laser(struct ixgbe_hw *hw) 668 { 669 if (hw->mac.ops.enable_tx_laser) 670 hw->mac.ops.enable_tx_laser(hw); 671 } 672 673 /** 674 * ixgbe_flap_tx_laser - flap Tx laser to start autotry process 675 * @hw: pointer to hardware structure 676 * 677 * When the driver changes the link speeds that it can support then 678 * flap the tx laser to alert the link partner to start autotry 679 * process on its end. 680 **/ 681 void ixgbe_flap_tx_laser(struct ixgbe_hw *hw) 682 { 683 if (hw->mac.ops.flap_tx_laser) 684 hw->mac.ops.flap_tx_laser(hw); 685 } 686 687 /** 688 * ixgbe_setup_link - Set link speed 689 * @hw: pointer to hardware structure 690 * @speed: new link speed 691 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 692 * 693 * Configures link settings. Restarts the link. 694 * Performs autonegotiation if needed. 695 **/ 696 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 697 bool autoneg_wait_to_complete) 698 { 699 return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed, 700 autoneg_wait_to_complete), 701 IXGBE_NOT_IMPLEMENTED); 702 } 703 704 /** 705 * ixgbe_setup_mac_link - Set link speed 706 * @hw: pointer to hardware structure 707 * @speed: new link speed 708 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 709 * 710 * Configures link settings. Restarts the link. 711 * Performs autonegotiation if needed. 712 **/ 713 s32 ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 714 bool autoneg_wait_to_complete) 715 { 716 return ixgbe_call_func(hw, hw->mac.ops.setup_mac_link, (hw, speed, 717 autoneg_wait_to_complete), 718 IXGBE_NOT_IMPLEMENTED); 719 } 720 721 /** 722 * ixgbe_get_link_capabilities - Returns link capabilities 723 * @hw: pointer to hardware structure 724 * @speed: link speed capabilities 725 * @autoneg: TRUE when autoneg or autotry is enabled 726 * 727 * Determines the link capabilities of the current configuration. 728 **/ 729 s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 730 bool *autoneg) 731 { 732 return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw, 733 speed, autoneg), IXGBE_NOT_IMPLEMENTED); 734 } 735 736 /** 737 * ixgbe_led_on - Turn on LEDs 738 * @hw: pointer to hardware structure 739 * @index: led number to turn on 740 * 741 * Turns on the software controllable LEDs. 742 **/ 743 s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index) 744 { 745 return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index), 746 IXGBE_NOT_IMPLEMENTED); 747 } 748 749 /** 750 * ixgbe_led_off - Turn off LEDs 751 * @hw: pointer to hardware structure 752 * @index: led number to turn off 753 * 754 * Turns off the software controllable LEDs. 755 **/ 756 s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index) 757 { 758 return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index), 759 IXGBE_NOT_IMPLEMENTED); 760 } 761 762 /** 763 * ixgbe_blink_led_start - Blink LEDs 764 * @hw: pointer to hardware structure 765 * @index: led number to blink 766 * 767 * Blink LED based on index. 768 **/ 769 s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index) 770 { 771 return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index), 772 IXGBE_NOT_IMPLEMENTED); 773 } 774 775 /** 776 * ixgbe_blink_led_stop - Stop blinking LEDs 777 * @hw: pointer to hardware structure 778 * @index: led number to stop 779 * 780 * Stop blinking LED based on index. 781 **/ 782 s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index) 783 { 784 return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index), 785 IXGBE_NOT_IMPLEMENTED); 786 } 787 788 /** 789 * ixgbe_init_eeprom_params - Initialize EEPROM parameters 790 * @hw: pointer to hardware structure 791 * 792 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 793 * ixgbe_hw struct in order to set up EEPROM access. 794 **/ 795 s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw) 796 { 797 return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw), 798 IXGBE_NOT_IMPLEMENTED); 799 } 800 801 802 /** 803 * ixgbe_write_eeprom - Write word to EEPROM 804 * @hw: pointer to hardware structure 805 * @offset: offset within the EEPROM to be written to 806 * @data: 16 bit word to be written to the EEPROM 807 * 808 * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not 809 * called after this function, the EEPROM will most likely contain an 810 * invalid checksum. 811 **/ 812 s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data) 813 { 814 return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data), 815 IXGBE_NOT_IMPLEMENTED); 816 } 817 818 /** 819 * ixgbe_write_eeprom_buffer - Write word(s) to EEPROM 820 * @hw: pointer to hardware structure 821 * @offset: offset within the EEPROM to be written to 822 * @data: 16 bit word(s) to be written to the EEPROM 823 * @words: number of words 824 * 825 * Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not 826 * called after this function, the EEPROM will most likely contain an 827 * invalid checksum. 828 **/ 829 s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, u16 words, 830 u16 *data) 831 { 832 return ixgbe_call_func(hw, hw->eeprom.ops.write_buffer, 833 (hw, offset, words, data), 834 IXGBE_NOT_IMPLEMENTED); 835 } 836 837 /** 838 * ixgbe_read_eeprom - Read word from EEPROM 839 * @hw: pointer to hardware structure 840 * @offset: offset within the EEPROM to be read 841 * @data: read 16 bit value from EEPROM 842 * 843 * Reads 16 bit value from EEPROM 844 **/ 845 s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data) 846 { 847 return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data), 848 IXGBE_NOT_IMPLEMENTED); 849 } 850 851 /** 852 * ixgbe_read_eeprom_buffer - Read word(s) from EEPROM 853 * @hw: pointer to hardware structure 854 * @offset: offset within the EEPROM to be read 855 * @data: read 16 bit word(s) from EEPROM 856 * @words: number of words 857 * 858 * Reads 16 bit word(s) from EEPROM 859 **/ 860 s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, 861 u16 words, u16 *data) 862 { 863 return ixgbe_call_func(hw, hw->eeprom.ops.read_buffer, 864 (hw, offset, words, data), 865 IXGBE_NOT_IMPLEMENTED); 866 } 867 868 /** 869 * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum 870 * @hw: pointer to hardware structure 871 * @checksum_val: calculated checksum 872 * 873 * Performs checksum calculation and validates the EEPROM checksum 874 **/ 875 s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val) 876 { 877 return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum, 878 (hw, checksum_val), IXGBE_NOT_IMPLEMENTED); 879 } 880 881 /** 882 * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum 883 * @hw: pointer to hardware structure 884 **/ 885 s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw) 886 { 887 return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw), 888 IXGBE_NOT_IMPLEMENTED); 889 } 890 891 /** 892 * ixgbe_insert_mac_addr - Find a RAR for this mac address 893 * @hw: pointer to hardware structure 894 * @addr: Address to put into receive address register 895 * @vmdq: VMDq pool to assign 896 * 897 * Puts an ethernet address into a receive address register, or 898 * finds the rar that it is already in; adds to the pool list 899 **/ 900 s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 901 { 902 return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr, 903 (hw, addr, vmdq), 904 IXGBE_NOT_IMPLEMENTED); 905 } 906 907 /** 908 * ixgbe_set_rar - Set Rx address register 909 * @hw: pointer to hardware structure 910 * @index: Receive address register to write 911 * @addr: Address to put into receive address register 912 * @vmdq: VMDq "set" 913 * @enable_addr: set flag that address is active 914 * 915 * Puts an ethernet address into a receive address register. 916 **/ 917 s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 918 u32 enable_addr) 919 { 920 return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq, 921 enable_addr), IXGBE_NOT_IMPLEMENTED); 922 } 923 924 /** 925 * ixgbe_clear_rar - Clear Rx address register 926 * @hw: pointer to hardware structure 927 * @index: Receive address register to write 928 * 929 * Puts an ethernet address into a receive address register. 930 **/ 931 s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index) 932 { 933 return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index), 934 IXGBE_NOT_IMPLEMENTED); 935 } 936 937 /** 938 * ixgbe_set_vmdq - Associate a VMDq index with a receive address 939 * @hw: pointer to hardware structure 940 * @rar: receive address register index to associate with VMDq index 941 * @vmdq: VMDq set or pool index 942 **/ 943 s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 944 { 945 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq), 946 IXGBE_NOT_IMPLEMENTED); 947 948 } 949 950 /** 951 * ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address 952 * @hw: pointer to hardware structure 953 * @vmdq: VMDq default pool index 954 **/ 955 s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq) 956 { 957 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq_san_mac, 958 (hw, vmdq), IXGBE_NOT_IMPLEMENTED); 959 } 960 961 /** 962 * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address 963 * @hw: pointer to hardware structure 964 * @rar: receive address register index to disassociate with VMDq index 965 * @vmdq: VMDq set or pool index 966 **/ 967 s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 968 { 969 return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq), 970 IXGBE_NOT_IMPLEMENTED); 971 } 972 973 /** 974 * ixgbe_init_rx_addrs - Initializes receive address filters. 975 * @hw: pointer to hardware structure 976 * 977 * Places the MAC address in receive address register 0 and clears the rest 978 * of the receive address registers. Clears the multicast table. Assumes 979 * the receiver is in reset when the routine is called. 980 **/ 981 s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw) 982 { 983 return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw), 984 IXGBE_NOT_IMPLEMENTED); 985 } 986 987 /** 988 * ixgbe_get_num_rx_addrs - Returns the number of RAR entries. 989 * @hw: pointer to hardware structure 990 **/ 991 u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw) 992 { 993 return hw->mac.num_rar_entries; 994 } 995 996 /** 997 * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses 998 * @hw: pointer to hardware structure 999 * @addr_list: the list of new multicast addresses 1000 * @addr_count: number of addresses 1001 * @func: iterator function to walk the multicast address list 1002 * 1003 * The given list replaces any existing list. Clears the secondary addrs from 1004 * receive address registers. Uses unused receive address registers for the 1005 * first secondary addresses, and falls back to promiscuous mode as needed. 1006 **/ 1007 s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, 1008 u32 addr_count, ixgbe_mc_addr_itr func) 1009 { 1010 return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw, 1011 addr_list, addr_count, func), 1012 IXGBE_NOT_IMPLEMENTED); 1013 } 1014 1015 /** 1016 * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses 1017 * @hw: pointer to hardware structure 1018 * @mc_addr_list: the list of new multicast addresses 1019 * @mc_addr_count: number of addresses 1020 * @func: iterator function to walk the multicast address list 1021 * @clear: flag, when set clears the table beforehand 1022 * 1023 * The given list replaces any existing list. Clears the MC addrs from receive 1024 * address registers and the multicast table. Uses unused receive address 1025 * registers for the first multicast addresses, and hashes the rest into the 1026 * multicast table. 1027 **/ 1028 s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, 1029 u32 mc_addr_count, ixgbe_mc_addr_itr func, 1030 bool clear) 1031 { 1032 return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw, 1033 mc_addr_list, mc_addr_count, func, clear), 1034 IXGBE_NOT_IMPLEMENTED); 1035 } 1036 1037 /** 1038 * ixgbe_enable_mc - Enable multicast address in RAR 1039 * @hw: pointer to hardware structure 1040 * 1041 * Enables multicast address in RAR and the use of the multicast hash table. 1042 **/ 1043 s32 ixgbe_enable_mc(struct ixgbe_hw *hw) 1044 { 1045 return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw), 1046 IXGBE_NOT_IMPLEMENTED); 1047 } 1048 1049 /** 1050 * ixgbe_disable_mc - Disable multicast address in RAR 1051 * @hw: pointer to hardware structure 1052 * 1053 * Disables multicast address in RAR and the use of the multicast hash table. 1054 **/ 1055 s32 ixgbe_disable_mc(struct ixgbe_hw *hw) 1056 { 1057 return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw), 1058 IXGBE_NOT_IMPLEMENTED); 1059 } 1060 1061 /** 1062 * ixgbe_clear_vfta - Clear VLAN filter table 1063 * @hw: pointer to hardware structure 1064 * 1065 * Clears the VLAN filter table, and the VMDq index associated with the filter 1066 **/ 1067 s32 ixgbe_clear_vfta(struct ixgbe_hw *hw) 1068 { 1069 return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw), 1070 IXGBE_NOT_IMPLEMENTED); 1071 } 1072 1073 /** 1074 * ixgbe_set_vfta - Set VLAN filter table 1075 * @hw: pointer to hardware structure 1076 * @vlan: VLAN id to write to VLAN filter 1077 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 1078 * @vlan_on: boolean flag to turn on/off VLAN 1079 * @vlvf_bypass: boolean flag indicating updating the default pool is okay 1080 * 1081 * Turn on/off specified VLAN in the VLAN filter table. 1082 **/ 1083 s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, 1084 bool vlvf_bypass) 1085 { 1086 return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind, 1087 vlan_on, vlvf_bypass), IXGBE_NOT_IMPLEMENTED); 1088 } 1089 1090 /** 1091 * ixgbe_set_vlvf - Set VLAN Pool Filter 1092 * @hw: pointer to hardware structure 1093 * @vlan: VLAN id to write to VLAN filter 1094 * @vind: VMDq output index that maps queue to VLAN id in VLVFB 1095 * @vlan_on: boolean flag to turn on/off VLAN in VLVF 1096 * @vfta_delta: pointer to the difference between the current value of VFTA 1097 * and the desired value 1098 * @vfta: the desired value of the VFTA 1099 * @vlvf_bypass: boolean flag indicating updating the default pool is okay 1100 * 1101 * Turn on/off specified bit in VLVF table. 1102 **/ 1103 s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, 1104 u32 *vfta_delta, u32 vfta, bool vlvf_bypass) 1105 { 1106 return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind, 1107 vlan_on, vfta_delta, vfta, vlvf_bypass), 1108 IXGBE_NOT_IMPLEMENTED); 1109 } 1110 1111 /** 1112 * ixgbe_toggle_txdctl - Toggle VF's queues 1113 * @hw: pointer to hardware structure 1114 * @vind: VMDq pool index 1115 * 1116 * Enable and disable each queue in VF. 1117 */ 1118 s32 ixgbe_toggle_txdctl(struct ixgbe_hw *hw, u32 vind) 1119 { 1120 return ixgbe_call_func(hw, hw->mac.ops.toggle_txdctl, (hw, 1121 vind), IXGBE_NOT_IMPLEMENTED); 1122 } 1123 1124 /** 1125 * ixgbe_fc_enable - Enable flow control 1126 * @hw: pointer to hardware structure 1127 * 1128 * Configures the flow control settings based on SW configuration. 1129 **/ 1130 s32 ixgbe_fc_enable(struct ixgbe_hw *hw) 1131 { 1132 return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw), 1133 IXGBE_NOT_IMPLEMENTED); 1134 } 1135 1136 /** 1137 * ixgbe_setup_fc - Set up flow control 1138 * @hw: pointer to hardware structure 1139 * 1140 * Called at init time to set up flow control. 1141 **/ 1142 s32 ixgbe_setup_fc(struct ixgbe_hw *hw) 1143 { 1144 return ixgbe_call_func(hw, hw->mac.ops.setup_fc, (hw), 1145 IXGBE_NOT_IMPLEMENTED); 1146 } 1147 1148 /** 1149 * ixgbe_set_fw_drv_ver - Try to send the driver version number FW 1150 * @hw: pointer to hardware structure 1151 * @maj: driver major number to be sent to firmware 1152 * @minr: driver minor number to be sent to firmware 1153 * @build: driver build number to be sent to firmware 1154 * @ver: driver version number to be sent to firmware 1155 * @len: length of driver_ver string 1156 * @driver_ver: driver string 1157 **/ 1158 s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 minr, u8 build, 1159 u8 ver, u16 len, char *driver_ver) 1160 { 1161 return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, minr, 1162 build, ver, len, driver_ver), 1163 IXGBE_NOT_IMPLEMENTED); 1164 } 1165 1166 1167 1168 /** 1169 * ixgbe_dmac_config - Configure DMA Coalescing registers. 1170 * @hw: pointer to hardware structure 1171 * 1172 * Configure DMA coalescing. If enabling dmac, dmac is activated. 1173 * When disabling dmac, dmac enable dmac bit is cleared. 1174 **/ 1175 s32 ixgbe_dmac_config(struct ixgbe_hw *hw) 1176 { 1177 return ixgbe_call_func(hw, hw->mac.ops.dmac_config, (hw), 1178 IXGBE_NOT_IMPLEMENTED); 1179 } 1180 1181 /** 1182 * ixgbe_dmac_update_tcs - Configure DMA Coalescing registers. 1183 * @hw: pointer to hardware structure 1184 * 1185 * Disables dmac, updates per TC settings, and then enable dmac. 1186 **/ 1187 s32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw) 1188 { 1189 return ixgbe_call_func(hw, hw->mac.ops.dmac_update_tcs, (hw), 1190 IXGBE_NOT_IMPLEMENTED); 1191 } 1192 1193 /** 1194 * ixgbe_dmac_config_tcs - Configure DMA Coalescing registers. 1195 * @hw: pointer to hardware structure 1196 * 1197 * Configure DMA coalescing threshold per TC and set high priority bit for 1198 * FCOE TC. The dmac enable bit must be cleared before configuring. 1199 **/ 1200 s32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw) 1201 { 1202 return ixgbe_call_func(hw, hw->mac.ops.dmac_config_tcs, (hw), 1203 IXGBE_NOT_IMPLEMENTED); 1204 } 1205 1206 /** 1207 * ixgbe_setup_eee - Enable/disable EEE support 1208 * @hw: pointer to the HW structure 1209 * @enable_eee: boolean flag to enable EEE 1210 * 1211 * Enable/disable EEE based on enable_ee flag. 1212 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C 1213 * are modified. 1214 * 1215 **/ 1216 s32 ixgbe_setup_eee(struct ixgbe_hw *hw, bool enable_eee) 1217 { 1218 return ixgbe_call_func(hw, hw->mac.ops.setup_eee, (hw, enable_eee), 1219 IXGBE_NOT_IMPLEMENTED); 1220 } 1221 1222 /** 1223 * ixgbe_set_source_address_pruning - Enable/Disable source address pruning 1224 * @hw: pointer to hardware structure 1225 * @enable: enable or disable source address pruning 1226 * @pool: Rx pool - Rx pool to toggle source address pruning 1227 **/ 1228 void ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable, 1229 unsigned int pool) 1230 { 1231 if (hw->mac.ops.set_source_address_pruning) 1232 hw->mac.ops.set_source_address_pruning(hw, enable, pool); 1233 } 1234 1235 /** 1236 * ixgbe_set_ethertype_anti_spoofing - Enable/Disable Ethertype anti-spoofing 1237 * @hw: pointer to hardware structure 1238 * @enable: enable or disable switch for Ethertype anti-spoofing 1239 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 1240 * 1241 **/ 1242 void ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 1243 { 1244 if (hw->mac.ops.set_ethertype_anti_spoofing) 1245 hw->mac.ops.set_ethertype_anti_spoofing(hw, enable, vf); 1246 } 1247 1248 /** 1249 * ixgbe_read_iosf_sb_reg - Read 32 bit PHY register 1250 * @hw: pointer to hardware structure 1251 * @reg_addr: 32 bit address of PHY register to read 1252 * @device_type: type of device you want to communicate with 1253 * @phy_data: Pointer to read data from PHY register 1254 * 1255 * Reads a value from a specified PHY register 1256 **/ 1257 s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1258 u32 device_type, u32 *phy_data) 1259 { 1260 return ixgbe_call_func(hw, hw->mac.ops.read_iosf_sb_reg, (hw, reg_addr, 1261 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1262 } 1263 1264 /** 1265 * ixgbe_write_iosf_sb_reg - Write 32 bit register through IOSF Sideband 1266 * @hw: pointer to hardware structure 1267 * @reg_addr: 32 bit PHY register to write 1268 * @device_type: type of device you want to communicate with 1269 * @phy_data: Data to write to the PHY register 1270 * 1271 * Writes a value to specified PHY register 1272 **/ 1273 s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1274 u32 device_type, u32 phy_data) 1275 { 1276 return ixgbe_call_func(hw, hw->mac.ops.write_iosf_sb_reg, (hw, reg_addr, 1277 device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1278 } 1279 1280 /** 1281 * ixgbe_disable_mdd - Disable malicious driver detection 1282 * @hw: pointer to hardware structure 1283 * 1284 **/ 1285 void ixgbe_disable_mdd(struct ixgbe_hw *hw) 1286 { 1287 if (hw->mac.ops.disable_mdd) 1288 hw->mac.ops.disable_mdd(hw); 1289 } 1290 1291 /** 1292 * ixgbe_enable_mdd - Enable malicious driver detection 1293 * @hw: pointer to hardware structure 1294 * 1295 **/ 1296 void ixgbe_enable_mdd(struct ixgbe_hw *hw) 1297 { 1298 if (hw->mac.ops.enable_mdd) 1299 hw->mac.ops.enable_mdd(hw); 1300 } 1301 1302 /** 1303 * ixgbe_mdd_event - Handle malicious driver detection event 1304 * @hw: pointer to hardware structure 1305 * @vf_bitmap: vf bitmap of malicious vfs 1306 * 1307 **/ 1308 void ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap) 1309 { 1310 if (hw->mac.ops.mdd_event) 1311 hw->mac.ops.mdd_event(hw, vf_bitmap); 1312 } 1313 1314 /** 1315 * ixgbe_restore_mdd_vf - Restore VF that was disabled during malicious driver 1316 * detection event 1317 * @hw: pointer to hardware structure 1318 * @vf: vf index 1319 * 1320 **/ 1321 void ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf) 1322 { 1323 if (hw->mac.ops.restore_mdd_vf) 1324 hw->mac.ops.restore_mdd_vf(hw, vf); 1325 } 1326 1327 /** 1328 * ixgbe_fw_recovery_mode - Check if in FW NVM recovery mode 1329 * @hw: pointer to hardware structure 1330 * 1331 **/ 1332 bool ixgbe_fw_recovery_mode(struct ixgbe_hw *hw) 1333 { 1334 if (hw->mac.ops.fw_recovery_mode) 1335 return hw->mac.ops.fw_recovery_mode(hw); 1336 return FALSE; 1337 } 1338 1339 /** 1340 * ixgbe_enter_lplu - Transition to low power states 1341 * @hw: pointer to hardware structure 1342 * 1343 * Configures Low Power Link Up on transition to low power states 1344 * (from D0 to non-D0). 1345 **/ 1346 s32 ixgbe_enter_lplu(struct ixgbe_hw *hw) 1347 { 1348 return ixgbe_call_func(hw, hw->phy.ops.enter_lplu, (hw), 1349 IXGBE_NOT_IMPLEMENTED); 1350 } 1351 1352 /** 1353 * ixgbe_handle_lasi - Handle external Base T PHY interrupt 1354 * @hw: pointer to hardware structure 1355 * 1356 * Handle external Base T PHY interrupt. If high temperature 1357 * failure alarm then return error, else if link status change 1358 * then setup internal/external PHY link 1359 * 1360 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 1361 * failure alarm, else return PHY access status. 1362 */ 1363 s32 ixgbe_handle_lasi(struct ixgbe_hw *hw) 1364 { 1365 return ixgbe_call_func(hw, hw->phy.ops.handle_lasi, (hw), 1366 IXGBE_NOT_IMPLEMENTED); 1367 } 1368 1369 /** 1370 * ixgbe_bypass_rw - Bit bang data into by_pass FW 1371 * @hw: pointer to hardware structure 1372 * @cmd: Command we send to the FW 1373 * @status: The reply from the FW 1374 * 1375 * Bit-bangs the cmd to the by_pass FW status points to what is returned. 1376 **/ 1377 s32 ixgbe_bypass_rw(struct ixgbe_hw *hw, u32 cmd, u32 *status) 1378 { 1379 return ixgbe_call_func(hw, hw->mac.ops.bypass_rw, (hw, cmd, status), 1380 IXGBE_NOT_IMPLEMENTED); 1381 } 1382 1383 /** 1384 * ixgbe_bypass_valid_rd - Verify valid return from bit-bang. 1385 * @hw: pointer to hardware structure 1386 * @in_reg: The register cmd for the bit-bang read. 1387 * @out_reg: The register returned from a bit-bang read. 1388 * 1389 * If we send a write we can't be sure it took until we can read back 1390 * that same register. It can be a problem as some of the fields may 1391 * for valid reasons change in-between the time wrote the register and 1392 * we read it again to verify. So this function check everything we 1393 * can check and then assumes it worked. 1394 **/ 1395 bool ixgbe_bypass_valid_rd(struct ixgbe_hw *hw, u32 in_reg, u32 out_reg) 1396 { 1397 return ixgbe_call_func(hw, hw->mac.ops.bypass_valid_rd, 1398 (in_reg, out_reg), IXGBE_NOT_IMPLEMENTED); 1399 } 1400 1401 /** 1402 * ixgbe_bypass_set - Set a bypass field in the FW CTRL Register. 1403 * @hw: pointer to hardware structure 1404 * @cmd: The control word we are setting. 1405 * @event: The event we are setting in the FW. This also happens to 1406 * be the mask for the event we are setting (handy) 1407 * @action: The action we set the event to in the FW. This is in a 1408 * bit field that happens to be what we want to put in 1409 * the event spot (also handy) 1410 * 1411 * Writes to the cmd control the bits in actions. 1412 **/ 1413 s32 ixgbe_bypass_set(struct ixgbe_hw *hw, u32 cmd, u32 event, u32 action) 1414 { 1415 return ixgbe_call_func(hw, hw->mac.ops.bypass_set, 1416 (hw, cmd, event, action), 1417 IXGBE_NOT_IMPLEMENTED); 1418 } 1419 1420 /** 1421 * ixgbe_bypass_rd_eep - Read the bypass FW eeprom address 1422 * @hw: pointer to hardware structure 1423 * @addr: The bypass eeprom address to read. 1424 * @value: The 8b of data at the address above. 1425 **/ 1426 s32 ixgbe_bypass_rd_eep(struct ixgbe_hw *hw, u32 addr, u8 *value) 1427 { 1428 return ixgbe_call_func(hw, hw->mac.ops.bypass_rd_eep, 1429 (hw, addr, value), IXGBE_NOT_IMPLEMENTED); 1430 } 1431 1432 /** 1433 * ixgbe_read_analog_reg8 - Reads 8 bit analog register 1434 * @hw: pointer to hardware structure 1435 * @reg: analog register to read 1436 * @val: read value 1437 * 1438 * Performs write operation to analog register specified. 1439 **/ 1440 s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val) 1441 { 1442 return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg, 1443 val), IXGBE_NOT_IMPLEMENTED); 1444 } 1445 1446 /** 1447 * ixgbe_write_analog_reg8 - Writes 8 bit analog register 1448 * @hw: pointer to hardware structure 1449 * @reg: analog register to write 1450 * @val: value to write 1451 * 1452 * Performs write operation to Atlas analog register specified. 1453 **/ 1454 s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val) 1455 { 1456 return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg, 1457 val), IXGBE_NOT_IMPLEMENTED); 1458 } 1459 1460 /** 1461 * ixgbe_init_uta_tables - Initializes Unicast Table Arrays. 1462 * @hw: pointer to hardware structure 1463 * 1464 * Initializes the Unicast Table Arrays to zero on device load. This 1465 * is part of the Rx init addr execution path. 1466 **/ 1467 s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw) 1468 { 1469 return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw), 1470 IXGBE_NOT_IMPLEMENTED); 1471 } 1472 1473 /** 1474 * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address 1475 * @hw: pointer to hardware structure 1476 * @byte_offset: byte offset to read 1477 * @dev_addr: I2C bus address to read from 1478 * @data: value read 1479 * 1480 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1481 **/ 1482 s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1483 u8 *data) 1484 { 1485 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset, 1486 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1487 } 1488 1489 /** 1490 * ixgbe_read_i2c_byte_unlocked - Reads 8 bit word via I2C from device address 1491 * @hw: pointer to hardware structure 1492 * @byte_offset: byte offset to read 1493 * @dev_addr: I2C bus address to read from 1494 * @data: value read 1495 * 1496 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1497 **/ 1498 s32 ixgbe_read_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1499 u8 dev_addr, u8 *data) 1500 { 1501 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte_unlocked, 1502 (hw, byte_offset, dev_addr, data), 1503 IXGBE_NOT_IMPLEMENTED); 1504 } 1505 1506 /** 1507 * ixgbe_read_link - Perform read operation on link device 1508 * @hw: pointer to the hardware structure 1509 * @addr: bus address to read from 1510 * @reg: device register to read from 1511 * @val: pointer to location to receive read value 1512 * 1513 * Returns an error code on error. 1514 */ 1515 s32 ixgbe_read_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) 1516 { 1517 return ixgbe_call_func(hw, hw->link.ops.read_link, (hw, addr, 1518 reg, val), IXGBE_NOT_IMPLEMENTED); 1519 } 1520 1521 /** 1522 * ixgbe_read_link_unlocked - Perform read operation on link device 1523 * @hw: pointer to the hardware structure 1524 * @addr: bus address to read from 1525 * @reg: device register to read from 1526 * @val: pointer to location to receive read value 1527 * 1528 * Returns an error code on error. 1529 **/ 1530 s32 ixgbe_read_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) 1531 { 1532 return ixgbe_call_func(hw, hw->link.ops.read_link_unlocked, 1533 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1534 } 1535 1536 /** 1537 * ixgbe_write_i2c_byte - Writes 8 bit word over I2C 1538 * @hw: pointer to hardware structure 1539 * @byte_offset: byte offset to write 1540 * @dev_addr: I2C bus address to write to 1541 * @data: value to write 1542 * 1543 * Performs byte write operation to SFP module's EEPROM over I2C interface 1544 * at a specified device address. 1545 **/ 1546 s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1547 u8 data) 1548 { 1549 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset, 1550 dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1551 } 1552 1553 /** 1554 * ixgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C 1555 * @hw: pointer to hardware structure 1556 * @byte_offset: byte offset to write 1557 * @dev_addr: I2C bus address to write to 1558 * @data: value to write 1559 * 1560 * Performs byte write operation to SFP module's EEPROM over I2C interface 1561 * at a specified device address. 1562 **/ 1563 s32 ixgbe_write_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1564 u8 dev_addr, u8 data) 1565 { 1566 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte_unlocked, 1567 (hw, byte_offset, dev_addr, data), 1568 IXGBE_NOT_IMPLEMENTED); 1569 } 1570 1571 /** 1572 * ixgbe_write_link - Perform write operation on link device 1573 * @hw: pointer to the hardware structure 1574 * @addr: bus address to write to 1575 * @reg: device register to write to 1576 * @val: value to write 1577 * 1578 * Returns an error code on error. 1579 */ 1580 s32 ixgbe_write_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) 1581 { 1582 return ixgbe_call_func(hw, hw->link.ops.write_link, 1583 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1584 } 1585 1586 /** 1587 * ixgbe_write_link_unlocked - Perform write operation on link device 1588 * @hw: pointer to the hardware structure 1589 * @addr: bus address to write to 1590 * @reg: device register to write to 1591 * @val: value to write 1592 * 1593 * Returns an error code on error. 1594 **/ 1595 s32 ixgbe_write_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) 1596 { 1597 return ixgbe_call_func(hw, hw->link.ops.write_link_unlocked, 1598 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1599 } 1600 1601 /** 1602 * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface 1603 * @hw: pointer to hardware structure 1604 * @byte_offset: EEPROM byte offset to write 1605 * @eeprom_data: value to write 1606 * 1607 * Performs byte write operation to SFP module's EEPROM over I2C interface. 1608 **/ 1609 s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, 1610 u8 byte_offset, u8 eeprom_data) 1611 { 1612 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom, 1613 (hw, byte_offset, eeprom_data), 1614 IXGBE_NOT_IMPLEMENTED); 1615 } 1616 1617 /** 1618 * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface 1619 * @hw: pointer to hardware structure 1620 * @byte_offset: EEPROM byte offset to read 1621 * @eeprom_data: value read 1622 * 1623 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1624 **/ 1625 s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data) 1626 { 1627 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom, 1628 (hw, byte_offset, eeprom_data), 1629 IXGBE_NOT_IMPLEMENTED); 1630 } 1631 1632 /** 1633 * ixgbe_get_supported_physical_layer - Returns physical layer type 1634 * @hw: pointer to hardware structure 1635 * 1636 * Determines physical layer capabilities of the current configuration. 1637 **/ 1638 u64 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw) 1639 { 1640 return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer, 1641 (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN); 1642 } 1643 1644 /** 1645 * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics 1646 * @hw: pointer to hardware structure 1647 * @regval: bitfield to write to the Rx DMA register 1648 * 1649 * Enables the Rx DMA unit of the device. 1650 **/ 1651 s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval) 1652 { 1653 return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma, 1654 (hw, regval), IXGBE_NOT_IMPLEMENTED); 1655 } 1656 1657 /** 1658 * ixgbe_disable_sec_rx_path - Stops the receive data path 1659 * @hw: pointer to hardware structure 1660 * 1661 * Stops the receive data path. 1662 **/ 1663 s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw) 1664 { 1665 return ixgbe_call_func(hw, hw->mac.ops.disable_sec_rx_path, 1666 (hw), IXGBE_NOT_IMPLEMENTED); 1667 } 1668 1669 /** 1670 * ixgbe_enable_sec_rx_path - Enables the receive data path 1671 * @hw: pointer to hardware structure 1672 * 1673 * Enables the receive data path. 1674 **/ 1675 s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw) 1676 { 1677 return ixgbe_call_func(hw, hw->mac.ops.enable_sec_rx_path, 1678 (hw), IXGBE_NOT_IMPLEMENTED); 1679 } 1680 1681 /** 1682 * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore 1683 * @hw: pointer to hardware structure 1684 * @mask: Mask to specify which semaphore to acquire 1685 * 1686 * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified 1687 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1688 **/ 1689 s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1690 { 1691 return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync, 1692 (hw, mask), IXGBE_NOT_IMPLEMENTED); 1693 } 1694 1695 /** 1696 * ixgbe_release_swfw_semaphore - Release SWFW semaphore 1697 * @hw: pointer to hardware structure 1698 * @mask: Mask to specify which semaphore to release 1699 * 1700 * Releases the SWFW semaphore through SW_FW_SYNC register for the specified 1701 * function (CSR, PHY0, PHY1, EEPROM, Flash) 1702 **/ 1703 void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1704 { 1705 if (hw->mac.ops.release_swfw_sync) 1706 hw->mac.ops.release_swfw_sync(hw, mask); 1707 } 1708 1709 /** 1710 * ixgbe_init_swfw_semaphore - Clean up SWFW semaphore 1711 * @hw: pointer to hardware structure 1712 * 1713 * Attempts to acquire the SWFW semaphore through SW_FW_SYNC register. 1714 * Regardless of whether is succeeds or not it then release the semaphore. 1715 * This is function is called to recover from catastrophic failures that 1716 * may have left the semaphore locked. 1717 **/ 1718 void ixgbe_init_swfw_semaphore(struct ixgbe_hw *hw) 1719 { 1720 if (hw->mac.ops.init_swfw_sync) 1721 hw->mac.ops.init_swfw_sync(hw); 1722 } 1723 1724 1725 void ixgbe_disable_rx(struct ixgbe_hw *hw) 1726 { 1727 if (hw->mac.ops.disable_rx) 1728 hw->mac.ops.disable_rx(hw); 1729 } 1730 1731 void ixgbe_enable_rx(struct ixgbe_hw *hw) 1732 { 1733 if (hw->mac.ops.enable_rx) 1734 hw->mac.ops.enable_rx(hw); 1735 } 1736 1737 /** 1738 * ixgbe_set_rate_select_speed - Set module link speed 1739 * @hw: pointer to hardware structure 1740 * @speed: link speed to set 1741 * 1742 * Set module link speed via the rate select. 1743 */ 1744 void ixgbe_set_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed) 1745 { 1746 if (hw->mac.ops.set_rate_select_speed) 1747 hw->mac.ops.set_rate_select_speed(hw, speed); 1748 } 1749