1 /* $NetBSD: iteide.c,v 1.11 2010/11/05 18:07:24 jakllsch Exp $ */ 2 3 /* 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Grant Beattie. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: iteide.c,v 1.11 2010/11/05 18:07:24 jakllsch Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pciidereg.h> 42 #include <dev/pci/pciidevar.h> 43 #include <dev/pci/pciide_ite_reg.h> 44 45 static void ite_chip_map(struct pciide_softc*, struct pci_attach_args*); 46 static void ite_setup_channel(struct ata_channel*); 47 48 static int iteide_match(device_t, cfdata_t, void *); 49 static void iteide_attach(device_t, device_t, void *); 50 51 CFATTACH_DECL_NEW(iteide, sizeof(struct pciide_softc), 52 iteide_match, iteide_attach, NULL, NULL); 53 54 static const struct pciide_product_desc pciide_ite_products[] = { 55 { PCI_PRODUCT_ITE_IT8211, 56 0, 57 "Integrated Technology Express IDE controller", 58 ite_chip_map, 59 }, 60 { PCI_PRODUCT_ITE_IT8212, 61 0, 62 "Integrated Technology Express IDE controller", 63 ite_chip_map, 64 }, 65 { 0, 66 0, 67 NULL, 68 NULL 69 } 70 }; 71 72 static int 73 iteide_match(device_t parent, cfdata_t match, void *aux) 74 { 75 struct pci_attach_args *pa = aux; 76 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ITE && 77 PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE) { 78 if (pciide_lookup_product(pa->pa_id, pciide_ite_products)) 79 return (2); 80 } 81 return (0); 82 } 83 84 static void 85 iteide_attach(device_t parent, device_t self, void *aux) 86 { 87 struct pci_attach_args *pa = aux; 88 struct pciide_softc *sc = device_private(self); 89 90 sc->sc_wdcdev.sc_atac.atac_dev = self; 91 92 pciide_common_attach(sc, pa, 93 pciide_lookup_product(pa->pa_id, pciide_ite_products)); 94 } 95 96 static void 97 ite_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 98 { 99 struct pciide_channel *cp; 100 int channel; 101 pcireg_t interface; 102 pcireg_t cfg, modectl; 103 104 /* fake interface since IT8212 claims to be a RAID device */ 105 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 106 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 107 108 cfg = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_CFG); 109 modectl = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_MODE); 110 ATADEBUG_PRINT(("%s: cfg=0x%x, modectl=0x%x\n", 111 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), cfg & IT_CFG_MASK, 112 modectl & IT_MODE_MASK), DEBUG_PROBE); 113 114 if (pciide_chipen(sc, pa) == 0) 115 return; 116 117 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 118 "bus-master DMA support present"); 119 pciide_mapreg_dma(sc, pa); 120 aprint_verbose("\n"); 121 122 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 123 124 if (sc->sc_dma_ok) { 125 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 126 sc->sc_wdcdev.irqack = pciide_irqack; 127 } 128 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 129 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 130 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 131 132 sc->sc_wdcdev.sc_atac.atac_set_modes = ite_setup_channel; 133 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 134 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 135 136 wdc_allocate_regs(&sc->sc_wdcdev); 137 138 /* Disable RAID */ 139 modectl &= ~IT_MODE_RAID1; 140 /* Disable CPU firmware mode */ 141 modectl &= ~IT_MODE_CPU; 142 143 pci_conf_write(sc->sc_pc, sc->sc_tag, IT_MODE, modectl); 144 145 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; channel++) { 146 cp = &sc->pciide_channels[channel]; 147 148 if (pciide_chansetup(sc, channel, interface) == 0) 149 continue; 150 151 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 152 } 153 /* Re-read configuration registers after channels setup */ 154 cfg = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_CFG); 155 modectl = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_MODE); 156 ATADEBUG_PRINT(("%s: cfg=0x%x, modectl=0x%x\n", 157 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), cfg & IT_CFG_MASK, 158 modectl & IT_MODE_MASK), DEBUG_PROBE); 159 } 160 161 static void 162 ite_setup_channel(struct ata_channel *chp) 163 { 164 struct ata_drive_datas *drvp; 165 int drive, mode = 0; 166 u_int32_t idedma_ctl; 167 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 168 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 169 int channel = chp->ch_channel; 170 pcireg_t cfg, modectl; 171 pcireg_t tim; 172 173 cfg = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_CFG); 174 modectl = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_MODE); 175 tim = pci_conf_read(sc->sc_pc, sc->sc_tag, IT_TIM(channel)); 176 ATADEBUG_PRINT(("%s:%d: tim=0x%x\n", 177 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), 178 channel, tim), DEBUG_PROBE); 179 180 /* Setup DMA if needed */ 181 pciide_channel_dma_setup(cp); 182 183 /* Clear all bits for this channel */ 184 idedma_ctl = 0; 185 186 /* Per channel settings */ 187 for (drive = 0; drive < 2; drive++) { 188 drvp = &chp->ch_drive[drive]; 189 190 /* If no drive, skip */ 191 if ((drvp->drive_flags & DRIVE) == 0) 192 continue; 193 194 if ((chp->ch_atac->atac_cap & ATAC_CAP_UDMA) != 0 && 195 (drvp->drive_flags & DRIVE_UDMA) != 0) { 196 /* Setup UltraDMA mode */ 197 drvp->drive_flags &= ~DRIVE_DMA; 198 modectl &= ~IT_MODE_DMA(channel, drive); 199 200 #if 0 201 /* Check cable, only works in CPU firmware mode */ 202 if (drvp->UDMA_mode > 2 && 203 (cfg & IT_CFG_CABLE(channel, drive)) == 0) { 204 ATADEBUG_PRINT(("(%s:%d:%d): " 205 "80-wire cable not detected\n", 206 device_xname(&sc->sc_wdcdev.sc_atac.atac_dev), 207 channel, drive), DEBUG_PROBE); 208 drvp->UDMA_mode = 2; 209 } 210 #endif 211 212 if (drvp->UDMA_mode >= 5) 213 tim |= IT_TIM_UDMA5(drive); 214 else 215 tim &= ~IT_TIM_UDMA5(drive); 216 217 mode = drvp->PIO_mode; 218 } else if ((chp->ch_atac->atac_cap & ATAC_CAP_DMA) != 0 && 219 (drvp->drive_flags & DRIVE_DMA) != 0) { 220 /* Setup multiword DMA mode */ 221 drvp->drive_flags &= ~DRIVE_UDMA; 222 modectl |= IT_MODE_DMA(channel, drive); 223 224 /* mode = min(pio, dma + 2) */ 225 if (drvp->PIO_mode <= (drvp->DMA_mode + 2)) 226 mode = drvp->PIO_mode; 227 else 228 mode = drvp->DMA_mode + 2; 229 } else { 230 goto pio; 231 } 232 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 233 234 pio: 235 /* Setup PIO mode */ 236 if (mode <= 2) { 237 drvp->DMA_mode = 0; 238 drvp->PIO_mode = 0; 239 mode = 0; 240 } else { 241 drvp->PIO_mode = mode; 242 drvp->DMA_mode = mode - 2; 243 } 244 245 /* Enable IORDY if PIO mode >= 3 */ 246 if (drvp->PIO_mode >= 3) 247 cfg |= IT_CFG_IORDY(channel); 248 } 249 250 ATADEBUG_PRINT(("%s: tim=0x%x\n", 251 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), tim), DEBUG_PROBE); 252 253 pci_conf_write(sc->sc_pc, sc->sc_tag, IT_CFG, cfg); 254 pci_conf_write(sc->sc_pc, sc->sc_tag, IT_MODE, modectl); 255 pci_conf_write(sc->sc_pc, sc->sc_tag, IT_TIM(channel), tim); 256 257 if (idedma_ctl != 0) { 258 /* Add software bits in status register */ 259 bus_space_write_1(sc->sc_dma_iot, 260 cp->dma_iohs[IDEDMA_CTL], 0, idedma_ctl); 261 } 262 } 263