1 /* $NetBSD: isp_pci.c,v 1.112 2010/04/12 14:26:21 mjacob Exp $ */ 2 /* 3 * Copyright (C) 1997, 1998, 1999 National Aeronautics & Space Administration 4 * All rights reserved. 5 * 6 * Additional Copyright (C) 2000-2007 by Matthew Jacob 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * PCI specific probe and attach routines for Qlogic ISP SCSI adapters. 33 */ 34 35 /* 36 * 24XX 4Gb material support provided by MetrumRG Associates. 37 * Many thanks are due to them. 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: isp_pci.c,v 1.112 2010/04/12 14:26:21 mjacob Exp $"); 42 43 #include <dev/ic/isp_netbsd.h> 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcidevs.h> 47 #include <uvm/uvm_extern.h> 48 #include <sys/reboot.h> 49 50 static uint32_t isp_pci_rd_reg(struct ispsoftc *, int); 51 static void isp_pci_wr_reg(struct ispsoftc *, int, uint32_t); 52 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) 53 static uint32_t isp_pci_rd_reg_1080(struct ispsoftc *, int); 54 static void isp_pci_wr_reg_1080(struct ispsoftc *, int, uint32_t); 55 #endif 56 #if !defined(ISP_DISABLE_2100_SUPPORT) && \ 57 !defined(ISP_DISABLE_2200_SUPPORT) && \ 58 !defined(ISP_DISABLE_1020_SUPPORT) && \ 59 !defined(ISP_DISABLE_1080_SUPPORT) && \ 60 !defined(ISP_DISABLE_12160_SUPPORT) 61 static int 62 isp_pci_rd_isr(struct ispsoftc *, uint32_t *, uint16_t *, uint16_t *); 63 #endif 64 #if !(defined(ISP_DISABLE_2300_SUPPORT) && defined(ISP_DISABLE_2322_SUPPORT)) 65 static int 66 isp_pci_rd_isr_2300(struct ispsoftc *, uint32_t *, uint16_t *, uint16_t *); 67 #endif 68 #if !defined(ISP_DISABLE_2400_SUPPORT) 69 static uint32_t isp_pci_rd_reg_2400(struct ispsoftc *, int); 70 static void isp_pci_wr_reg_2400(struct ispsoftc *, int, uint32_t); 71 static int 72 isp_pci_rd_isr_2400(struct ispsoftc *, uint32_t *, uint16_t *, uint16_t *); 73 #endif 74 static int isp_pci_mbxdma(struct ispsoftc *); 75 static int isp_pci_dmasetup(struct ispsoftc *, XS_T *, void *); 76 static void isp_pci_dmateardown(struct ispsoftc *, XS_T *, uint32_t); 77 static void isp_pci_reset0(struct ispsoftc *); 78 static void isp_pci_reset1(struct ispsoftc *); 79 static void isp_pci_dumpregs(struct ispsoftc *, const char *); 80 static int isp_pci_intr(void *); 81 82 #if defined(ISP_DISABLE_1020_SUPPORT) || defined(ISP_DISABLE_FW) 83 #define ISP_1040_RISC_CODE NULL 84 #else 85 #define ISP_1040_RISC_CODE (const uint16_t *) isp_1040_risc_code 86 #include <dev/microcode/isp/asm_1040.h> 87 #endif 88 89 #if defined(ISP_DISABLE_1080_SUPPORT) || defined(ISP_DISABLE_FW) 90 #define ISP_1080_RISC_CODE NULL 91 #else 92 #define ISP_1080_RISC_CODE (const uint16_t *) isp_1080_risc_code 93 #include <dev/microcode/isp/asm_1080.h> 94 #endif 95 96 #if defined(ISP_DISABLE_12160_SUPPORT) || defined(ISP_DISABLE_FW) 97 #define ISP_12160_RISC_CODE NULL 98 #else 99 #define ISP_12160_RISC_CODE (const uint16_t *) isp_12160_risc_code 100 #include <dev/microcode/isp/asm_12160.h> 101 #endif 102 103 #if defined(ISP_DISABLE_2100_SUPPORT) || defined(ISP_DISABLE_FW) 104 #define ISP_2100_RISC_CODE NULL 105 #else 106 #define ISP_2100_RISC_CODE (const uint16_t *) isp_2100_risc_code 107 #include <dev/microcode/isp/asm_2100.h> 108 #endif 109 110 #if defined(ISP_DISABLE_2200_SUPPORT) || defined(ISP_DISABLE_FW) 111 #define ISP_2200_RISC_CODE NULL 112 #else 113 #define ISP_2200_RISC_CODE (const uint16_t *) isp_2200_risc_code 114 #include <dev/microcode/isp/asm_2200.h> 115 #endif 116 117 #if defined(ISP_DISABLE_2300_SUPPORT) || defined(ISP_DISABLE_FW) 118 #define ISP_2300_RISC_CODE NULL 119 #else 120 #define ISP_2300_RISC_CODE (const uint16_t *) isp_2300_risc_code 121 #include <dev/microcode/isp/asm_2300.h> 122 #endif 123 #if defined(ISP_DISABLE_2322_SUPPORT) || defined(ISP_DISABLE_FW) 124 #define ISP_2322_RISC_CODE NULL 125 #else 126 #define ISP_2322_RISC_CODE (const uint16_t *) isp_2322_risc_code 127 #include <dev/microcode/isp/asm_2322.h> 128 #endif 129 130 #if defined(ISP_DISABLE_2400_SUPPORT) || defined(ISP_DISABLE_FW) 131 #define ISP_2400_RISC_CODE NULL 132 #define ISP_2500_RISC_CODE NULL 133 #else 134 #define ISP_2400_RISC_CODE (const uint32_t *) isp_2400_risc_code 135 #define ISP_2500_RISC_CODE (const uint32_t *) isp_2500_risc_code 136 #include <dev/microcode/isp/asm_2400.h> 137 #include <dev/microcode/isp/asm_2500.h> 138 #endif 139 140 #ifndef ISP_DISABLE_1020_SUPPORT 141 static struct ispmdvec mdvec = { 142 isp_pci_rd_isr, 143 isp_pci_rd_reg, 144 isp_pci_wr_reg, 145 isp_pci_mbxdma, 146 isp_pci_dmasetup, 147 isp_pci_dmateardown, 148 isp_pci_reset0, 149 isp_pci_reset1, 150 isp_pci_dumpregs, 151 ISP_1040_RISC_CODE, 152 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64, 153 0 154 }; 155 #endif 156 157 #ifndef ISP_DISABLE_1080_SUPPORT 158 static struct ispmdvec mdvec_1080 = { 159 isp_pci_rd_isr, 160 isp_pci_rd_reg_1080, 161 isp_pci_wr_reg_1080, 162 isp_pci_mbxdma, 163 isp_pci_dmasetup, 164 isp_pci_dmateardown, 165 isp_pci_reset0, 166 isp_pci_reset1, 167 isp_pci_dumpregs, 168 ISP_1080_RISC_CODE, 169 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64, 170 0 171 }; 172 #endif 173 174 #ifndef ISP_DISABLE_12160_SUPPORT 175 static struct ispmdvec mdvec_12160 = { 176 isp_pci_rd_isr, 177 isp_pci_rd_reg_1080, 178 isp_pci_wr_reg_1080, 179 isp_pci_mbxdma, 180 isp_pci_dmasetup, 181 isp_pci_dmateardown, 182 isp_pci_reset0, 183 isp_pci_reset1, 184 isp_pci_dumpregs, 185 ISP_12160_RISC_CODE, 186 BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64, 187 0 188 }; 189 #endif 190 191 #ifndef ISP_DISABLE_2100_SUPPORT 192 static struct ispmdvec mdvec_2100 = { 193 isp_pci_rd_isr, 194 isp_pci_rd_reg, 195 isp_pci_wr_reg, 196 isp_pci_mbxdma, 197 isp_pci_dmasetup, 198 isp_pci_dmateardown, 199 isp_pci_reset0, 200 isp_pci_reset1, 201 isp_pci_dumpregs, 202 ISP_2100_RISC_CODE, 203 0, 204 0 205 }; 206 #endif 207 208 #ifndef ISP_DISABLE_2200_SUPPORT 209 static struct ispmdvec mdvec_2200 = { 210 isp_pci_rd_isr, 211 isp_pci_rd_reg, 212 isp_pci_wr_reg, 213 isp_pci_mbxdma, 214 isp_pci_dmasetup, 215 isp_pci_dmateardown, 216 isp_pci_reset0, 217 isp_pci_reset1, 218 isp_pci_dumpregs, 219 ISP_2200_RISC_CODE, 220 0, 221 0 222 }; 223 #endif 224 225 #ifndef ISP_DISABLE_2300_SUPPORT 226 static struct ispmdvec mdvec_2300 = { 227 isp_pci_rd_isr_2300, 228 isp_pci_rd_reg, 229 isp_pci_wr_reg, 230 isp_pci_mbxdma, 231 isp_pci_dmasetup, 232 isp_pci_dmateardown, 233 isp_pci_reset0, 234 isp_pci_reset1, 235 isp_pci_dumpregs, 236 ISP_2300_RISC_CODE, 237 0, 238 0 239 }; 240 #endif 241 242 #ifndef ISP_DISABLE_2322_SUPPORT 243 static struct ispmdvec mdvec_2322 = { 244 isp_pci_rd_isr_2300, 245 isp_pci_rd_reg, 246 isp_pci_wr_reg, 247 isp_pci_mbxdma, 248 isp_pci_dmasetup, 249 isp_pci_dmateardown, 250 isp_pci_reset0, 251 isp_pci_reset1, 252 isp_pci_dumpregs, 253 ISP_2322_RISC_CODE, 254 0, 255 0 256 }; 257 #endif 258 259 #ifndef ISP_DISABLE_2400_SUPPORT 260 static struct ispmdvec mdvec_2400 = { 261 isp_pci_rd_isr_2400, 262 isp_pci_rd_reg_2400, 263 isp_pci_wr_reg_2400, 264 isp_pci_mbxdma, 265 isp_pci_dmasetup, 266 isp_pci_dmateardown, 267 isp_pci_reset0, 268 isp_pci_reset1, 269 NULL, 270 ISP_2400_RISC_CODE, 271 0, 272 0 273 }; 274 static struct ispmdvec mdvec_2500 = { 275 isp_pci_rd_isr_2400, 276 isp_pci_rd_reg_2400, 277 isp_pci_wr_reg_2400, 278 isp_pci_mbxdma, 279 isp_pci_dmasetup, 280 isp_pci_dmateardown, 281 isp_pci_reset0, 282 isp_pci_reset1, 283 NULL, 284 ISP_2500_RISC_CODE, 285 0, 286 0 287 }; 288 #endif 289 290 #ifndef PCI_VENDOR_QLOGIC 291 #define PCI_VENDOR_QLOGIC 0x1077 292 #endif 293 294 #ifndef PCI_PRODUCT_QLOGIC_ISP1020 295 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 296 #endif 297 298 #ifndef PCI_PRODUCT_QLOGIC_ISP1080 299 #define PCI_PRODUCT_QLOGIC_ISP1080 0x1080 300 #endif 301 302 #ifndef PCI_PRODUCT_QLOGIC_ISP1240 303 #define PCI_PRODUCT_QLOGIC_ISP1240 0x1240 304 #endif 305 306 #ifndef PCI_PRODUCT_QLOGIC_ISP1280 307 #define PCI_PRODUCT_QLOGIC_ISP1280 0x1280 308 #endif 309 310 #ifndef PCI_PRODUCT_QLOGIC_ISP10160 311 #define PCI_PRODUCT_QLOGIC_ISP10160 0x1016 312 #endif 313 314 #ifndef PCI_PRODUCT_QLOGIC_ISP12160 315 #define PCI_PRODUCT_QLOGIC_ISP12160 0x1216 316 #endif 317 318 #ifndef PCI_PRODUCT_QLOGIC_ISP2100 319 #define PCI_PRODUCT_QLOGIC_ISP2100 0x2100 320 #endif 321 322 #ifndef PCI_PRODUCT_QLOGIC_ISP2200 323 #define PCI_PRODUCT_QLOGIC_ISP2200 0x2200 324 #endif 325 326 #ifndef PCI_PRODUCT_QLOGIC_ISP2300 327 #define PCI_PRODUCT_QLOGIC_ISP2300 0x2300 328 #endif 329 330 #ifndef PCI_PRODUCT_QLOGIC_ISP2312 331 #define PCI_PRODUCT_QLOGIC_ISP2312 0x2312 332 #endif 333 334 #ifndef PCI_PRODUCT_QLOGIC_ISP2322 335 #define PCI_PRODUCT_QLOGIC_ISP2322 0x2322 336 #endif 337 338 #ifndef PCI_PRODUCT_QLOGIC_ISP2422 339 #define PCI_PRODUCT_QLOGIC_ISP2422 0x2422 340 #endif 341 342 #ifndef PCI_PRODUCT_QLOGIC_ISP2432 343 #define PCI_PRODUCT_QLOGIC_ISP2432 0x2432 344 #endif 345 346 #ifndef PCI_PRODUCT_QLOGIC_ISP2532 347 #define PCI_PRODUCT_QLOGIC_ISP2532 0x2532 348 #endif 349 350 #ifndef PCI_PRODUCT_QLOGIC_ISP6312 351 #define PCI_PRODUCT_QLOGIC_ISP6312 0x6312 352 #endif 353 354 #ifndef PCI_PRODUCT_QLOGIC_ISP6322 355 #define PCI_PRODUCT_QLOGIC_ISP6322 0x6322 356 #endif 357 358 359 #define PCI_QLOGIC_ISP ((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC) 360 361 #define PCI_QLOGIC_ISP1080 \ 362 ((PCI_PRODUCT_QLOGIC_ISP1080 << 16) | PCI_VENDOR_QLOGIC) 363 364 #define PCI_QLOGIC_ISP10160 \ 365 ((PCI_PRODUCT_QLOGIC_ISP10160 << 16) | PCI_VENDOR_QLOGIC) 366 367 #define PCI_QLOGIC_ISP12160 \ 368 ((PCI_PRODUCT_QLOGIC_ISP12160 << 16) | PCI_VENDOR_QLOGIC) 369 370 #define PCI_QLOGIC_ISP1240 \ 371 ((PCI_PRODUCT_QLOGIC_ISP1240 << 16) | PCI_VENDOR_QLOGIC) 372 373 #define PCI_QLOGIC_ISP1280 \ 374 ((PCI_PRODUCT_QLOGIC_ISP1280 << 16) | PCI_VENDOR_QLOGIC) 375 376 #define PCI_QLOGIC_ISP2100 \ 377 ((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC) 378 379 #define PCI_QLOGIC_ISP2200 \ 380 ((PCI_PRODUCT_QLOGIC_ISP2200 << 16) | PCI_VENDOR_QLOGIC) 381 382 #define PCI_QLOGIC_ISP2300 \ 383 ((PCI_PRODUCT_QLOGIC_ISP2300 << 16) | PCI_VENDOR_QLOGIC) 384 385 #define PCI_QLOGIC_ISP2312 \ 386 ((PCI_PRODUCT_QLOGIC_ISP2312 << 16) | PCI_VENDOR_QLOGIC) 387 388 #define PCI_QLOGIC_ISP2322 \ 389 ((PCI_PRODUCT_QLOGIC_ISP2322 << 16) | PCI_VENDOR_QLOGIC) 390 391 #define PCI_QLOGIC_ISP2422 \ 392 ((PCI_PRODUCT_QLOGIC_ISP2422 << 16) | PCI_VENDOR_QLOGIC) 393 394 #define PCI_QLOGIC_ISP2432 \ 395 ((PCI_PRODUCT_QLOGIC_ISP2432 << 16) | PCI_VENDOR_QLOGIC) 396 397 #define PCI_QLOGIC_ISP2532 \ 398 ((PCI_PRODUCT_QLOGIC_ISP2532 << 16) | PCI_VENDOR_QLOGIC) 399 400 #define PCI_QLOGIC_ISP6312 \ 401 ((PCI_PRODUCT_QLOGIC_ISP6312 << 16) | PCI_VENDOR_QLOGIC) 402 403 #define PCI_QLOGIC_ISP6322 \ 404 ((PCI_PRODUCT_QLOGIC_ISP6322 << 16) | PCI_VENDOR_QLOGIC) 405 406 #define IO_MAP_REG 0x10 407 #define MEM_MAP_REG 0x14 408 #define PCIR_ROMADDR 0x30 409 410 #define PCI_DFLT_LTNCY 0x40 411 #define PCI_DFLT_LNSZ 0x10 412 413 static int isp_pci_probe(device_t, cfdata_t, void *); 414 static void isp_pci_attach(device_t, device_t, void *); 415 416 struct isp_pcisoftc { 417 struct ispsoftc pci_isp; 418 pci_chipset_tag_t pci_pc; 419 pcitag_t pci_tag; 420 bus_space_tag_t pci_st; 421 bus_space_handle_t pci_sh; 422 bus_dmamap_t *pci_xfer_dmap; 423 void * pci_ih; 424 int16_t pci_poff[_NREG_BLKS]; 425 }; 426 427 CFATTACH_DECL_NEW(isp_pci, sizeof (struct isp_pcisoftc), 428 isp_pci_probe, isp_pci_attach, NULL, NULL); 429 430 static int 431 isp_pci_probe(device_t parent, cfdata_t match, void *aux) 432 { 433 struct pci_attach_args *pa = aux; 434 switch (pa->pa_id) { 435 #ifndef ISP_DISABLE_1020_SUPPORT 436 case PCI_QLOGIC_ISP: 437 return (1); 438 #endif 439 #ifndef ISP_DISABLE_1080_SUPPORT 440 case PCI_QLOGIC_ISP1080: 441 case PCI_QLOGIC_ISP1240: 442 case PCI_QLOGIC_ISP1280: 443 return (1); 444 #endif 445 #ifndef ISP_DISABLE_12160_SUPPORT 446 case PCI_QLOGIC_ISP10160: 447 case PCI_QLOGIC_ISP12160: 448 return (1); 449 #endif 450 #ifndef ISP_DISABLE_2100_SUPPORT 451 case PCI_QLOGIC_ISP2100: 452 return (1); 453 #endif 454 #ifndef ISP_DISABLE_2200_SUPPORT 455 case PCI_QLOGIC_ISP2200: 456 return (1); 457 #endif 458 #ifndef ISP_DISABLE_2300_SUPPORT 459 case PCI_QLOGIC_ISP2300: 460 case PCI_QLOGIC_ISP2312: 461 case PCI_QLOGIC_ISP6312: 462 #endif 463 #ifndef ISP_DISABLE_2322_SUPPORT 464 case PCI_QLOGIC_ISP2322: 465 case PCI_QLOGIC_ISP6322: 466 return (1); 467 #endif 468 #ifndef ISP_DISABLE_2400_SUPPORT 469 case PCI_QLOGIC_ISP2422: 470 case PCI_QLOGIC_ISP2432: 471 case PCI_QLOGIC_ISP2532: 472 return (1); 473 #endif 474 default: 475 return (0); 476 } 477 } 478 479 static void 480 isp_pci_attach(device_t parent, device_t self, void *aux) 481 { 482 static const char nomem[] = "\n%s: no mem for sdparam table\n"; 483 uint32_t data, rev, linesz = PCI_DFLT_LNSZ; 484 struct pci_attach_args *pa = aux; 485 struct isp_pcisoftc *pcs = device_private(self); 486 struct ispsoftc *isp = &pcs->pci_isp; 487 bus_space_tag_t st, iot, memt; 488 bus_space_handle_t sh, ioh, memh; 489 pci_intr_handle_t ih; 490 pcireg_t mem_type; 491 const char *dstring; 492 const char *intrstr; 493 int ioh_valid, memh_valid; 494 size_t mamt; 495 496 isp->isp_osinfo.dev = self; 497 498 ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG, 499 PCI_MAPREG_TYPE_IO, 0, 500 &iot, &ioh, NULL, NULL) == 0); 501 502 mem_type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, MEM_MAP_REG); 503 if (PCI_MAPREG_TYPE(mem_type) != PCI_MAPREG_TYPE_MEM) { 504 memh_valid = 0; 505 } else if (PCI_MAPREG_MEM_TYPE(mem_type) != PCI_MAPREG_MEM_TYPE_32BIT && 506 PCI_MAPREG_MEM_TYPE(mem_type) != PCI_MAPREG_MEM_TYPE_64BIT) { 507 memh_valid = 0; 508 } else { 509 memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG, mem_type, 0, 510 &memt, &memh, NULL, NULL) == 0); 511 } 512 if (memh_valid) { 513 st = memt; 514 sh = memh; 515 } else if (ioh_valid) { 516 st = iot; 517 sh = ioh; 518 } else { 519 printf(": unable to map device registers\n"); 520 return; 521 } 522 dstring = "\n"; 523 524 isp->isp_nchan = 1; 525 mamt = 0; 526 527 pcs->pci_st = st; 528 pcs->pci_sh = sh; 529 pcs->pci_pc = pa->pa_pc; 530 pcs->pci_tag = pa->pa_tag; 531 pcs->pci_poff[BIU_BLOCK >> _BLK_REG_SHFT] = BIU_REGS_OFF; 532 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = PCI_MBOX_REGS_OFF; 533 pcs->pci_poff[SXP_BLOCK >> _BLK_REG_SHFT] = PCI_SXP_REGS_OFF; 534 pcs->pci_poff[RISC_BLOCK >> _BLK_REG_SHFT] = PCI_RISC_REGS_OFF; 535 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = DMA_REGS_OFF; 536 rev = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG) & 0xff; 537 538 539 #ifndef ISP_DISABLE_1020_SUPPORT 540 if (pa->pa_id == PCI_QLOGIC_ISP) { 541 dstring = ": QLogic 1020 Fast Wide SCSI HBA\n"; 542 isp->isp_mdvec = &mdvec; 543 isp->isp_type = ISP_HA_SCSI_UNKNOWN; 544 mamt = sizeof (sdparam); 545 } 546 #endif 547 #ifndef ISP_DISABLE_1080_SUPPORT 548 if (pa->pa_id == PCI_QLOGIC_ISP1080) { 549 dstring = ": QLogic 1080 Ultra-2 Wide SCSI HBA\n"; 550 isp->isp_mdvec = &mdvec_1080; 551 isp->isp_type = ISP_HA_SCSI_1080; 552 mamt = sizeof (sdparam); 553 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 554 ISP1080_DMA_REGS_OFF; 555 } 556 if (pa->pa_id == PCI_QLOGIC_ISP1240) { 557 dstring = ": QLogic Dual Channel Ultra Wide SCSI HBA\n"; 558 isp->isp_mdvec = &mdvec_1080; 559 isp->isp_type = ISP_HA_SCSI_1240; 560 isp->isp_nchan++; 561 mamt = sizeof (sdparam) * 2; 562 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 563 ISP1080_DMA_REGS_OFF; 564 } 565 if (pa->pa_id == PCI_QLOGIC_ISP1280) { 566 dstring = ": QLogic Dual Channel Ultra-2 Wide SCSI HBA\n"; 567 isp->isp_mdvec = &mdvec_1080; 568 isp->isp_type = ISP_HA_SCSI_1280; 569 isp->isp_nchan++; 570 mamt = sizeof (sdparam) * 2; 571 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 572 ISP1080_DMA_REGS_OFF; 573 } 574 #endif 575 #ifndef ISP_DISABLE_12160_SUPPORT 576 if (pa->pa_id == PCI_QLOGIC_ISP10160) { 577 dstring = ": QLogic Ultra-3 Wide SCSI HBA\n"; 578 isp->isp_mdvec = &mdvec_12160; 579 isp->isp_type = ISP_HA_SCSI_10160; 580 mamt = sizeof (sdparam); 581 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 582 ISP1080_DMA_REGS_OFF; 583 } 584 if (pa->pa_id == PCI_QLOGIC_ISP12160) { 585 dstring = ": QLogic Dual Channel Ultra-3 Wide SCSI HBA\n"; 586 isp->isp_mdvec = &mdvec_12160; 587 isp->isp_type = ISP_HA_SCSI_12160; 588 isp->isp_nchan++; 589 mamt = sizeof (sdparam) * 2; 590 pcs->pci_poff[DMA_BLOCK >> _BLK_REG_SHFT] = 591 ISP1080_DMA_REGS_OFF; 592 } 593 #endif 594 #ifndef ISP_DISABLE_2100_SUPPORT 595 if (pa->pa_id == PCI_QLOGIC_ISP2100) { 596 dstring = ": QLogic FC-AL HBA\n"; 597 isp->isp_mdvec = &mdvec_2100; 598 isp->isp_type = ISP_HA_FC_2100; 599 mamt = sizeof (fcparam); 600 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 601 PCI_MBOX_REGS2100_OFF; 602 if (rev < 3) { 603 /* 604 * XXX: Need to get the actual revision 605 * XXX: number of the 2100 FB. At any rate, 606 * XXX: lower cache line size for early revision 607 * XXX; boards. 608 */ 609 linesz = 1; 610 } 611 } 612 #endif 613 #ifndef ISP_DISABLE_2200_SUPPORT 614 if (pa->pa_id == PCI_QLOGIC_ISP2200) { 615 dstring = ": QLogic FC-AL and Fabric HBA\n"; 616 isp->isp_mdvec = &mdvec_2200; 617 isp->isp_type = ISP_HA_FC_2200; 618 mamt = sizeof (fcparam); 619 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 620 PCI_MBOX_REGS2100_OFF; 621 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 622 } 623 #endif 624 #ifndef ISP_DISABLE_2300_SUPPORT 625 if (pa->pa_id == PCI_QLOGIC_ISP2300 || 626 pa->pa_id == PCI_QLOGIC_ISP2312 || 627 pa->pa_id == PCI_QLOGIC_ISP6312) { 628 isp->isp_mdvec = &mdvec_2300; 629 if (pa->pa_id == PCI_QLOGIC_ISP2300 || 630 pa->pa_id == PCI_QLOGIC_ISP6312) { 631 dstring = ": QLogic FC-AL and 2Gbps Fabric HBA\n"; 632 isp->isp_type = ISP_HA_FC_2300; 633 } else { 634 dstring = 635 ": QLogic Dual Port FC-AL and 2Gbps Fabric HBA\n"; 636 isp->isp_port = pa->pa_function; 637 } 638 isp->isp_type = ISP_HA_FC_2312; 639 mamt = sizeof (fcparam); 640 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 641 PCI_MBOX_REGS2300_OFF; 642 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 643 } 644 #endif 645 #ifndef ISP_DISABLE_2322_SUPPORT 646 if (pa->pa_id == PCI_QLOGIC_ISP2322 || 647 pa->pa_id == PCI_QLOGIC_ISP6322) { 648 isp->isp_mdvec = &mdvec_2322; 649 dstring = ": QLogic FC-AL and 2Gbps Fabric PCI-E HBA\n"; 650 isp->isp_type = ISP_HA_FC_2322; 651 isp->isp_port = pa->pa_function; 652 mamt = sizeof (fcparam); 653 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 654 PCI_MBOX_REGS2300_OFF; 655 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 656 } 657 #endif 658 #ifndef ISP_DISABLE_2400_SUPPORT 659 if (pa->pa_id == PCI_QLOGIC_ISP2422 || 660 pa->pa_id == PCI_QLOGIC_ISP2432) { 661 isp->isp_mdvec = &mdvec_2400; 662 if (pa->pa_id == PCI_QLOGIC_ISP2422) { 663 dstring = ": QLogic FC-AL and 4Gbps Fabric PCI-X HBA\n"; 664 } else { 665 dstring = ": QLogic FC-AL and 4Gbps Fabric PCI-E HBA\n"; 666 } 667 isp->isp_type = ISP_HA_FC_2400; 668 isp->isp_port = pa->pa_function; 669 mamt = sizeof (fcparam); 670 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 671 PCI_MBOX_REGS2400_OFF; 672 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 673 } 674 if (pa->pa_id == PCI_QLOGIC_ISP2532) { 675 isp->isp_mdvec = &mdvec_2500; 676 dstring = ": QLogic FC-AL and 8Gbps Fabric PCI-E HBA\n"; 677 isp->isp_type = ISP_HA_FC_2500; 678 isp->isp_port = pa->pa_function; 679 mamt = sizeof (fcparam); 680 pcs->pci_poff[MBOX_BLOCK >> _BLK_REG_SHFT] = 681 PCI_MBOX_REGS2400_OFF; 682 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG); 683 } 684 #endif 685 if (mamt == 0) { 686 return; 687 } 688 689 isp->isp_param = malloc(mamt, M_DEVBUF, M_NOWAIT); 690 if (isp->isp_param == NULL) { 691 printf(nomem, device_xname(self)); 692 return; 693 } 694 memset(isp->isp_param, 0, mamt); 695 mamt = sizeof (struct scsipi_channel) * isp->isp_nchan; 696 isp->isp_osinfo.chan = malloc(mamt, M_DEVBUF, M_NOWAIT); 697 if (isp->isp_osinfo.chan == NULL) { 698 free(isp->isp_param, M_DEVBUF); 699 printf(nomem, device_xname(self)); 700 return; 701 } 702 memset(isp->isp_osinfo.chan, 0, mamt); 703 isp->isp_osinfo.adapter.adapt_nchannels = isp->isp_nchan; 704 705 /* 706 * Set up logging levels. 707 */ 708 #ifdef ISP_LOGDEFAULT 709 isp->isp_dblev = ISP_LOGDEFAULT; 710 #else 711 isp->isp_dblev = ISP_LOGWARN|ISP_LOGERR; 712 if (bootverbose) 713 isp->isp_dblev |= ISP_LOGCONFIG|ISP_LOGINFO; 714 #ifdef SCSIDEBUG 715 isp->isp_dblev |= ISP_LOGDEBUG0|ISP_LOGDEBUG1|ISP_LOGDEBUG2; 716 #endif 717 #endif 718 if (isp->isp_dblev & ISP_LOGCONFIG) { 719 printf("\n"); 720 } else { 721 printf(dstring); 722 } 723 724 isp->isp_dmatag = pa->pa_dmat; 725 isp->isp_revision = rev; 726 727 /* 728 * Make sure that command register set sanely. 729 */ 730 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 731 data |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_INVALIDATE_ENABLE; 732 733 /* 734 * Not so sure about these- but I think it's important that they get 735 * enabled...... 736 */ 737 data |= PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE; 738 if (IS_2300(isp)) { /* per QLogic errata */ 739 data &= ~PCI_COMMAND_INVALIDATE_ENABLE; 740 } 741 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, data); 742 743 /* 744 * Make sure that the latency timer, cache line size, 745 * and ROM is disabled. 746 */ 747 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 748 data &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 749 data &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT); 750 data |= (PCI_DFLT_LTNCY << PCI_LATTIMER_SHIFT); 751 data |= (linesz << PCI_CACHELINE_SHIFT); 752 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, data); 753 754 data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR); 755 data &= ~1; 756 pci_conf_write(pa->pa_pc, pa->pa_tag, PCIR_ROMADDR, data); 757 758 if (pci_intr_map(pa, &ih)) { 759 aprint_error_dev(self, "couldn't map interrupt\n"); 760 free(isp->isp_param, M_DEVBUF); 761 free(isp->isp_osinfo.chan, M_DEVBUF); 762 return; 763 } 764 intrstr = pci_intr_string(pa->pa_pc, ih); 765 if (intrstr == NULL) 766 intrstr = "<I dunno>"; 767 pcs->pci_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 768 isp_pci_intr, isp); 769 if (pcs->pci_ih == NULL) { 770 aprint_error_dev(self, "couldn't establish interrupt at %s\n", 771 intrstr); 772 free(isp->isp_param, M_DEVBUF); 773 free(isp->isp_osinfo.chan, M_DEVBUF); 774 return; 775 } 776 777 printf("%s: interrupting at %s\n", device_xname(self), intrstr); 778 779 isp->isp_confopts = device_cfdata(self)->cf_flags; 780 ISP_LOCK(isp); 781 isp_reset(isp, 1); 782 if (isp->isp_state != ISP_RESETSTATE) { 783 ISP_UNLOCK(isp); 784 free(isp->isp_param, M_DEVBUF); 785 free(isp->isp_osinfo.chan, M_DEVBUF); 786 return; 787 } 788 isp_init(isp); 789 if (isp->isp_state != ISP_INITSTATE) { 790 isp_uninit(isp); 791 ISP_UNLOCK(isp); 792 free(isp->isp_param, M_DEVBUF); 793 free(isp->isp_osinfo.chan, M_DEVBUF); 794 return; 795 } 796 /* 797 * Do platform attach. 798 */ 799 ISP_UNLOCK(isp); 800 isp_attach(isp); 801 } 802 803 #define IspVirt2Off(a, x) \ 804 (((struct isp_pcisoftc *)a)->pci_poff[((x) & _BLK_REG_MASK) >> \ 805 _BLK_REG_SHFT] + ((x) & 0xff)) 806 807 #define BXR2(pcs, off) \ 808 bus_space_read_2(pcs->pci_st, pcs->pci_sh, off) 809 #define BXW2(pcs, off, v) \ 810 bus_space_write_2(pcs->pci_st, pcs->pci_sh, off, v) 811 #define BXR4(pcs, off) \ 812 bus_space_read_4(pcs->pci_st, pcs->pci_sh, off) 813 #define BXW4(pcs, off, v) \ 814 bus_space_write_4(pcs->pci_st, pcs->pci_sh, off, v) 815 816 817 static int 818 isp_pci_rd_debounced(struct ispsoftc *isp, int off, uint16_t *rp) 819 { 820 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 821 uint16_t val0, val1; 822 int i = 0; 823 824 do { 825 val0 = BXR2(pcs, IspVirt2Off(isp, off)); 826 val1 = BXR2(pcs, IspVirt2Off(isp, off)); 827 } while (val0 != val1 && ++i < 1000); 828 if (val0 != val1) { 829 return (1); 830 } 831 *rp = val0; 832 return (0); 833 } 834 835 #if !defined(ISP_DISABLE_2100_SUPPORT) && \ 836 !defined(ISP_DISABLE_2200_SUPPORT) && \ 837 !defined(ISP_DISABLE_1020_SUPPORT) && \ 838 !defined(ISP_DISABLE_1080_SUPPORT) && \ 839 !defined(ISP_DISABLE_12160_SUPPORT) 840 static int 841 isp_pci_rd_isr(struct ispsoftc *isp, uint32_t *isrp, 842 uint16_t *semap, uint16_t *mbp) 843 { 844 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 845 uint16_t isr, sema; 846 847 if (IS_2100(isp)) { 848 if (isp_pci_rd_debounced(isp, BIU_ISR, &isr)) { 849 return (0); 850 } 851 if (isp_pci_rd_debounced(isp, BIU_SEMA, &sema)) { 852 return (0); 853 } 854 } else { 855 isr = BXR2(pcs, IspVirt2Off(isp, BIU_ISR)); 856 sema = BXR2(pcs, IspVirt2Off(isp, BIU_SEMA)); 857 } 858 isp_prt(isp, ISP_LOGDEBUG3, "ISR 0x%x SEMA 0x%x", isr, sema); 859 isr &= INT_PENDING_MASK(isp); 860 sema &= BIU_SEMA_LOCK; 861 if (isr == 0 && sema == 0) { 862 return (0); 863 } 864 *isrp = isr; 865 if ((*semap = sema) != 0) { 866 if (IS_2100(isp)) { 867 if (isp_pci_rd_debounced(isp, OUTMAILBOX0, mbp)) { 868 return (0); 869 } 870 } else { 871 *mbp = BXR2(pcs, IspVirt2Off(isp, OUTMAILBOX0)); 872 } 873 } 874 return (1); 875 } 876 #endif 877 878 #if !(defined(ISP_DISABLE_2300_SUPPORT) || defined(ISP_DISABLE_2322_SUPPORT)) 879 static int 880 isp_pci_rd_isr_2300(struct ispsoftc *isp, uint32_t *isrp, 881 uint16_t *semap, uint16_t *mbox0p) 882 { 883 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 884 uint32_t r2hisr; 885 886 if (!(BXR2(pcs, IspVirt2Off(isp, BIU_ISR)) & BIU2100_ISR_RISC_INT)) { 887 *isrp = 0; 888 return (0); 889 } 890 r2hisr = bus_space_read_4(pcs->pci_st, pcs->pci_sh, 891 IspVirt2Off(pcs, BIU_R2HSTSLO)); 892 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 893 if ((r2hisr & BIU_R2HST_INTR) == 0) { 894 *isrp = 0; 895 return (0); 896 } 897 switch (r2hisr & BIU_R2HST_ISTAT_MASK) { 898 case ISPR2HST_ROM_MBX_OK: 899 case ISPR2HST_ROM_MBX_FAIL: 900 case ISPR2HST_MBX_OK: 901 case ISPR2HST_MBX_FAIL: 902 case ISPR2HST_ASYNC_EVENT: 903 *isrp = r2hisr & 0xffff; 904 *mbox0p = (r2hisr >> 16); 905 *semap = 1; 906 return (1); 907 case ISPR2HST_RIO_16: 908 *isrp = r2hisr & 0xffff; 909 *mbox0p = ASYNC_RIO16_1; 910 *semap = 1; 911 return (1); 912 case ISPR2HST_FPOST: 913 *isrp = r2hisr & 0xffff; 914 *mbox0p = ASYNC_CMD_CMPLT; 915 *semap = 1; 916 return (1); 917 case ISPR2HST_FPOST_CTIO: 918 *isrp = r2hisr & 0xffff; 919 *mbox0p = ASYNC_CTIO_DONE; 920 *semap = 1; 921 return (1); 922 case ISPR2HST_RSPQ_UPDATE: 923 *isrp = r2hisr & 0xffff; 924 *mbox0p = 0; 925 *semap = 0; 926 return (1); 927 default: 928 return (0); 929 } 930 } 931 #endif 932 933 #ifndef ISP_DISABLE_2400_SUPPORT 934 static int 935 isp_pci_rd_isr_2400(ispsoftc_t *isp, uint32_t *isrp, 936 uint16_t *semap, uint16_t *mbox0p) 937 { 938 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 939 uint32_t r2hisr; 940 941 r2hisr = BXR4(pcs, IspVirt2Off(pcs, BIU2400_R2HSTSLO)); 942 isp_prt(isp, ISP_LOGDEBUG3, "RISC2HOST ISR 0x%x", r2hisr); 943 if ((r2hisr & BIU2400_R2HST_INTR) == 0) { 944 *isrp = 0; 945 return (0); 946 } 947 switch (r2hisr & BIU2400_R2HST_ISTAT_MASK) { 948 case ISP2400R2HST_ROM_MBX_OK: 949 case ISP2400R2HST_ROM_MBX_FAIL: 950 case ISP2400R2HST_MBX_OK: 951 case ISP2400R2HST_MBX_FAIL: 952 case ISP2400R2HST_ASYNC_EVENT: 953 *isrp = r2hisr & 0xffff; 954 *mbox0p = (r2hisr >> 16); 955 *semap = 1; 956 return (1); 957 case ISP2400R2HST_RSPQ_UPDATE: 958 case ISP2400R2HST_ATIO_RSPQ_UPDATE: 959 case ISP2400R2HST_ATIO_RQST_UPDATE: 960 *isrp = r2hisr & 0xffff; 961 *mbox0p = 0; 962 *semap = 0; 963 return (1); 964 default: 965 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT); 966 isp_prt(isp, ISP_LOGERR, "unknown interrupt 0x%x\n", r2hisr); 967 return (0); 968 } 969 } 970 971 static uint32_t 972 isp_pci_rd_reg_2400(ispsoftc_t *isp, int regoff) 973 { 974 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 975 uint32_t rv; 976 int block = regoff & _BLK_REG_MASK; 977 978 switch (block) { 979 case BIU_BLOCK: 980 break; 981 case MBOX_BLOCK: 982 return (BXR2(pcs, IspVirt2Off(pcs, regoff))); 983 case SXP_BLOCK: 984 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK read at 0x%x", regoff); 985 return (0xffffffff); 986 case RISC_BLOCK: 987 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK read at 0x%x", regoff); 988 return (0xffffffff); 989 case DMA_BLOCK: 990 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK read at 0x%x", regoff); 991 return (0xffffffff); 992 default: 993 isp_prt(isp, ISP_LOGWARN, "unknown block read at 0x%x", regoff); 994 return (0xffffffff); 995 } 996 997 998 switch (regoff) { 999 case BIU2400_FLASH_ADDR: 1000 case BIU2400_FLASH_DATA: 1001 case BIU2400_ICR: 1002 case BIU2400_ISR: 1003 case BIU2400_CSR: 1004 case BIU2400_REQINP: 1005 case BIU2400_REQOUTP: 1006 case BIU2400_RSPINP: 1007 case BIU2400_RSPOUTP: 1008 case BIU2400_PRI_REQINP: 1009 case BIU2400_PRI_REQOUTP: 1010 case BIU2400_ATIO_RSPINP: 1011 case BIU2400_ATIO_RSPOUTP: 1012 case BIU2400_HCCR: 1013 case BIU2400_GPIOD: 1014 case BIU2400_GPIOE: 1015 case BIU2400_HSEMA: 1016 rv = BXR4(pcs, IspVirt2Off(pcs, regoff)); 1017 break; 1018 case BIU2400_R2HSTSLO: 1019 rv = BXR4(pcs, IspVirt2Off(pcs, regoff)); 1020 break; 1021 case BIU2400_R2HSTSHI: 1022 rv = BXR4(pcs, IspVirt2Off(pcs, regoff)) >> 16; 1023 break; 1024 default: 1025 isp_prt(isp, ISP_LOGERR, 1026 "isp_pci_rd_reg_2400: unknown offset %x", regoff); 1027 rv = 0xffffffff; 1028 break; 1029 } 1030 return (rv); 1031 } 1032 1033 static void 1034 isp_pci_wr_reg_2400(ispsoftc_t *isp, int regoff, uint32_t val) 1035 { 1036 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 1037 int block = regoff & _BLK_REG_MASK; 1038 volatile int junk; 1039 1040 switch (block) { 1041 case BIU_BLOCK: 1042 break; 1043 case MBOX_BLOCK: 1044 BXW2(pcs, IspVirt2Off(pcs, regoff), val); 1045 junk = BXR2(pcs, IspVirt2Off(pcs, regoff)); 1046 return; 1047 case SXP_BLOCK: 1048 isp_prt(isp, ISP_LOGWARN, "SXP_BLOCK write at 0x%x", regoff); 1049 return; 1050 case RISC_BLOCK: 1051 isp_prt(isp, ISP_LOGWARN, "RISC_BLOCK write at 0x%x", regoff); 1052 return; 1053 case DMA_BLOCK: 1054 isp_prt(isp, ISP_LOGWARN, "DMA_BLOCK write at 0x%x", regoff); 1055 return; 1056 default: 1057 isp_prt(isp, ISP_LOGWARN, "unknown block write at 0x%x", 1058 regoff); 1059 break; 1060 } 1061 1062 switch (regoff) { 1063 case BIU2400_FLASH_ADDR: 1064 case BIU2400_FLASH_DATA: 1065 case BIU2400_ICR: 1066 case BIU2400_ISR: 1067 case BIU2400_CSR: 1068 case BIU2400_REQINP: 1069 case BIU2400_REQOUTP: 1070 case BIU2400_RSPINP: 1071 case BIU2400_RSPOUTP: 1072 case BIU2400_PRI_REQINP: 1073 case BIU2400_PRI_REQOUTP: 1074 case BIU2400_ATIO_RSPINP: 1075 case BIU2400_ATIO_RSPOUTP: 1076 case BIU2400_HCCR: 1077 case BIU2400_GPIOD: 1078 case BIU2400_GPIOE: 1079 case BIU2400_HSEMA: 1080 BXW4(pcs, IspVirt2Off(pcs, regoff), val); 1081 junk = BXR4(pcs, IspVirt2Off(pcs, regoff)); 1082 break; 1083 default: 1084 isp_prt(isp, ISP_LOGERR, 1085 "isp_pci_wr_reg_2400: bad offset 0x%x", regoff); 1086 break; 1087 } 1088 } 1089 #endif 1090 1091 static uint32_t 1092 isp_pci_rd_reg(struct ispsoftc *isp, int regoff) 1093 { 1094 uint32_t rv; 1095 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 1096 int oldconf = 0; 1097 1098 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1099 /* 1100 * We will assume that someone has paused the RISC processor. 1101 */ 1102 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1103 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 1104 oldconf | BIU_PCI_CONF1_SXP); 1105 } 1106 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 1107 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1108 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 1109 } 1110 return (rv); 1111 } 1112 1113 static void 1114 isp_pci_wr_reg(struct ispsoftc *isp, int regoff, uint32_t val) 1115 { 1116 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 1117 int oldconf = 0; 1118 1119 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1120 /* 1121 * We will assume that someone has paused the RISC processor. 1122 */ 1123 oldconf = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1124 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 1125 oldconf | BIU_PCI_CONF1_SXP); 1126 } 1127 BXW2(pcs, IspVirt2Off(isp, regoff), val); 1128 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK) { 1129 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oldconf); 1130 } 1131 } 1132 1133 #if !(defined(ISP_DISABLE_1080_SUPPORT) && defined(ISP_DISABLE_12160_SUPPORT)) 1134 static uint32_t 1135 isp_pci_rd_reg_1080(struct ispsoftc *isp, int regoff) 1136 { 1137 uint16_t rv, oc = 0; 1138 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 1139 1140 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 1141 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 1142 uint16_t tc; 1143 /* 1144 * We will assume that someone has paused the RISC processor. 1145 */ 1146 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1147 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1148 if (regoff & SXP_BANK1_SELECT) 1149 tc |= BIU_PCI1080_CONF1_SXP1; 1150 else 1151 tc |= BIU_PCI1080_CONF1_SXP0; 1152 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 1153 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1154 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1155 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 1156 oc | BIU_PCI1080_CONF1_DMA); 1157 } 1158 rv = BXR2(pcs, IspVirt2Off(isp, regoff)); 1159 if (oc) { 1160 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 1161 } 1162 return (rv); 1163 } 1164 1165 static void 1166 isp_pci_wr_reg_1080(struct ispsoftc *isp, int regoff, uint32_t val) 1167 { 1168 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp; 1169 int oc = 0; 1170 1171 if ((regoff & _BLK_REG_MASK) == SXP_BLOCK || 1172 (regoff & _BLK_REG_MASK) == (SXP_BLOCK|SXP_BANK1_SELECT)) { 1173 uint16_t tc; 1174 /* 1175 * We will assume that someone has paused the RISC processor. 1176 */ 1177 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1178 tc = oc & ~BIU_PCI1080_CONF1_DMA; 1179 if (regoff & SXP_BANK1_SELECT) 1180 tc |= BIU_PCI1080_CONF1_SXP1; 1181 else 1182 tc |= BIU_PCI1080_CONF1_SXP0; 1183 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), tc); 1184 } else if ((regoff & _BLK_REG_MASK) == DMA_BLOCK) { 1185 oc = BXR2(pcs, IspVirt2Off(isp, BIU_CONF1)); 1186 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), 1187 oc | BIU_PCI1080_CONF1_DMA); 1188 } 1189 BXW2(pcs, IspVirt2Off(isp, regoff), val); 1190 if (oc) { 1191 BXW2(pcs, IspVirt2Off(isp, BIU_CONF1), oc); 1192 } 1193 } 1194 #endif 1195 1196 static int 1197 isp_pci_mbxdma(struct ispsoftc *isp) 1198 { 1199 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1200 bus_dma_tag_t dmat = isp->isp_dmatag; 1201 bus_dma_segment_t sg; 1202 bus_size_t len, dbound; 1203 fcparam *fcp; 1204 int rs, i; 1205 1206 if (isp->isp_rquest_dma) /* been here before? */ 1207 return (0); 1208 1209 if (isp->isp_type <= ISP_HA_SCSI_1040B) { 1210 dbound = 1 << 24; 1211 } else { 1212 /* 1213 * For 32-bit PCI DMA, the range is 32 bits or zero :-) 1214 */ 1215 dbound = 0; 1216 } 1217 len = isp->isp_maxcmds * sizeof (isp_hdl_t); 1218 isp->isp_xflist = (isp_hdl_t *) malloc(len, M_DEVBUF, M_WAITOK); 1219 if (isp->isp_xflist == NULL) { 1220 isp_prt(isp, ISP_LOGERR, "cannot malloc xflist array"); 1221 return (1); 1222 } 1223 memset(isp->isp_xflist, 0, len); 1224 for (len = 0; len < isp->isp_maxcmds - 1; len++) { 1225 isp->isp_xflist[len].cmd = &isp->isp_xflist[len+1]; 1226 } 1227 isp->isp_xffree = isp->isp_xflist; 1228 len = isp->isp_maxcmds * sizeof (bus_dmamap_t); 1229 pcs->pci_xfer_dmap = (bus_dmamap_t *) malloc(len, M_DEVBUF, M_WAITOK); 1230 if (pcs->pci_xfer_dmap == NULL) { 1231 free(isp->isp_xflist, M_DEVBUF); 1232 isp->isp_xflist = NULL; 1233 isp_prt(isp, ISP_LOGERR, "cannot malloc DMA map array"); 1234 return (1); 1235 } 1236 for (i = 0; i < isp->isp_maxcmds; i++) { 1237 if (bus_dmamap_create(dmat, MAXPHYS, (MAXPHYS / PAGE_SIZE) + 1, 1238 MAXPHYS, dbound, BUS_DMA_NOWAIT, &pcs->pci_xfer_dmap[i])) { 1239 isp_prt(isp, ISP_LOGERR, "cannot create DMA maps"); 1240 break; 1241 } 1242 } 1243 if (i < isp->isp_maxcmds) { 1244 while (--i >= 0) { 1245 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]); 1246 } 1247 free(isp->isp_xflist, M_DEVBUF); 1248 free(pcs->pci_xfer_dmap, M_DEVBUF); 1249 isp->isp_xflist = NULL; 1250 pcs->pci_xfer_dmap = NULL; 1251 return (1); 1252 } 1253 1254 /* 1255 * Allocate and map the request queue. 1256 */ 1257 len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN(isp)); 1258 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 0)) { 1259 goto dmafail; 1260 } 1261 if (bus_dmamem_map(isp->isp_dmatag, &sg, rs, len, 1262 (void *)&isp->isp_rquest, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 1263 goto dmafail; 1264 } 1265 if (bus_dmamap_create(dmat, len, 1, len, dbound, BUS_DMA_NOWAIT, 1266 &isp->isp_rqdmap)) { 1267 goto dmafail; 1268 } 1269 if (bus_dmamap_load(dmat, isp->isp_rqdmap, isp->isp_rquest, len, NULL, 1270 BUS_DMA_NOWAIT)) { 1271 goto dmafail; 1272 } 1273 isp->isp_rquest_dma = isp->isp_rqdmap->dm_segs[0].ds_addr; 1274 1275 /* 1276 * Allocate and map the result queue. 1277 */ 1278 len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN(isp)); 1279 if (bus_dmamem_alloc(dmat, len, PAGE_SIZE, 0, &sg, 1, &rs, 1280 BUS_DMA_NOWAIT)) { 1281 goto dmafail; 1282 } 1283 if (bus_dmamem_map(dmat, &sg, rs, len, 1284 (void *)&isp->isp_result, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 1285 goto dmafail; 1286 } 1287 if (bus_dmamap_create(dmat, len, 1, len, dbound, BUS_DMA_NOWAIT, 1288 &isp->isp_rsdmap)) { 1289 goto dmafail; 1290 } 1291 if (bus_dmamap_load(dmat, isp->isp_rsdmap, isp->isp_result, len, NULL, 1292 BUS_DMA_NOWAIT)) { 1293 goto dmafail; 1294 } 1295 isp->isp_result_dma = isp->isp_rsdmap->dm_segs[0].ds_addr; 1296 1297 if (IS_SCSI(isp)) { 1298 return (0); 1299 } 1300 1301 /* 1302 * Allocate and map an FC scratch area 1303 */ 1304 fcp = isp->isp_param; 1305 len = ISP_FC_SCRLEN; 1306 if (bus_dmamem_alloc(dmat, len, sizeof (uint64_t), 0, &sg, 1, &rs, 1307 BUS_DMA_NOWAIT)) { 1308 goto dmafail; 1309 } 1310 if (bus_dmamem_map(dmat, &sg, rs, len, 1311 (void *)&fcp->isp_scratch, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) { 1312 goto dmafail; 1313 } 1314 if (bus_dmamap_create(dmat, len, 1, len, dbound, BUS_DMA_NOWAIT, 1315 &isp->isp_scdmap)) { 1316 goto dmafail; 1317 } 1318 if (bus_dmamap_load(dmat, isp->isp_scdmap, fcp->isp_scratch, len, NULL, 1319 BUS_DMA_NOWAIT)) { 1320 goto dmafail; 1321 } 1322 fcp->isp_scdma = isp->isp_scdmap->dm_segs[0].ds_addr; 1323 return (0); 1324 dmafail: 1325 isp_prt(isp, ISP_LOGERR, "mailbox DMA setup failure"); 1326 for (i = 0; i < isp->isp_maxcmds; i++) { 1327 bus_dmamap_destroy(dmat, pcs->pci_xfer_dmap[i]); 1328 } 1329 free(isp->isp_xflist, M_DEVBUF); 1330 free(pcs->pci_xfer_dmap, M_DEVBUF); 1331 isp->isp_xflist = NULL; 1332 pcs->pci_xfer_dmap = NULL; 1333 return (1); 1334 } 1335 1336 static int 1337 isp_pci_dmasetup(struct ispsoftc *isp, struct scsipi_xfer *xs, void *arg) 1338 { 1339 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1340 ispreq_t *rq = arg; 1341 bus_dmamap_t dmap; 1342 bus_dma_segment_t *dm_segs; 1343 uint32_t nsegs, hidx; 1344 isp_ddir_t ddir; 1345 1346 hidx = isp_handle_index(isp, rq->req_handle); 1347 if (hidx == ISP_BAD_HANDLE_INDEX) { 1348 XS_SETERR(xs, HBA_BOTCH); 1349 return (CMD_COMPLETE); 1350 } 1351 dmap = pcs->pci_xfer_dmap[hidx]; 1352 if (xs->datalen == 0) { 1353 ddir = ISP_NOXFR; 1354 nsegs = 0; 1355 dm_segs = NULL; 1356 } else { 1357 int error; 1358 uint32_t flag, flg2; 1359 1360 if (sizeof (bus_addr_t) > 4) { 1361 if (rq->req_header.rqs_entry_type == RQSTYPE_T2RQS) { 1362 rq->req_header.rqs_entry_type = RQSTYPE_T3RQS; 1363 } else if (rq->req_header.rqs_entry_type == RQSTYPE_REQUEST) { 1364 rq->req_header.rqs_entry_type = RQSTYPE_A64; 1365 } 1366 } 1367 1368 if (xs->xs_control & XS_CTL_DATA_IN) { 1369 flg2 = BUS_DMASYNC_PREREAD; 1370 flag = BUS_DMA_READ; 1371 ddir = ISP_FROM_DEVICE; 1372 } else { 1373 flg2 = BUS_DMASYNC_PREWRITE; 1374 flag = BUS_DMA_WRITE; 1375 ddir = ISP_TO_DEVICE; 1376 } 1377 error = bus_dmamap_load(isp->isp_dmatag, dmap, xs->data, xs->datalen, 1378 NULL, ((xs->xs_control & XS_CTL_NOSLEEP) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING | flag); 1379 if (error) { 1380 isp_prt(isp, ISP_LOGWARN, "unable to load DMA (%d)", error); 1381 XS_SETERR(xs, HBA_BOTCH); 1382 if (error == EAGAIN || error == ENOMEM) { 1383 return (CMD_EAGAIN); 1384 } else { 1385 return (CMD_COMPLETE); 1386 } 1387 } 1388 dm_segs = dmap->dm_segs; 1389 nsegs = dmap->dm_nsegs; 1390 bus_dmamap_sync(isp->isp_dmatag, dmap, 0, dmap->dm_mapsize, flg2); 1391 } 1392 1393 if (isp_send_cmd(isp, rq, dm_segs, nsegs, xs->datalen, ddir) != CMD_QUEUED) { 1394 return (CMD_EAGAIN); 1395 } else { 1396 return (CMD_QUEUED); 1397 } 1398 } 1399 1400 static int 1401 isp_pci_intr(void *arg) 1402 { 1403 uint32_t isr; 1404 uint16_t sema, mbox; 1405 struct ispsoftc *isp = arg; 1406 1407 isp->isp_intcnt++; 1408 if (ISP_READ_ISR(isp, &isr, &sema, &mbox) == 0) { 1409 isp->isp_intbogus++; 1410 return (0); 1411 } else { 1412 isp->isp_osinfo.onintstack = 1; 1413 isp_intr(isp, isr, sema, mbox); 1414 isp->isp_osinfo.onintstack = 0; 1415 return (1); 1416 } 1417 } 1418 1419 static void 1420 isp_pci_dmateardown(struct ispsoftc *isp, XS_T *xs, uint32_t handle) 1421 { 1422 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1423 uint32_t hidx; 1424 bus_dmamap_t dmap; 1425 1426 hidx = isp_handle_index(isp, handle); 1427 if (hidx == ISP_BAD_HANDLE_INDEX) { 1428 isp_xs_prt(isp, xs, ISP_LOGERR, "bad handle on teardown"); 1429 return; 1430 } 1431 dmap = pcs->pci_xfer_dmap[hidx]; 1432 bus_dmamap_sync(isp->isp_dmatag, dmap, 0, dmap->dm_mapsize, 1433 xs->xs_control & XS_CTL_DATA_IN ? 1434 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1435 bus_dmamap_unload(isp->isp_dmatag, dmap); 1436 } 1437 1438 static void 1439 isp_pci_reset0(ispsoftc_t *isp) 1440 { 1441 ISP_DISABLE_INTS(isp); 1442 } 1443 1444 static void 1445 isp_pci_reset1(ispsoftc_t *isp) 1446 { 1447 if (!IS_24XX(isp)) { 1448 /* Make sure the BIOS is disabled */ 1449 isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS); 1450 } 1451 /* and enable interrupts */ 1452 ISP_ENABLE_INTS(isp); 1453 } 1454 1455 static void 1456 isp_pci_dumpregs(struct ispsoftc *isp, const char *msg) 1457 { 1458 struct isp_pcisoftc *pcs = (struct isp_pcisoftc *)isp; 1459 if (msg) 1460 printf("%s: %s\n", device_xname(isp->isp_osinfo.dev), msg); 1461 if (IS_SCSI(isp)) 1462 printf(" biu_conf1=%x", ISP_READ(isp, BIU_CONF1)); 1463 else 1464 printf(" biu_csr=%x", ISP_READ(isp, BIU2100_CSR)); 1465 printf(" biu_icr=%x biu_isr=%x biu_sema=%x ", ISP_READ(isp, BIU_ICR), 1466 ISP_READ(isp, BIU_ISR), ISP_READ(isp, BIU_SEMA)); 1467 printf("risc_hccr=%x\n", ISP_READ(isp, HCCR)); 1468 1469 1470 if (IS_SCSI(isp)) { 1471 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE); 1472 printf(" cdma_conf=%x cdma_sts=%x cdma_fifostat=%x\n", 1473 ISP_READ(isp, CDMA_CONF), ISP_READ(isp, CDMA_STATUS), 1474 ISP_READ(isp, CDMA_FIFO_STS)); 1475 printf(" ddma_conf=%x ddma_sts=%x ddma_fifostat=%x\n", 1476 ISP_READ(isp, DDMA_CONF), ISP_READ(isp, DDMA_STATUS), 1477 ISP_READ(isp, DDMA_FIFO_STS)); 1478 printf(" sxp_int=%x sxp_gross=%x sxp(scsi_ctrl)=%x\n", 1479 ISP_READ(isp, SXP_INTERRUPT), 1480 ISP_READ(isp, SXP_GROSS_ERR), 1481 ISP_READ(isp, SXP_PINS_CTRL)); 1482 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE); 1483 } 1484 printf(" mbox regs: %x %x %x %x %x\n", 1485 ISP_READ(isp, OUTMAILBOX0), ISP_READ(isp, OUTMAILBOX1), 1486 ISP_READ(isp, OUTMAILBOX2), ISP_READ(isp, OUTMAILBOX3), 1487 ISP_READ(isp, OUTMAILBOX4)); 1488 printf(" PCI Status Command/Status=%x\n", 1489 pci_conf_read(pcs->pci_pc, pcs->pci_tag, PCI_COMMAND_STATUS_REG)); 1490 } 1491