1*fb38d839Srin /* $NetBSD: igc_phy.h,v 1.2 2023/10/04 07:35:27 rin Exp $ */ 2d0d8f2a5Srin /* $OpenBSD: igc_phy.h,v 1.2 2022/05/11 06:14:15 kevlo Exp $ */ 3d0d8f2a5Srin /*- 4d0d8f2a5Srin * Copyright 2021 Intel Corp 5d0d8f2a5Srin * Copyright 2021 Rubicon Communications, LLC (Netgate) 6d0d8f2a5Srin * SPDX-License-Identifier: BSD-3-Clause 7d0d8f2a5Srin * 8d0d8f2a5Srin * $FreeBSD$ 9d0d8f2a5Srin */ 10d0d8f2a5Srin 11d0d8f2a5Srin #ifndef _IGC_PHY_H_ 12d0d8f2a5Srin #define _IGC_PHY_H_ 13d0d8f2a5Srin 14d0d8f2a5Srin void igc_init_phy_ops_generic(struct igc_hw *); 15d0d8f2a5Srin int igc_null_read_reg(struct igc_hw *, uint32_t, uint16_t *); 16d0d8f2a5Srin void igc_null_phy_generic(struct igc_hw *); 17d0d8f2a5Srin int igc_null_lplu_state(struct igc_hw *, bool); 18d0d8f2a5Srin int igc_null_write_reg(struct igc_hw *, uint32_t, uint16_t); 19d0d8f2a5Srin int igc_null_set_page(struct igc_hw *, uint16_t); 20d0d8f2a5Srin int igc_check_downshift_generic(struct igc_hw *); 21d0d8f2a5Srin int igc_check_reset_block_generic(struct igc_hw *); 22d0d8f2a5Srin int igc_get_phy_id(struct igc_hw *); 23d0d8f2a5Srin int igc_phy_hw_reset_generic(struct igc_hw *); 24d0d8f2a5Srin int igc_phy_reset_dsp_generic(struct igc_hw *); 25d0d8f2a5Srin int igc_set_d3_lplu_state_generic(struct igc_hw *, bool); 26d0d8f2a5Srin int igc_setup_copper_link_generic(struct igc_hw *); 27d0d8f2a5Srin int igc_phy_has_link_generic(struct igc_hw *, uint32_t, uint32_t, bool *); 28d0d8f2a5Srin int igc_determine_phy_address(struct igc_hw *); 29d0d8f2a5Srin int igc_enable_phy_wakeup_reg_access_bm(struct igc_hw *, uint16_t *); 30d0d8f2a5Srin int igc_disable_phy_wakeup_reg_access_bm(struct igc_hw *, uint16_t *); 31d0d8f2a5Srin void igc_power_up_phy_copper(struct igc_hw *); 32d0d8f2a5Srin void igc_power_down_phy_copper(struct igc_hw *); 33d0d8f2a5Srin int igc_read_phy_reg_mdic(struct igc_hw *, uint32_t offset, uint16_t *); 34d0d8f2a5Srin int igc_write_phy_reg_mdic(struct igc_hw *, uint32_t offset, uint16_t); 35d0d8f2a5Srin int igc_read_xmdio_reg(struct igc_hw *, uint16_t, uint8_t, uint16_t *); 36d0d8f2a5Srin int igc_write_xmdio_reg(struct igc_hw *, uint16_t, uint8_t, uint16_t); 37d0d8f2a5Srin int igc_write_phy_reg_gpy(struct igc_hw *, uint32_t, uint16_t); 38d0d8f2a5Srin int igc_read_phy_reg_gpy(struct igc_hw *, uint32_t, uint16_t *); 39d0d8f2a5Srin int igc_wait_autoneg(struct igc_hw *); 40d0d8f2a5Srin 41d0d8f2a5Srin /* IGP01IGC Specific Registers */ 42d0d8f2a5Srin #define IGP01IGC_PHY_PORT_CONFIG 0x10 /* Port Config */ 43d0d8f2a5Srin #define IGP01IGC_PHY_PORT_STATUS 0x11 /* Status */ 44d0d8f2a5Srin #define IGP01IGC_PHY_PORT_CTRL 0x12 /* Control */ 45d0d8f2a5Srin #define IGP01IGC_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ 46d0d8f2a5Srin #define IGP02IGC_PHY_POWER_MGMT 0x19 /* Power Management */ 47d0d8f2a5Srin #define IGP01IGC_PHY_PAGE_SELECT 0x1F /* Page Select */ 48d0d8f2a5Srin #define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */ 49d0d8f2a5Srin #define IGP_PAGE_SHIFT 5 50d0d8f2a5Srin #define PHY_REG_MASK 0x1F 51d0d8f2a5Srin #define IGC_I225_PHPM 0x0E14 /* I225 PHY Power Management */ 52d0d8f2a5Srin #define IGC_I225_PHPM_DIS_1000_D3 0x0008 /* Disable 1G in D3 */ 53d0d8f2a5Srin #define IGC_I225_PHPM_LINK_ENERGY 0x0010 /* Link Energy Detect */ 54d0d8f2a5Srin #define IGC_I225_PHPM_GO_LINKD 0x0020 /* Go Link Disconnect */ 55d0d8f2a5Srin #define IGC_I225_PHPM_DIS_1000 0x0040 /* Disable 1G globally */ 56d0d8f2a5Srin #define IGC_I225_PHPM_SPD_B2B_EN 0x0080 /* Smart Power Down Back2Back */ 57d0d8f2a5Srin #define IGC_I225_PHPM_RST_COMPL 0x0100 /* PHY Reset Completed */ 58d0d8f2a5Srin #define IGC_I225_PHPM_DIS_100_D3 0x0200 /* Disable 100M in D3 */ 59d0d8f2a5Srin #define IGC_I225_PHPM_ULP 0x0400 /* Ultra Low-Power Mode */ 60d0d8f2a5Srin #define IGC_I225_PHPM_DIS_2500 0x0800 /* Disable 2.5G globally */ 61d0d8f2a5Srin #define IGC_I225_PHPM_DIS_2500_D3 0x1000 /* Disable 2.5G in D3 */ 62d0d8f2a5Srin /* GPY211 - I225 defines */ 63d0d8f2a5Srin #define GPY_MMD_MASK 0xFFFF0000 64d0d8f2a5Srin #define GPY_MMD_SHIFT 16 65d0d8f2a5Srin #define GPY_REG_MASK 0x0000FFFF 66d0d8f2a5Srin #define IGP01IGC_PHY_PCS_INIT_REG 0x00B4 67d0d8f2a5Srin #define IGP01IGC_PHY_POLARITY_MASK 0x0078 68d0d8f2a5Srin 69d0d8f2a5Srin #define IGP01IGC_PSCR_AUTO_MDIX 0x1000 70d0d8f2a5Srin #define IGP01IGC_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */ 71d0d8f2a5Srin 72d0d8f2a5Srin #define IGP01IGC_PSCFR_SMART_SPEED 0x0080 73d0d8f2a5Srin 74d0d8f2a5Srin #define IGP02IGC_PM_SPD 0x0001 /* Smart Power Down */ 75d0d8f2a5Srin #define IGP02IGC_PM_D0_LPLU 0x0002 /* For D0a states */ 76d0d8f2a5Srin #define IGP02IGC_PM_D3_LPLU 0x0004 /* For all other states */ 77d0d8f2a5Srin 78d0d8f2a5Srin #define IGP01IGC_PLHR_SS_DOWNGRADE 0x8000 79d0d8f2a5Srin 80d0d8f2a5Srin #define IGP01IGC_PSSR_POLARITY_REVERSED 0x0002 81d0d8f2a5Srin #define IGP01IGC_PSSR_MDIX 0x0800 82d0d8f2a5Srin #define IGP01IGC_PSSR_SPEED_MASK 0xC000 83d0d8f2a5Srin #define IGP01IGC_PSSR_SPEED_1000MBPS 0xC000 84d0d8f2a5Srin 85d0d8f2a5Srin #define IGP02IGC_PHY_CHANNEL_NUM 4 86d0d8f2a5Srin #define IGP02IGC_PHY_AGC_A 0x11B1 87d0d8f2a5Srin #define IGP02IGC_PHY_AGC_B 0x12B1 88d0d8f2a5Srin #define IGP02IGC_PHY_AGC_C 0x14B1 89d0d8f2a5Srin #define IGP02IGC_PHY_AGC_D 0x18B1 90d0d8f2a5Srin 91d0d8f2a5Srin #define IGP02IGC_AGC_LENGTH_SHIFT 9 /* Course=15:13, Fine=12:9 */ 92d0d8f2a5Srin #define IGP02IGC_AGC_LENGTH_MASK 0x7F 93d0d8f2a5Srin #define IGP02IGC_AGC_RANGE 15 94d0d8f2a5Srin 95d0d8f2a5Srin #define IGC_CABLE_LENGTH_UNDEFINED 0xFF 96d0d8f2a5Srin 97d0d8f2a5Srin #define IGC_KMRNCTRLSTA_OFFSET 0x001F0000 98d0d8f2a5Srin #define IGC_KMRNCTRLSTA_OFFSET_SHIFT 16 99d0d8f2a5Srin #define IGC_KMRNCTRLSTA_REN 0x00200000 100d0d8f2a5Srin #define IGC_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */ 101d0d8f2a5Srin #define IGC_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */ 102d0d8f2a5Srin #define IGC_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */ 103d0d8f2a5Srin #define IGC_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */ 104d0d8f2a5Srin #define IGC_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */ 105d0d8f2a5Srin 106d0d8f2a5Srin #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 107d0d8f2a5Srin #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Ctrl */ 108d0d8f2a5Srin #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Ctrl */ 109d0d8f2a5Srin #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */ 110d0d8f2a5Srin 111d0d8f2a5Srin /* IFE PHY Extended Status Control */ 112d0d8f2a5Srin #define IFE_PESC_POLARITY_REVERSED 0x0100 113d0d8f2a5Srin 114d0d8f2a5Srin /* IFE PHY Special Control */ 115d0d8f2a5Srin #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 116d0d8f2a5Srin #define IFE_PSC_FORCE_POLARITY 0x0020 117d0d8f2a5Srin 118d0d8f2a5Srin /* IFE PHY Special Control and LED Control */ 119d0d8f2a5Srin #define IFE_PSCL_PROBE_MODE 0x0020 120d0d8f2a5Srin #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ 121d0d8f2a5Srin #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ 122d0d8f2a5Srin 123d0d8f2a5Srin /* IFE PHY MDIX Control */ 124d0d8f2a5Srin #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ 125d0d8f2a5Srin #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */ 126d0d8f2a5Srin #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto, 0=disable */ 127d0d8f2a5Srin 128d0d8f2a5Srin #endif /* _IGC_PHY_H_ */ 129