1 /* $NetBSD: igc_i225.c,v 1.2 2023/10/04 07:35:27 rin Exp $ */ 2 /* $OpenBSD: igc_i225.c,v 1.4 2023/02/03 11:31:52 mbuhl Exp $ */ 3 /*- 4 * Copyright 2021 Intel Corp 5 * Copyright 2021 Rubicon Communications, LLC (Netgate) 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <sys/cdefs.h> 10 __KERNEL_RCSID(0, "$NetBSD: igc_i225.c,v 1.2 2023/10/04 07:35:27 rin Exp $"); 11 12 #include <dev/pci/igc/igc_api.h> 13 14 int igc_init_nvm_params_i225(struct igc_hw *); 15 int igc_init_mac_params_i225(struct igc_hw *); 16 int igc_init_phy_params_i225(struct igc_hw *); 17 int igc_reset_hw_i225(struct igc_hw *); 18 int igc_acquire_nvm_i225(struct igc_hw *); 19 void igc_release_nvm_i225(struct igc_hw *); 20 int igc_get_hw_semaphore_i225(struct igc_hw *); 21 int __igc_write_nvm_srwr(struct igc_hw *, uint16_t, uint16_t, uint16_t *); 22 int igc_pool_flash_update_done_i225(struct igc_hw *); 23 24 /** 25 * igc_init_nvm_params_i225 - Init NVM func ptrs. 26 * @hw: pointer to the HW structure 27 **/ 28 int 29 igc_init_nvm_params_i225(struct igc_hw *hw) 30 { 31 struct igc_nvm_info *nvm = &hw->nvm; 32 uint32_t eecd = IGC_READ_REG(hw, IGC_EECD); 33 uint16_t size; 34 35 DEBUGFUNC("igc_init_nvm_params_i225"); 36 37 size = (uint16_t)((eecd & IGC_EECD_SIZE_EX_MASK) >> 38 IGC_EECD_SIZE_EX_SHIFT); 39 /* 40 * Added to a constant, "size" becomes the left-shift value 41 * for setting word_size. 42 */ 43 size += NVM_WORD_SIZE_BASE_SHIFT; 44 45 /* Just in case size is out of range, cap it to the largest 46 * EEPROM size supported. 47 */ 48 if (size > 15) 49 size = 15; 50 51 nvm->word_size = 1 << size; 52 nvm->opcode_bits = 8; 53 nvm->delay_usec = 1; 54 nvm->type = igc_nvm_eeprom_spi; 55 56 nvm->page_size = eecd & IGC_EECD_ADDR_BITS ? 32 : 8; 57 nvm->address_bits = eecd & IGC_EECD_ADDR_BITS ? 16 : 8; 58 59 if (nvm->word_size == (1 << 15)) 60 nvm->page_size = 128; 61 62 nvm->ops.acquire = igc_acquire_nvm_i225; 63 nvm->ops.release = igc_release_nvm_i225; 64 if (igc_get_flash_presence_i225(hw)) { 65 hw->nvm.type = igc_nvm_flash_hw; 66 nvm->ops.read = igc_read_nvm_srrd_i225; 67 nvm->ops.write = igc_write_nvm_srwr_i225; 68 nvm->ops.validate = igc_validate_nvm_checksum_i225; 69 nvm->ops.update = igc_update_nvm_checksum_i225; 70 } else { 71 hw->nvm.type = igc_nvm_invm; 72 nvm->ops.write = igc_null_write_nvm; 73 nvm->ops.validate = igc_null_ops_generic; 74 nvm->ops.update = igc_null_ops_generic; 75 } 76 77 return IGC_SUCCESS; 78 } 79 80 /** 81 * igc_init_mac_params_i225 - Init MAC func ptrs. 82 * @hw: pointer to the HW structure 83 **/ 84 int 85 igc_init_mac_params_i225(struct igc_hw *hw) 86 { 87 struct igc_mac_info *mac = &hw->mac; 88 struct igc_dev_spec_i225 *dev_spec = &hw->dev_spec._i225; 89 90 DEBUGFUNC("igc_init_mac_params_i225"); 91 92 /* Initialize function pointer */ 93 igc_init_mac_ops_generic(hw); 94 95 /* Set media type */ 96 hw->phy.media_type = igc_media_type_copper; 97 /* Set mta register count */ 98 mac->mta_reg_count = 128; 99 /* Set rar entry count */ 100 mac->rar_entry_count = IGC_RAR_ENTRIES_BASE; 101 102 /* reset */ 103 mac->ops.reset_hw = igc_reset_hw_i225; 104 /* hw initialization */ 105 mac->ops.init_hw = igc_init_hw_i225; 106 /* link setup */ 107 mac->ops.setup_link = igc_setup_link_generic; 108 /* check for link */ 109 mac->ops.check_for_link = igc_check_for_link_i225; 110 /* link info */ 111 mac->ops.get_link_up_info = igc_get_speed_and_duplex_copper_generic; 112 /* acquire SW_FW sync */ 113 mac->ops.acquire_swfw_sync = igc_acquire_swfw_sync_i225; 114 /* release SW_FW sync */ 115 mac->ops.release_swfw_sync = igc_release_swfw_sync_i225; 116 117 /* Allow a single clear of the SW semaphore on I225 */ 118 dev_spec->clear_semaphore_once = true; 119 mac->ops.setup_physical_interface = igc_setup_copper_link_i225; 120 121 /* Set if part includes ASF firmware */ 122 mac->asf_firmware_present = true; 123 124 /* multicast address update */ 125 mac->ops.update_mc_addr_list = igc_update_mc_addr_list_generic; 126 127 mac->ops.write_vfta = igc_write_vfta_generic; 128 129 return IGC_SUCCESS; 130 } 131 132 /** 133 * igc_init_phy_params_i225 - Init PHY func ptrs. 134 * @hw: pointer to the HW structure 135 **/ 136 int 137 igc_init_phy_params_i225(struct igc_hw *hw) 138 { 139 struct igc_phy_info *phy = &hw->phy; 140 int ret_val = IGC_SUCCESS; 141 142 DEBUGFUNC("igc_init_phy_params_i225"); 143 144 if (hw->phy.media_type != igc_media_type_copper) { 145 phy->type = igc_phy_none; 146 goto out; 147 } 148 149 phy->ops.power_up = igc_power_up_phy_copper; 150 phy->ops.power_down = igc_power_down_phy_copper_base; 151 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT_2500; 152 phy->reset_delay_us = 100; 153 phy->ops.acquire = igc_acquire_phy_base; 154 phy->ops.check_reset_block = igc_check_reset_block_generic; 155 phy->ops.release = igc_release_phy_base; 156 phy->ops.reset = igc_phy_hw_reset_generic; 157 phy->ops.read_reg = igc_read_phy_reg_gpy; 158 phy->ops.write_reg = igc_write_phy_reg_gpy; 159 160 /* Make sure the PHY is in a good state. Several people have reported 161 * firmware leaving the PHY's page select register set to something 162 * other than the default of zero, which causes the PHY ID read to 163 * access something other than the intended register. 164 */ 165 ret_val = hw->phy.ops.reset(hw); 166 if (ret_val) 167 goto out; 168 169 ret_val = igc_get_phy_id(hw); 170 phy->type = igc_phy_i225; 171 172 out: 173 return ret_val; 174 } 175 176 /** 177 * igc_reset_hw_i225 - Reset hardware 178 * @hw: pointer to the HW structure 179 * 180 * This resets the hardware into a known state. 181 **/ 182 int 183 igc_reset_hw_i225(struct igc_hw *hw) 184 { 185 uint32_t ctrl; 186 int ret_val; 187 188 DEBUGFUNC("igc_reset_hw_i225"); 189 190 /* 191 * Prevent the PCI-E bus from sticking if there is no TLP connection 192 * on the last TLP read/write transaction when MAC is reset. 193 */ 194 ret_val = igc_disable_pcie_master_generic(hw); 195 if (ret_val) 196 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 197 198 DEBUGOUT("Masking off all interrupts\n"); 199 IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff); 200 201 IGC_WRITE_REG(hw, IGC_RCTL, 0); 202 IGC_WRITE_REG(hw, IGC_TCTL, IGC_TCTL_PSP); 203 IGC_WRITE_FLUSH(hw); 204 205 msec_delay(10); 206 207 ctrl = IGC_READ_REG(hw, IGC_CTRL); 208 209 DEBUGOUT("Issuing a global reset to MAC\n"); 210 IGC_WRITE_REG(hw, IGC_CTRL, ctrl | IGC_CTRL_DEV_RST); 211 212 ret_val = igc_get_auto_rd_done_generic(hw); 213 if (ret_val) { 214 /* 215 * When auto config read does not complete, do not 216 * return with an error. This can happen in situations 217 * where there is no eeprom and prevents getting link. 218 */ 219 DEBUGOUT("Auto Read Done did not complete\n"); 220 } 221 222 /* Clear any pending interrupt events. */ 223 IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff); 224 IGC_READ_REG(hw, IGC_ICR); 225 226 /* Install any alternate MAC address into RAR0 */ 227 ret_val = igc_check_alt_mac_addr_generic(hw); 228 229 return ret_val; 230 } 231 232 /* igc_acquire_nvm_i225 - Request for access to EEPROM 233 * @hw: pointer to the HW structure 234 * 235 * Acquire the necessary semaphores for exclusive access to the EEPROM. 236 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 237 * Return successful if access grant bit set, else clear the request for 238 * EEPROM access and return -IGC_ERR_NVM (-1). 239 */ 240 int 241 igc_acquire_nvm_i225(struct igc_hw *hw) 242 { 243 int ret_val; 244 245 DEBUGFUNC("igc_acquire_nvm_i225"); 246 247 ret_val = igc_acquire_swfw_sync_i225(hw, IGC_SWFW_EEP_SM); 248 249 return ret_val; 250 } 251 252 /* igc_release_nvm_i225 - Release exclusive access to EEPROM 253 * @hw: pointer to the HW structure 254 * 255 * Stop any current commands to the EEPROM and clear the EEPROM request bit, 256 * then release the semaphores acquired. 257 */ 258 void 259 igc_release_nvm_i225(struct igc_hw *hw) 260 { 261 DEBUGFUNC("igc_release_nvm_i225"); 262 263 igc_release_swfw_sync_i225(hw, IGC_SWFW_EEP_SM); 264 } 265 266 /* igc_acquire_swfw_sync_i225 - Acquire SW/FW semaphore 267 * @hw: pointer to the HW structure 268 * @mask: specifies which semaphore to acquire 269 * 270 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 271 * will also specify which port we're acquiring the lock for. 272 */ 273 int 274 igc_acquire_swfw_sync_i225(struct igc_hw *hw, uint16_t mask) 275 { 276 uint32_t swfw_sync; 277 uint32_t swmask = mask; 278 uint32_t fwmask = mask << 16; 279 int ret_val = IGC_SUCCESS; 280 int i = 0, timeout = 200; /* FIXME: find real value to use here */ 281 282 DEBUGFUNC("igc_acquire_swfw_sync_i225"); 283 284 while (i < timeout) { 285 if (igc_get_hw_semaphore_i225(hw)) { 286 ret_val = -IGC_ERR_SWFW_SYNC; 287 goto out; 288 } 289 290 swfw_sync = IGC_READ_REG(hw, IGC_SW_FW_SYNC); 291 if (!(swfw_sync & (fwmask | swmask))) 292 break; 293 294 /* Firmware currently using resource (fwmask) 295 * or other software thread using resource (swmask) 296 */ 297 igc_put_hw_semaphore_generic(hw); 298 msec_delay(5); 299 i++; 300 } 301 302 if (i == timeout) { 303 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 304 ret_val = -IGC_ERR_SWFW_SYNC; 305 goto out; 306 } 307 308 swfw_sync |= swmask; 309 IGC_WRITE_REG(hw, IGC_SW_FW_SYNC, swfw_sync); 310 311 igc_put_hw_semaphore_generic(hw); 312 313 out: 314 return ret_val; 315 } 316 317 /* igc_release_swfw_sync_i225 - Release SW/FW semaphore 318 * @hw: pointer to the HW structure 319 * @mask: specifies which semaphore to acquire 320 * 321 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 322 * will also specify which port we're releasing the lock for. 323 */ 324 void 325 igc_release_swfw_sync_i225(struct igc_hw *hw, uint16_t mask) 326 { 327 uint32_t swfw_sync; 328 329 DEBUGFUNC("igc_release_swfw_sync_i225"); 330 331 while (igc_get_hw_semaphore_i225(hw) != IGC_SUCCESS) 332 ; /* Empty */ 333 334 swfw_sync = IGC_READ_REG(hw, IGC_SW_FW_SYNC); 335 swfw_sync &= ~mask; 336 IGC_WRITE_REG(hw, IGC_SW_FW_SYNC, swfw_sync); 337 338 igc_put_hw_semaphore_generic(hw); 339 } 340 341 /* 342 * igc_setup_copper_link_i225 - Configure copper link settings 343 * @hw: pointer to the HW structure 344 * 345 * Configures the link for auto-neg or forced speed and duplex. Then we check 346 * for link, once link is established calls to configure collision distance 347 * and flow control are called. 348 */ 349 int 350 igc_setup_copper_link_i225(struct igc_hw *hw) 351 { 352 uint32_t ctrl, phpm_reg; 353 int ret_val; 354 355 DEBUGFUNC("igc_setup_copper_link_i225"); 356 357 ctrl = IGC_READ_REG(hw, IGC_CTRL); 358 ctrl |= IGC_CTRL_SLU; 359 ctrl &= ~(IGC_CTRL_FRCSPD | IGC_CTRL_FRCDPX); 360 IGC_WRITE_REG(hw, IGC_CTRL, ctrl); 361 362 phpm_reg = IGC_READ_REG(hw, IGC_I225_PHPM); 363 phpm_reg &= ~IGC_I225_PHPM_GO_LINKD; 364 IGC_WRITE_REG(hw, IGC_I225_PHPM, phpm_reg); 365 366 ret_val = igc_setup_copper_link_generic(hw); 367 368 return ret_val; 369 } 370 371 /* igc_get_hw_semaphore_i225 - Acquire hardware semaphore 372 * @hw: pointer to the HW structure 373 * 374 * Acquire the HW semaphore to access the PHY or NVM 375 */ 376 int 377 igc_get_hw_semaphore_i225(struct igc_hw *hw) 378 { 379 uint32_t swsm; 380 int timeout = hw->nvm.word_size + 1; 381 int i = 0; 382 383 DEBUGFUNC("igc_get_hw_semaphore_i225"); 384 385 /* Get the SW semaphore */ 386 while (i < timeout) { 387 swsm = IGC_READ_REG(hw, IGC_SWSM); 388 if (!(swsm & IGC_SWSM_SMBI)) 389 break; 390 391 DELAY(50); 392 i++; 393 } 394 395 if (i == timeout) { 396 /* In rare circumstances, the SW semaphore may already be held 397 * unintentionally. Clear the semaphore once before giving up. 398 */ 399 if (hw->dev_spec._i225.clear_semaphore_once) { 400 hw->dev_spec._i225.clear_semaphore_once = false; 401 igc_put_hw_semaphore_generic(hw); 402 for (i = 0; i < timeout; i++) { 403 swsm = IGC_READ_REG(hw, IGC_SWSM); 404 if (!(swsm & IGC_SWSM_SMBI)) 405 break; 406 407 DELAY(50); 408 } 409 } 410 411 /* If we do not have the semaphore here, we have to give up. */ 412 if (i == timeout) { 413 DEBUGOUT("Driver can't access device -\n"); 414 DEBUGOUT("SMBI bit is set.\n"); 415 return -IGC_ERR_NVM; 416 } 417 } 418 419 /* Get the FW semaphore. */ 420 for (i = 0; i < timeout; i++) { 421 swsm = IGC_READ_REG(hw, IGC_SWSM); 422 IGC_WRITE_REG(hw, IGC_SWSM, swsm | IGC_SWSM_SWESMBI); 423 424 /* Semaphore acquired if bit latched */ 425 if (IGC_READ_REG(hw, IGC_SWSM) & IGC_SWSM_SWESMBI) 426 break; 427 428 DELAY(50); 429 } 430 431 if (i == timeout) { 432 /* Release semaphores */ 433 igc_put_hw_semaphore_generic(hw); 434 DEBUGOUT("Driver can't access the NVM\n"); 435 return -IGC_ERR_NVM; 436 } 437 438 return IGC_SUCCESS; 439 } 440 441 /* igc_read_nvm_srrd_i225 - Reads Shadow Ram using EERD register 442 * @hw: pointer to the HW structure 443 * @offset: offset of word in the Shadow Ram to read 444 * @words: number of words to read 445 * @data: word read from the Shadow Ram 446 * 447 * Reads a 16 bit word from the Shadow Ram using the EERD register. 448 * Uses necessary synchronization semaphores. 449 */ 450 int 451 igc_read_nvm_srrd_i225(struct igc_hw *hw, uint16_t offset, uint16_t words, 452 uint16_t *data) 453 { 454 uint16_t i, count; 455 int status = IGC_SUCCESS; 456 457 DEBUGFUNC("igc_read_nvm_srrd_i225"); 458 459 /* We cannot hold synchronization semaphores for too long, 460 * because of forceful takeover procedure. However it is more efficient 461 * to read in bursts than synchronizing access for each word. 462 */ 463 for (i = 0; i < words; i += IGC_EERD_EEWR_MAX_COUNT) { 464 count = (words - i) / IGC_EERD_EEWR_MAX_COUNT > 0 ? 465 IGC_EERD_EEWR_MAX_COUNT : (words - i); 466 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) { 467 status = igc_read_nvm_eerd(hw, offset, count, data + i); 468 hw->nvm.ops.release(hw); 469 } else { 470 status = IGC_ERR_SWFW_SYNC; 471 } 472 473 if (status != IGC_SUCCESS) 474 break; 475 } 476 477 return status; 478 } 479 480 /* igc_write_nvm_srwr_i225 - Write to Shadow RAM using EEWR 481 * @hw: pointer to the HW structure 482 * @offset: offset within the Shadow RAM to be written to 483 * @words: number of words to write 484 * @data: 16 bit word(s) to be written to the Shadow RAM 485 * 486 * Writes data to Shadow RAM at offset using EEWR register. 487 * 488 * If igc_update_nvm_checksum is not called after this function , the 489 * data will not be committed to FLASH and also Shadow RAM will most likely 490 * contain an invalid checksum. 491 * 492 * If error code is returned, data and Shadow RAM may be inconsistent - buffer 493 * partially written. 494 */ 495 int 496 igc_write_nvm_srwr_i225(struct igc_hw *hw, uint16_t offset, uint16_t words, 497 uint16_t *data) 498 { 499 uint16_t i, count; 500 int status = IGC_SUCCESS; 501 502 DEBUGFUNC("igc_write_nvm_srwr_i225"); 503 504 /* We cannot hold synchronization semaphores for too long, 505 * because of forceful takeover procedure. However it is more efficient 506 * to write in bursts than synchronizing access for each word. 507 */ 508 for (i = 0; i < words; i += IGC_EERD_EEWR_MAX_COUNT) { 509 count = (words - i) / IGC_EERD_EEWR_MAX_COUNT > 0 ? 510 IGC_EERD_EEWR_MAX_COUNT : (words - i); 511 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) { 512 status = __igc_write_nvm_srwr(hw, offset, count, 513 data + i); 514 hw->nvm.ops.release(hw); 515 } else 516 status = IGC_ERR_SWFW_SYNC; 517 518 if (status != IGC_SUCCESS) 519 break; 520 } 521 522 return status; 523 } 524 525 /* __igc_write_nvm_srwr - Write to Shadow Ram using EEWR 526 * @hw: pointer to the HW structure 527 * @offset: offset within the Shadow Ram to be written to 528 * @words: number of words to write 529 * @data: 16 bit word(s) to be written to the Shadow Ram 530 * 531 * Writes data to Shadow Ram at offset using EEWR register. 532 * 533 * If igc_update_nvm_checksum is not called after this function , the 534 * Shadow Ram will most likely contain an invalid checksum. 535 */ 536 int 537 __igc_write_nvm_srwr(struct igc_hw *hw, uint16_t offset, uint16_t words, 538 uint16_t *data) 539 { 540 struct igc_nvm_info *nvm = &hw->nvm; 541 uint32_t i, k, eewr = 0; 542 uint32_t attempts = 100000; 543 int ret_val = IGC_SUCCESS; 544 545 DEBUGFUNC("__igc_write_nvm_srwr"); 546 547 /* A check for invalid values: offset too large, too many words, 548 * too many words for the offset, and not enough words. 549 */ 550 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 551 (words == 0)) { 552 DEBUGOUT("nvm parameter(s) out of bounds\n"); 553 ret_val = -IGC_ERR_NVM; 554 goto out; 555 } 556 557 for (i = 0; i < words; i++) { 558 eewr = ((offset + i) << IGC_NVM_RW_ADDR_SHIFT) | 559 (data[i] << IGC_NVM_RW_REG_DATA) | IGC_NVM_RW_REG_START; 560 561 IGC_WRITE_REG(hw, IGC_SRWR, eewr); 562 563 for (k = 0; k < attempts; k++) { 564 if (IGC_NVM_RW_REG_DONE & IGC_READ_REG(hw, IGC_SRWR)) { 565 ret_val = IGC_SUCCESS; 566 break; 567 } 568 DELAY(5); 569 } 570 571 if (ret_val != IGC_SUCCESS) { 572 DEBUGOUT("Shadow RAM write EEWR timed out\n"); 573 break; 574 } 575 } 576 577 out: 578 return ret_val; 579 } 580 581 /* igc_validate_nvm_checksum_i225 - Validate EEPROM checksum 582 * @hw: pointer to the HW structure 583 * 584 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 585 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 586 */ 587 int 588 igc_validate_nvm_checksum_i225(struct igc_hw *hw) 589 { 590 int status = IGC_SUCCESS; 591 int (*read_op_ptr)(struct igc_hw *, uint16_t, uint16_t, uint16_t *); 592 593 DEBUGFUNC("igc_validate_nvm_checksum_i225"); 594 595 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) { 596 /* Replace the read function with semaphore grabbing with 597 * the one that skips this for a while. 598 * We have semaphore taken already here. 599 */ 600 read_op_ptr = hw->nvm.ops.read; 601 hw->nvm.ops.read = igc_read_nvm_eerd; 602 603 status = igc_validate_nvm_checksum_generic(hw); 604 605 /* Revert original read operation. */ 606 hw->nvm.ops.read = read_op_ptr; 607 608 hw->nvm.ops.release(hw); 609 } else { 610 status = IGC_ERR_SWFW_SYNC; 611 } 612 613 return status; 614 } 615 616 /* igc_update_nvm_checksum_i225 - Update EEPROM checksum 617 * @hw: pointer to the HW structure 618 * 619 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 620 * up to the checksum. Then calculates the EEPROM checksum and writes the 621 * value to the EEPROM. Next commit EEPROM data onto the Flash. 622 */ 623 int 624 igc_update_nvm_checksum_i225(struct igc_hw *hw) 625 { 626 uint16_t checksum = 0; 627 uint16_t i, nvm_data; 628 int ret_val; 629 630 DEBUGFUNC("igc_update_nvm_checksum_i225"); 631 632 /* Read the first word from the EEPROM. If this times out or fails, do 633 * not continue or we could be in for a very long wait while every 634 * EEPROM read fails 635 */ 636 ret_val = igc_read_nvm_eerd(hw, 0, 1, &nvm_data); 637 if (ret_val != IGC_SUCCESS) { 638 DEBUGOUT("EEPROM read failed\n"); 639 goto out; 640 } 641 642 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) { 643 /* Do not use hw->nvm.ops.write, hw->nvm.ops.read 644 * because we do not want to take the synchronization 645 * semaphores twice here. 646 */ 647 648 for (i = 0; i < NVM_CHECKSUM_REG; i++) { 649 ret_val = igc_read_nvm_eerd(hw, i, 1, &nvm_data); 650 if (ret_val) { 651 hw->nvm.ops.release(hw); 652 DEBUGOUT("NVM Read Error while updating\n"); 653 DEBUGOUT("checksum.\n"); 654 goto out; 655 } 656 checksum += nvm_data; 657 } 658 checksum = (uint16_t)NVM_SUM - checksum; 659 ret_val = __igc_write_nvm_srwr(hw, NVM_CHECKSUM_REG, 1, 660 &checksum); 661 if (ret_val != IGC_SUCCESS) { 662 hw->nvm.ops.release(hw); 663 DEBUGOUT("NVM Write Error while updating checksum.\n"); 664 goto out; 665 } 666 667 hw->nvm.ops.release(hw); 668 669 ret_val = igc_update_flash_i225(hw); 670 } else { 671 ret_val = IGC_ERR_SWFW_SYNC; 672 } 673 out: 674 return ret_val; 675 } 676 677 /* igc_get_flash_presence_i225 - Check if flash device is detected. 678 * @hw: pointer to the HW structure 679 */ 680 bool 681 igc_get_flash_presence_i225(struct igc_hw *hw) 682 { 683 uint32_t eec = 0; 684 bool ret_val = false; 685 686 DEBUGFUNC("igc_get_flash_presence_i225"); 687 688 eec = IGC_READ_REG(hw, IGC_EECD); 689 690 if (eec & IGC_EECD_FLASH_DETECTED_I225) 691 ret_val = true; 692 693 return ret_val; 694 } 695 696 /* igc_set_flsw_flash_burst_counter_i225 - sets FLSW NVM Burst 697 * Counter in FLSWCNT register. 698 * 699 * @hw: pointer to the HW structure 700 * @burst_counter: size in bytes of the Flash burst to read or write 701 */ 702 int 703 igc_set_flsw_flash_burst_counter_i225(struct igc_hw *hw, uint32_t burst_counter) 704 { 705 int ret_val = IGC_SUCCESS; 706 707 DEBUGFUNC("igc_set_flsw_flash_burst_counter_i225"); 708 709 /* Validate input data */ 710 if (burst_counter < IGC_I225_SHADOW_RAM_SIZE) { 711 /* Write FLSWCNT - burst counter */ 712 IGC_WRITE_REG(hw, IGC_I225_FLSWCNT, burst_counter); 713 } else { 714 ret_val = IGC_ERR_INVALID_ARGUMENT; 715 } 716 717 return ret_val; 718 } 719 720 721 /* igc_write_erase_flash_command_i225 - write/erase to a sector 722 * region on a given address. 723 * 724 * @hw: pointer to the HW structure 725 * @opcode: opcode to be used for the write command 726 * @address: the offset to write into the FLASH image 727 */ 728 int 729 igc_write_erase_flash_command_i225(struct igc_hw *hw, uint32_t opcode, 730 uint32_t address) 731 { 732 uint32_t flswctl = 0; 733 int timeout = IGC_NVM_GRANT_ATTEMPTS; 734 int ret_val = IGC_SUCCESS; 735 736 DEBUGFUNC("igc_write_erase_flash_command_i225"); 737 738 flswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL); 739 /* Polling done bit on FLSWCTL register */ 740 while (timeout) { 741 if (flswctl & IGC_FLSWCTL_DONE) 742 break; 743 DELAY(5); 744 flswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL); 745 timeout--; 746 } 747 748 if (!timeout) { 749 DEBUGOUT("Flash transaction was not done\n"); 750 return -IGC_ERR_NVM; 751 } 752 753 /* Build and issue command on FLSWCTL register */ 754 flswctl = address | opcode; 755 IGC_WRITE_REG(hw, IGC_I225_FLSWCTL, flswctl); 756 757 /* Check if issued command is valid on FLSWCTL register */ 758 flswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL); 759 if (!(flswctl & IGC_FLSWCTL_CMDV)) { 760 DEBUGOUT("Write flash command failed\n"); 761 ret_val = IGC_ERR_INVALID_ARGUMENT; 762 } 763 764 return ret_val; 765 } 766 767 /* igc_update_flash_i225 - Commit EEPROM to the flash 768 * if fw_valid_bit is set, FW is active. setting FLUPD bit in EEC 769 * register makes the FW load the internal shadow RAM into the flash. 770 * Otherwise, fw_valid_bit is 0. if FL_SECU.block_prtotected_sw = 0 771 * then FW is not active so the SW is responsible shadow RAM dump. 772 * 773 * @hw: pointer to the HW structure 774 */ 775 int 776 igc_update_flash_i225(struct igc_hw *hw) 777 { 778 uint32_t block_sw_protect = 1; 779 uint32_t i, flup, fw_valid_bit; 780 uint16_t current_offset; 781 uint16_t base_address = 0x0; 782 uint16_t current_offset_data = 0; 783 int ret_val = 0; 784 785 DEBUGFUNC("igc_update_flash_i225"); 786 787 block_sw_protect = IGC_READ_REG(hw, IGC_I225_FLSECU) & 788 IGC_FLSECU_BLK_SW_ACCESS_I225; 789 790 fw_valid_bit = IGC_READ_REG(hw, IGC_FWSM) & IGC_FWSM_FW_VALID_I225; 791 if (fw_valid_bit) { 792 ret_val = igc_pool_flash_update_done_i225(hw); 793 if (ret_val == -IGC_ERR_NVM) { 794 DEBUGOUT("Flash update time out\n"); 795 goto out; 796 } 797 798 flup = IGC_READ_REG(hw, IGC_EECD) | IGC_EECD_FLUPD_I225; 799 IGC_WRITE_REG(hw, IGC_EECD, flup); 800 801 ret_val = igc_pool_flash_update_done_i225(hw); 802 if (ret_val == IGC_SUCCESS) 803 DEBUGOUT("Flash update complete\n"); 804 else 805 DEBUGOUT("Flash update time out\n"); 806 } else if (!block_sw_protect) { 807 /* FW is not active and security protection is disabled. 808 * therefore, SW is in charge of shadow RAM dump. 809 * Check which sector is valid. if sector 0 is valid, 810 * base address remains 0x0. otherwise, sector 1 is 811 * valid and its base address is 0x1000 812 */ 813 if (IGC_READ_REG(hw, IGC_EECD) & IGC_EECD_SEC1VAL_I225) 814 base_address = 0x1000; 815 816 /* Valid sector erase */ 817 ret_val = igc_write_erase_flash_command_i225(hw, 818 IGC_I225_ERASE_CMD_OPCODE, base_address); 819 if (!ret_val) { 820 DEBUGOUT("Sector erase failed\n"); 821 goto out; 822 } 823 824 current_offset = base_address; 825 826 /* Write */ 827 for (i = 0; i < IGC_I225_SHADOW_RAM_SIZE / 2; i++) { 828 /* Set burst write length */ 829 ret_val = igc_set_flsw_flash_burst_counter_i225(hw, 830 0x2); 831 if (ret_val != IGC_SUCCESS) 832 break; 833 834 /* Set address and opcode */ 835 ret_val = igc_write_erase_flash_command_i225(hw, 836 IGC_I225_WRITE_CMD_OPCODE, 2 * current_offset); 837 if (ret_val != IGC_SUCCESS) 838 break; 839 840 ret_val = igc_read_nvm_eerd(hw, current_offset, 1, 841 ¤t_offset_data); 842 if (ret_val) { 843 DEBUGOUT("Failed to read from EEPROM\n"); 844 goto out; 845 } 846 847 /* Write CurrentOffseData to FLSWDATA register */ 848 IGC_WRITE_REG(hw, IGC_I225_FLSWDATA, 849 current_offset_data); 850 current_offset++; 851 852 /* Wait till operation has finished */ 853 ret_val = igc_poll_eerd_eewr_done(hw, 854 IGC_NVM_POLL_READ); 855 if (ret_val) 856 break; 857 858 DELAY(1000); 859 } 860 } 861 out: 862 return ret_val; 863 } 864 865 /* igc_pool_flash_update_done_i225 - Pool FLUDONE status. 866 * @hw: pointer to the HW structure 867 */ 868 int 869 igc_pool_flash_update_done_i225(struct igc_hw *hw) 870 { 871 uint32_t i, reg; 872 int ret_val = -IGC_ERR_NVM; 873 874 DEBUGFUNC("igc_pool_flash_update_done_i225"); 875 876 for (i = 0; i < IGC_FLUDONE_ATTEMPTS; i++) { 877 reg = IGC_READ_REG(hw, IGC_EECD); 878 if (reg & IGC_EECD_FLUDONE_I225) { 879 ret_val = IGC_SUCCESS; 880 break; 881 } 882 DELAY(5); 883 } 884 885 return ret_val; 886 } 887 888 /* igc_set_ltr_i225 - Set Latency Tolerance Reporting thresholds. 889 * @hw: pointer to the HW structure 890 * @link: bool indicating link status 891 * 892 * Set the LTR thresholds based on the link speed (Mbps), EEE, and DMAC 893 * settings, otherwise specify that there is no LTR requirement. 894 */ 895 int 896 igc_set_ltr_i225(struct igc_hw *hw, bool link) 897 { 898 uint16_t speed, duplex; 899 uint32_t tw_system, ltrc, ltrv, ltr_min, ltr_max, scale_min, scale_max; 900 int size; 901 902 DEBUGFUNC("igc_set_ltr_i225"); 903 904 /* If we do not have link, LTR thresholds are zero. */ 905 if (link) { 906 hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 907 908 /* Check if using copper interface with EEE enabled or if the 909 * link speed is 10 Mbps. 910 */ 911 if ((hw->phy.media_type == igc_media_type_copper) && 912 !(hw->dev_spec._i225.eee_disable) && 913 (speed != SPEED_10)) { 914 /* EEE enabled, so send LTRMAX threshold. */ 915 ltrc = IGC_READ_REG(hw, IGC_LTRC) | IGC_LTRC_EEEMS_EN; 916 IGC_WRITE_REG(hw, IGC_LTRC, ltrc); 917 918 /* Calculate tw_system (nsec). */ 919 if (speed == SPEED_100) { 920 tw_system = ((IGC_READ_REG(hw, IGC_EEE_SU) & 921 IGC_TW_SYSTEM_100_MASK) >> 922 IGC_TW_SYSTEM_100_SHIFT) * 500; 923 } else { 924 tw_system = (IGC_READ_REG(hw, IGC_EEE_SU) & 925 IGC_TW_SYSTEM_1000_MASK) * 500; 926 } 927 } else { 928 tw_system = 0; 929 } 930 931 /* Get the Rx packet buffer size. */ 932 size = IGC_READ_REG(hw, IGC_RXPBS) & IGC_RXPBS_SIZE_I225_MASK; 933 934 /* Calculations vary based on DMAC settings. */ 935 if (IGC_READ_REG(hw, IGC_DMACR) & IGC_DMACR_DMAC_EN) { 936 size -= (IGC_READ_REG(hw, IGC_DMACR) & 937 IGC_DMACR_DMACTHR_MASK) >> IGC_DMACR_DMACTHR_SHIFT; 938 /* Convert size to bits. */ 939 size *= 1024 * 8; 940 } else { 941 /* Convert size to bytes, subtract the MTU, and then 942 * convert the size to bits. 943 */ 944 size *= 1024; 945 size -= hw->dev_spec._i225.mtu; 946 size *= 8; 947 } 948 949 if (size < 0) { 950 DEBUGOUT1("Invalid effective Rx buffer size %d\n", 951 size); 952 return -IGC_ERR_CONFIG; 953 } 954 955 /* Calculate the thresholds. Since speed is in Mbps, simplify 956 * the calculation by multiplying size/speed by 1000 for result 957 * to be in nsec before dividing by the scale in nsec. Set the 958 * scale such that the LTR threshold fits in the register. 959 */ 960 ltr_min = (1000 * size) / speed; 961 ltr_max = ltr_min + tw_system; 962 scale_min = (ltr_min / 1024) < 1024 ? IGC_LTRMINV_SCALE_1024 : 963 IGC_LTRMINV_SCALE_32768; 964 scale_max = (ltr_max / 1024) < 1024 ? IGC_LTRMAXV_SCALE_1024 : 965 IGC_LTRMAXV_SCALE_32768; 966 ltr_min /= scale_min == IGC_LTRMINV_SCALE_1024 ? 1024 : 32768; 967 ltr_max /= scale_max == IGC_LTRMAXV_SCALE_1024 ? 1024 : 32768; 968 969 /* Only write the LTR thresholds if they differ from before. */ 970 ltrv = IGC_READ_REG(hw, IGC_LTRMINV); 971 if (ltr_min != (ltrv & IGC_LTRMINV_LTRV_MASK)) { 972 ltrv = IGC_LTRMINV_LSNP_REQ | ltr_min | 973 (scale_min << IGC_LTRMINV_SCALE_SHIFT); 974 IGC_WRITE_REG(hw, IGC_LTRMINV, ltrv); 975 } 976 977 ltrv = IGC_READ_REG(hw, IGC_LTRMAXV); 978 if (ltr_max != (ltrv & IGC_LTRMAXV_LTRV_MASK)) { 979 ltrv = IGC_LTRMAXV_LSNP_REQ | ltr_max | 980 (scale_min << IGC_LTRMAXV_SCALE_SHIFT); 981 IGC_WRITE_REG(hw, IGC_LTRMAXV, ltrv); 982 } 983 } 984 985 return IGC_SUCCESS; 986 } 987 988 /* igc_check_for_link_i225 - Check for link 989 * @hw: pointer to the HW structure 990 * 991 * Checks to see of the link status of the hardware has changed. If a 992 * change in link status has been detected, then we read the PHY registers 993 * to get the current speed/duplex if link exists. 994 */ 995 int 996 igc_check_for_link_i225(struct igc_hw *hw) 997 { 998 struct igc_mac_info *mac = &hw->mac; 999 int ret_val; 1000 bool link = false; 1001 1002 DEBUGFUNC("igc_check_for_link_i225"); 1003 1004 /* We only want to go out to the PHY registers to see if 1005 * Auto-Neg has completed and/or if our link status has 1006 * changed. The get_link_status flag is set upon receiving 1007 * a Link Status Change or Rx Sequence Error interrupt. 1008 */ 1009 if (!mac->get_link_status) { 1010 ret_val = IGC_SUCCESS; 1011 goto out; 1012 } 1013 1014 /* First we want to see if the MII Status Register reports 1015 * link. If so, then we want to get the current speed/duplex 1016 * of the PHY. 1017 */ 1018 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link); 1019 if (ret_val) 1020 goto out; 1021 1022 if (!link) 1023 goto out; /* No link detected */ 1024 1025 /* First we want to see if the MII Status Register reports 1026 * link. If so, then we want to get the current speed/duplex 1027 * of the PHY. 1028 */ 1029 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link); 1030 if (ret_val) 1031 goto out; 1032 1033 if (!link) 1034 goto out; /* No link detected */ 1035 1036 mac->get_link_status = false; 1037 1038 /* Check if there was DownShift, must be checked 1039 * immediately after link-up 1040 */ 1041 igc_check_downshift_generic(hw); 1042 1043 /* If we are forcing speed/duplex, then we simply return since 1044 * we have already determined whether we have link or not. 1045 */ 1046 if (!mac->autoneg) 1047 goto out; 1048 1049 /* Auto-Neg is enabled. Auto Speed Detection takes care 1050 * of MAC speed/duplex configuration. So we only need to 1051 * configure Collision Distance in the MAC. 1052 */ 1053 mac->ops.config_collision_dist(hw); 1054 1055 /* Configure Flow Control now that Auto-Neg has completed. 1056 * First, we need to restore the desired flow control 1057 * settings because we may have had to re-autoneg with a 1058 * different link partner. 1059 */ 1060 ret_val = igc_config_fc_after_link_up_generic(hw); 1061 if (ret_val) 1062 DEBUGOUT("Error configuring flow control\n"); 1063 out: 1064 /* Now that we are aware of our link settings, we can set the LTR 1065 * thresholds. 1066 */ 1067 ret_val = igc_set_ltr_i225(hw, link); 1068 1069 return ret_val; 1070 } 1071 1072 /* igc_init_function_pointers_i225 - Init func ptrs. 1073 * @hw: pointer to the HW structure 1074 * 1075 * Called to initialize all function pointers and parameters. 1076 */ 1077 void 1078 igc_init_function_pointers_i225(struct igc_hw *hw) 1079 { 1080 igc_init_mac_ops_generic(hw); 1081 igc_init_phy_ops_generic(hw); 1082 igc_init_nvm_ops_generic(hw); 1083 hw->mac.ops.init_params = igc_init_mac_params_i225; 1084 hw->nvm.ops.init_params = igc_init_nvm_params_i225; 1085 hw->phy.ops.init_params = igc_init_phy_params_i225; 1086 } 1087 1088 /* igc_init_hw_i225 - Init hw for I225 1089 * @hw: pointer to the HW structure 1090 * 1091 * Called to initialize hw for i225 hw family. 1092 */ 1093 int 1094 igc_init_hw_i225(struct igc_hw *hw) 1095 { 1096 int ret_val; 1097 1098 DEBUGFUNC("igc_init_hw_i225"); 1099 1100 ret_val = igc_init_hw_base(hw); 1101 return ret_val; 1102 } 1103 1104 /** 1105 * igc_set_eee_i225 - Enable/disable EEE support 1106 * @hw: pointer to the HW structure 1107 * @adv2p5G: boolean flag enabling 2.5G EEE advertisement 1108 * @adv1G: boolean flag enabling 1G EEE advertisement 1109 * @adv100M: boolean flag enabling 100M EEE advertisement 1110 * 1111 * Enable/disable EEE based on setting in dev_spec structure. 1112 * 1113 **/ 1114 int 1115 igc_set_eee_i225(struct igc_hw *hw, bool adv2p5G, bool adv1G, 1116 bool adv100M) 1117 { 1118 uint32_t ipcnfg, eeer; 1119 1120 DEBUGFUNC("igc_set_eee_i225"); 1121 1122 if (hw->mac.type != igc_i225 || 1123 hw->phy.media_type != igc_media_type_copper) 1124 goto out; 1125 ipcnfg = IGC_READ_REG(hw, IGC_IPCNFG); 1126 eeer = IGC_READ_REG(hw, IGC_EEER); 1127 1128 /* enable or disable per user setting */ 1129 if (!(hw->dev_spec._i225.eee_disable)) { 1130 uint32_t eee_su = IGC_READ_REG(hw, IGC_EEE_SU); 1131 1132 if (adv100M) 1133 ipcnfg |= IGC_IPCNFG_EEE_100M_AN; 1134 else 1135 ipcnfg &= ~IGC_IPCNFG_EEE_100M_AN; 1136 1137 if (adv1G) 1138 ipcnfg |= IGC_IPCNFG_EEE_1G_AN; 1139 else 1140 ipcnfg &= ~IGC_IPCNFG_EEE_1G_AN; 1141 1142 if (adv2p5G) 1143 ipcnfg |= IGC_IPCNFG_EEE_2_5G_AN; 1144 else 1145 ipcnfg &= ~IGC_IPCNFG_EEE_2_5G_AN; 1146 1147 eeer |= (IGC_EEER_TX_LPI_EN | IGC_EEER_RX_LPI_EN | 1148 IGC_EEER_LPI_FC); 1149 1150 /* This bit should not be set in normal operation. */ 1151 if (eee_su & IGC_EEE_SU_LPI_CLK_STP) 1152 DEBUGOUT("LPI Clock Stop Bit should not be set!\n"); 1153 } else { 1154 ipcnfg &= ~(IGC_IPCNFG_EEE_2_5G_AN | IGC_IPCNFG_EEE_1G_AN | 1155 IGC_IPCNFG_EEE_100M_AN); 1156 eeer &= ~(IGC_EEER_TX_LPI_EN | IGC_EEER_RX_LPI_EN | 1157 IGC_EEER_LPI_FC); 1158 } 1159 IGC_WRITE_REG(hw, IGC_IPCNFG, ipcnfg); 1160 IGC_WRITE_REG(hw, IGC_EEER, eeer); 1161 IGC_READ_REG(hw, IGC_IPCNFG); 1162 IGC_READ_REG(hw, IGC_EEER); 1163 out: 1164 1165 return IGC_SUCCESS; 1166 } 1167