1 /* $NetBSD: if_igc.h,v 1.2 2023/10/04 07:35:27 rin Exp $ */ 2 /* $OpenBSD: if_igc.h,v 1.2 2022/01/09 05:42:50 jsg Exp $ */ 3 /*- 4 * SPDX-License-Identifier: BSD-2-Clause 5 * 6 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 7 * All rights reserved. 8 * Copyright (c) 2021 Rubicon Communications, LLC (Netgate) 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD$ 32 */ 33 34 #ifndef _IGC_H_ 35 #define _IGC_H_ 36 37 #ifdef _KERNEL_OPT 38 #include "opt_if_igc.h" 39 #endif 40 41 #include <sys/types.h> 42 #include <sys/pcq.h> 43 #include <sys/workqueue.h> 44 45 #include <dev/pci/igc/igc_api.h> 46 #include <dev/pci/igc/igc_i225.h> 47 48 #ifdef __HAVE_ATOMIC64_OPS 49 #define IGC_EVENT_COUNTERS 50 #endif 51 52 /* 53 * IGC_MAX_TXD: Maximum number of Transmit Descriptors 54 * Valid Range: 128-4096 55 * Default Value: 1024 56 * This value is the number of transmit descriptors allocated by the driver. 57 * Increasing this value allows the driver to queue more transmits. Each 58 * descriptor is 16 bytes. 59 * Since TDLEN should be multiple of 128bytes, the number of transmit 60 * descriptors should meet the following condition. 61 * (num_tx_desc * sizeof(struct igc_tx_desc)) % 128 == 0 62 */ 63 #define IGC_MIN_TXD 128 64 #define IGC_MAX_TXD 4096 65 #define IGC_DEFAULT_TXD 1024 66 #define IGC_DEFAULT_MULTI_TXD 4096 67 #define IGC_MAX_TXD 4096 68 69 /* 70 * IGC_MAX_RXD - Maximum number of receive Descriptors 71 * Valid Range: 128-4096 72 * Default Value: 1024 73 * This value is the number of receive descriptors allocated by the driver. 74 * Increasing this value allows the driver to buffer more incoming packets. 75 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 76 * descriptor. The maximum MTU size is 16110. 77 * Since TDLEN should be multiple of 128bytes, the number of transmit 78 * descriptors should meet the following condition. 79 * (num_tx_desc * sizeof(struct igc_tx_desc)) % 128 == 0 80 */ 81 #define IGC_MIN_RXD 128 82 #define IGC_MAX_RXD 4096 83 #define IGC_DEFAULT_RXD 1024 84 #define IGC_DEFAULT_MULTI_RXD 4096 85 #define IGC_MAX_RXD 4096 86 87 /* 88 * IGC_TIDV_VAL - Transmit Interrupt Delay Value 89 * Valid Range: 0-65535 (0=off) 90 * Default Value: 64 91 * This value delays the generation of transmit interrupts in units of 92 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 93 * efficiency if properly tuned for specific network traffic. If the 94 * system is reporting dropped transmits, this value may be set too high 95 * causing the driver to run out of available transmit descriptors. 96 */ 97 #define IGC_TIDV_VAL 64 98 99 /* 100 * IGC_TADV_VAL - Transmit Absolute Interrupt Delay Value 101 * Valid Range: 0-65535 (0=off) 102 * Default Value: 64 103 * This value, in units of 1.024 microseconds, limits the delay in which a 104 * transmit interrupt is generated. Useful only if IGC_TIDV is non-zero, 105 * this value ensures that an interrupt is generated after the initial 106 * packet is sent on the wire within the set amount of time. Proper tuning, 107 * along with IGC_TIDV_VAL, may improve traffic throughput in specific 108 * network conditions. 109 */ 110 #define IGC_TADV_VAL 64 111 112 /* 113 * IGC_RDTR_VAL - Receive Interrupt Delay Timer (Packet Timer) 114 * Valid Range: 0-65535 (0=off) 115 * Default Value: 0 116 * This value delays the generation of receive interrupts in units of 1.024 117 * microseconds. Receive interrupt reduction can improve CPU efficiency if 118 * properly tuned for specific network traffic. Increasing this value adds 119 * extra latency to frame reception and can end up decreasing the throughput 120 * of TCP traffic. If the system is reporting dropped receives, this value 121 * may be set too high, causing the driver to run out of available receive 122 * descriptors. 123 * 124 * CAUTION: When setting IGC_RDTR to a value other than 0, adapters 125 * may hang (stop transmitting) under certain network conditions. 126 * If this occurs a WATCHDOG message is logged in the system 127 * event log. In addition, the controller is automatically reset, 128 * restoring the network connection. To eliminate the potential 129 * for the hang ensure that IGC_RDTR is set to 0. 130 */ 131 #define IGC_RDTR_VAL 0 132 133 /* 134 * Receive Interrupt Absolute Delay Timer 135 * Valid Range: 0-65535 (0=off) 136 * Default Value: 64 137 * This value, in units of 1.024 microseconds, limits the delay in which a 138 * receive interrupt is generated. Useful only if IGC_RDTR is non-zero, 139 * this value ensures that an interrupt is generated after the initial 140 * packet is received within the set amount of time. Proper tuning, 141 * along with IGC_RDTR, may improve traffic throughput in specific network 142 * conditions. 143 */ 144 #define IGC_RADV_VAL 64 145 146 /* 147 * This parameter controls whether or not autonegotiation is enabled. 148 * 0 - Disable autonegotiation 149 * 1 - Enable autonegotiation 150 */ 151 #define DO_AUTO_NEG true 152 153 #define AUTONEG_ADV_DEFAULT \ 154 (ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ 155 ADVERTISE_100_FULL | ADVERTISE_1000_FULL | ADVERTISE_2500_FULL) 156 157 #define AUTO_ALL_MODES 0 158 159 /* 160 * Miscellaneous constants 161 */ 162 #define MAX_NUM_MULTICAST_ADDRESSES 128 163 #define IGC_FC_PAUSE_TIME 0x0680 164 165 #define IGC_TXPBSIZE 20408 166 #define IGC_PKTTYPE_MASK 0x0000FFF0 167 #define IGC_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coalesce Flush */ 168 169 #define IGC_RX_PTHRESH 8 170 #define IGC_RX_HTHRESH 8 171 #define IGC_RX_WTHRESH 4 172 173 #define IGC_TX_PTHRESH 8 174 #define IGC_TX_HTHRESH 1 175 176 /* 177 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 178 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 179 * also optimize cache line size effect. H/W supports up to cache line size 128. 180 */ 181 #define IGC_DBA_ALIGN 128 182 183 /* 184 * This parameter controls the duration of transmit watchdog timer. 185 */ 186 #define IGC_TX_TIMEOUT 5 /* set to 5 seconds */ 187 188 #define IGC_PCIREG PCI_MAPREG_START 189 190 #define IGC_MAX_VECTORS 8 191 192 /* Enable/disable debugging statements in shared code */ 193 #define DBG 0 194 195 #define DEBUGOUT(...) \ 196 do { if (DBG) printf(__VA_ARGS__); } while (0) 197 #define DEBUGOUT1(...) DEBUGOUT(__VA_ARGS__) 198 #define DEBUGOUT2(...) DEBUGOUT(__VA_ARGS__) 199 #define DEBUGOUT3(...) DEBUGOUT(__VA_ARGS__) 200 #define DEBUGOUT7(...) DEBUGOUT(__VA_ARGS__) 201 #define DEBUGFUNC(F) DEBUGOUT(F "\n") 202 203 /* Compatibility glue. */ 204 #define msec_delay(x) DELAY(1000 * (x)) 205 206 #define IGC_MAX_SCATTER 40 207 #define IGC_TSO_SIZE 65535 208 209 #define MAX_INTS_PER_SEC 8000 210 #define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256)) 211 212 #define IGC_MAX_INTRS (IGC_MAX_NQUEUES + 1) 213 214 /* Forward declaration. */ 215 struct igc_hw; 216 217 struct igc_osdep { 218 bus_dma_tag_t os_dmat; 219 bus_space_tag_t os_memt; 220 bus_space_handle_t os_memh; 221 222 bus_size_t os_memsize; 223 bus_addr_t os_membase; 224 225 void *os_sc; 226 struct pci_attach_args os_pa; 227 }; 228 229 230 struct igc_tx_buf { 231 uint32_t eop_index; 232 struct mbuf *m_head; 233 bus_dmamap_t map; 234 }; 235 236 struct igc_rx_buf { 237 struct mbuf *buf; 238 struct mbuf *fmp; /* First mbuf pointers. */ 239 bus_dmamap_t map; 240 }; 241 242 /* 243 * Bus dma allocation structure used by igc_dma_malloc and igc_dma_free. 244 */ 245 struct igc_dma_alloc { 246 void *dma_vaddr; 247 bus_dma_tag_t dma_tag; 248 bus_dmamap_t dma_map; 249 bus_dma_segment_t dma_seg; 250 bus_size_t dma_size; 251 int dma_nseg; 252 }; 253 254 /* 255 * Driver queue struct: this is the interrupt container 256 * for the associated tx and rx ring. 257 */ 258 struct igc_queue { 259 struct igc_softc *sc; 260 uint32_t msix; 261 uint32_t eims; 262 uint32_t eitr_setting; 263 pci_intr_handle_t ih; 264 void *tag; 265 struct tx_ring *txr; 266 struct rx_ring *rxr; 267 268 void *igcq_si; 269 bool igcq_workqueue; 270 struct work igcq_wq_cookie; 271 272 #ifdef IGC_EVENT_COUNTERS 273 uint64_t *igcq_driver_counters; 274 275 struct evcnt *igcq_queue_evcnts; 276 char igcq_queue_evname[EVCNT_STRING_MAX]; 277 #endif 278 }; 279 280 /* 281 * The transmit ring, one per tx queue. 282 */ 283 struct tx_ring { 284 struct igc_softc *sc; 285 struct ifqueue *ifq; 286 uint32_t me; 287 uint32_t watchdog_timer; 288 union igc_adv_tx_desc *tx_base; 289 struct igc_tx_buf *tx_buffers; 290 struct igc_dma_alloc txdma; 291 uint32_t next_avail_desc; 292 uint32_t next_to_clean; 293 bus_dma_tag_t txtag; 294 295 pcq_t *txr_interq; 296 297 kmutex_t txr_lock; 298 299 struct igc_queue *txr_igcq; 300 }; 301 302 /* 303 * The Receive ring, one per rx queue. 304 */ 305 struct rx_ring { 306 struct igc_softc *sc; 307 uint32_t me; 308 union igc_adv_rx_desc *rx_base; 309 struct igc_rx_buf *rx_buffers; 310 struct igc_dma_alloc rxdma; 311 uint32_t last_desc_filled; 312 uint32_t next_to_check; 313 #if IF_RXR 314 struct if_rxring rx_ring; 315 #endif 316 317 kmutex_t rxr_lock; 318 319 struct igc_queue *rxr_igcq; 320 }; 321 322 /* Our adapter structure. */ 323 struct igc_softc { 324 device_t sc_dev; 325 struct ethercom sc_ec; 326 struct ifmedia media; 327 #if 1 328 pci_intr_type_t sc_intr_type; 329 int sc_nintrs; 330 pci_intr_handle_t *sc_intrs; 331 void *sc_ihs[IGC_MAX_INTRS]; 332 #else 333 struct intrmap *sc_intrmap; 334 #endif 335 336 struct igc_osdep osdep; 337 struct igc_hw hw; 338 339 uint16_t sc_if_flags; 340 uint16_t fc; 341 uint16_t link_active; 342 uint16_t link_speed; 343 uint16_t link_duplex; 344 uint32_t dmac; 345 346 int num_tx_desc; 347 int num_rx_desc; 348 349 uint32_t max_frame_size; 350 uint32_t rx_mbuf_sz; 351 uint32_t linkvec; 352 uint32_t msix_linkmask; 353 uint32_t msix_queuesmask; 354 355 struct if_percpuq *sc_ipq; 356 unsigned int sc_nqueues; 357 struct igc_queue *queues; 358 bool sc_txrx_workqueue; 359 struct workqueue *sc_queue_wq; 360 361 u_int sc_rx_intr_process_limit; 362 u_int sc_tx_intr_process_limit; 363 u_int sc_rx_process_limit; 364 u_int sc_tx_process_limit; 365 366 struct tx_ring *tx_rings; 367 struct rx_ring *rx_rings; 368 369 /* Multicast array memory */ 370 #define IGC_MTA_LEN (ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES) 371 uint8_t *mta; 372 373 kmutex_t sc_core_lock; 374 375 callout_t sc_tick_ch; 376 bool sc_core_stopping; 377 378 #ifdef IGC_EVENT_COUNTERS 379 struct evcnt *sc_global_evcnts; 380 381 struct evcnt *sc_driver_evcnts; 382 383 struct evcnt *sc_mac_evcnts; 384 char sc_mac_evname[EVCNT_STRING_MAX]; 385 #endif 386 }; 387 388 #define DEVNAME(_sc) ((_sc)->sc_dev.dv_xname) 389 390 /* Register READ/WRITE macros */ 391 #define IGC_WRITE_FLUSH(a) IGC_READ_REG(a, IGC_STATUS) 392 #define IGC_READ_REG(a, reg) \ 393 bus_space_read_4(((struct igc_osdep *)(a)->back)->os_memt, \ 394 ((struct igc_osdep *)(a)->back)->os_memh, reg) 395 #define IGC_WRITE_REG(a, reg, value) \ 396 bus_space_write_4(((struct igc_osdep *)(a)->back)->os_memt, \ 397 ((struct igc_osdep *)(a)->back)->os_memh, reg, value) 398 #define IGC_READ_REG_ARRAY(a, reg, off) \ 399 bus_space_read_4(((struct igc_osdep *)(a)->back)->os_memt, \ 400 ((struct igc_osdep *)(a)->back)->os_memh, (reg + ((off) << 2))) 401 #define IGC_WRITE_REG_ARRAY(a, reg, off, value) \ 402 bus_space_write_4(((struct igc_osdep *)(a)->back)->os_memt, \ 403 ((struct igc_osdep *)(a)->back)->os_memh, \ 404 (reg + ((off) << 2)),value) 405 406 #endif /* _IGC_H_ */ 407