1 /* $NetBSD: if_wpireg.h,v 1.7 2007/10/21 16:47:27 degroote Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #define WPI_TX_RING_COUNT 256 21 #define WPI_CMD_RING_COUNT 256 22 #define WPI_RX_RING_COUNT 64 23 24 #define WPI_BUF_ALIGN 4096 25 26 /* 27 * Rings must be aligned on a four 4K-pages boundary. 28 * I had a hard time figuring this out. 29 */ 30 #define WPI_RING_DMA_ALIGN 0x4000 31 32 /* maximum scatter/gather */ 33 #define WPI_MAX_SCATTER 4 34 35 /* maximum Rx buffer size (larger than MCLBYTES) */ 36 #define WPI_RBUF_SIZE (3 * 1024) /* XXX 3000 but must be aligned! */ 37 38 /* 39 * Control and status registers. 40 */ 41 #define WPI_HWCONFIG 0x000 42 #define WPI_INTR 0x008 43 #define WPI_MASK 0x00c 44 #define WPI_INTR_STATUS 0x010 45 #define WPI_GPIO_STATUS 0x018 46 #define WPI_RESET 0x020 47 #define WPI_GPIO_CTL 0x024 48 #define WPI_EEPROM_CTL 0x02c 49 #define WPI_EEPROM_STATUS 0x030 50 #define WPI_UCODE_CLR 0x05c 51 #define WPI_TEMPERATURE 0x060 52 #define WPI_CHICKEN 0x100 53 #define WPI_PLL_CTL 0x20c 54 #define WPI_WRITE_MEM_ADDR 0x444 55 #define WPI_READ_MEM_ADDR 0x448 56 #define WPI_WRITE_MEM_DATA 0x44c 57 #define WPI_READ_MEM_DATA 0x450 58 #define WPI_TX_WIDX 0x460 59 #define WPI_TX_CTL(qid) (0x940 + (qid) * 8) 60 #define WPI_TX_BASE(qid) (0x944 + (qid) * 8) 61 #define WPI_TX_DESC(qid) (0x980 + (qid) * 80) 62 #define WPI_RX_CONFIG 0xc00 63 #define WPI_RX_BASE 0xc04 64 #define WPI_RX_WIDX 0xc20 65 #define WPI_RX_RIDX_PTR 0xc24 66 #define WPI_RX_CTL 0xcc0 67 #define WPI_RX_STATUS 0xcc4 68 #define WPI_TX_CONFIG(qid) (0xd00 + (qid) * 32) 69 #define WPI_TX_CREDIT(qid) (0xd04 + (qid) * 32) 70 #define WPI_TX_STATE(qid) (0xd08 + (qid) * 32) 71 #define WPI_TX_BASE_PTR 0xe80 72 #define WPI_MSG_CONFIG 0xe88 73 #define WPI_TX_STATUS 0xe90 74 75 76 /* 77 * NIC internal memory offsets. 78 */ 79 #define WPI_MEM_MODE 0x2e00 80 #define WPI_MEM_RA 0x2e04 81 #define WPI_MEM_TXCFG 0x2e10 82 #define WPI_MEM_MAGIC4 0x2e14 83 #define WPI_MEM_MAGIC5 0x2e20 84 #define WPI_MEM_BYPASS1 0x2e2c 85 #define WPI_MEM_BYPASS2 0x2e30 86 #define WPI_MEM_CLOCK1 0x3004 87 #define WPI_MEM_CLOCK2 0x3008 88 #define WPI_MEM_POWER 0x300c 89 #define WPI_MEM_PCIDEV 0x3010 90 #define WPI_MEM_UCODE_CTL 0x3400 91 #define WPI_MEM_UCODE_SRC 0x3404 92 #define WPI_MEM_UCODE_DST 0x3408 93 #define WPI_MEM_UCODE_SIZE 0x340c 94 #define WPI_MEM_UCODE_BASE 0x3800 95 96 97 #define WPI_MEM_TEXT_BASE 0x3490 98 #define WPI_MEM_TEXT_SIZE 0x3494 99 #define WPI_MEM_DATA_BASE 0x3498 100 #define WPI_MEM_DATA_SIZE 0x349c 101 102 /* possible flags for register WPI_HWCONFIG */ 103 #define WPI_HW_ALM_MB (1 << 8) 104 #define WPI_HW_ALM_MM (1 << 9) 105 #define WPI_HW_SKU_MRC (1 << 10) 106 #define WPI_HW_REV_D (1 << 11) 107 #define WPI_HW_TYPE_B (1 << 12) 108 109 /* possible flags for registers WPI_READ_MEM_ADDR/WPI_WRITE_MEM_ADDR */ 110 #define WPI_MEM_4 ((sizeof (uint32_t) - 1) << 24) 111 112 /* possible values for WPI_MEM_UCODE_DST */ 113 #define WPI_FW_TEXT 0x00000000 114 115 /* possible flags for WPI_GPIO_STATUS */ 116 #define WPI_POWERED (1 << 9) 117 118 /* possible flags for register WPI_RESET */ 119 #define WPI_NEVO_RESET (1 << 0) 120 #define WPI_SW_RESET (1 << 7) 121 #define WPI_MASTER_DISABLED (1 << 8) 122 #define WPI_STOP_MASTER (1 << 9) 123 124 /* possible flags for register WPI_GPIO_CTL */ 125 #define WPI_GPIO_CLOCK (1 << 0) 126 #define WPI_GPIO_INIT (1 << 2) 127 #define WPI_GPIO_MAC (1 << 3) 128 #define WPI_GPIO_SLEEP (1 << 4) 129 #define WPI_GPIO_PWR_STATUS 0x07000000 130 #define WPI_GPIO_PWR_SLEEP (4 << 24) 131 132 /* possible flags for register WPI_CHICKEN */ 133 #define WPI_CHICKEN_RXNOLOS (1 << 23) 134 135 /* possible flags for register WPI_PLL_CTL */ 136 #define WPI_PLL_INIT (1 << 24) 137 138 /* possible flags for register WPI_UCODE_CLR */ 139 #define WPI_RADIO_OFF (1 << 1) 140 #define WPI_DISABLE_CMD (1 << 2) 141 142 /* possible flags for WPI_RX_STATUS */ 143 #define WPI_RX_IDLE (1 << 24) 144 145 /* possible flags for register WPI_UC_CTL */ 146 #define WPI_UC_ENABLE (1 << 30) 147 #define WPI_UC_RUN (1 << 31) 148 149 /* possible flags for register WPI_INTR_CSR */ 150 #define WPI_ALIVE_INTR (1 << 0) 151 #define WPI_WAKEUP_INTR (1 << 1) 152 #define WPI_SW_ERROR (1 << 25) 153 #define WPI_TX_INTR (1 << 27) 154 #define WPI_HW_ERROR (1 << 29) 155 #define WPI_RX_INTR (1 << 31) 156 157 #define WPI_INTR_MASK \ 158 (WPI_SW_ERROR | WPI_HW_ERROR | WPI_TX_INTR | WPI_RX_INTR | \ 159 WPI_ALIVE_INTR | WPI_WAKEUP_INTR) 160 161 /* possible flags for register WPI_TX_STATUS */ 162 #define WPI_TX_IDLE(qid) (1 << ((qid) + 24) | 1 << ((qid) + 16)) 163 164 /* possible flags for register WPI_EEPROM_CTL */ 165 #define WPI_EEPROM_READY (1 << 0) 166 167 /* possible flags for register WPI_EEPROM_STATUS */ 168 #define WPI_EEPROM_VERSION 0x00000007 169 #define WPI_EEPROM_LOCKED 0x00000180 170 171 172 struct wpi_shared { 173 uint32_t txbase[8]; 174 uint32_t next; 175 uint32_t reserved[2]; 176 } __attribute__((__packed__)); 177 178 #define WPI_MAX_SEG_LEN 65520 179 struct wpi_tx_desc { 180 uint32_t flags; 181 #define WPI_PAD32(x) ((((x) + 3) & ~3) - (x)) 182 183 struct { 184 uint32_t addr; 185 uint32_t len; 186 } __attribute__((__packed__)) segs[WPI_MAX_SCATTER]; 187 uint8_t reserved[28]; 188 } __attribute__((__packed__)); 189 190 struct wpi_tx_stat { 191 uint8_t nrts; 192 uint8_t ntries; 193 uint8_t nkill; 194 uint8_t rate; 195 uint32_t duration; 196 uint32_t status; 197 } __attribute__((__packed__)); 198 199 struct wpi_rx_desc { 200 uint32_t len; 201 uint8_t type; 202 #define WPI_UC_READY 1 203 #define WPI_RX_DONE 27 204 #define WPI_TX_DONE 28 205 #define WPI_START_SCAN 130 206 #define WPI_STOP_SCAN 132 207 #define WPI_STATE_CHANGED 161 208 209 uint8_t flags; 210 uint8_t idx; 211 uint8_t qid; 212 } __attribute__((__packed__)); 213 214 struct wpi_rx_stat { 215 uint8_t len; 216 #define WPI_STAT_MAXLEN 20 217 218 uint8_t id; 219 uint8_t rssi; /* received signal strength */ 220 #define WPI_RSSI_OFFSET 95 221 222 uint8_t agc; /* access gain control */ 223 uint16_t signal; 224 uint16_t noise; 225 } __attribute__((__packed__)); 226 227 struct wpi_rx_head { 228 uint16_t chan; 229 uint16_t flags; 230 uint8_t reserved; 231 uint8_t rate; 232 uint16_t len; 233 } __attribute__((__packed__)); 234 235 struct wpi_rx_tail { 236 uint32_t flags; 237 #define WPI_RX_NO_CRC_ERR (1 << 0) 238 #define WPI_RX_NO_OVFL_ERR (1 << 1) 239 /* shortcut for the above */ 240 #define WPI_RX_NOERROR (WPI_RX_NO_CRC_ERR | WPI_RX_NO_OVFL_ERR) 241 242 uint64_t tstamp; 243 uint32_t tbeacon; 244 } __attribute__((__packed__)); 245 246 struct wpi_tx_cmd { 247 uint8_t code; 248 #define WPI_CMD_CONFIGURE 16 249 #define WPI_CMD_ASSOCIATE 17 250 #define WPI_CMD_SET_WME 19 251 #define WPI_CMD_TSF 20 252 #define WPI_CMD_ADD_NODE 24 253 #define WPI_CMD_TX_DATA 28 254 #define WPI_CMD_MRR_SETUP 71 255 #define WPI_CMD_SET_LED 72 256 #define WPI_CMD_SET_POWER_MODE 119 257 #define WPI_CMD_SCAN 128 258 #define WPI_CMD_SET_BEACON 145 259 #define WPI_CMD_TXPOWER 151 260 #define WPI_CMD_BLUETOOTH 155 261 262 uint8_t flags; 263 uint8_t idx; 264 uint8_t qid; 265 uint8_t data[124]; 266 } __attribute__((__packed__)); 267 268 /* structure for WPI_CMD_CONFIGURE */ 269 struct wpi_config { 270 uint8_t myaddr[IEEE80211_ADDR_LEN]; 271 uint16_t reserved1; 272 uint8_t bssid[IEEE80211_ADDR_LEN]; 273 uint16_t reserved2; 274 uint32_t reserved3[2]; 275 uint8_t mode; 276 #define WPI_MODE_HOSTAP 1 277 #define WPI_MODE_STA 3 278 #define WPI_MODE_IBSS 4 279 #define WPI_MODE_MONITOR 6 280 281 uint8_t reserved4[3]; 282 uint8_t ofdm_mask; 283 uint8_t cck_mask; 284 uint16_t associd; 285 286 uint32_t flags; 287 #define WPI_CONFIG_24GHZ (1 << 0) 288 #define WPI_CONFIG_CCK (1 << 1) 289 #define WPI_CONFIG_AUTO (1 << 2) 290 #define WPI_CONFIG_SHSLOT (1 << 4) 291 #define WPI_CONFIG_SHPREAMBLE (1 << 5) 292 #define WPI_CONFIG_NODIVERSITY (1 << 7) 293 #define WPI_CONFIG_ANTENNA_A (1 << 8) 294 #define WPI_CONFIG_ANTENNA_B (1 << 9) 295 #define WPI_CONFIG_TSF (1 << 15) 296 297 uint32_t filter; 298 #define WPI_FILTER_PROMISC (1 << 0) 299 #define WPI_FILTER_CTL (1 << 1) 300 #define WPI_FILTER_MULTICAST (1 << 2) 301 #define WPI_FILTER_NODECRYPT (1 << 3) 302 #define WPI_FILTER_BSS (1 << 5) 303 #define WPI_FILTER_BEACON (1 << 6) 304 305 uint8_t chan; 306 uint8_t reserved6[3]; 307 } __attribute__((__packed__)); 308 309 /* structure for command WPI_CMD_ASSOCIATE */ 310 struct wpi_assoc { 311 uint32_t flags; 312 uint32_t filter; 313 uint8_t ofdm_mask; 314 uint8_t cck_mask; 315 uint16_t reserved; 316 } __attribute__((__packed__)); 317 318 /* structure for command WPI_CMD_SET_WME */ 319 struct wpi_wme_setup { 320 uint32_t flags; 321 struct { 322 uint16_t cwmin; 323 uint16_t cwmax; 324 uint8_t aifsn; 325 uint8_t reserved; 326 uint16_t txop; 327 } __packed ac[WME_NUM_AC]; 328 } __attribute__((__packed__)); 329 330 /* structure for command WPI_CMD_TSF */ 331 struct wpi_cmd_tsf { 332 uint64_t tstamp; 333 uint16_t bintval; 334 uint16_t atim; 335 uint32_t binitval; 336 uint16_t lintval; 337 uint16_t reserved; 338 } __attribute__((__packed__)); 339 340 /* structure for WPI_CMD_ADD_NODE */ 341 struct wpi_node_info { 342 uint8_t control; 343 #define WPI_NODE_UPDATE (1 << 0) 344 345 uint8_t reserved1[3]; 346 uint8_t bssid[IEEE80211_ADDR_LEN]; 347 uint16_t reserved2; 348 uint8_t id; 349 #define WPI_ID_BSS 0 350 #define WPI_ID_BROADCAST 24 351 352 uint8_t flags; 353 uint16_t reserved3; 354 uint16_t key_flags; 355 uint8_t tkip; 356 uint8_t reserved4; 357 uint16_t ttak[5]; 358 uint16_t reserved5; 359 uint8_t key[IEEE80211_KEYBUF_SIZE]; 360 uint32_t action; 361 #define WPI_ACTION_SET_RATE 4 362 363 uint32_t mask; 364 uint16_t tid; 365 uint8_t rate; 366 uint8_t antenna; 367 #define WPI_ANTENNA_A (1 << 6) 368 #define WPI_ANTENNA_B (1 << 7) 369 #define WPI_ANTENNA_BOTH (WPI_ANTENNA_A | WPI_ANTENNA_B) 370 371 uint8_t add_imm; 372 uint8_t del_imm; 373 uint16_t add_imm_start; 374 } __attribute__((__packed__)); 375 376 /* structure for command WPI_CMD_TX_DATA */ 377 struct wpi_cmd_data { 378 uint16_t len; 379 uint16_t lnext; 380 uint32_t flags; 381 #define WPI_TX_NEED_RTS (1 << 1) 382 #define WPI_TX_NEED_ACK (1 << 3) 383 #define WPI_TX_FULL_TXOP (1 << 7) 384 #define WPI_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 385 #define WPI_TX_AUTO_SEQ (1 << 13) 386 #define WPI_TX_INSERT_TSTAMP (1 << 16) 387 388 uint8_t rate; 389 uint8_t id; 390 uint8_t tid; 391 uint8_t security; 392 uint8_t key[IEEE80211_KEYBUF_SIZE]; 393 uint8_t tkip[IEEE80211_WEP_MICLEN]; 394 uint32_t fnext; 395 uint32_t lifetime; 396 #define WPI_LIFETIME_INFINITE 0xffffffff 397 398 uint8_t ofdm_mask; 399 uint8_t cck_mask; 400 uint8_t rts_ntries; 401 uint8_t data_ntries; 402 uint16_t timeout; 403 uint16_t txop; 404 } __attribute__((__packed__)); 405 406 /* structure for command WPI_CMD_SET_BEACON */ 407 struct wpi_cmd_beacon { 408 uint16_t len; 409 uint16_t reserved1; 410 uint32_t flags; /* same as wpi_cmd_data */ 411 uint8_t rate; 412 uint8_t id; 413 uint8_t reserved2[30]; 414 uint32_t lifetime; 415 uint8_t ofdm_mask; 416 uint8_t cck_mask; 417 uint16_t reserved3[3]; 418 uint16_t tim; 419 uint8_t timsz; 420 uint8_t reserved4; 421 struct ieee80211_frame wh; 422 } __attribute__((__packed__)); 423 424 /* structure for WPI_CMD_MRR_SETUP */ 425 struct wpi_mrr_setup { 426 uint32_t which; 427 #define WPI_MRR_CTL 0 428 #define WPI_MRR_DATA 1 429 430 struct { 431 uint8_t plcp; 432 uint8_t flags; 433 uint8_t ntries; 434 uint8_t next; 435 #define WPI_OFDM6 0 436 #define WPI_OFDM54 7 437 #define WPI_CCK1 8 438 #define WPI_CCK2 9 439 #define WPI_CCK11 11 440 441 } __attribute__((__packed__)) rates[WPI_CCK11 + 1]; 442 } __attribute__((__packed__)); 443 444 /* structure for WPI_CMD_SET_LED */ 445 struct wpi_cmd_led { 446 uint32_t unit; /* multiplier (in usecs) */ 447 uint8_t which; 448 #define WPI_LED_ACTIVITY 1 449 #define WPI_LED_LINK 2 450 451 uint8_t off; 452 uint8_t on; 453 uint8_t reserved; 454 } __attribute__((__packed__)); 455 456 /* structure for WPI_CMD_SET_POWER_MODE */ 457 struct wpi_power { 458 uint32_t flags; 459 #define WPI_POWER_CAM 0 /* constantly awake mode */ 460 461 uint32_t rx_timeout; 462 uint32_t tx_timeout; 463 uint32_t sleep[5]; 464 } __attribute__((__packed__)); 465 466 /* structure for command WPI_CMD_SCAN */ 467 468 struct wpi_scan_essid { 469 uint8_t id; 470 uint8_t len; 471 uint8_t data[IEEE80211_NWID_LEN]; 472 } __attribute__((__packed__)); 473 474 struct wpi_scan_hdr { 475 uint16_t len; 476 uint8_t reserved1; 477 uint8_t nchan; 478 uint16_t quiet; 479 uint16_t plcp_threshold; 480 uint16_t crc_threshold; 481 uint16_t reserved2; 482 uint32_t max_svc; /* background scans */ 483 uint32_t pause_svc; /* background scans */ 484 uint32_t flags; 485 uint32_t filter; 486 487 /* wpi_cmd_data structure */ 488 uint16_t paylen; 489 uint16_t lnext; 490 uint32_t txflags; 491 uint8_t rate; 492 uint8_t id; 493 uint8_t tid; 494 uint8_t security; 495 uint8_t key[IEEE80211_KEYBUF_SIZE]; 496 uint8_t tkip[IEEE80211_WEP_MICLEN]; 497 uint32_t fnext; 498 uint32_t lifetime; 499 uint8_t ofdm_mask; 500 uint8_t cck_mask; 501 uint8_t rts_ntries; 502 uint8_t data_ntries; 503 uint16_t timeout; 504 uint16_t txop; 505 506 struct wpi_scan_essid essid[4]; 507 508 /* followed by probe request body */ 509 /* followed by nchan x wpi_scan_chan */ 510 } __attribute__((__packed__)); 511 512 struct wpi_scan_chan { 513 uint8_t flags; 514 uint8_t chan; 515 #define WPI_CHAN_ACTIVE (1 << 0) 516 #define WPI_CHAN_DIRECT (1 << 1) 517 518 uint8_t rf_gain; 519 uint8_t dsp_gain; 520 uint16_t active; /* msecs */ 521 uint16_t passive; /* msecs */ 522 } __attribute__((__packed__)); 523 524 /* structure for WPI_CMD_TXPOWER */ 525 struct wpi_cmd_txpower { 526 uint8_t band; 527 #define WPI_BAND_5GHZ 0 528 #define WPI_BAND_2GHZ 1 529 530 uint8_t reserved; 531 uint16_t chan; 532 struct { 533 uint8_t plcp; 534 uint8_t rf_gain; 535 uint8_t dsp_gain; 536 uint8_t reserved; 537 } __attribute__((__packed__)) rates[WPI_CCK11 + 1]; 538 } __attribute__((__packed__)); 539 540 /* structure for WPI_CMD_BLUETOOTH */ 541 struct wpi_bluetooth { 542 uint8_t flags; 543 uint8_t lead; 544 uint8_t kill; 545 uint8_t reserved; 546 uint32_t ack; 547 uint32_t cts; 548 } __attribute__((__packed__)); 549 550 551 /* structure for WPI_UC_READY notification */ 552 struct wpi_ucode_info { 553 uint32_t version; 554 uint8_t revision[8]; 555 uint8_t type; 556 uint8_t subtype; 557 uint16_t reserved; 558 uint32_t logptr; 559 uint32_t errorptr; 560 uint32_t timestamp; 561 uint32_t valid; 562 } __attribute__((__packed__)); 563 564 /* structure for WPI_START_SCAN notification */ 565 struct wpi_start_scan { 566 uint64_t tstamp; 567 uint32_t tbeacon; 568 uint8_t chan; 569 uint8_t band; 570 uint16_t reserved; 571 uint32_t status; 572 } __attribute__((__packed__)); 573 574 /* structure for WPI_STOP_SCAN notification */ 575 struct wpi_stop_scan { 576 uint8_t nchan; 577 uint8_t status; 578 uint8_t reserved; 579 uint8_t chan; 580 uint64_t tsf; 581 } __attribute__((__packed__)); 582 583 /* firmware image header */ 584 struct wpi_firmware_hdr { 585 uint32_t version; 586 uint32_t main_textsz; 587 uint32_t main_datasz; 588 uint32_t init_textsz; 589 uint32_t init_datasz; 590 uint32_t boot_textsz; 591 } __attribute__((__packed__)); 592 593 #define WPI_FW_MAIN_TEXT_MAXSZ (80 * 1024) 594 #define WPI_FW_MAIN_DATA_MAXSZ (32 * 1024) 595 #define WPI_FW_INIT_TEXT_MAXSZ (80 * 1024) 596 #define WPI_FW_INIT_DATA_MAXSZ (32 * 1024) 597 #define WPI_FW_BOOT_TEXT_MAXSZ (80 * 1024) 598 599 #define WPI_FW_UPDATED (1 << 31) 600 /* 601 + * Offsets into EEPROM. 602 + */ 603 604 #define WPI_EEPROM_MAC 0x015 605 #define WPI_EEPROM_REVISION 0x035 606 #define WPI_EEPROM_CAPABILITIES 0x045 607 #define WPI_EEPROM_TYPE 0x04a 608 #define WPI_EEPROM_DOMAIN 0x060 609 #define WPI_EEPROM_BAND1 0x063 610 #define WPI_EEPROM_BAND2 0x072 611 #define WPI_EEPROM_BAND3 0x080 612 #define WPI_EEPROM_BAND4 0x08d 613 #define WPI_EEPROM_BAND5 0x099 614 #define WPI_EEPROM_POWER_GRP 0x100 615 616 struct wpi_eeprom_chan { 617 uint8_t flags; 618 #define WPI_EEPROM_CHAN_VALID (1 << 0) 619 #define WPI_EEPROM_CHAN_IBSS (1 << 1) 620 #define WPI_EEPROM_CHAN_ACTIVE (1 << 3) 621 #define WPI_EEPROM_CHAN_RADAR (1 << 4) 622 623 int8_t maxpwr; 624 } __attribute__((__packed__)); 625 626 struct wpi_eeprom_sample { 627 uint8_t index; 628 int8_t power; 629 uint16_t volt; 630 } __attribute__((__packed__)); 631 632 #define WPI_POWER_GROUPS_COUNT 5 633 struct wpi_eeprom_group { 634 struct wpi_eeprom_sample samples[5]; 635 int32_t coef[5]; 636 int32_t corr[5]; 637 int8_t maxpwr; 638 uint8_t chan; 639 int16_t temp; 640 } __attribute__((__packed__)); 641 642 #define WPI_CHAN_BANDS_COUNT 5 643 #define WPI_MAX_CHAN_PER_BAND 14 644 static const struct wpi_chan_band { 645 uint32_t addr; /* offset in EEPROM */ 646 uint8_t nchan; 647 uint8_t chan[WPI_MAX_CHAN_PER_BAND]; 648 } wpi_bands[5] = { 649 { WPI_EEPROM_BAND1, 14, 650 { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 651 { WPI_EEPROM_BAND2, 13, 652 { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 653 { WPI_EEPROM_BAND3, 12, 654 { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 655 { WPI_EEPROM_BAND4, 11, 656 { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 657 { WPI_EEPROM_BAND5, 6, 658 { 145, 149, 153, 157, 161, 165 } } 659 }; 660 661 /* convert rate index (device view) into rate in 500Kbps unit */ 662 static const uint8_t wpi_ridx_to_rate[] = { 663 12, 18, 24, 36, 48, 72, 96, 108, /* OFDM */ 664 2, 4, 11, 22 /* CCK */ 665 }; 666 667 /* convert rate index (device view) into PLCP code */ 668 static const uint8_t wpi_ridx_to_plcp[] = { 669 0xd, 0xf, 0x5, 0x7, 0x9, 0xb, 0x1, 0x3, /* OFDM R1-R4 */ 670 10, 20, 55, 110 /* CCK */ 671 }; 672 673 #define WPI_MAX_PWR_INDEX 77 674 /* 675 * RF Tx gain values from highest to lowest power (values obtained from 676 * the reference driver.) 677 */ 678 static const uint8_t wpi_rf_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { 679 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xbb, 0xbb, 0xbb, 680 0xbb, 0xf3, 0xf3, 0xf3, 0xf3, 0xf3, 0xd3, 0xd3, 0xb3, 0xb3, 0xb3, 681 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x73, 0xeb, 0xeb, 0xeb, 682 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xab, 0xab, 0xab, 0x8b, 683 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xc3, 0xc3, 0xc3, 0xc3, 0xa3, 684 0xa3, 0xa3, 0xa3, 0x83, 0x83, 0x83, 0x83, 0x63, 0x63, 0x63, 0x63, 685 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 0x03, 0x03, 0x03, 686 0x03 687 }; 688 689 static const uint8_t wpi_rf_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { 690 0xfb, 0xfb, 0xfb, 0xdb, 0xdb, 0xbb, 0xbb, 0x9b, 0x9b, 0x7b, 0x7b, 691 0x7b, 0x7b, 0x5b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x1b, 0x1b, 692 0x1b, 0x73, 0x73, 0x73, 0x53, 0x53, 0x53, 0x53, 0x53, 0x33, 0x33, 693 0x33, 0x33, 0x13, 0x13, 0x13, 0x13, 0x13, 0xab, 0xab, 0xab, 0x8b, 694 0x8b, 0x8b, 0x8b, 0x6b, 0x6b, 0x6b, 0x6b, 0x4b, 0x4b, 0x4b, 0x4b, 695 0x2b, 0x2b, 0x2b, 0x2b, 0x0b, 0x0b, 0x0b, 0x0b, 0x83, 0x83, 0x63, 696 0x63, 0x63, 0x63, 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 697 0x03 698 }; 699 700 /* 701 * DSP pre-DAC gain values from highest to lowest power (values obtained 702 * from the reference driver.) 703 */ 704 static const uint8_t wpi_dsp_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { 705 0x7f, 0x7f, 0x7f, 0x7f, 0x7d, 0x6e, 0x69, 0x62, 0x7d, 0x73, 0x6c, 706 0x63, 0x77, 0x6f, 0x69, 0x61, 0x5c, 0x6a, 0x64, 0x78, 0x71, 0x6b, 707 0x7d, 0x77, 0x70, 0x6a, 0x65, 0x61, 0x5b, 0x6b, 0x79, 0x73, 0x6d, 708 0x7f, 0x79, 0x73, 0x6c, 0x66, 0x60, 0x5c, 0x6e, 0x68, 0x62, 0x74, 709 0x7d, 0x77, 0x71, 0x6b, 0x65, 0x60, 0x71, 0x6a, 0x66, 0x5f, 0x71, 710 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 711 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 712 0x5f 713 }; 714 715 static const uint8_t wpi_dsp_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { 716 0x7f, 0x78, 0x72, 0x77, 0x65, 0x71, 0x66, 0x72, 0x67, 0x75, 0x6b, 717 0x63, 0x5c, 0x6c, 0x7d, 0x76, 0x6d, 0x66, 0x60, 0x5a, 0x68, 0x62, 718 0x5c, 0x76, 0x6f, 0x68, 0x7e, 0x79, 0x71, 0x69, 0x63, 0x76, 0x6f, 719 0x68, 0x62, 0x74, 0x6d, 0x66, 0x62, 0x5d, 0x71, 0x6b, 0x63, 0x78, 720 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 721 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x6b, 0x63, 0x78, 722 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 723 0x78 724 }; 725 726 #define WPI_READ(sc, reg) \ 727 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 728 729 #define WPI_WRITE(sc, reg, val) \ 730 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 731 732 #define WPI_WRITE_REGION_4(sc, offset, datap, count) \ 733 bus_space_write_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 734 (datap), (count)) 735