1 /* $NetBSD: if_wpireg.h,v 1.9 2007/12/25 18:33:41 perry Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #define WPI_TX_RING_COUNT 256 21 #define WPI_CMD_RING_COUNT 256 22 #define WPI_RX_RING_COUNT 64 23 24 #define WPI_BUF_ALIGN 4096 25 26 /* 27 * Rings must be aligned on a four 4K-pages boundary. 28 * I had a hard time figuring this out. 29 */ 30 #define WPI_RING_DMA_ALIGN 0x4000 31 32 /* maximum scatter/gather */ 33 #define WPI_MAX_SCATTER 4 34 35 /* maximum Rx buffer size (larger than MCLBYTES) */ 36 #define WPI_RBUF_SIZE (3 * 1024) /* XXX 3000 but must be aligned! */ 37 38 /* 39 * Control and status registers. 40 */ 41 #define WPI_HWCONFIG 0x000 42 #define WPI_INTR 0x008 43 #define WPI_MASK 0x00c 44 #define WPI_INTR_STATUS 0x010 45 #define WPI_GPIO_STATUS 0x018 46 #define WPI_RESET 0x020 47 #define WPI_GPIO_CTL 0x024 48 #define WPI_EEPROM_CTL 0x02c 49 #define WPI_EEPROM_STATUS 0x030 50 #define WPI_UCODE_CLR 0x05c 51 #define WPI_TEMPERATURE 0x060 52 #define WPI_CHICKEN 0x100 53 #define WPI_PLL_CTL 0x20c 54 #define WPI_WRITE_MEM_ADDR 0x444 55 #define WPI_READ_MEM_ADDR 0x448 56 #define WPI_WRITE_MEM_DATA 0x44c 57 #define WPI_READ_MEM_DATA 0x450 58 #define WPI_TX_WIDX 0x460 59 #define WPI_TX_CTL(qid) (0x940 + (qid) * 8) 60 #define WPI_TX_BASE(qid) (0x944 + (qid) * 8) 61 #define WPI_TX_DESC(qid) (0x980 + (qid) * 80) 62 #define WPI_RX_CONFIG 0xc00 63 #define WPI_RX_BASE 0xc04 64 #define WPI_RX_WIDX 0xc20 65 #define WPI_RX_RIDX_PTR 0xc24 66 #define WPI_RX_CTL 0xcc0 67 #define WPI_RX_STATUS 0xcc4 68 #define WPI_TX_CONFIG(qid) (0xd00 + (qid) * 32) 69 #define WPI_TX_CREDIT(qid) (0xd04 + (qid) * 32) 70 #define WPI_TX_STATE(qid) (0xd08 + (qid) * 32) 71 #define WPI_TX_BASE_PTR 0xe80 72 #define WPI_MSG_CONFIG 0xe88 73 #define WPI_TX_STATUS 0xe90 74 75 76 /* 77 * NIC internal memory offsets. 78 */ 79 #define WPI_MEM_MODE 0x2e00 80 #define WPI_MEM_RA 0x2e04 81 #define WPI_MEM_TXCFG 0x2e10 82 #define WPI_MEM_MAGIC4 0x2e14 83 #define WPI_MEM_MAGIC5 0x2e20 84 #define WPI_MEM_BYPASS1 0x2e2c 85 #define WPI_MEM_BYPASS2 0x2e30 86 #define WPI_MEM_CLOCK1 0x3004 87 #define WPI_MEM_CLOCK2 0x3008 88 #define WPI_MEM_POWER 0x300c 89 #define WPI_MEM_PCIDEV 0x3010 90 #define WPI_MEM_RFKILL 0x3014 91 #define WPI_MEM_UCODE_CTL 0x3400 92 #define WPI_MEM_UCODE_SRC 0x3404 93 #define WPI_MEM_UCODE_DST 0x3408 94 #define WPI_MEM_UCODE_SIZE 0x340c 95 #define WPI_MEM_UCODE_BASE 0x3800 96 97 98 #define WPI_MEM_TEXT_BASE 0x3490 99 #define WPI_MEM_TEXT_SIZE 0x3494 100 #define WPI_MEM_DATA_BASE 0x3498 101 #define WPI_MEM_DATA_SIZE 0x349c 102 103 /* possible flags for register WPI_HWCONFIG */ 104 #define WPI_HW_ALM_MB (1 << 8) 105 #define WPI_HW_ALM_MM (1 << 9) 106 #define WPI_HW_SKU_MRC (1 << 10) 107 #define WPI_HW_REV_D (1 << 11) 108 #define WPI_HW_TYPE_B (1 << 12) 109 110 /* possible flags for registers WPI_READ_MEM_ADDR/WPI_WRITE_MEM_ADDR */ 111 #define WPI_MEM_4 ((sizeof (uint32_t) - 1) << 24) 112 113 /* possible values for WPI_MEM_UCODE_DST */ 114 #define WPI_FW_TEXT 0x00000000 115 116 /* possible flags for WPI_GPIO_STATUS */ 117 #define WPI_POWERED (1 << 9) 118 119 /* possible flags for register WPI_RESET */ 120 #define WPI_NEVO_RESET (1 << 0) 121 #define WPI_SW_RESET (1 << 7) 122 #define WPI_MASTER_DISABLED (1 << 8) 123 #define WPI_STOP_MASTER (1 << 9) 124 125 /* possible flags for register WPI_GPIO_CTL */ 126 #define WPI_GPIO_CLOCK (1 << 0) 127 #define WPI_GPIO_INIT (1 << 2) 128 #define WPI_GPIO_MAC (1 << 3) 129 #define WPI_GPIO_SLEEP (1 << 4) 130 #define WPI_GPIO_PWR_STATUS 0x07000000 131 #define WPI_GPIO_PWR_SLEEP (4 << 24) 132 133 /* possible flags for register WPI_CHICKEN */ 134 #define WPI_CHICKEN_RXNOLOS (1 << 23) 135 136 /* possible flags for register WPI_PLL_CTL */ 137 #define WPI_PLL_INIT (1 << 24) 138 139 /* possible flags for register WPI_UCODE_CLR */ 140 #define WPI_RADIO_OFF (1 << 1) 141 #define WPI_DISABLE_CMD (1 << 2) 142 143 /* possible flags for WPI_RX_STATUS */ 144 #define WPI_RX_IDLE (1 << 24) 145 146 /* possible flags for register WPI_UC_CTL */ 147 #define WPI_UC_ENABLE (1 << 30) 148 #define WPI_UC_RUN (1 << 31) 149 150 /* possible flags for register WPI_INTR_CSR */ 151 #define WPI_ALIVE_INTR (1 << 0) 152 #define WPI_WAKEUP_INTR (1 << 1) 153 #define WPI_SW_ERROR (1 << 25) 154 #define WPI_TX_INTR (1 << 27) 155 #define WPI_HW_ERROR (1 << 29) 156 #define WPI_RX_INTR (1 << 31) 157 158 #define WPI_INTR_MASK \ 159 (WPI_SW_ERROR | WPI_HW_ERROR | WPI_TX_INTR | WPI_RX_INTR | \ 160 WPI_ALIVE_INTR | WPI_WAKEUP_INTR) 161 162 /* possible flags for register WPI_TX_STATUS */ 163 #define WPI_TX_IDLE(qid) (1 << ((qid) + 24) | 1 << ((qid) + 16)) 164 165 /* possible flags for register WPI_EEPROM_CTL */ 166 #define WPI_EEPROM_READY (1 << 0) 167 168 /* possible flags for register WPI_EEPROM_STATUS */ 169 #define WPI_EEPROM_VERSION 0x00000007 170 #define WPI_EEPROM_LOCKED 0x00000180 171 172 173 struct wpi_shared { 174 uint32_t txbase[8]; 175 uint32_t next; 176 uint32_t reserved[2]; 177 } __packed; 178 179 #define WPI_MAX_SEG_LEN 65520 180 struct wpi_tx_desc { 181 uint32_t flags; 182 #define WPI_PAD32(x) ((((x) + 3) & ~3) - (x)) 183 184 struct { 185 uint32_t addr; 186 uint32_t len; 187 } __packed segs[WPI_MAX_SCATTER]; 188 uint8_t reserved[28]; 189 } __packed; 190 191 struct wpi_tx_stat { 192 uint8_t nrts; 193 uint8_t ntries; 194 uint8_t nkill; 195 uint8_t rate; 196 uint32_t duration; 197 uint32_t status; 198 } __packed; 199 200 struct wpi_rx_desc { 201 uint32_t len; 202 uint8_t type; 203 #define WPI_UC_READY 1 204 #define WPI_RX_DONE 27 205 #define WPI_TX_DONE 28 206 #define WPI_START_SCAN 130 207 #define WPI_STOP_SCAN 132 208 #define WPI_STATE_CHANGED 161 209 210 uint8_t flags; 211 uint8_t idx; 212 uint8_t qid; 213 } __packed; 214 215 struct wpi_rx_stat { 216 uint8_t len; 217 #define WPI_STAT_MAXLEN 20 218 219 uint8_t id; 220 uint8_t rssi; /* received signal strength */ 221 #define WPI_RSSI_OFFSET 95 222 223 uint8_t agc; /* access gain control */ 224 uint16_t signal; 225 uint16_t noise; 226 } __packed; 227 228 struct wpi_rx_head { 229 uint16_t chan; 230 uint16_t flags; 231 uint8_t reserved; 232 uint8_t rate; 233 uint16_t len; 234 } __packed; 235 236 struct wpi_rx_tail { 237 uint32_t flags; 238 #define WPI_RX_NO_CRC_ERR (1 << 0) 239 #define WPI_RX_NO_OVFL_ERR (1 << 1) 240 /* shortcut for the above */ 241 #define WPI_RX_NOERROR (WPI_RX_NO_CRC_ERR | WPI_RX_NO_OVFL_ERR) 242 243 uint64_t tstamp; 244 uint32_t tbeacon; 245 } __packed; 246 247 struct wpi_tx_cmd { 248 uint8_t code; 249 #define WPI_CMD_CONFIGURE 16 250 #define WPI_CMD_ASSOCIATE 17 251 #define WPI_CMD_SET_WME 19 252 #define WPI_CMD_TSF 20 253 #define WPI_CMD_ADD_NODE 24 254 #define WPI_CMD_TX_DATA 28 255 #define WPI_CMD_MRR_SETUP 71 256 #define WPI_CMD_SET_LED 72 257 #define WPI_CMD_SET_POWER_MODE 119 258 #define WPI_CMD_SCAN 128 259 #define WPI_CMD_SET_BEACON 145 260 #define WPI_CMD_TXPOWER 151 261 #define WPI_CMD_BLUETOOTH 155 262 263 uint8_t flags; 264 uint8_t idx; 265 uint8_t qid; 266 uint8_t data[124]; 267 } __packed; 268 269 /* structure for WPI_CMD_CONFIGURE */ 270 struct wpi_config { 271 uint8_t myaddr[IEEE80211_ADDR_LEN]; 272 uint16_t reserved1; 273 uint8_t bssid[IEEE80211_ADDR_LEN]; 274 uint16_t reserved2; 275 uint32_t reserved3[2]; 276 uint8_t mode; 277 #define WPI_MODE_HOSTAP 1 278 #define WPI_MODE_STA 3 279 #define WPI_MODE_IBSS 4 280 #define WPI_MODE_MONITOR 6 281 282 uint8_t reserved4[3]; 283 uint8_t ofdm_mask; 284 uint8_t cck_mask; 285 uint16_t associd; 286 287 uint32_t flags; 288 #define WPI_CONFIG_24GHZ (1 << 0) 289 #define WPI_CONFIG_CCK (1 << 1) 290 #define WPI_CONFIG_AUTO (1 << 2) 291 #define WPI_CONFIG_SHSLOT (1 << 4) 292 #define WPI_CONFIG_SHPREAMBLE (1 << 5) 293 #define WPI_CONFIG_NODIVERSITY (1 << 7) 294 #define WPI_CONFIG_ANTENNA_A (1 << 8) 295 #define WPI_CONFIG_ANTENNA_B (1 << 9) 296 #define WPI_CONFIG_TSF (1 << 15) 297 298 uint32_t filter; 299 #define WPI_FILTER_PROMISC (1 << 0) 300 #define WPI_FILTER_CTL (1 << 1) 301 #define WPI_FILTER_MULTICAST (1 << 2) 302 #define WPI_FILTER_NODECRYPT (1 << 3) 303 #define WPI_FILTER_BSS (1 << 5) 304 #define WPI_FILTER_BEACON (1 << 6) 305 306 uint8_t chan; 307 uint8_t reserved6[3]; 308 } __packed; 309 310 /* structure for command WPI_CMD_ASSOCIATE */ 311 struct wpi_assoc { 312 uint32_t flags; 313 uint32_t filter; 314 uint8_t ofdm_mask; 315 uint8_t cck_mask; 316 uint16_t reserved; 317 } __packed; 318 319 /* structure for command WPI_CMD_SET_WME */ 320 struct wpi_wme_setup { 321 uint32_t flags; 322 struct { 323 uint16_t cwmin; 324 uint16_t cwmax; 325 uint8_t aifsn; 326 uint8_t reserved; 327 uint16_t txop; 328 } __packed ac[WME_NUM_AC]; 329 } __packed; 330 331 /* structure for command WPI_CMD_TSF */ 332 struct wpi_cmd_tsf { 333 uint64_t tstamp; 334 uint16_t bintval; 335 uint16_t atim; 336 uint32_t binitval; 337 uint16_t lintval; 338 uint16_t reserved; 339 } __packed; 340 341 /* structure for WPI_CMD_ADD_NODE */ 342 struct wpi_node_info { 343 uint8_t control; 344 #define WPI_NODE_UPDATE (1 << 0) 345 346 uint8_t reserved1[3]; 347 uint8_t bssid[IEEE80211_ADDR_LEN]; 348 uint16_t reserved2; 349 uint8_t id; 350 #define WPI_ID_BSS 0 351 #define WPI_ID_BROADCAST 24 352 353 uint8_t flags; 354 uint16_t reserved3; 355 uint16_t key_flags; 356 uint8_t tkip; 357 uint8_t reserved4; 358 uint16_t ttak[5]; 359 uint16_t reserved5; 360 uint8_t key[IEEE80211_KEYBUF_SIZE]; 361 uint32_t action; 362 #define WPI_ACTION_SET_RATE 4 363 364 uint32_t mask; 365 uint16_t tid; 366 uint8_t rate; 367 uint8_t antenna; 368 #define WPI_ANTENNA_A (1 << 6) 369 #define WPI_ANTENNA_B (1 << 7) 370 #define WPI_ANTENNA_BOTH (WPI_ANTENNA_A | WPI_ANTENNA_B) 371 372 uint8_t add_imm; 373 uint8_t del_imm; 374 uint16_t add_imm_start; 375 } __packed; 376 377 /* structure for command WPI_CMD_TX_DATA */ 378 struct wpi_cmd_data { 379 uint16_t len; 380 uint16_t lnext; 381 uint32_t flags; 382 #define WPI_TX_NEED_RTS (1 << 1) 383 #define WPI_TX_NEED_ACK (1 << 3) 384 #define WPI_TX_FULL_TXOP (1 << 7) 385 #define WPI_TX_BT_DISABLE (1 << 12) /* bluetooth coexistence */ 386 #define WPI_TX_AUTO_SEQ (1 << 13) 387 #define WPI_TX_INSERT_TSTAMP (1 << 16) 388 389 uint8_t rate; 390 uint8_t id; 391 uint8_t tid; 392 uint8_t security; 393 uint8_t key[IEEE80211_KEYBUF_SIZE]; 394 uint8_t tkip[IEEE80211_WEP_MICLEN]; 395 uint32_t fnext; 396 uint32_t lifetime; 397 #define WPI_LIFETIME_INFINITE 0xffffffff 398 399 uint8_t ofdm_mask; 400 uint8_t cck_mask; 401 uint8_t rts_ntries; 402 uint8_t data_ntries; 403 uint16_t timeout; 404 uint16_t txop; 405 } __packed; 406 407 /* structure for command WPI_CMD_SET_BEACON */ 408 struct wpi_cmd_beacon { 409 uint16_t len; 410 uint16_t reserved1; 411 uint32_t flags; /* same as wpi_cmd_data */ 412 uint8_t rate; 413 uint8_t id; 414 uint8_t reserved2[30]; 415 uint32_t lifetime; 416 uint8_t ofdm_mask; 417 uint8_t cck_mask; 418 uint16_t reserved3[3]; 419 uint16_t tim; 420 uint8_t timsz; 421 uint8_t reserved4; 422 struct ieee80211_frame wh; 423 } __packed; 424 425 /* structure for WPI_CMD_MRR_SETUP */ 426 struct wpi_mrr_setup { 427 uint32_t which; 428 #define WPI_MRR_CTL 0 429 #define WPI_MRR_DATA 1 430 431 struct { 432 uint8_t plcp; 433 uint8_t flags; 434 uint8_t ntries; 435 uint8_t next; 436 #define WPI_OFDM6 0 437 #define WPI_OFDM54 7 438 #define WPI_CCK1 8 439 #define WPI_CCK2 9 440 #define WPI_CCK11 11 441 442 } __packed rates[WPI_CCK11 + 1]; 443 } __packed; 444 445 /* structure for WPI_CMD_SET_LED */ 446 struct wpi_cmd_led { 447 uint32_t unit; /* multiplier (in usecs) */ 448 uint8_t which; 449 #define WPI_LED_ACTIVITY 1 450 #define WPI_LED_LINK 2 451 452 uint8_t off; 453 uint8_t on; 454 uint8_t reserved; 455 } __packed; 456 457 /* structure for WPI_CMD_SET_POWER_MODE */ 458 struct wpi_power { 459 uint32_t flags; 460 #define WPI_POWER_CAM 0 /* constantly awake mode */ 461 462 uint32_t rx_timeout; 463 uint32_t tx_timeout; 464 uint32_t sleep[5]; 465 } __packed; 466 467 /* structure for command WPI_CMD_SCAN */ 468 469 struct wpi_scan_essid { 470 uint8_t id; 471 uint8_t len; 472 uint8_t data[IEEE80211_NWID_LEN]; 473 } __packed; 474 475 struct wpi_scan_hdr { 476 uint16_t len; 477 uint8_t reserved1; 478 uint8_t nchan; 479 uint16_t quiet; 480 uint16_t plcp_threshold; 481 uint16_t crc_threshold; 482 uint16_t reserved2; 483 uint32_t max_svc; /* background scans */ 484 uint32_t pause_svc; /* background scans */ 485 uint32_t flags; 486 uint32_t filter; 487 488 /* wpi_cmd_data structure */ 489 uint16_t paylen; 490 uint16_t lnext; 491 uint32_t txflags; 492 uint8_t rate; 493 uint8_t id; 494 uint8_t tid; 495 uint8_t security; 496 uint8_t key[IEEE80211_KEYBUF_SIZE]; 497 uint8_t tkip[IEEE80211_WEP_MICLEN]; 498 uint32_t fnext; 499 uint32_t lifetime; 500 uint8_t ofdm_mask; 501 uint8_t cck_mask; 502 uint8_t rts_ntries; 503 uint8_t data_ntries; 504 uint16_t timeout; 505 uint16_t txop; 506 507 struct wpi_scan_essid essid[4]; 508 509 /* followed by probe request body */ 510 /* followed by nchan x wpi_scan_chan */ 511 } __packed; 512 513 struct wpi_scan_chan { 514 uint8_t flags; 515 uint8_t chan; 516 #define WPI_CHAN_ACTIVE (1 << 0) 517 #define WPI_CHAN_DIRECT (1 << 1) 518 519 uint8_t rf_gain; 520 uint8_t dsp_gain; 521 uint16_t active; /* msecs */ 522 uint16_t passive; /* msecs */ 523 } __packed; 524 525 /* structure for WPI_CMD_TXPOWER */ 526 struct wpi_cmd_txpower { 527 uint8_t band; 528 #define WPI_BAND_5GHZ 0 529 #define WPI_BAND_2GHZ 1 530 531 uint8_t reserved; 532 uint16_t chan; 533 struct { 534 uint8_t plcp; 535 uint8_t rf_gain; 536 uint8_t dsp_gain; 537 uint8_t reserved; 538 } __packed rates[WPI_CCK11 + 1]; 539 } __packed; 540 541 /* structure for WPI_CMD_BLUETOOTH */ 542 struct wpi_bluetooth { 543 uint8_t flags; 544 uint8_t lead; 545 uint8_t kill; 546 uint8_t reserved; 547 uint32_t ack; 548 uint32_t cts; 549 } __packed; 550 551 552 /* structure for WPI_UC_READY notification */ 553 struct wpi_ucode_info { 554 uint32_t version; 555 uint8_t revision[8]; 556 uint8_t type; 557 uint8_t subtype; 558 uint16_t reserved; 559 uint32_t logptr; 560 uint32_t errorptr; 561 uint32_t timestamp; 562 uint32_t valid; 563 } __packed; 564 565 /* structure for WPI_START_SCAN notification */ 566 struct wpi_start_scan { 567 uint64_t tstamp; 568 uint32_t tbeacon; 569 uint8_t chan; 570 uint8_t band; 571 uint16_t reserved; 572 uint32_t status; 573 } __packed; 574 575 /* structure for WPI_STOP_SCAN notification */ 576 struct wpi_stop_scan { 577 uint8_t nchan; 578 uint8_t status; 579 uint8_t reserved; 580 uint8_t chan; 581 uint64_t tsf; 582 } __packed; 583 584 /* firmware image header */ 585 struct wpi_firmware_hdr { 586 uint32_t version; 587 uint32_t main_textsz; 588 uint32_t main_datasz; 589 uint32_t init_textsz; 590 uint32_t init_datasz; 591 uint32_t boot_textsz; 592 } __packed; 593 594 #define WPI_FW_MAIN_TEXT_MAXSZ (80 * 1024) 595 #define WPI_FW_MAIN_DATA_MAXSZ (32 * 1024) 596 #define WPI_FW_INIT_TEXT_MAXSZ (80 * 1024) 597 #define WPI_FW_INIT_DATA_MAXSZ (32 * 1024) 598 #define WPI_FW_BOOT_TEXT_MAXSZ (80 * 1024) 599 600 #define WPI_FW_UPDATED (1 << 31) 601 /* 602 + * Offsets into EEPROM. 603 + */ 604 605 #define WPI_EEPROM_MAC 0x015 606 #define WPI_EEPROM_REVISION 0x035 607 #define WPI_EEPROM_CAPABILITIES 0x045 608 #define WPI_EEPROM_TYPE 0x04a 609 #define WPI_EEPROM_DOMAIN 0x060 610 #define WPI_EEPROM_BAND1 0x063 611 #define WPI_EEPROM_BAND2 0x072 612 #define WPI_EEPROM_BAND3 0x080 613 #define WPI_EEPROM_BAND4 0x08d 614 #define WPI_EEPROM_BAND5 0x099 615 #define WPI_EEPROM_POWER_GRP 0x100 616 617 struct wpi_eeprom_chan { 618 uint8_t flags; 619 #define WPI_EEPROM_CHAN_VALID (1 << 0) 620 #define WPI_EEPROM_CHAN_IBSS (1 << 1) 621 #define WPI_EEPROM_CHAN_ACTIVE (1 << 3) 622 #define WPI_EEPROM_CHAN_RADAR (1 << 4) 623 624 int8_t maxpwr; 625 } __packed; 626 627 struct wpi_eeprom_sample { 628 uint8_t index; 629 int8_t power; 630 uint16_t volt; 631 } __packed; 632 633 #define WPI_POWER_GROUPS_COUNT 5 634 struct wpi_eeprom_group { 635 struct wpi_eeprom_sample samples[5]; 636 int32_t coef[5]; 637 int32_t corr[5]; 638 int8_t maxpwr; 639 uint8_t chan; 640 int16_t temp; 641 } __packed; 642 643 #define WPI_CHAN_BANDS_COUNT 5 644 #define WPI_MAX_CHAN_PER_BAND 14 645 static const struct wpi_chan_band { 646 uint32_t addr; /* offset in EEPROM */ 647 uint8_t nchan; 648 uint8_t chan[WPI_MAX_CHAN_PER_BAND]; 649 } wpi_bands[5] = { 650 { WPI_EEPROM_BAND1, 14, 651 { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 } }, 652 { WPI_EEPROM_BAND2, 13, 653 { 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 } }, 654 { WPI_EEPROM_BAND3, 12, 655 { 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 } }, 656 { WPI_EEPROM_BAND4, 11, 657 { 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 } }, 658 { WPI_EEPROM_BAND5, 6, 659 { 145, 149, 153, 157, 161, 165 } } 660 }; 661 662 /* convert rate index (device view) into rate in 500Kbps unit */ 663 static const uint8_t wpi_ridx_to_rate[] = { 664 12, 18, 24, 36, 48, 72, 96, 108, /* OFDM */ 665 2, 4, 11, 22 /* CCK */ 666 }; 667 668 /* convert rate index (device view) into PLCP code */ 669 static const uint8_t wpi_ridx_to_plcp[] = { 670 0xd, 0xf, 0x5, 0x7, 0x9, 0xb, 0x1, 0x3, /* OFDM R1-R4 */ 671 10, 20, 55, 110 /* CCK */ 672 }; 673 674 #define WPI_MAX_PWR_INDEX 77 675 /* 676 * RF Tx gain values from highest to lowest power (values obtained from 677 * the reference driver.) 678 */ 679 static const uint8_t wpi_rf_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { 680 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xbb, 0xbb, 0xbb, 681 0xbb, 0xf3, 0xf3, 0xf3, 0xf3, 0xf3, 0xd3, 0xd3, 0xb3, 0xb3, 0xb3, 682 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x73, 0xeb, 0xeb, 0xeb, 683 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xab, 0xab, 0xab, 0x8b, 684 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xc3, 0xc3, 0xc3, 0xc3, 0xa3, 685 0xa3, 0xa3, 0xa3, 0x83, 0x83, 0x83, 0x83, 0x63, 0x63, 0x63, 0x63, 686 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 0x03, 0x03, 0x03, 687 0x03 688 }; 689 690 static const uint8_t wpi_rf_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { 691 0xfb, 0xfb, 0xfb, 0xdb, 0xdb, 0xbb, 0xbb, 0x9b, 0x9b, 0x7b, 0x7b, 692 0x7b, 0x7b, 0x5b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x1b, 0x1b, 693 0x1b, 0x73, 0x73, 0x73, 0x53, 0x53, 0x53, 0x53, 0x53, 0x33, 0x33, 694 0x33, 0x33, 0x13, 0x13, 0x13, 0x13, 0x13, 0xab, 0xab, 0xab, 0x8b, 695 0x8b, 0x8b, 0x8b, 0x6b, 0x6b, 0x6b, 0x6b, 0x4b, 0x4b, 0x4b, 0x4b, 696 0x2b, 0x2b, 0x2b, 0x2b, 0x0b, 0x0b, 0x0b, 0x0b, 0x83, 0x83, 0x63, 697 0x63, 0x63, 0x63, 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 698 0x03 699 }; 700 701 /* 702 * DSP pre-DAC gain values from highest to lowest power (values obtained 703 * from the reference driver.) 704 */ 705 static const uint8_t wpi_dsp_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = { 706 0x7f, 0x7f, 0x7f, 0x7f, 0x7d, 0x6e, 0x69, 0x62, 0x7d, 0x73, 0x6c, 707 0x63, 0x77, 0x6f, 0x69, 0x61, 0x5c, 0x6a, 0x64, 0x78, 0x71, 0x6b, 708 0x7d, 0x77, 0x70, 0x6a, 0x65, 0x61, 0x5b, 0x6b, 0x79, 0x73, 0x6d, 709 0x7f, 0x79, 0x73, 0x6c, 0x66, 0x60, 0x5c, 0x6e, 0x68, 0x62, 0x74, 710 0x7d, 0x77, 0x71, 0x6b, 0x65, 0x60, 0x71, 0x6a, 0x66, 0x5f, 0x71, 711 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 712 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 713 0x5f 714 }; 715 716 static const uint8_t wpi_dsp_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = { 717 0x7f, 0x78, 0x72, 0x77, 0x65, 0x71, 0x66, 0x72, 0x67, 0x75, 0x6b, 718 0x63, 0x5c, 0x6c, 0x7d, 0x76, 0x6d, 0x66, 0x60, 0x5a, 0x68, 0x62, 719 0x5c, 0x76, 0x6f, 0x68, 0x7e, 0x79, 0x71, 0x69, 0x63, 0x76, 0x6f, 720 0x68, 0x62, 0x74, 0x6d, 0x66, 0x62, 0x5d, 0x71, 0x6b, 0x63, 0x78, 721 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 722 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x6b, 0x63, 0x78, 723 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 724 0x78 725 }; 726 727 #define WPI_READ(sc, reg) \ 728 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 729 730 #define WPI_WRITE(sc, reg, val) \ 731 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 732 733 #define WPI_WRITE_REGION_4(sc, offset, datap, count) \ 734 bus_space_write_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 735 (datap), (count)) 736