xref: /netbsd-src/sys/dev/pci/if_wmvar.h (revision c38e7cc395b1472a774ff828e46123de44c628e9)
1 /*	$NetBSD: if_wmvar.h,v 1.38 2018/04/12 03:25:08 msaitoh Exp $	*/
2 
3 /*
4  * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
5  * All rights reserved.
6  *
7  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  * 3. All advertising materials mentioning features or use of this software
18  *    must display the following acknowledgement:
19  *	This product includes software developed for the NetBSD Project by
20  *	Wasabi Systems, Inc.
21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22  *    or promote products derived from this software without specific prior
23  *    written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35  * POSSIBILITY OF SUCH DAMAGE.
36  */
37 
38 /*******************************************************************************
39 
40   Copyright (c) 2001-2005, Intel Corporation
41   All rights reserved.
42 
43   Redistribution and use in source and binary forms, with or without
44   modification, are permitted provided that the following conditions are met:
45 
46    1. Redistributions of source code must retain the above copyright notice,
47       this list of conditions and the following disclaimer.
48 
49    2. Redistributions in binary form must reproduce the above copyright
50       notice, this list of conditions and the following disclaimer in the
51       documentation and/or other materials provided with the distribution.
52 
53    3. Neither the name of the Intel Corporation nor the names of its
54       contributors may be used to endorse or promote products derived from
55       this software without specific prior written permission.
56 
57   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
58   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
59   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
60   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
61   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
62   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
63   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
64   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
65   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
66   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
67   POSSIBILITY OF SUCH DAMAGE.
68 
69 *******************************************************************************/
70 
71 #ifndef _DEV_PCI_IF_WMVAR_H_
72 #define _DEV_PCI_IF_WMVAR_H_
73 
74 /* sc_flags */
75 #define	WM_F_HAS_MII		0x00000001 /* has MII */
76 #define	WM_F_LOCK_EECD		0x00000002 /* Lock using with EECD register */
77 #define	WM_F_EEPROM_INVM	0x00000020 /* NVM is iNVM */
78 #define	WM_F_EEPROM_SPI		0x00000040 /* EEPROM is SPI */
79 #define	WM_F_EEPROM_FLASH	0x00000080 /* EEPROM is FLASH */
80 #define	WM_F_EEPROM_FLASH_HW	0x00000100 /* EEPROM is FLASH */
81 #define	WM_F_EEPROM_INVALID	0x00000200 /* EEPROM not present (bad cksum) */
82 #define	WM_F_IOH_VALID		0x00000400 /* I/O handle is valid */
83 #define	WM_F_BUS64		0x00000800 /* bus is 64-bit */
84 #define	WM_F_PCIX		0x00001000 /* bus is PCI-X */
85 #define	WM_F_CSA		0x00002000 /* bus is CSA */
86 #define	WM_F_PCIE		0x00004000 /* bus is PCI-Express */
87 #define WM_F_SGMII		0x00008000 /* use SGMII */
88 #define WM_F_NEWQUEUE		0x00010000 /* use new queue system */
89 #define WM_F_ASF_FIRMWARE_PRES	0x00020000
90 #define WM_F_ARC_SUBSYS_VALID	0x00040000
91 #define WM_F_HAS_AMT		0x00080000
92 #define WM_F_HAS_MANAGE		0x00100000
93 #define WM_F_WOL		0x00200000
94 #define WM_F_EEE		0x00400000 /* Energy Efficiency Ethernet */
95 #define WM_F_ATTACHED		0x00800000 /* attach() finished successfully */
96 #define WM_F_80003_MDIC_WA	0x01000000 /* 80003 MDIC workaround */
97 #define	WM_F_PCS_DIS_AUTONEGO	0x02000000 /* PCS Disable Autonego */
98 #define	WM_F_PLL_WA_I210	0x04000000 /* I21[01] PLL workaround */
99 #define	WM_F_WA_I210_CLSEM	0x08000000 /* I21[01] Semaphore workaround */
100 
101 #define WM_FLAGS "\20" \
102 	"\1" "HAS_MII"	"\2" "LOCK_EECD" "\3" "_B02"	"\4" "_B03"	\
103 	"\5" "_B04"	"\6" "INVM"	"\7" "SPI"	"\10" "FLASH"	\
104 	"\11" "FLASH_HW" "\12" "INVALID" "\13" "IOH_VALID" "\14" "BUS64" \
105 	"\15" "PCIX"	"\16" "CSA"	"\17" "PCIE"	"\20" "SGMII"	\
106 	"\21" "NEWQUEUE" "\22" "ASF_FIRM" "\23" "ARC_SUBSYS" "\24" "AMT" \
107 	"\25" "MANAGE"	"\26" "WOL"	"\27" "EEE"	"\30" "ATTACHED" \
108 	"\31" "_B24"	"\32" "PCS_DIS_AUTONEGO" "\33" "PLLWA"
109 
110 /*
111  * Variations of Intel gigabit Ethernet controller:
112  *
113  *  +-- 82542
114  *  |  +-- 82543 - 82544
115  *  |  |  +-- 82540 - 82545 - 82546
116  *  |  |  |  +-- 82541 - 82547
117  *  |  |  |  |  +---------- 82571 - 82572 - 82573 - 82574 - 82583
118  *  |  |  |  |  |  +--------- 82575 - 82576 - 82580 - I350 - I354 - I210 - I211
119  *  |  |  |  |  |  |  +-- 80003
120  *  |  |  |  |  |  |  |  +-- ICH8 - 9 - 10 - PCH - 2 - LPT - SPT - CNP
121  *  |  |  |  |  |  |  |  |
122  * -+--+--+--+--+--+--+--+----------------------------------------------->
123  */
124 
125 typedef enum {
126 	WM_T_unknown		= 0,
127 	WM_T_82542_2_0,			/* i82542 2.0 (really old) */
128 	WM_T_82542_2_1,			/* i82542 2.1+ (old) */
129 	WM_T_82543,			/* i82543 */
130 	WM_T_82544,			/* i82544 */
131 	WM_T_82540,			/* i82540 */
132 	WM_T_82545,			/* i82545 */
133 	WM_T_82545_3,			/* i82545 3.0+ */
134 	WM_T_82546,			/* i82546 */
135 	WM_T_82546_3,			/* i82546 3.0+ */
136 	WM_T_82541,			/* i82541 */
137 	WM_T_82541_2,			/* i82541 2.0+ */
138 	WM_T_82547,			/* i82547 */
139 	WM_T_82547_2,			/* i82547 2.0+ */
140 	WM_T_82571,			/* i82571 */
141 	WM_T_82572,			/* i82572 */
142 	WM_T_82573,			/* i82573 */
143 	WM_T_82574,			/* i82574 */
144 	WM_T_82583,			/* i82583 */
145 	WM_T_82575,			/* i82575 */
146 	WM_T_82576,			/* i82576 */
147 	WM_T_82580,			/* i82580 */
148 	WM_T_I350,			/* I350 */
149 	WM_T_I354,			/* I354 */
150 	WM_T_I210,			/* I210 */
151 	WM_T_I211,			/* I211 */
152 	WM_T_80003,			/* i80003 */
153 	WM_T_ICH8,			/* ICH8 (I/O Controller Hub) LAN */
154 	WM_T_ICH9,			/* ICH9 LAN */
155 	WM_T_ICH10,			/* ICH10 LAN */
156 	WM_T_PCH,			/* PCH (Platform Controller Hub) LAN */
157 	WM_T_PCH2,			/* PCH2 LAN */
158 	WM_T_PCH_LPT,			/* PCH "Lynx Point" LAN (I217, I218) */
159 	WM_T_PCH_SPT,			/* PCH "Sunrise Point" LAN (I219) */
160 	WM_T_PCH_CNP,			/* (I219) */
161 } wm_chip_type;
162 
163 typedef enum {
164 	WMPHY_UNKNOWN = 0,
165 	WMPHY_NONE,
166 	WMPHY_M88,
167 	WMPHY_IGP,
168 	WMPHY_IGP_2,
169 	WMPHY_GG82563,
170 	WMPHY_IGP_3,
171 	WMPHY_IFE,
172 	WMPHY_BM,
173 	WMPHY_82577,
174 	WMPHY_82578,
175 	WMPHY_82579,
176 	WMPHY_I217,
177 	WMPHY_82580,
178 	WMPHY_VF,
179 	WMPHY_I210
180 } wm_phy_type;
181 
182 
183 #define WM_GEN_POLL_TIMEOUT	640
184 #define WM_PHY_CFG_TIMEOUT	100
185 #define	WM_ICH8_LAN_INIT_TIMEOUT 1500
186 #define	WM_MDIO_OWNERSHIP_TIMEOUT 10
187 #define	WM_MAX_PLL_TRIES	5
188 
189 #endif /* _DEV_PCI_IF_WMVAR_H_ */
190