1 /* $NetBSD: if_wmreg.h,v 1.54 2013/06/25 17:38:38 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /****************************************************************************** 39 40 Copyright (c) 2001-2012, Intel Corporation 41 All rights reserved. 42 43 Redistribution and use in source and binary forms, with or without 44 modification, are permitted provided that the following conditions are met: 45 46 1. Redistributions of source code must retain the above copyright notice, 47 this list of conditions and the following disclaimer. 48 49 2. Redistributions in binary form must reproduce the above copyright 50 notice, this list of conditions and the following disclaimer in the 51 documentation and/or other materials provided with the distribution. 52 53 3. Neither the name of the Intel Corporation nor the names of its 54 contributors may be used to endorse or promote products derived from 55 this software without specific prior written permission. 56 57 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 58 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 61 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 67 POSSIBILITY OF SUCH DAMAGE. 68 69 ******************************************************************************/ 70 71 /* 72 * Register description for the Intel i82542 (``Wiseman''), 73 * i82543 (``Livengood''), and i82544 (``Cordova'') Gigabit 74 * Ethernet chips. 75 */ 76 77 /* 78 * The wiseman supports 64-bit PCI addressing. This structure 79 * describes the address in descriptors. 80 */ 81 typedef struct wiseman_addr { 82 uint32_t wa_low; /* low-order 32 bits */ 83 uint32_t wa_high; /* high-order 32 bits */ 84 } __packed wiseman_addr_t; 85 86 /* 87 * The Wiseman receive descriptor. 88 * 89 * The receive descriptor ring must be aligned to a 4K boundary, 90 * and there must be an even multiple of 8 descriptors in the ring. 91 */ 92 typedef struct wiseman_rxdesc { 93 volatile wiseman_addr_t wrx_addr; /* buffer address */ 94 95 volatile uint16_t wrx_len; /* buffer length */ 96 volatile uint16_t wrx_cksum; /* checksum (starting at PCSS)*/ 97 98 volatile uint8_t wrx_status; /* Rx status */ 99 volatile uint8_t wrx_errors; /* Rx errors */ 100 volatile uint16_t wrx_special; /* special field (VLAN, etc.) */ 101 } __packed wiseman_rxdesc_t; 102 103 /* wrx_status bits */ 104 #define WRX_ST_DD (1U << 0) /* descriptor done */ 105 #define WRX_ST_EOP (1U << 1) /* end of packet */ 106 #define WRX_ST_IXSM (1U << 2) /* ignore checksum indication */ 107 #define WRX_ST_VP (1U << 3) /* VLAN packet */ 108 #define WRX_ST_BPDU (1U << 4) /* ??? */ 109 #define WRX_ST_TCPCS (1U << 5) /* TCP checksum performed */ 110 #define WRX_ST_IPCS (1U << 6) /* IP checksum performed */ 111 #define WRX_ST_PIF (1U << 7) /* passed in-exact filter */ 112 113 /* wrx_error bits */ 114 #define WRX_ER_CE (1U << 0) /* CRC error */ 115 #define WRX_ER_SE (1U << 1) /* symbol error */ 116 #define WRX_ER_SEQ (1U << 2) /* sequence error */ 117 #define WRX_ER_ICE (1U << 3) /* ??? */ 118 #define WRX_ER_CXE (1U << 4) /* carrier extension error */ 119 #define WRX_ER_TCPE (1U << 5) /* TCP checksum error */ 120 #define WRX_ER_IPE (1U << 6) /* IP checksum error */ 121 #define WRX_ER_RXE (1U << 7) /* Rx data error */ 122 123 /* wrx_special field for VLAN packets */ 124 #define WRX_VLAN_ID(x) ((x) & 0x0fff) /* VLAN identifier */ 125 #define WRX_VLAN_CFI (1U << 12) /* Canonical Form Indicator */ 126 #define WRX_VLAN_PRI(x) (((x) >> 13) & 7)/* VLAN priority field */ 127 128 /* 129 * The Wiseman transmit descriptor. 130 * 131 * The transmit descriptor ring must be aligned to a 4K boundary, 132 * and there must be an even multiple of 8 descriptors in the ring. 133 */ 134 typedef struct wiseman_tx_fields { 135 uint8_t wtxu_status; /* Tx status */ 136 uint8_t wtxu_options; /* options */ 137 uint16_t wtxu_vlan; /* VLAN info */ 138 } __packed wiseman_txfields_t; 139 typedef struct wiseman_txdesc { 140 wiseman_addr_t wtx_addr; /* buffer address */ 141 uint32_t wtx_cmdlen; /* command and length */ 142 wiseman_txfields_t wtx_fields; /* fields; see below */ 143 } __packed wiseman_txdesc_t; 144 145 /* Commands for wtx_cmdlen */ 146 #define WTX_CMD_EOP (1U << 24) /* end of packet */ 147 #define WTX_CMD_IFCS (1U << 25) /* insert FCS */ 148 #define WTX_CMD_RS (1U << 27) /* report status */ 149 #define WTX_CMD_RPS (1U << 28) /* report packet sent */ 150 #define WTX_CMD_DEXT (1U << 29) /* descriptor extension */ 151 #define WTX_CMD_VLE (1U << 30) /* VLAN enable */ 152 #define WTX_CMD_IDE (1U << 31) /* interrupt delay enable */ 153 154 /* Descriptor types (if DEXT is set) */ 155 #define WTX_DTYP_C (0U << 20) /* context */ 156 #define WTX_DTYP_D (1U << 20) /* data */ 157 158 /* wtx_fields status bits */ 159 #define WTX_ST_DD (1U << 0) /* descriptor done */ 160 #define WTX_ST_EC (1U << 1) /* excessive collisions */ 161 #define WTX_ST_LC (1U << 2) /* late collision */ 162 #define WTX_ST_TU (1U << 3) /* transmit underrun */ 163 164 /* wtx_fields option bits for IP/TCP/UDP checksum offload */ 165 #define WTX_IXSM (1U << 0) /* IP checksum offload */ 166 #define WTX_TXSM (1U << 1) /* TCP/UDP checksum offload */ 167 168 /* Maximum payload per Tx descriptor */ 169 #define WTX_MAX_LEN 4096 170 171 /* 172 * The Livengood TCP/IP context descriptor. 173 */ 174 struct livengood_tcpip_ctxdesc { 175 uint32_t tcpip_ipcs; /* IP checksum context */ 176 uint32_t tcpip_tucs; /* TCP/UDP checksum context */ 177 uint32_t tcpip_cmdlen; 178 uint32_t tcpip_seg; /* TCP segmentation context */ 179 }; 180 181 /* commands for context descriptors */ 182 #define WTX_TCPIP_CMD_TCP (1U << 24) /* 1 = TCP, 0 = UDP */ 183 #define WTX_TCPIP_CMD_IP (1U << 25) /* 1 = IPv4, 0 = IPv6 */ 184 #define WTX_TCPIP_CMD_TSE (1U << 26) /* segmentation context valid */ 185 186 #define WTX_TCPIP_IPCSS(x) ((x) << 0) /* checksum start */ 187 #define WTX_TCPIP_IPCSO(x) ((x) << 8) /* checksum value offset */ 188 #define WTX_TCPIP_IPCSE(x) ((x) << 16) /* checksum end */ 189 190 #define WTX_TCPIP_TUCSS(x) ((x) << 0) /* checksum start */ 191 #define WTX_TCPIP_TUCSO(x) ((x) << 8) /* checksum value offset */ 192 #define WTX_TCPIP_TUCSE(x) ((x) << 16) /* checksum end */ 193 194 #define WTX_TCPIP_SEG_STATUS(x) ((x) << 0) 195 #define WTX_TCPIP_SEG_HDRLEN(x) ((x) << 8) 196 #define WTX_TCPIP_SEG_MSS(x) ((x) << 16) 197 198 /* 199 * PCI config registers used by the Wiseman. 200 */ 201 #define WM_PCI_MMBA PCI_MAPREG_START 202 /* registers for FLASH access on ICH8 */ 203 #define WM_ICH8_FLASH 0x0014 204 205 /* 206 * Wiseman Control/Status Registers. 207 */ 208 #define WMREG_CTRL 0x0000 /* Device Control Register */ 209 #define CTRL_FD (1U << 0) /* full duplex */ 210 #define CTRL_BEM (1U << 1) /* big-endian mode */ 211 #define CTRL_PRIOR (1U << 2) /* 0 = receive, 1 = fair */ 212 #define CTRL_LRST (1U << 3) /* link reset */ 213 #define CTRL_GIO_M_DIS (1U << 3) /* disabl PCI master access */ 214 #define CTRL_ASDE (1U << 5) /* auto speed detect enable */ 215 #define CTRL_SLU (1U << 6) /* set link up */ 216 #define CTRL_ILOS (1U << 7) /* invert loss of signal */ 217 #define CTRL_SPEED(x) ((x) << 8) /* speed (Livengood) */ 218 #define CTRL_SPEED_10 CTRL_SPEED(0) 219 #define CTRL_SPEED_100 CTRL_SPEED(1) 220 #define CTRL_SPEED_1000 CTRL_SPEED(2) 221 #define CTRL_SPEED_MASK CTRL_SPEED(3) 222 #define CTRL_FRCSPD (1U << 11) /* force speed (Livengood) */ 223 #define CTRL_FRCFDX (1U << 12) /* force full-duplex (Livengood) */ 224 #define CTRL_D_UD_EN (1U << 13) /* Dock/Undock enable */ 225 #define CTRL_D_UD_POL (1U << 14) /* Defined polarity of Dock/Undock indication in SDP[0] */ 226 #define CTRL_F_PHY_R (1U << 15) /* Reset both PHY ports, through PHYRST_N pin */ 227 #define CTRL_EXT_LINK_EN (1U << 16) /* enable link status from external LINK_0 and LINK_1 pins */ 228 #define CTRL_LANPHYPC_OVERRIDE (1U << 16) /* SW control of LANPHYPC */ 229 #define CTRL_LANPHYPC_VALUE (1U << 17) /* SW value of LANPHYPC */ 230 #define CTRL_SWDPINS_SHIFT 18 231 #define CTRL_SWDPINS_MASK 0x0f 232 #define CTRL_SWDPIN(x) (1U << (CTRL_SWDPINS_SHIFT + (x))) 233 #define CTRL_SWDPIO_SHIFT 22 234 #define CTRL_SWDPIO_MASK 0x0f 235 #define CTRL_SWDPIO(x) (1U << (CTRL_SWDPIO_SHIFT + (x))) 236 #define CTRL_MEHE (1U << 17) /* Memory Error Handling Enable(I217)*/ 237 #define CTRL_RST (1U << 26) /* device reset */ 238 #define CTRL_RFCE (1U << 27) /* Rx flow control enable */ 239 #define CTRL_TFCE (1U << 28) /* Tx flow control enable */ 240 #define CTRL_VME (1U << 30) /* VLAN Mode Enable */ 241 #define CTRL_PHY_RESET (1U << 31) /* PHY reset (Cordova) */ 242 243 #define WMREG_CTRL_SHADOW 0x0004 /* Device Control Register (shadow) */ 244 245 #define WMREG_STATUS 0x0008 /* Device Status Register */ 246 #define STATUS_FD (1U << 0) /* full duplex */ 247 #define STATUS_LU (1U << 1) /* link up */ 248 #define STATUS_TCKOK (1U << 2) /* Tx clock running */ 249 #define STATUS_RBCOK (1U << 3) /* Rx clock running */ 250 #define STATUS_FUNCID_SHIFT 2 /* 82546 function ID */ 251 #define STATUS_FUNCID_MASK 3 /* ... */ 252 #define STATUS_TXOFF (1U << 4) /* Tx paused */ 253 #define STATUS_TBIMODE (1U << 5) /* fiber mode (Livengood) */ 254 #define STATUS_SPEED(x) ((x) << 6) /* speed indication */ 255 #define STATUS_SPEED_10 STATUS_SPEED(0) 256 #define STATUS_SPEED_100 STATUS_SPEED(1) 257 #define STATUS_SPEED_1000 STATUS_SPEED(2) 258 #define STATUS_ASDV(x) ((x) << 8) /* auto speed det. val. (Livengood) */ 259 #define STATUS_LAN_INIT_DONE (1U << 9) /* Lan Init Completion by NVM */ 260 #define STATUS_MTXCKOK (1U << 10) /* MTXD clock running */ 261 #define STATUS_PHYRA (1U << 10) /* PHY Reset Asserted (PCH) */ 262 #define STATUS_PCI66 (1U << 11) /* 66MHz bus (Livengood) */ 263 #define STATUS_BUS64 (1U << 12) /* 64-bit bus (Livengood) */ 264 #define STATUS_PCIX_MODE (1U << 13) /* PCIX mode (Cordova) */ 265 #define STATUS_PCIXSPD(x) ((x) << 14) /* PCIX speed indication (Cordova) */ 266 #define STATUS_PCIXSPD_50_66 STATUS_PCIXSPD(0) 267 #define STATUS_PCIXSPD_66_100 STATUS_PCIXSPD(1) 268 #define STATUS_PCIXSPD_100_133 STATUS_PCIXSPD(2) 269 #define STATUS_PCIXSPD_MASK STATUS_PCIXSPD(3) 270 #define STATUS_GIO_M_ENA (1U << 19) /* GIO master enable */ 271 #define STATUS_DEV_RST_SET (1U << 20) /* Device Reset Set */ 272 273 #define WMREG_EECD 0x0010 /* EEPROM Control Register */ 274 #define EECD_SK (1U << 0) /* clock */ 275 #define EECD_CS (1U << 1) /* chip select */ 276 #define EECD_DI (1U << 2) /* data in */ 277 #define EECD_DO (1U << 3) /* data out */ 278 #define EECD_FWE(x) ((x) << 4) /* flash write enable control */ 279 #define EECD_FWE_DISABLED EECD_FWE(1) 280 #define EECD_FWE_ENABLED EECD_FWE(2) 281 #define EECD_EE_REQ (1U << 6) /* (shared) EEPROM request */ 282 #define EECD_EE_GNT (1U << 7) /* (shared) EEPROM grant */ 283 #define EECD_EE_PRES (1U << 8) /* EEPROM present */ 284 #define EECD_EE_SIZE (1U << 9) /* EEPROM size 285 (0 = 64 word, 1 = 256 word) */ 286 #define EECD_EE_AUTORD (1U << 9) /* auto read done */ 287 #define EECD_EE_ABITS (1U << 10) /* EEPROM address bits 288 (based on type) */ 289 #define EECD_EE_TYPE (1U << 13) /* EEPROM type 290 (0 = Microwire, 1 = SPI) */ 291 #define EECD_SEC1VAL (1U << 22) /* Sector One Valid */ 292 #define EECD_SEC1VAL_VALMASK (EECD_EE_AUTORD | EECD_EE_PRES) /* Valid Mask */ 293 294 #define UWIRE_OPC_ERASE 0x04 /* MicroWire "erase" opcode */ 295 #define UWIRE_OPC_WRITE 0x05 /* MicroWire "write" opcode */ 296 #define UWIRE_OPC_READ 0x06 /* MicroWire "read" opcode */ 297 298 #define SPI_OPC_WRITE 0x02 /* SPI "write" opcode */ 299 #define SPI_OPC_READ 0x03 /* SPI "read" opcode */ 300 #define SPI_OPC_A8 0x08 /* opcode bit 3 == address bit 8 */ 301 #define SPI_OPC_WREN 0x06 /* SPI "set write enable" opcode */ 302 #define SPI_OPC_WRDI 0x04 /* SPI "clear write enable" opcode */ 303 #define SPI_OPC_RDSR 0x05 /* SPI "read status" opcode */ 304 #define SPI_OPC_WRSR 0x01 /* SPI "write status" opcode */ 305 #define SPI_MAX_RETRIES 5000 /* max wait of 5ms for RDY signal */ 306 307 #define SPI_SR_RDY 0x01 308 #define SPI_SR_WEN 0x02 309 #define SPI_SR_BP0 0x04 310 #define SPI_SR_BP1 0x08 311 #define SPI_SR_WPEN 0x80 312 313 #define EEPROM_OFF_MACADDR 0x00 /* MAC address offset */ 314 #define EEPROM_OFF_CFG1 0x0a /* config word 1 */ 315 #define EEPROM_OFF_CFG2 0x0f /* config word 2 */ 316 #define EEPROM_OFF_CFG3_PORTB 0x14 /* config word 3 */ 317 #define EEPROM_INIT_3GIO_3 0x1a /* PCIe Initial Configuration Word 3 */ 318 #define EEPROM_OFF_K1_CONFIG 0x1b /* NVM K1 Config */ 319 #define EEPROM_OFF_SWDPIN 0x20 /* SWD Pins (Cordova) */ 320 #define EEPROM_OFF_CFG3_PORTA 0x24 /* config word 3 */ 321 #define EEPROM_ALT_MAC_ADDR_PTR 0x37 /* to the alternative MAC addresses */ 322 323 #define EEPROM_CFG1_LVDID (1U << 0) 324 #define EEPROM_CFG1_LSSID (1U << 1) 325 #define EEPROM_CFG1_PME_CLOCK (1U << 2) 326 #define EEPROM_CFG1_PM (1U << 3) 327 #define EEPROM_CFG1_ILOS (1U << 4) 328 #define EEPROM_CFG1_SWDPIO_SHIFT 5 329 #define EEPROM_CFG1_SWDPIO_MASK (0xf << EEPROM_CFG1_SWDPIO_SHIFT) 330 #define EEPROM_CFG1_IPS1 (1U << 8) 331 #define EEPROM_CFG1_LRST (1U << 9) 332 #define EEPROM_CFG1_FD (1U << 10) 333 #define EEPROM_CFG1_FRCSPD (1U << 11) 334 #define EEPROM_CFG1_IPS0 (1U << 12) 335 #define EEPROM_CFG1_64_32_BAR (1U << 13) 336 337 #define EEPROM_CFG2_CSR_RD_SPLIT (1U << 1) 338 #define EEPROM_CFG2_82544_APM_EN (1U << 2) 339 #define EEPROM_CFG2_64_BIT (1U << 3) 340 #define EEPROM_CFG2_MAX_READ (1U << 4) 341 #define EEPROM_CFG2_DMCR_MAP (1U << 5) 342 #define EEPROM_CFG2_133_CAP (1U << 6) 343 #define EEPROM_CFG2_MSI_DIS (1U << 7) 344 #define EEPROM_CFG2_FLASH_DIS (1U << 8) 345 #define EEPROM_CFG2_FLASH_SIZE(x) (((x) & 3) >> 9) 346 #define EEPROM_CFG2_APM_EN (1U << 10) 347 #define EEPROM_CFG2_ANE (1U << 11) 348 #define EEPROM_CFG2_PAUSE(x) (((x) & 3) >> 12) 349 #define EEPROM_CFG2_ASDE (1U << 14) 350 #define EEPROM_CFG2_APM_PME (1U << 15) 351 #define EEPROM_CFG2_SWDPIO_SHIFT 4 352 #define EEPROM_CFG2_SWDPIO_MASK (0xf << EEPROM_CFG2_SWDPIO_SHIFT) 353 #define EEPROM_CFG2_MNGM_SHIFT 13 /* Manageability Operation mode */ 354 #define EEPROM_CFG2_MNGM_MASK (3U << EEPROM_CFG2_MNGM_SHIFT) 355 #define EEPROM_CFG2_MNGM_DIS 0 356 #define EEPROM_CFG2_MNGM_NCSI 1 357 #define EEPROM_CFG2_MNGM_PT 2 358 359 #define EEPROM_K1_CONFIG_ENABLE 0x01 360 361 #define EEPROM_SWDPIN_MASK 0xdf 362 #define EEPROM_SWDPIN_SWDPIN_SHIFT 0 363 #define EEPROM_SWDPIN_SWDPIO_SHIFT 8 364 365 #define EEPROM_3GIO_3_ASPM_MASK (0x3 << 2) /* Active State PM Support */ 366 367 #define EEPROM_CFG3_APME (1U << 10) 368 369 #define EEPROM_OFF_MACADDR_LAN1 3 /* macaddr offset from PTR (port 1) */ 370 #define EEPROM_OFF_MACADDR_LAN2 6 /* macaddr offset from PTR (port 2) */ 371 #define EEPROM_OFF_MACADDR_LAN3 9 /* macaddr offset from PTR (port 3) */ 372 373 /* 374 * EEPROM Partitioning. See Table 6-1, "EEPROM Top Level Partitioning" 375 * in 82580's datasheet. 376 */ 377 #define EEPROM_OFF_LAN1 0x0080 /* Offset for LAN1 (82580)*/ 378 #define EEPROM_OFF_LAN2 0x00c0 /* Offset for LAN2 (82580)*/ 379 #define EEPROM_OFF_LAN3 0x0100 /* Offset for LAN3 (82580)*/ 380 381 #define WMREG_EERD 0x0014 /* EEPROM read */ 382 #define EERD_DONE 0x02 /* done bit */ 383 #define EERD_START 0x01 /* First bit for telling part to start operation */ 384 #define EERD_ADDR_SHIFT 2 /* Shift to the address bits */ 385 #define EERD_DATA_SHIFT 16 /* Offset to data in EEPROM read/write registers */ 386 387 #define WMREG_CTRL_EXT 0x0018 /* Extended Device Control Register */ 388 #define CTRL_EXT_GPI_EN(x) (1U << (x)) /* gpin interrupt enable */ 389 #define CTRL_EXT_SWDPINS_SHIFT 4 390 #define CTRL_EXT_SWDPINS_MASK 0x0d 391 /* The bit order of the SW Definable pin is not 6543 but 3654! */ 392 #define CTRL_EXT_SWDPIN(x) (1U << (CTRL_EXT_SWDPINS_SHIFT \ 393 + ((x) == 3 ? 3 : ((x) - 4)))) 394 #define CTRL_EXT_SWDPIO_SHIFT 8 395 #define CTRL_EXT_SWDPIO_MASK 0x0d 396 #define CTRL_EXT_SWDPIO(x) (1U << (CTRL_EXT_SWDPIO_SHIFT \ 397 + ((x) == 3 ? 3 : ((x) - 4)))) 398 #define CTRL_EXT_ASDCHK (1U << 12) /* ASD check */ 399 #define CTRL_EXT_EE_RST (1U << 13) /* EEPROM reset */ 400 #define CTRL_EXT_IPS (1U << 14) /* invert power state bit 0 */ 401 #define CTRL_EXT_SPD_BYPS (1U << 15) /* speed select bypass */ 402 #define CTRL_EXT_IPS1 (1U << 16) /* invert power state bit 1 */ 403 #define CTRL_EXT_RO_DIS (1U << 17) /* relaxed ordering disabled */ 404 #define CTRL_EXT_LINK_MODE_MASK 0x00C00000 405 #define CTRL_EXT_LINK_MODE_GMII 0x00000000 406 #define CTRL_EXT_LINK_MODE_KMRN 0x00000000 407 #define CTRL_EXT_LINK_MODE_1000KX 0x00400000 408 #define CTRL_EXT_LINK_MODE_SGMII 0x00800000 409 #define CTRL_EXT_LINK_MODE_PCIX_SERDES 0x00800000 410 #define CTRL_EXT_LINK_MODE_TBI 0x00C00000 411 #define CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 412 #define CTRL_EXT_PHYPDEN 0x00100000 413 #define CTRL_EXT_I2C_ENA 0x02000000 /* I2C enable */ 414 #define CTRL_EXT_DRV_LOAD 0x10000000 415 416 417 #define WMREG_MDIC 0x0020 /* MDI Control Register */ 418 #define MDIC_DATA(x) ((x) & 0xffff) 419 #define MDIC_REGADD(x) ((x) << 16) 420 #define MDIC_PHYADD(x) ((x) << 21) 421 #define MDIC_OP_WRITE (1U << 26) 422 #define MDIC_OP_READ (2U << 26) 423 #define MDIC_READY (1U << 28) 424 #define MDIC_I (1U << 29) /* interrupt on MDI complete */ 425 #define MDIC_E (1U << 30) /* MDI error */ 426 427 #define WMREG_SCTL 0x0024 /* SerDes Control - RW */ 428 /* 429 * These 4 macros are also used for other 8bit control registers on the 430 * 82575 431 */ 432 #define SCTL_CTL_READY (1U << 31) 433 #define SCTL_CTL_DATA_MASK 0x000000ff 434 #define SCTL_CTL_ADDR_SHIFT 8 435 #define SCTL_CTL_POLL_TIMEOUT 640 436 437 #define WMREG_FCAL 0x0028 /* Flow Control Address Low */ 438 #define FCAL_CONST 0x00c28001 /* Flow Control MAC addr low */ 439 440 #define WMREG_FCAH 0x002c /* Flow Control Address High */ 441 #define FCAH_CONST 0x00000100 /* Flow Control MAC addr high */ 442 443 #define WMREG_FCT 0x0030 /* Flow Control Type */ 444 445 #define WMREG_VET 0x0038 /* VLAN Ethertype */ 446 447 #define WMREG_RAL_BASE 0x0040 /* Receive Address List */ 448 #define WMREG_CORDOVA_RAL_BASE 0x5400 449 #define WMREG_RAL_LO(b, x) ((b) + ((x) << 3)) 450 #define WMREG_RAL_HI(b, x) (WMREG_RAL_LO(b, x) + 4) 451 /* 452 * Receive Address List: The LO part is the low-order 32-bits 453 * of the MAC address. The HI part is the high-order 16-bits 454 * along with a few control bits. 455 */ 456 #define RAL_AS(x) ((x) << 16) /* address select */ 457 #define RAL_AS_DEST RAL_AS(0) /* (cordova?) */ 458 #define RAL_AS_SOURCE RAL_AS(1) /* (cordova?) */ 459 #define RAL_RDR1 (1U << 30) /* put packet in alt. rx ring */ 460 #define RAL_AV (1U << 31) /* entry is valid */ 461 462 #define WM_RAL_TABSIZE 15 /* RAL size for old devices */ 463 #define WM_RAL_TABSIZE_ICH8 7 /* RAL size for ICH* and PCH* */ 464 #define WM_RAL_TABSIZE_82575 16 /* RAL size for 82575 */ 465 #define WM_RAL_TABSIZE_82576 24 /* RAL size for 82576 and 82580 */ 466 #define WM_RAL_TABSIZE_I350 32 /* RAL size for I350 */ 467 468 #define WMREG_ICR 0x00c0 /* Interrupt Cause Register */ 469 #define ICR_TXDW (1U << 0) /* Tx desc written back */ 470 #define ICR_TXQE (1U << 1) /* Tx queue empty */ 471 #define ICR_LSC (1U << 2) /* link status change */ 472 #define ICR_RXSEQ (1U << 3) /* receive sequence error */ 473 #define ICR_RXDMT0 (1U << 4) /* Rx ring 0 nearly empty */ 474 #define ICR_RXO (1U << 6) /* Rx overrun */ 475 #define ICR_RXT0 (1U << 7) /* Rx ring 0 timer */ 476 #define ICR_MDAC (1U << 9) /* MDIO access complete */ 477 #define ICR_RXCFG (1U << 10) /* Receiving /C/ */ 478 #define ICR_GPI(x) (1U << (x)) /* general purpose interrupts */ 479 #define ICR_INT (1U << 31) /* device generated an interrupt */ 480 481 #define WMREG_ITR 0x00c4 /* Interrupt Throttling Register */ 482 #define ITR_IVAL_MASK 0xffff /* Interval mask */ 483 #define ITR_IVAL_SHIFT 0 /* Interval shift */ 484 485 #define WMREG_ICS 0x00c8 /* Interrupt Cause Set Register */ 486 /* See ICR bits. */ 487 488 #define WMREG_IMS 0x00d0 /* Interrupt Mask Set Register */ 489 /* See ICR bits. */ 490 491 #define WMREG_IMC 0x00d8 /* Interrupt Mask Clear Register */ 492 /* See ICR bits. */ 493 494 #define WMREG_RCTL 0x0100 /* Receive Control */ 495 #define RCTL_EN (1U << 1) /* receiver enable */ 496 #define RCTL_SBP (1U << 2) /* store bad packets */ 497 #define RCTL_UPE (1U << 3) /* unicast promisc. enable */ 498 #define RCTL_MPE (1U << 4) /* multicast promisc. enable */ 499 #define RCTL_LPE (1U << 5) /* large packet enable */ 500 #define RCTL_LBM(x) ((x) << 6) /* loopback mode */ 501 #define RCTL_LBM_NONE RCTL_LBM(0) 502 #define RCTL_LBM_PHY RCTL_LBM(3) 503 #define RCTL_RDMTS(x) ((x) << 8) /* receive desc. min thresh size */ 504 #define RCTL_RDMTS_1_2 RCTL_RDMTS(0) 505 #define RCTL_RDMTS_1_4 RCTL_RDMTS(1) 506 #define RCTL_RDMTS_1_8 RCTL_RDMTS(2) 507 #define RCTL_RDMTS_MASK RCTL_RDMTS(3) 508 #define RCTL_MO(x) ((x) << 12) /* multicast offset */ 509 #define RCTL_BAM (1U << 15) /* broadcast accept mode */ 510 #define RCTL_2k (0 << 16) /* 2k Rx buffers */ 511 #define RCTL_1k (1 << 16) /* 1k Rx buffers */ 512 #define RCTL_512 (2 << 16) /* 512 byte Rx buffers */ 513 #define RCTL_256 (3 << 16) /* 256 byte Rx buffers */ 514 #define RCTL_BSEX_16k (1 << 16) /* 16k Rx buffers (BSEX) */ 515 #define RCTL_BSEX_8k (2 << 16) /* 8k Rx buffers (BSEX) */ 516 #define RCTL_BSEX_4k (3 << 16) /* 4k Rx buffers (BSEX) */ 517 #define RCTL_DPF (1U << 22) /* discard pause frames */ 518 #define RCTL_PMCF (1U << 23) /* pass MAC control frames */ 519 #define RCTL_BSEX (1U << 25) /* buffer size extension (Livengood) */ 520 #define RCTL_SECRC (1U << 26) /* strip Ethernet CRC */ 521 522 #define WMREG_OLD_RDTR0 0x0108 /* Receive Delay Timer (ring 0) */ 523 #define WMREG_RDTR 0x2820 524 #define RDTR_FPD (1U << 31) /* flush partial descriptor */ 525 526 #define WMREG_RADV 0x282c /* Receive Interrupt Absolute Delay Timer */ 527 528 #define WMREG_OLD_RDBAL0 0x0110 /* Receive Descriptor Base Low (ring 0) */ 529 #define WMREG_RDBAL 0x2800 530 #define WMREG_RDBAL_2 0x0c00 /* for 82576 ... */ 531 532 #define WMREG_OLD_RDBAH0 0x0114 /* Receive Descriptor Base High (ring 0) */ 533 #define WMREG_RDBAH 0x2804 534 #define WMREG_RDBAH_2 0x0c04 /* for 82576 ... */ 535 536 #define WMREG_OLD_RDLEN0 0x0118 /* Receive Descriptor Length (ring 0) */ 537 #define WMREG_RDLEN 0x2808 538 #define WMREG_RDLEN_2 0x0c08 /* for 82576 ... */ 539 540 #define WMREG_SRRCTL 0x280c /* additional recieve control used in 82575 ... */ 541 #define WMREG_SRRCTL_2 0x0c0c /* for 82576 ... */ 542 #define SRRCTL_BSIZEPKT_MASK 0x0000007f 543 #define SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ 544 #define SRRCTL_BSIZEHDRSIZE_MASK 0x00000f00 545 #define SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ 546 #define SRRCTL_DESCTYPE_LEGACY 0x00000000 547 #define SRRCTL_DESCTYPE_ADV_ONEBUF (1U << 25) 548 #define SRRCTL_DESCTYPE_HDR_SPLIT (2U << 25) 549 #define SRRCTL_DESCTYPE_HDR_REPLICATION (3U << 25) 550 #define SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT (4U << 25) 551 #define SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS (5U << 25) /* 82575 only */ 552 #define SRRCTL_DESCTYPE_MASK (7U << 25) 553 #define SRRCTL_DROP_EN 0x80000000 554 555 #define WMREG_OLD_RDH0 0x0120 /* Receive Descriptor Head (ring 0) */ 556 #define WMREG_RDH 0x2810 557 #define WMREG_RDH_2 0x0c10 /* for 82576 ... */ 558 559 #define WMREG_OLD_RDT0 0x0128 /* Receive Descriptor Tail (ring 0) */ 560 #define WMREG_RDT 0x2818 561 #define WMREG_RDT_2 0x0c18 /* for 82576 ... */ 562 563 #define WMREG_RXDCTL 0x2828 /* Receive Descriptor Control */ 564 #define WMREG_RXDCTL_2 0x0c28 /* for 82576 ... */ 565 #define RXDCTL_PTHRESH(x) ((x) << 0) /* prefetch threshold */ 566 #define RXDCTL_HTHRESH(x) ((x) << 8) /* host threshold */ 567 #define RXDCTL_WTHRESH(x) ((x) << 16) /* write back threshold */ 568 #define RXDCTL_GRAN (1U << 24) /* 0 = cacheline, 1 = descriptor */ 569 /* flags used starting with 82575 ... */ 570 #define RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */ 571 #define RXDCTL_SWFLSH 0x04000000 /* Rx Desc. write-back flushing */ 572 573 #define WMREG_OLD_RDTR1 0x0130 /* Receive Delay Timer (ring 1) */ 574 575 #define WMREG_OLD_RDBA1_LO 0x0138 /* Receive Descriptor Base Low (ring 1) */ 576 577 #define WMREG_OLD_RDBA1_HI 0x013c /* Receive Descriptor Base High (ring 1) */ 578 579 #define WMREG_OLD_RDLEN1 0x0140 /* Receive Drscriptor Length (ring 1) */ 580 581 #define WMREG_OLD_RDH1 0x0148 582 583 #define WMREG_OLD_RDT1 0x0150 584 585 #define WMREG_OLD_FCRTH 0x0160 /* Flow Control Rx Threshold Hi (OLD) */ 586 #define WMREG_FCRTL 0x2160 /* Flow Control Rx Threshold Lo */ 587 #define FCRTH_DFLT 0x00008000 588 589 #define WMREG_OLD_FCRTL 0x0168 /* Flow Control Rx Threshold Lo (OLD) */ 590 #define WMREG_FCRTH 0x2168 /* Flow Control Rx Threhsold Hi */ 591 #define FCRTL_DFLT 0x00004000 592 #define FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 593 594 #define WMREG_FCTTV 0x0170 /* Flow Control Transmit Timer Value */ 595 #define FCTTV_DFLT 0x00000600 596 597 #define WMREG_TXCW 0x0178 /* Transmit Configuration Word (TBI mode) */ 598 /* See MII ANAR_X bits. */ 599 #define TXCW_SYM_PAUSE (1U << 7) /* sym pause request */ 600 #define TXCW_ASYM_PAUSE (1U << 8) /* asym pause request */ 601 #define TXCW_TxConfig (1U << 30) /* Tx Config */ 602 #define TXCW_ANE (1U << 31) /* Autonegotiate */ 603 604 #define WMREG_RXCW 0x0180 /* Receive Configuration Word (TBI mode) */ 605 /* See MII ANLPAR_X bits. */ 606 #define RXCW_NC (1U << 26) /* no carrier */ 607 #define RXCW_IV (1U << 27) /* config invalid */ 608 #define RXCW_CC (1U << 28) /* config change */ 609 #define RXCW_C (1U << 29) /* /C/ reception */ 610 #define RXCW_SYNCH (1U << 30) /* synchronized */ 611 #define RXCW_ANC (1U << 31) /* autonegotiation complete */ 612 613 #define WMREG_MTA 0x0200 /* Multicast Table Array */ 614 #define WMREG_CORDOVA_MTA 0x5200 615 616 #define WMREG_TCTL 0x0400 /* Transmit Control Register */ 617 #define TCTL_EN (1U << 1) /* transmitter enable */ 618 #define TCTL_PSP (1U << 3) /* pad short packets */ 619 #define TCTL_CT(x) (((x) & 0xff) << 4) /* 4:11 - collision threshold */ 620 #define TCTL_COLD(x) (((x) & 0x3ff) << 12) /* 12:21 - collision distance */ 621 #define TCTL_SWXOFF (1U << 22) /* software XOFF */ 622 #define TCTL_RTLC (1U << 24) /* retransmit on late collision */ 623 #define TCTL_NRTU (1U << 25) /* no retransmit on underrun */ 624 #define TCTL_MULR (1U << 28) /* multiple request */ 625 626 #define TX_COLLISION_THRESHOLD 15 627 #define TX_COLLISION_DISTANCE_HDX 512 628 #define TX_COLLISION_DISTANCE_FDX 64 629 630 #define WMREG_TCTL_EXT 0x0404 /* Transmit Control Register */ 631 #define TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */ 632 #define TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */ 633 634 #define DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000 635 636 #define WMREG_TQSA_LO 0x0408 637 638 #define WMREG_TQSA_HI 0x040c 639 640 #define WMREG_TIPG 0x0410 /* Transmit IPG Register */ 641 #define TIPG_IPGT(x) (x) /* IPG transmit time */ 642 #define TIPG_IPGR1(x) ((x) << 10) /* IPG receive time 1 */ 643 #define TIPG_IPGR2(x) ((x) << 20) /* IPG receive time 2 */ 644 645 #define TIPG_WM_DFLT (TIPG_IPGT(0x0a) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x0a)) 646 #define TIPG_LG_DFLT (TIPG_IPGT(0x06) | TIPG_IPGR1(0x08) | TIPG_IPGR2(0x06)) 647 #define TIPG_1000T_DFLT (TIPG_IPGT(0x08) | TIPG_IPGR1(0x08) | TIPG_IPGR2(0x06)) 648 #define TIPG_1000T_80003_DFLT \ 649 (TIPG_IPGT(0x08) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x07)) 650 #define TIPG_10_100_80003_DFLT \ 651 (TIPG_IPGT(0x09) | TIPG_IPGR1(0x02) | TIPG_IPGR2(0x07)) 652 653 #define WMREG_TQC 0x0418 654 655 #define WMREG_EEWR 0x102c /* EEPROM write */ 656 657 #define WMREG_RDFH 0x2410 /* Receive Data FIFO Head */ 658 659 #define WMREG_RDFT 0x2418 /* Receive Data FIFO Tail */ 660 661 #define WMREG_RDFHS 0x2420 /* Receive Data FIFO Head Saved */ 662 663 #define WMREG_RDFTS 0x2428 /* Receive Data FIFO Tail Saved */ 664 665 #define WMREG_TDFH 0x3410 /* Transmit Data FIFO Head */ 666 667 #define WMREG_TDFT 0x3418 /* Transmit Data FIFO Tail */ 668 669 #define WMREG_TDFHS 0x3420 /* Transmit Data FIFO Head Saved */ 670 671 #define WMREG_TDFTS 0x3428 /* Transmit Data FIFO Tail Saved */ 672 673 #define WMREG_TDFPC 0x3430 /* Transmit Data FIFO Packet Count */ 674 675 #define WMREG_OLD_TDBAL 0x0420 /* Transmit Descriptor Base Lo */ 676 #define WMREG_TDBAL 0x3800 677 678 #define WMREG_OLD_TDBAH 0x0424 /* Transmit Descriptor Base Hi */ 679 #define WMREG_TDBAH 0x3804 680 681 #define WMREG_OLD_TDLEN 0x0428 /* Transmit Descriptor Length */ 682 #define WMREG_TDLEN 0x3808 683 684 #define WMREG_OLD_TDH 0x0430 /* Transmit Descriptor Head */ 685 #define WMREG_TDH 0x3810 686 687 #define WMREG_OLD_TDT 0x0438 /* Transmit Descriptor Tail */ 688 #define WMREG_TDT 0x3818 689 690 #define WMREG_OLD_TIDV 0x0440 /* Transmit Delay Interrupt Value */ 691 #define WMREG_TIDV 0x3820 692 693 #define WMREG_TXDCTL 0x3828 /* Trandmit Descriptor Control */ 694 #define TXDCTL_PTHRESH(x) ((x) << 0) /* prefetch threshold */ 695 #define TXDCTL_HTHRESH(x) ((x) << 8) /* host threshold */ 696 #define TXDCTL_WTHRESH(x) ((x) << 16) /* write back threshold */ 697 /* flags used starting with 82575 ... */ 698 #define TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */ 699 #define TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */ 700 #define TXDCTL_PRIORITY 0x08000000 701 702 #define WMREG_TADV 0x382c /* Transmit Absolute Interrupt Delay Timer */ 703 704 #define WMREG_AIT 0x0458 /* Adaptive IFS Throttle */ 705 706 #define WMREG_VFTA 0x0600 707 708 #define WM_MC_TABSIZE 128 709 #define WM_ICH8_MC_TABSIZE 32 710 #define WM_VLAN_TABSIZE 128 711 712 #define WMREG_PBA 0x1000 /* Packet Buffer Allocation */ 713 #define PBA_BYTE_SHIFT 10 /* KB -> bytes */ 714 #define PBA_ADDR_SHIFT 7 /* KB -> quadwords */ 715 #define PBA_8K 0x0008 716 #define PBA_10K 0x000a 717 #define PBA_12K 0x000c 718 #define PBA_16K 0x0010 /* 16K, default Tx allocation */ 719 #define PBA_20K 0x0014 720 #define PBA_22K 0x0016 721 #define PBA_24K 0x0018 722 #define PBA_26K 0x001a 723 #define PBA_30K 0x001e 724 #define PBA_32K 0x0020 725 #define PBA_34K 0x0022 726 #define PBA_35K 0x0023 727 #define PBA_40K 0x0028 728 #define PBA_48K 0x0030 /* 48K, default Rx allocation */ 729 #define PBA_64K 0x0040 730 731 #define WMREG_PBS 0x1008 /* Packet Buffer Size (ICH) */ 732 733 #define WMREG_PBECCSTS 0x100c /* Packet Buffer ECC Status (PCH_LPT) */ 734 #define PBECCSTS_CORR_ERR_CNT_MASK 0x000000ff 735 #define PBECCSTS_UNCORR_ERR_CNT_MASK 0x0000ff00 736 #define PBECCSTS_UNCORR_ECC_ENABLE 0x00010000 737 738 #define WMREG_EEMNGCTL 0x1010 /* MNG EEprom Control */ 739 #define EEMNGCTL_CFGDONE_0 0x040000 /* MNG config cycle done */ 740 #define EEMNGCTL_CFGDONE_1 0x080000 /* 2nd port */ 741 742 #define WMREG_I2CCMD 0x1028 /* SFPI2C Command Register - RW */ 743 #define I2CCMD_REG_ADDR_SHIFT 16 744 #define I2CCMD_REG_ADDR 0x00ff0000 745 #define I2CCMD_PHY_ADDR_SHIFT 24 746 #define I2CCMD_PHY_ADDR 0x07000000 747 #define I2CCMD_OPCODE_READ 0x08000000 748 #define I2CCMD_OPCODE_WRITE 0x00000000 749 #define I2CCMD_RESET 0x10000000 750 #define I2CCMD_READY 0x20000000 751 #define I2CCMD_INTERRUPT_ENA 0x40000000 752 #define I2CCMD_ERROR 0x80000000 753 #define MAX_SGMII_PHY_REG_ADDR 255 754 #define I2CCMD_PHY_TIMEOUT 200 755 756 #define WMREG_PBA_ECC 0x01100 /* PBA ECC */ 757 #define PBA_ECC_COUNTER_MASK 0xfff00000 /* ECC counter mask */ 758 #define PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */ 759 #define PBA_ECC_CORR_EN 0x00000001 /* Enable ECC error correction */ 760 #define PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */ 761 #define PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 on ECC error */ 762 763 #define WMREG_EICS 0x01520 /* Ext. Interrupt Cause Set - WO */ 764 #define WMREG_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */ 765 #define WMREG_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */ 766 #define WMREG_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */ 767 #define WMREG_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */ 768 769 #define WMREG_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */ 770 771 #define EITR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */ 772 #define EITR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */ 773 #define EITR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */ 774 #define EITR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */ 775 #define EITR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */ 776 #define EITR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */ 777 #define EITR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */ 778 #define EITR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */ 779 #define EITR_TCP_TIMER 0x40000000 /* TCP Timer */ 780 #define EITR_OTHER 0x80000000 /* Interrupt Cause Active */ 781 782 #define WMREG_EITR(x) (0x01680 + (0x4 * (x))) 783 #define EITR_ITR_INT_MASK 0x0000ffff 784 785 #define WMREG_TXDMAC 0x3000 /* Transfer DMA Control */ 786 #define TXDMAC_DPP (1U << 0) /* disable packet prefetch */ 787 788 #define WMREG_KABGTXD 0x3004 /* AFE and Gap Transmit Ref Data */ 789 #define KABGTXD_BGSQLBIAS 0x00050000 790 791 #define WMREG_TSPMT 0x3830 /* TCP Segmentation Pad and Minimum 792 Threshold (Cordova) */ 793 794 #define WMREG_TARC0 0x3840 /* Tx arbitration count */ 795 796 #define TSPMT_TSMT(x) (x) /* TCP seg min transfer */ 797 #define TSPMT_TSPBP(x) ((x) << 16) /* TCP seg pkt buf padding */ 798 799 #define WMREG_CRCERRS 0x4000 /* CRC Error Count */ 800 #define WMREG_ALGNERRC 0x4004 /* Alignment Error Count */ 801 #define WMREG_SYMERRC 0x4008 /* Symbol Error Count */ 802 #define WMREG_RXERRC 0x400c /* receive error Count - R/clr */ 803 #define WMREG_MPC 0x4010 /* Missed Packets Count - R/clr */ 804 #define WMREG_COLC 0x4028 /* collision Count - R/clr */ 805 #define WMREG_SEC 0x4038 /* Sequence Error Count */ 806 #define WMREG_CEXTERR 0x403c /* Carrier Extension Error Count */ 807 #define WMREG_RLEC 0x4040 /* Receive Length Error Count */ 808 #define WMREG_XONRXC 0x4048 /* XON Rx Count - R/clr */ 809 #define WMREG_XONTXC 0x404c /* XON Tx Count - R/clr */ 810 #define WMREG_XOFFRXC 0x4050 /* XOFF Rx Count - R/clr */ 811 #define WMREG_XOFFTXC 0x4054 /* XOFF Tx Count - R/clr */ 812 #define WMREG_FCRUC 0x4058 /* Flow Control Rx Unsupported Count - R/clr */ 813 #define WMREG_RNBC 0x40a0 /* Receive No Buffers Count */ 814 815 #define WMREG_KUMCTRLSTA 0x0034 /* MAC-PHY interface - RW */ 816 #define KUMCTRLSTA_MASK 0x0000FFFF 817 #define KUMCTRLSTA_OFFSET 0x001F0000 818 #define KUMCTRLSTA_OFFSET_SHIFT 16 819 #define KUMCTRLSTA_REN 0x00200000 820 821 #define KUMCTRLSTA_OFFSET_FIFO_CTRL 0x00000000 822 #define KUMCTRLSTA_OFFSET_CTRL 0x00000001 823 #define KUMCTRLSTA_OFFSET_INB_CTRL 0x00000002 824 #define KUMCTRLSTA_OFFSET_DIAG 0x00000003 825 #define KUMCTRLSTA_OFFSET_TIMEOUTS 0x00000004 826 #define KUMCTRLSTA_OFFSET_K1_CONFIG 0x00000007 827 #define KUMCTRLSTA_OFFSET_INB_PARAM 0x00000009 828 #define KUMCTRLSTA_OFFSET_HD_CTRL 0x00000010 829 #define KUMCTRLSTA_OFFSET_M2P_SERDES 0x0000001E 830 #define KUMCTRLSTA_OFFSET_M2P_MODES 0x0000001F 831 832 /* FIFO Control */ 833 #define KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 0x00000008 834 #define KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800 835 836 /* In-Band Control */ 837 #define KUMCTRLSTA_INB_CTRL_LINK_TMOUT_DFLT 0x00000500 838 #define KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010 839 840 /* Diag */ 841 #define KUMCTRLSTA_DIAG_NELPBK 0x1000 842 843 /* K1 Config */ 844 #define KUMCTRLSTA_K1_ENABLE 0x0002 845 846 /* Half-Duplex Control */ 847 #define KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004 848 #define KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000 849 850 #define WMREG_MDPHYA 0x003C /* PHY address - RW */ 851 852 #define WMREG_RXCSUM 0x5000 /* Receive Checksum register */ 853 #define RXCSUM_PCSS 0x000000ff /* Packet Checksum Start */ 854 #define RXCSUM_IPOFL (1U << 8) /* IP checksum offload */ 855 #define RXCSUM_TUOFL (1U << 9) /* TCP/UDP checksum offload */ 856 #define RXCSUM_IPV6OFL (1U << 10) /* IPv6 checksum offload */ 857 858 #define WMREG_RLPML 0x5004 /* Rx Long Packet Max Length */ 859 860 #define WMREG_WUC 0x5800 /* Wakeup Control */ 861 #define WUC_APME 0x00000001 /* APM Enable */ 862 #define WUC_PME_EN 0x00000002 /* PME Enable */ 863 864 #define WMREG_WUFC 0x5808 /* Wakeup Filter COntrol */ 865 #define WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 866 #define WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 867 #define WUFC_MC 0x00000008 /* Directed Multicast Wakeup En */ 868 #define WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 869 #define WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup En */ 870 #define WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup En */ 871 #define WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup En */ 872 873 #define WMREG_MANC 0x5820 /* Management Control */ 874 #define MANC_SMBUS_EN 0x00000001 875 #define MANC_ASF_EN 0x00000002 876 #define MANC_ARP_EN 0x00002000 877 #define MANC_RECV_TCO_RESET 0x00010000 878 #define MANC_RECV_TCO_EN 0x00020000 879 #define MANC_BLK_PHY_RST_ON_IDE 0x00040000 880 #define MANC_RECV_ALL 0x00080000 881 #define MANC_EN_MAC_ADDR_FILTER 0x00100000 882 #define MANC_EN_MNG2HOST 0x00200000 883 884 #define WMREG_MANC2H 0x5860 /* Manaegment Control To Host - RW */ 885 #define MANC2H_PORT_623 (1 << 5) 886 #define MANC2H_PORT_624 (1 << 6) 887 888 #define WMREG_GCR 0x5b00 /* PCIe Control */ 889 #define GCR_RXD_NO_SNOOP 0x00000001 890 #define GCR_RXDSCW_NO_SNOOP 0x00000002 891 #define GCR_RXDSCR_NO_SNOOP 0x00000004 892 #define GCR_TXD_NO_SNOOP 0x00000008 893 #define GCR_TXDSCW_NO_SNOOP 0x00000010 894 #define GCR_TXDSCR_NO_SNOOP 0x00000020 895 #define GCR_CMPL_TMOUT_MASK 0x0000f000 896 #define GCR_CMPL_TMOUT_10MS 0x00001000 897 #define GCR_CMPL_TMOUT_RESEND 0x00010000 898 #define GCR_CAP_VER2 0x00040000 899 900 #define WMREG_FACTPS 0x5b30 /* Function Active and Power State to MNG */ 901 #define FACTPS_MNGCG 0x20000000 902 #define FACTPS_LFS 0x40000000 /* LAN Function Select */ 903 904 #define WMREG_GIOCTL 0x5b44 /* GIO Analog Control Register */ 905 #define WMREG_CCMCTL 0x5b48 /* CCM Control Register */ 906 #define WMREG_SCCTL 0x5b4c /* PCIc PLL Configuration Register */ 907 908 #define WMREG_SWSM 0x5b50 /* SW Semaphore */ 909 #define SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 910 #define SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 911 #define SWSM_WMNG 0x00000004 /* Wake MNG Clock */ 912 #define SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ 913 914 #define WMREG_FWSM 0x5b54 /* FW Semaphore */ 915 #define FWSM_MODE_MASK 0xe 916 #define FWSM_MODE_SHIFT 0x1 917 #define MNG_ICH_IAMT_MODE 0x2 /* PT mode? */ 918 #define MNG_IAMT_MODE 0x3 919 #define FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */ 920 #define FWSM_FW_VALID 0x00008000 /* FW established a valid mode */ 921 922 #define WMREG_SW_FW_SYNC 0x5b5c /* software-firmware semaphore */ 923 #define SWFW_EEP_SM 0x0001 /* eeprom access */ 924 #define SWFW_PHY0_SM 0x0002 /* first ctrl phy access */ 925 #define SWFW_PHY1_SM 0x0004 /* second ctrl phy access */ 926 #define SWFW_MAC_CSR_SM 0x0008 927 #define SWFW_PHY2_SM 0x0020 /* first ctrl phy access */ 928 #define SWFW_PHY3_SM 0x0040 /* first ctrl phy access */ 929 #define SWFW_SOFT_SHIFT 0 /* software semaphores */ 930 #define SWFW_FIRM_SHIFT 16 /* firmware semaphores */ 931 932 #define WMREG_CRC_OFFSET 0x5f50 933 934 #define WMREG_EXTCNFCTR 0x0f00 /* Extended Configuration Control */ 935 #define EXTCNFCTR_PCIE_WRITE_ENABLE 0x00000001 936 #define EXTCNFCTR_PHY_WRITE_ENABLE 0x00000002 937 #define EXTCNFCTR_D_UD_ENABLE 0x00000004 938 #define EXTCNFCTR_D_UD_LATENCY 0x00000008 939 #define EXTCNFCTR_D_UD_OWNER 0x00000010 940 #define EXTCNFCTR_MDIO_SW_OWNERSHIP 0x00000020 941 #define EXTCNFCTR_MDIO_HW_OWNERSHIP 0x00000040 942 #define EXTCNFCTR_GATE_PHY_CFG 0x00000080 943 #define EXTCNFCTR_EXT_CNF_POINTER 0x0FFF0000 944 #define E1000_EXTCNF_CTRL_SWFLAG EXTCNFCTR_MDIO_SW_OWNERSHIP 945 946 #define WMREG_PHY_CTRL 0x0f10 /* PHY control */ 947 #define PHY_CTRL_SPD_EN (1 << 0) 948 #define PHY_CTRL_D0A_LPLU (1 << 1) 949 #define PHY_CTRL_NOND0A_LPLU (1 << 2) 950 #define PHY_CTRL_NOND0A_GBE_DIS (1 << 3) 951 #define PHY_CTRL_GBE_DIS (1 << 4) 952 953 /* Energy Efficient Ethernet "EEE" registers */ 954 #define WMREG_LTRC 0x01a0 /* Latency Tolerance Reportiong Control */ 955 #define WMREG_EEER 0x0e30 /* Energy Efficiency Ethernet "EEE" */ 956 #define EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */ 957 #define EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */ 958 #define EEER_LPI_FC 0x00040000 /* EEER Ena on Flow Cntrl */ 959 #define EEER_EEER_NEG 0x20000000 /* EEER capability nego */ 960 #define EEER_EEER_RX_LPI_STATUS 0x40000000 /* EEER Rx in LPI state */ 961 #define EEER_EEER_TX_LPI_STATUS 0x80000000 /* EEER Tx in LPI state */ 962 #define WMREG_EEE_SU 0x0e34 /* EEE Setup */ 963 #define WMREG_IPCNFG 0x0e38 /* Internal PHY Configuration */ 964 #define IPCNFG_EEE_100M_AN 0x00000004 /* IPCNFG EEE Ena 100M AN */ 965 #define IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Ena 1G AN */ 966 #define WMREG_TLPIC 0x4148 /* EEE Tx LPI Count */ 967 #define WMREG_RLPIC 0x414c /* EEE Rx LPI Count */ 968 969 /* ich8 flash control */ 970 #define ICH_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */ 971 #define ICH_FLASH_ERASE_TIMEOUT 3000000 /* Up to 3 seconds - worst case */ 972 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles */ 973 #define ICH_FLASH_SEG_SIZE_256 256 974 #define ICH_FLASH_SEG_SIZE_4K 4096 975 #define ICH_FLASH_SEG_SIZE_64K 65536 976 977 #define ICH_CYCLE_READ 0x0 978 #define ICH_CYCLE_RESERVED 0x1 979 #define ICH_CYCLE_WRITE 0x2 980 #define ICH_CYCLE_ERASE 0x3 981 982 #define ICH_FLASH_GFPREG 0x0000 983 #define ICH_FLASH_HSFSTS 0x0004 /* Flash Status Register */ 984 #define HSFSTS_DONE 0x0001 /* Flash Cycle Done */ 985 #define HSFSTS_ERR 0x0002 /* Flash Cycle Error */ 986 #define HSFSTS_DAEL 0x0004 /* Direct Access error Log */ 987 #define HSFSTS_ERSZ_MASK 0x0018 /* Block/Sector Erase Size */ 988 #define HSFSTS_ERSZ_SHIFT 3 989 #define HSFSTS_FLINPRO 0x0020 /* flash SPI cycle in Progress */ 990 #define HSFSTS_FLDVAL 0x4000 /* Flash Descriptor Valid */ 991 #define HSFSTS_FLLK 0x8000 /* Flash Configuration Lock-Down */ 992 #define ICH_FLASH_HSFCTL 0x0006 /* Flash control Register */ 993 #define HSFCTL_GO 0x0001 /* Flash Cycle Go */ 994 #define HSFCTL_CYCLE_MASK 0x0006 /* Flash Cycle */ 995 #define HSFCTL_CYCLE_SHIFT 1 996 #define HSFCTL_BCOUNT_MASK 0x0300 /* Data Byte Count */ 997 #define HSFCTL_BCOUNT_SHIFT 8 998 #define ICH_FLASH_FADDR 0x0008 999 #define ICH_FLASH_FDATA0 0x0010 1000 #define ICH_FLASH_FRACC 0x0050 1001 #define ICH_FLASH_FREG0 0x0054 1002 #define ICH_FLASH_FREG1 0x0058 1003 #define ICH_FLASH_FREG2 0x005C 1004 #define ICH_FLASH_FREG3 0x0060 1005 #define ICH_FLASH_FPR0 0x0074 1006 #define ICH_FLASH_FPR1 0x0078 1007 #define ICH_FLASH_SSFSTS 0x0090 1008 #define ICH_FLASH_SSFCTL 0x0092 1009 #define ICH_FLASH_PREOP 0x0094 1010 #define ICH_FLASH_OPTYPE 0x0096 1011 #define ICH_FLASH_OPMENU 0x0098 1012 1013 #define ICH_FLASH_REG_MAPSIZE 0x00A0 1014 #define ICH_FLASH_SECTOR_SIZE 4096 1015 #define ICH_GFPREG_BASE_MASK 0x1FFF 1016 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF 1017 1018 #define ICH_NVM_SIG_WORD 0x13 1019 #define ICH_NVM_SIG_MASK 0xc000 1020 #define ICH_NVM_VALID_SIG_MASK 0xc0 1021 #define ICH_NVM_SIG_VALUE 0x80 1022 1023 /* for PCI express Capability registers */ 1024 #define WM_PCIE_DCSR2_16MS 0x00000005 1025 1026 /* advanced TX descriptor for 82575 and newer */ 1027 typedef union nq_txdesc { 1028 struct { 1029 uint64_t nqtxd_addr; 1030 uint32_t nqtxd_cmdlen; 1031 uint32_t nqtxd_fields; 1032 } nqtx_data; 1033 struct { 1034 uint32_t nqtxc_vl_len; 1035 uint32_t nqtxc_sn; 1036 uint32_t nqtxc_cmd; 1037 uint32_t nqtxc_mssidx; 1038 } nqrx_ctx; 1039 } __packed nq_txdesc_t; 1040 1041 1042 /* Commands for nqtxd_cmdlen and nqtxc_cmd */ 1043 #define NQTX_CMD_EOP (1U << 24) /* end of packet */ 1044 #define NQTX_CMD_IFCS (1U << 25) /* insert FCS */ 1045 #define NQTX_CMD_RS (1U << 27) /* report status */ 1046 #define NQTX_CMD_DEXT (1U << 29) /* descriptor extension */ 1047 #define NQTX_CMD_VLE (1U << 30) /* VLAN enable */ 1048 #define NQTX_CMD_TSE (1U << 31) /* TCP segmentation enable */ 1049 1050 /* Descriptor types (if DEXT is set) */ 1051 #define NQTX_DTYP_C (2U << 20) /* context */ 1052 #define NQTX_DTYP_D (3U << 20) /* data */ 1053 1054 #define NQTXD_FIELDS_IDX_SHIFT 4 /* context index shift */ 1055 #define NQTXD_FIELDS_IDX_MASK 0xf 1056 #define NQTXD_FIELDS_PAYLEN_SHIFT 14 /* payload len shift */ 1057 #define NQTXD_FIELDS_PAYLEN_MASK 0x3ffff 1058 1059 #define NQTXD_FIELDS_IXSM (1U << 8) /* do IP checksum */ 1060 #define NQTXD_FIELDS_TUXSM (1U << 9) /* do TCP/UDP checksum */ 1061 1062 #define NQTXC_VLLEN_IPLEN_SHIFT 0 /* IP header len */ 1063 #define NQTXC_VLLEN_IPLEN_MASK 0x1ff 1064 #define NQTXC_VLLEN_MACLEN_SHIFT 9 /* MAC header len */ 1065 #define NQTXC_VLLEN_MACLEN_MASK 0x7f 1066 #define NQTXC_VLLEN_VLAN_SHIFT 16 /* vlan number */ 1067 #define NQTXC_VLLEN_VLAN_MASK 0xffff 1068 1069 #define NQTXC_CMD_MKRLOC_SHIFT 0 /* IP checksum offset */ 1070 #define NQTXC_CMD_MKRLOC_MASK 0x1ff 1071 #define NQTXC_CMD_SNAP (1U << 9) 1072 #define NQTXC_CMD_IP4 (1U << 10) 1073 #define NQTXC_CMD_IP6 (0U << 10) 1074 #define NQTXC_CMD_TCP (1U << 11) 1075 #define NQTXC_CMD_UDP (0U << 11) 1076 #define NQTXC_MSSIDX_IDX_SHIFT 4 /* context index shift */ 1077 #define NQTXC_MSSIDX_IDX_MASK 0xf 1078 #define NQTXC_MSSIDX_L4LEN_SHIFT 8 /* L4 header len shift */ 1079 #define NQTXC_MSSIDX_L4LEN_MASK 0xff 1080 #define NQTXC_MSSIDX_MSS_SHIFT 16 /* MSS */ 1081 #define NQTXC_MSSIDX_MSS_MASK 0xffff 1082