1 /* $NetBSD: if_wi_pci.c,v 1.40 2006/10/12 01:31:30 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Hideaki Imaizumi <hiddy@sfc.wide.ad.jp> 9 * and Ichiro FUKUHARA (ichiro@ichiro.org). 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * PCI bus front-end for the Intersil PCI WaveLan. 42 * Works with Prism2.5 Mini-PCI wavelan. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: if_wi_pci.c,v 1.40 2006/10/12 01:31:30 christos Exp $"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/mbuf.h> 51 #include <sys/syslog.h> 52 #include <sys/socket.h> 53 #include <sys/device.h> 54 #include <sys/callout.h> 55 56 #include <net/if.h> 57 #include <net/if_ether.h> 58 #include <net/if_media.h> 59 60 #include <net80211/ieee80211_netbsd.h> 61 #include <net80211/ieee80211_var.h> 62 #include <net80211/ieee80211_radiotap.h> 63 #include <net80211/ieee80211_rssadapt.h> 64 65 #include <machine/bus.h> 66 #include <machine/intr.h> 67 68 #include <dev/pci/pcireg.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/pcidevs.h> 71 72 #include <dev/ic/wi_ieee.h> 73 #include <dev/ic/wireg.h> 74 #include <dev/ic/wivar.h> 75 76 #define WI_PCI_CBMA 0x10 /* Configuration Base Memory Address */ 77 #define WI_PCI_PLX_LOMEM 0x10 /* PLX chip membase */ 78 #define WI_PCI_PLX_LOIO 0x14 /* PLX chip iobase */ 79 #define WI_PCI_LOMEM 0x18 /* ISA membase */ 80 #define WI_PCI_LOIO 0x1C /* ISA iobase */ 81 82 #define CHIP_PLX_OTHER 0x01 83 #define CHIP_PLX_9052 0x02 84 #define CHIP_TMD_7160 0x03 85 86 #define WI_PLX_COR_OFFSET 0x3E0 87 #define WI_PLX_COR_VALUE 0x41 88 89 struct wi_pci_softc { 90 struct wi_softc psc_wi; /* real "wi" softc */ 91 92 /* PCI-specific goo */ 93 pci_intr_handle_t psc_ih; 94 pci_chipset_tag_t psc_pc; 95 96 void *sc_powerhook; /* power hook descriptor */ 97 }; 98 99 static int wi_pci_match(struct device *, struct cfdata *, void *); 100 static void wi_pci_attach(struct device *, struct device *, void *); 101 static int wi_pci_enable(struct wi_softc *); 102 static void wi_pci_disable(struct wi_softc *); 103 static void wi_pci_reset(struct wi_softc *); 104 static void wi_pci_powerhook(int, void *); 105 106 static const struct wi_pci_product 107 *wi_pci_lookup(struct pci_attach_args *); 108 109 CFATTACH_DECL(wi_pci, sizeof(struct wi_pci_softc), 110 wi_pci_match, wi_pci_attach, NULL, NULL); 111 112 static const struct wi_pci_product { 113 pci_vendor_id_t wpp_vendor; /* vendor ID */ 114 pci_product_id_t wpp_product; /* product ID */ 115 int wpp_chip; /* uses other chip */ 116 } wi_pci_products[] = { 117 { PCI_VENDOR_GLOBALSUN, PCI_PRODUCT_GLOBALSUN_GL24110P, 118 CHIP_PLX_OTHER }, 119 { PCI_VENDOR_GLOBALSUN, PCI_PRODUCT_GLOBALSUN_GL24110P02, 120 CHIP_PLX_OTHER }, 121 { PCI_VENDOR_EUMITCOM, PCI_PRODUCT_EUMITCOM_WL11000P, 122 CHIP_PLX_OTHER }, 123 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CRWE777A, 124 CHIP_PLX_OTHER }, 125 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_MA301, 126 CHIP_PLX_OTHER }, 127 { PCI_VENDOR_INTERSIL, PCI_PRODUCT_INTERSIL_MINI_PCI_WLAN, 128 0 }, 129 { PCI_VENDOR_NDC, PCI_PRODUCT_NDC_NCP130, 130 CHIP_PLX_9052 }, 131 { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_2415, 132 CHIP_PLX_OTHER }, 133 { PCI_VENDOR_NDC, PCI_PRODUCT_NDC_NCP130A2, 134 CHIP_TMD_7160 }, 135 { 0, 0, 136 0}, 137 }; 138 139 static int 140 wi_pci_enable(struct wi_softc *sc) 141 { 142 struct wi_pci_softc *psc = (struct wi_pci_softc *)sc; 143 144 /* establish the interrupt. */ 145 sc->sc_ih = pci_intr_establish(psc->psc_pc, 146 psc->psc_ih, IPL_NET, wi_intr, sc); 147 if (sc->sc_ih == NULL) { 148 printf("%s: couldn't establish interrupt\n", 149 sc->sc_dev.dv_xname); 150 return (EIO); 151 } 152 153 /* reset HFA3842 MAC core */ 154 if (sc->sc_reset != NULL) 155 wi_pci_reset(sc); 156 157 return (0); 158 } 159 160 static void 161 wi_pci_disable(struct wi_softc *sc) 162 { 163 struct wi_pci_softc *psc = (struct wi_pci_softc *)sc; 164 165 pci_intr_disestablish(psc->psc_pc, sc->sc_ih); 166 } 167 168 static void 169 wi_pci_reset(struct wi_softc *sc) 170 { 171 int i, secs, usecs; 172 173 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 174 WI_PCI_COR, WI_COR_SOFT_RESET); 175 DELAY(250*1000); /* 1/4 second */ 176 177 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 178 WI_PCI_COR, WI_COR_CLEAR); 179 DELAY(500*1000); /* 1/2 second */ 180 181 /* wait 2 seconds for firmware to complete initialization. */ 182 183 for (i = 200000; i--; DELAY(10)) 184 if (!(CSR_READ_2(sc, WI_COMMAND) & WI_CMD_BUSY)) 185 break; 186 187 if (i < 0) { 188 printf("%s: PCI reset timed out\n", sc->sc_dev.dv_xname); 189 } else if (sc->sc_if.if_flags & IFF_DEBUG) { 190 usecs = (200000 - i) * 10; 191 secs = usecs / 1000000; 192 usecs %= 1000000; 193 194 printf("%s: PCI reset in %d.%06d seconds\n", 195 sc->sc_dev.dv_xname, secs, usecs); 196 } 197 198 return; 199 } 200 201 static const struct wi_pci_product * 202 wi_pci_lookup(struct pci_attach_args *pa) 203 { 204 const struct wi_pci_product *wpp; 205 206 for (wpp = wi_pci_products; wpp->wpp_vendor != 0; wpp++) { 207 if (PCI_VENDOR(pa->pa_id) == wpp->wpp_vendor && 208 PCI_PRODUCT(pa->pa_id) == wpp->wpp_product) 209 return (wpp); 210 } 211 return (NULL); 212 } 213 214 static int 215 wi_pci_match(struct device *parent __unused, struct cfdata *match __unused, 216 void *aux) 217 { 218 struct pci_attach_args *pa = aux; 219 220 if (wi_pci_lookup(pa) != NULL) 221 return (1); 222 return (0); 223 } 224 225 static void 226 wi_pci_attach(struct device *parent __unused, struct device *self, void *aux) 227 { 228 struct wi_pci_softc *psc = (struct wi_pci_softc *)self; 229 struct wi_softc *sc = &psc->psc_wi; 230 struct pci_attach_args *pa = aux; 231 pci_chipset_tag_t pc = pa->pa_pc; 232 const char *intrstr; 233 const struct wi_pci_product *wpp; 234 pci_intr_handle_t ih; 235 bus_space_tag_t memt, iot, plxt, tmdt; 236 bus_space_handle_t memh, ioh, plxh, tmdh; 237 238 psc->psc_pc = pc; 239 240 wpp = wi_pci_lookup(pa); 241 #ifdef DIAGNOSTIC 242 if (wpp == NULL) { 243 printf("\n"); 244 panic("wi_pci_attach: impossible"); 245 } 246 #endif 247 248 switch (wpp->wpp_chip) { 249 case CHIP_PLX_OTHER: 250 case CHIP_PLX_9052: 251 /* Map memory and I/O registers. */ 252 if (pci_mapreg_map(pa, WI_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 253 &memt, &memh, NULL, NULL) != 0) { 254 printf(": can't map mem space\n"); 255 return; 256 } 257 if (pci_mapreg_map(pa, WI_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 258 &iot, &ioh, NULL, NULL) != 0) { 259 printf(": can't map I/O space\n"); 260 return; 261 } 262 263 if (wpp->wpp_chip == CHIP_PLX_OTHER) { 264 /* The PLX 9052 doesn't have IO at 0x14. Perhaps 265 other chips have, so we'll make this conditional. */ 266 if (pci_mapreg_map(pa, WI_PCI_PLX_LOIO, 267 PCI_MAPREG_TYPE_IO, 0, &plxt, 268 &plxh, NULL, NULL) != 0) { 269 printf(": can't map PLX\n"); 270 return; 271 } 272 } 273 break; 274 case CHIP_TMD_7160: 275 /* Used instead of PLX on at least one revision of 276 * the National Datacomm Corporation NCP130. Values 277 * for registers acquired from OpenBSD, which in 278 * turn got them from a Linux driver. 279 */ 280 /* Map COR and I/O registers. */ 281 if (pci_mapreg_map(pa, WI_TMD_COR, PCI_MAPREG_TYPE_IO, 0, 282 &tmdt, &tmdh, NULL, NULL) != 0) { 283 printf(": can't map TMD\n"); 284 return; 285 } 286 if (pci_mapreg_map(pa, WI_TMD_IO, PCI_MAPREG_TYPE_IO, 0, 287 &iot, &ioh, NULL, NULL) != 0) { 288 printf(": can't map I/O space\n"); 289 return; 290 } 291 break; 292 default: 293 if (pci_mapreg_map(pa, WI_PCI_CBMA, 294 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 295 0, &iot, &ioh, NULL, NULL) != 0) { 296 printf(": can't map mem space\n"); 297 return; 298 } 299 300 memt = iot; 301 memh = ioh; 302 sc->sc_pci = 1; 303 break; 304 } 305 306 { 307 char devinfo[256]; 308 309 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 310 printf(": %s (rev. 0x%02x)\n", devinfo, 311 PCI_REVISION(pa->pa_class)); 312 } 313 314 sc->sc_enabled = 1; 315 sc->sc_enable = wi_pci_enable; 316 sc->sc_disable = wi_pci_disable; 317 318 sc->sc_iot = iot; 319 sc->sc_ioh = ioh; 320 /* Make sure interrupts are disabled. */ 321 CSR_WRITE_2(sc, WI_INT_EN, 0); 322 CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF); 323 324 if (wpp->wpp_chip == CHIP_PLX_OTHER) { 325 uint32_t command; 326 #define WI_LOCAL_INTCSR 0x4c 327 #define WI_LOCAL_INTEN 0x40 /* poke this into INTCSR */ 328 329 command = bus_space_read_4(plxt, plxh, WI_LOCAL_INTCSR); 330 command |= WI_LOCAL_INTEN; 331 bus_space_write_4(plxt, plxh, WI_LOCAL_INTCSR, command); 332 } 333 334 /* Map and establish the interrupt. */ 335 if (pci_intr_map(pa, &ih)) { 336 printf("%s: couldn't map interrupt\n", self->dv_xname); 337 return; 338 } 339 intrstr = pci_intr_string(pc, ih); 340 341 psc->psc_ih = ih; 342 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wi_intr, sc); 343 if (sc->sc_ih == NULL) { 344 printf("%s: couldn't establish interrupt", self->dv_xname); 345 if (intrstr != NULL) 346 printf(" at %s", intrstr); 347 printf("\n"); 348 return; 349 } 350 351 printf("%s: interrupting at %s\n", self->dv_xname, intrstr); 352 353 switch (wpp->wpp_chip) { 354 case CHIP_PLX_OTHER: 355 case CHIP_PLX_9052: 356 /* 357 * Setup the PLX chip for level interrupts and config index 1 358 * XXX - should really reset the PLX chip too. 359 */ 360 bus_space_write_1(memt, memh, 361 WI_PLX_COR_OFFSET, WI_PLX_COR_VALUE); 362 break; 363 case CHIP_TMD_7160: 364 /* Enable I/O mode and level interrupts on the embedded 365 * card. The card's COR is the first byte of BAR 0. 366 */ 367 bus_space_write_1(tmdt, tmdh, 0, WI_COR_IOMODE); 368 break; 369 default: 370 /* reset HFA3842 MAC core */ 371 wi_pci_reset(sc); 372 break; 373 } 374 375 printf("%s:", self->dv_xname); 376 377 if (wi_attach(sc, 0) != 0) { 378 printf("%s: failed to attach controller\n", self->dv_xname); 379 pci_intr_disestablish(pa->pa_pc, sc->sc_ih); 380 return; 381 } 382 383 if (!wpp->wpp_chip) 384 sc->sc_reset = wi_pci_reset; 385 386 /* Add a suspend hook to restore PCI config state */ 387 psc->sc_powerhook = powerhook_establish(self->dv_xname, 388 wi_pci_powerhook, psc); 389 if (psc->sc_powerhook == NULL) 390 printf("%s: WARNING: unable to establish pci power hook\n", 391 self->dv_xname); 392 } 393 394 static void 395 wi_pci_powerhook(int why, void *arg) 396 { 397 struct wi_pci_softc *psc = arg; 398 struct wi_softc *sc = &psc->psc_wi; 399 400 wi_power(sc, why); 401 } 402