1 /* $NetBSD: if_wi_pci.c,v 1.44 2008/04/10 19:13:37 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Hideaki Imaizumi <hiddy@sfc.wide.ad.jp> 9 * and Ichiro FUKUHARA (ichiro@ichiro.org). 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * PCI bus front-end for the Intersil PCI WaveLan. 42 * Works with Prism2.5 Mini-PCI wavelan. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: if_wi_pci.c,v 1.44 2008/04/10 19:13:37 cegger Exp $"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/mbuf.h> 51 #include <sys/syslog.h> 52 #include <sys/socket.h> 53 #include <sys/device.h> 54 #include <sys/callout.h> 55 56 #include <net/if.h> 57 #include <net/if_ether.h> 58 #include <net/if_media.h> 59 60 #include <net80211/ieee80211_netbsd.h> 61 #include <net80211/ieee80211_var.h> 62 #include <net80211/ieee80211_radiotap.h> 63 #include <net80211/ieee80211_rssadapt.h> 64 65 #include <sys/bus.h> 66 #include <sys/intr.h> 67 68 #include <dev/pci/pcireg.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/pcidevs.h> 71 72 #include <dev/ic/wi_ieee.h> 73 #include <dev/ic/wireg.h> 74 #include <dev/ic/wivar.h> 75 76 #define WI_PCI_CBMA 0x10 /* Configuration Base Memory Address */ 77 #define WI_PCI_PLX_LOMEM 0x10 /* PLX chip membase */ 78 #define WI_PCI_PLX_LOIO 0x14 /* PLX chip iobase */ 79 #define WI_PCI_LOMEM 0x18 /* ISA membase */ 80 #define WI_PCI_LOIO 0x1C /* ISA iobase */ 81 82 #define CHIP_PLX_OTHER 0x01 83 #define CHIP_PLX_9052 0x02 84 #define CHIP_TMD_7160 0x03 85 86 #define WI_PLX_COR_OFFSET 0x3E0 87 #define WI_PLX_COR_VALUE 0x41 88 89 struct wi_pci_softc { 90 struct wi_softc psc_wi; /* real "wi" softc */ 91 92 /* PCI-specific goo */ 93 pci_intr_handle_t psc_ih; 94 pci_chipset_tag_t psc_pc; 95 pcitag_t psc_pcitag; 96 }; 97 98 static int wi_pci_match(struct device *, struct cfdata *, void *); 99 static void wi_pci_attach(struct device *, struct device *, void *); 100 static int wi_pci_enable(struct wi_softc *); 101 static void wi_pci_disable(struct wi_softc *); 102 static void wi_pci_reset(struct wi_softc *); 103 104 static const struct wi_pci_product 105 *wi_pci_lookup(struct pci_attach_args *); 106 107 CFATTACH_DECL(wi_pci, sizeof(struct wi_pci_softc), 108 wi_pci_match, wi_pci_attach, NULL, NULL); 109 110 static const struct wi_pci_product { 111 pci_vendor_id_t wpp_vendor; /* vendor ID */ 112 pci_product_id_t wpp_product; /* product ID */ 113 int wpp_chip; /* uses other chip */ 114 } wi_pci_products[] = { 115 { PCI_VENDOR_GLOBALSUN, PCI_PRODUCT_GLOBALSUN_GL24110P, 116 CHIP_PLX_OTHER }, 117 { PCI_VENDOR_GLOBALSUN, PCI_PRODUCT_GLOBALSUN_GL24110P02, 118 CHIP_PLX_OTHER }, 119 { PCI_VENDOR_EUMITCOM, PCI_PRODUCT_EUMITCOM_WL11000P, 120 CHIP_PLX_OTHER }, 121 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CRWE777A, 122 CHIP_PLX_OTHER }, 123 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_MA301, 124 CHIP_PLX_OTHER }, 125 { PCI_VENDOR_INTERSIL, PCI_PRODUCT_INTERSIL_MINI_PCI_WLAN, 126 0 }, 127 { PCI_VENDOR_NDC, PCI_PRODUCT_NDC_NCP130, 128 CHIP_PLX_9052 }, 129 { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_2415, 130 CHIP_PLX_OTHER }, 131 { PCI_VENDOR_NDC, PCI_PRODUCT_NDC_NCP130A2, 132 CHIP_TMD_7160 }, 133 { 0, 0, 134 0}, 135 }; 136 137 static int 138 wi_pci_enable(struct wi_softc *sc) 139 { 140 struct wi_pci_softc *psc = (struct wi_pci_softc *)sc; 141 142 /* establish the interrupt. */ 143 sc->sc_ih = pci_intr_establish(psc->psc_pc, 144 psc->psc_ih, IPL_NET, wi_intr, sc); 145 if (sc->sc_ih == NULL) { 146 aprint_error_dev(&sc->sc_dev, "couldn't establish interrupt\n"); 147 return (EIO); 148 } 149 150 /* reset HFA3842 MAC core */ 151 if (sc->sc_reset != NULL) 152 wi_pci_reset(sc); 153 154 return (0); 155 } 156 157 static void 158 wi_pci_disable(struct wi_softc *sc) 159 { 160 struct wi_pci_softc *psc = (struct wi_pci_softc *)sc; 161 162 pci_intr_disestablish(psc->psc_pc, sc->sc_ih); 163 } 164 165 static void 166 wi_pci_reset(struct wi_softc *sc) 167 { 168 int i, secs, usecs; 169 170 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 171 WI_PCI_COR, WI_COR_SOFT_RESET); 172 DELAY(250*1000); /* 1/4 second */ 173 174 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 175 WI_PCI_COR, WI_COR_CLEAR); 176 DELAY(500*1000); /* 1/2 second */ 177 178 /* wait 2 seconds for firmware to complete initialization. */ 179 180 for (i = 200000; i--; DELAY(10)) 181 if (!(CSR_READ_2(sc, WI_COMMAND) & WI_CMD_BUSY)) 182 break; 183 184 if (i < 0) { 185 printf("%s: PCI reset timed out\n", device_xname(&sc->sc_dev)); 186 } else if (sc->sc_if.if_flags & IFF_DEBUG) { 187 usecs = (200000 - i) * 10; 188 secs = usecs / 1000000; 189 usecs %= 1000000; 190 191 printf("%s: PCI reset in %d.%06d seconds\n", 192 device_xname(&sc->sc_dev), secs, usecs); 193 } 194 195 return; 196 } 197 198 static const struct wi_pci_product * 199 wi_pci_lookup(struct pci_attach_args *pa) 200 { 201 const struct wi_pci_product *wpp; 202 203 for (wpp = wi_pci_products; wpp->wpp_vendor != 0; wpp++) { 204 if (PCI_VENDOR(pa->pa_id) == wpp->wpp_vendor && 205 PCI_PRODUCT(pa->pa_id) == wpp->wpp_product) 206 return (wpp); 207 } 208 return (NULL); 209 } 210 211 static int 212 wi_pci_match(struct device *parent, struct cfdata *match, 213 void *aux) 214 { 215 struct pci_attach_args *pa = aux; 216 217 if (wi_pci_lookup(pa) != NULL) 218 return (1); 219 return (0); 220 } 221 222 static void 223 wi_pci_attach(struct device *parent, struct device *self, void *aux) 224 { 225 struct wi_pci_softc *psc = (struct wi_pci_softc *)self; 226 struct wi_softc *sc = &psc->psc_wi; 227 struct pci_attach_args *pa = aux; 228 pci_chipset_tag_t pc = pa->pa_pc; 229 const char *intrstr; 230 const struct wi_pci_product *wpp; 231 pci_intr_handle_t ih; 232 bus_space_tag_t memt, iot, plxt, tmdt; 233 bus_space_handle_t memh, ioh, plxh, tmdh; 234 235 psc->psc_pc = pc; 236 psc->psc_pcitag = pa->pa_tag; 237 238 wpp = wi_pci_lookup(pa); 239 #ifdef DIAGNOSTIC 240 if (wpp == NULL) { 241 printf("\n"); 242 panic("wi_pci_attach: impossible"); 243 } 244 #endif 245 246 switch (wpp->wpp_chip) { 247 case CHIP_PLX_OTHER: 248 case CHIP_PLX_9052: 249 /* Map memory and I/O registers. */ 250 if (pci_mapreg_map(pa, WI_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 251 &memt, &memh, NULL, NULL) != 0) { 252 printf(": can't map mem space\n"); 253 return; 254 } 255 if (pci_mapreg_map(pa, WI_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 256 &iot, &ioh, NULL, NULL) != 0) { 257 printf(": can't map I/O space\n"); 258 return; 259 } 260 261 if (wpp->wpp_chip == CHIP_PLX_OTHER) { 262 /* The PLX 9052 doesn't have IO at 0x14. Perhaps 263 other chips have, so we'll make this conditional. */ 264 if (pci_mapreg_map(pa, WI_PCI_PLX_LOIO, 265 PCI_MAPREG_TYPE_IO, 0, &plxt, 266 &plxh, NULL, NULL) != 0) { 267 printf(": can't map PLX\n"); 268 return; 269 } 270 } 271 break; 272 case CHIP_TMD_7160: 273 /* Used instead of PLX on at least one revision of 274 * the National Datacomm Corporation NCP130. Values 275 * for registers acquired from OpenBSD, which in 276 * turn got them from a Linux driver. 277 */ 278 /* Map COR and I/O registers. */ 279 if (pci_mapreg_map(pa, WI_TMD_COR, PCI_MAPREG_TYPE_IO, 0, 280 &tmdt, &tmdh, NULL, NULL) != 0) { 281 printf(": can't map TMD\n"); 282 return; 283 } 284 if (pci_mapreg_map(pa, WI_TMD_IO, PCI_MAPREG_TYPE_IO, 0, 285 &iot, &ioh, NULL, NULL) != 0) { 286 printf(": can't map I/O space\n"); 287 return; 288 } 289 break; 290 default: 291 if (pci_mapreg_map(pa, WI_PCI_CBMA, 292 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 293 0, &iot, &ioh, NULL, NULL) != 0) { 294 printf(": can't map mem space\n"); 295 return; 296 } 297 298 memt = iot; 299 memh = ioh; 300 sc->sc_pci = 1; 301 break; 302 } 303 304 { 305 char devinfo[256]; 306 307 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 308 printf(": %s (rev. 0x%02x)\n", devinfo, 309 PCI_REVISION(pa->pa_class)); 310 } 311 312 sc->sc_enabled = 1; 313 sc->sc_enable = wi_pci_enable; 314 sc->sc_disable = wi_pci_disable; 315 316 sc->sc_iot = iot; 317 sc->sc_ioh = ioh; 318 /* Make sure interrupts are disabled. */ 319 CSR_WRITE_2(sc, WI_INT_EN, 0); 320 CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF); 321 322 if (wpp->wpp_chip == CHIP_PLX_OTHER) { 323 uint32_t command; 324 #define WI_LOCAL_INTCSR 0x4c 325 #define WI_LOCAL_INTEN 0x40 /* poke this into INTCSR */ 326 327 command = bus_space_read_4(plxt, plxh, WI_LOCAL_INTCSR); 328 command |= WI_LOCAL_INTEN; 329 bus_space_write_4(plxt, plxh, WI_LOCAL_INTCSR, command); 330 } 331 332 /* Map and establish the interrupt. */ 333 if (pci_intr_map(pa, &ih)) { 334 aprint_error_dev(self, "couldn't map interrupt\n"); 335 return; 336 } 337 intrstr = pci_intr_string(pc, ih); 338 339 psc->psc_ih = ih; 340 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wi_intr, sc); 341 if (sc->sc_ih == NULL) { 342 aprint_error_dev(self, "couldn't establish interrupt"); 343 if (intrstr != NULL) 344 printf(" at %s", intrstr); 345 printf("\n"); 346 return; 347 } 348 349 printf("%s: interrupting at %s\n", device_xname(self), intrstr); 350 351 switch (wpp->wpp_chip) { 352 case CHIP_PLX_OTHER: 353 case CHIP_PLX_9052: 354 /* 355 * Setup the PLX chip for level interrupts and config index 1 356 * XXX - should really reset the PLX chip too. 357 */ 358 bus_space_write_1(memt, memh, 359 WI_PLX_COR_OFFSET, WI_PLX_COR_VALUE); 360 break; 361 case CHIP_TMD_7160: 362 /* Enable I/O mode and level interrupts on the embedded 363 * card. The card's COR is the first byte of BAR 0. 364 */ 365 bus_space_write_1(tmdt, tmdh, 0, WI_COR_IOMODE); 366 break; 367 default: 368 /* reset HFA3842 MAC core */ 369 wi_pci_reset(sc); 370 break; 371 } 372 373 printf("%s:", device_xname(self)); 374 375 if (wi_attach(sc, 0) != 0) { 376 aprint_error_dev(self, "failed to attach controller\n"); 377 pci_intr_disestablish(pa->pa_pc, sc->sc_ih); 378 return; 379 } 380 381 if (!wpp->wpp_chip) 382 sc->sc_reset = wi_pci_reset; 383 384 if (!pmf_device_register(self, NULL, NULL)) 385 aprint_error_dev(self, "couldn't establish power handler\n"); 386 else 387 pmf_class_network_register(self, &sc->sc_if); 388 } 389