1 /* $NetBSD: if_vte.c,v 1.32 2021/08/30 20:09:22 andvar Exp $ */ 2 3 /* 4 * Copyright (c) 2011 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 2010, Pyun YongHyeon <yongari@FreeBSD.org> 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 1. Redistributions of source code must retain the above copyright 35 * notice unmodified, this list of conditions, and the following 36 * disclaimer. 37 * 2. Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in the 39 * documentation and/or other materials provided with the distribution. 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 51 * SUCH DAMAGE. 52 */ 53 /* FreeBSD: src/sys/dev/vte/if_vte.c,v 1.2 2010/12/31 01:23:04 yongari Exp */ 54 55 /* Driver for DM&P Electronics, Inc, Vortex86 RDC R6040 FastEthernet. */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: if_vte.c,v 1.32 2021/08/30 20:09:22 andvar Exp $"); 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/mbuf.h> 63 #include <sys/protosw.h> 64 #include <sys/socket.h> 65 #include <sys/ioctl.h> 66 #include <sys/errno.h> 67 #include <sys/malloc.h> 68 #include <sys/kernel.h> 69 #include <sys/device.h> 70 #include <sys/sysctl.h> 71 72 #include <net/if.h> 73 #include <net/if_media.h> 74 #include <net/if_types.h> 75 #include <net/if_dl.h> 76 #include <net/route.h> 77 #include <net/netisr.h> 78 #include <net/bpf.h> 79 80 #include <sys/rndsource.h> 81 82 #include "opt_inet.h" 83 #include <net/if_ether.h> 84 #ifdef INET 85 #include <netinet/in.h> 86 #include <netinet/in_systm.h> 87 #include <netinet/in_var.h> 88 #include <netinet/ip.h> 89 #include <netinet/if_inarp.h> 90 #endif 91 92 #include <sys/bus.h> 93 #include <sys/intr.h> 94 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pcidevs.h> 98 99 #include <dev/mii/mii.h> 100 #include <dev/mii/miivar.h> 101 102 #include <dev/pci/if_vtereg.h> 103 #include <dev/pci/if_vtevar.h> 104 105 static int vte_match(device_t, cfdata_t, void *); 106 static void vte_attach(device_t, device_t, void *); 107 static int vte_detach(device_t, int); 108 static int vte_dma_alloc(struct vte_softc *); 109 static void vte_dma_free(struct vte_softc *); 110 static struct vte_txdesc * 111 vte_encap(struct vte_softc *, struct mbuf **); 112 static void vte_get_macaddr(struct vte_softc *); 113 static int vte_init(struct ifnet *); 114 static int vte_init_rx_ring(struct vte_softc *); 115 static int vte_init_tx_ring(struct vte_softc *); 116 static int vte_intr(void *); 117 static int vte_ifioctl(struct ifnet *, u_long, void *); 118 static void vte_mac_config(struct vte_softc *); 119 static int vte_miibus_readreg(device_t, int, int, uint16_t *); 120 static void vte_miibus_statchg(struct ifnet *); 121 static int vte_miibus_writereg(device_t, int, int, uint16_t); 122 static int vte_mediachange(struct ifnet *); 123 static int vte_newbuf(struct vte_softc *, struct vte_rxdesc *); 124 static void vte_reset(struct vte_softc *); 125 static void vte_rxeof(struct vte_softc *); 126 static void vte_rxfilter(struct vte_softc *); 127 static bool vte_shutdown(device_t, int); 128 static bool vte_suspend(device_t, const pmf_qual_t *); 129 static bool vte_resume(device_t, const pmf_qual_t *); 130 static void vte_ifstart(struct ifnet *); 131 static void vte_start_mac(struct vte_softc *); 132 static void vte_stats_clear(struct vte_softc *); 133 static void vte_stats_update(struct vte_softc *); 134 static void vte_stop(struct ifnet *, int); 135 static void vte_stop_mac(struct vte_softc *); 136 static void vte_tick(void *); 137 static void vte_txeof(struct vte_softc *); 138 static void vte_ifwatchdog(struct ifnet *); 139 140 static int vte_sysctl_intrxct(SYSCTLFN_PROTO); 141 static int vte_sysctl_inttxct(SYSCTLFN_PROTO); 142 static int vte_root_num; 143 144 #define DPRINTF(a) 145 146 CFATTACH_DECL3_NEW(vte, sizeof(struct vte_softc), 147 vte_match, vte_attach, vte_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN); 148 149 150 static int 151 vte_match(device_t parent, cfdata_t cf, void *aux) 152 { 153 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 154 155 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_RDC && 156 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_RDC_R6040) 157 return 1; 158 159 return 0; 160 } 161 162 static void 163 vte_attach(device_t parent, device_t self, void *aux) 164 { 165 struct vte_softc *sc = device_private(self); 166 struct pci_attach_args * const pa = (struct pci_attach_args *)aux; 167 struct ifnet * const ifp = &sc->vte_if; 168 struct mii_data * const mii = &sc->vte_mii; 169 int h_valid; 170 pcireg_t reg, csr; 171 pci_intr_handle_t intrhandle; 172 const char *intrstr; 173 int error; 174 const struct sysctlnode *node; 175 int vte_nodenum; 176 char intrbuf[PCI_INTRSTR_LEN]; 177 178 sc->vte_dev = self; 179 180 callout_init(&sc->vte_tick_ch, 0); 181 callout_setfunc(&sc->vte_tick_ch, vte_tick, sc); 182 183 /* Map the device. */ 184 h_valid = 0; 185 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, VTE_PCI_BMEM); 186 if (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_MEM) { 187 h_valid = (pci_mapreg_map(pa, VTE_PCI_BMEM, 188 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 189 0, &sc->vte_bustag, &sc->vte_bushandle, NULL, NULL) == 0); 190 } 191 if (h_valid == 0) { 192 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, VTE_PCI_BIO); 193 if (PCI_MAPREG_TYPE(reg) == PCI_MAPREG_TYPE_IO) { 194 h_valid = (pci_mapreg_map(pa, VTE_PCI_BIO, 195 PCI_MAPREG_TYPE_IO, 0, &sc->vte_bustag, 196 &sc->vte_bushandle, NULL, NULL) == 0); 197 } 198 } 199 if (h_valid == 0) { 200 aprint_error_dev(self, "unable to map device registers\n"); 201 return; 202 } 203 sc->vte_dmatag = pa->pa_dmat; 204 /* Enable the device. */ 205 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 206 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 207 csr | PCI_COMMAND_MASTER_ENABLE); 208 209 pci_aprint_devinfo(pa, NULL); 210 211 /* Reset the ethernet controller. */ 212 vte_reset(sc); 213 214 if ((error = vte_dma_alloc(sc)) != 0) 215 return; 216 217 /* Load station address. */ 218 vte_get_macaddr(sc); 219 220 aprint_normal_dev(self, "Ethernet address %s\n", 221 ether_sprintf(sc->vte_eaddr)); 222 223 /* Map and establish interrupts */ 224 if (pci_intr_map(pa, &intrhandle)) { 225 aprint_error_dev(self, "couldn't map interrupt\n"); 226 return; 227 } 228 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, 229 sizeof(intrbuf)); 230 sc->vte_ih = pci_intr_establish_xname(pa->pa_pc, intrhandle, IPL_NET, 231 vte_intr, sc, device_xname(self)); 232 if (sc->vte_ih == NULL) { 233 aprint_error_dev(self, "couldn't establish interrupt"); 234 if (intrstr != NULL) 235 aprint_error(" at %s", intrstr); 236 aprint_error("\n"); 237 return; 238 } 239 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 240 241 sc->vte_if.if_softc = sc; 242 mii->mii_ifp = ifp; 243 mii->mii_readreg = vte_miibus_readreg; 244 mii->mii_writereg = vte_miibus_writereg; 245 mii->mii_statchg = vte_miibus_statchg; 246 sc->vte_ec.ec_mii = mii; 247 ifmedia_init(&mii->mii_media, IFM_IMASK, vte_mediachange, 248 ether_mediastatus); 249 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, 250 MII_OFFSET_ANY, 0); 251 if (LIST_FIRST(&mii->mii_phys) == NULL) { 252 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 253 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 254 } else 255 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 256 257 /* 258 * We can support 802.1Q VLAN-sized frames. 259 */ 260 sc->vte_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 261 262 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 263 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 264 ifp->if_ioctl = vte_ifioctl; 265 ifp->if_start = vte_ifstart; 266 ifp->if_watchdog = vte_ifwatchdog; 267 ifp->if_init = vte_init; 268 ifp->if_stop = vte_stop; 269 ifp->if_timer = 0; 270 IFQ_SET_READY(&ifp->if_snd); 271 if_attach(ifp); 272 if_deferred_start_init(ifp, NULL); 273 ether_ifattach(&(sc)->vte_if, (sc)->vte_eaddr); 274 275 if (pmf_device_register1(self, vte_suspend, vte_resume, vte_shutdown)) 276 pmf_class_network_register(self, ifp); 277 else 278 aprint_error_dev(self, "couldn't establish power handler\n"); 279 280 rnd_attach_source(&sc->rnd_source, device_xname(self), 281 RND_TYPE_NET, RND_FLAG_DEFAULT); 282 283 if (sysctl_createv(&sc->vte_clog, 0, NULL, &node, 284 0, CTLTYPE_NODE, device_xname(sc->vte_dev), 285 SYSCTL_DESCR("vte per-controller controls"), 286 NULL, 0, NULL, 0, CTL_HW, vte_root_num, CTL_CREATE, 287 CTL_EOL) != 0) { 288 aprint_normal_dev(sc->vte_dev, "couldn't create sysctl node\n"); 289 return; 290 } 291 vte_nodenum = node->sysctl_num; 292 if (sysctl_createv(&sc->vte_clog, 0, NULL, &node, 293 CTLFLAG_READWRITE, 294 CTLTYPE_INT, "int_rxct", 295 SYSCTL_DESCR("vte RX interrupt moderation packet counter"), 296 vte_sysctl_intrxct, 0, (void *)sc, 297 0, CTL_HW, vte_root_num, vte_nodenum, CTL_CREATE, 298 CTL_EOL) != 0) { 299 aprint_normal_dev(sc->vte_dev, 300 "couldn't create int_rxct sysctl node\n"); 301 } 302 if (sysctl_createv(&sc->vte_clog, 0, NULL, &node, 303 CTLFLAG_READWRITE, 304 CTLTYPE_INT, "int_txct", 305 SYSCTL_DESCR("vte TX interrupt moderation packet counter"), 306 vte_sysctl_inttxct, 0, (void *)sc, 307 0, CTL_HW, vte_root_num, vte_nodenum, CTL_CREATE, 308 CTL_EOL) != 0) { 309 aprint_normal_dev(sc->vte_dev, 310 "couldn't create int_txct sysctl node\n"); 311 } 312 } 313 314 static int 315 vte_detach(device_t dev, int flags __unused) 316 { 317 struct vte_softc *sc = device_private(dev); 318 struct ifnet *ifp = &sc->vte_if; 319 int s; 320 321 s = splnet(); 322 /* Stop the interface. Callouts are stopped in it. */ 323 vte_stop(ifp, 1); 324 splx(s); 325 326 pmf_device_deregister(dev); 327 328 mii_detach(&sc->vte_mii, MII_PHY_ANY, MII_OFFSET_ANY); 329 330 ether_ifdetach(ifp); 331 if_detach(ifp); 332 ifmedia_fini(&sc->vte_mii.mii_media); 333 334 vte_dma_free(sc); 335 336 return (0); 337 } 338 339 static int 340 vte_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 341 { 342 struct vte_softc *sc = device_private(dev); 343 int i; 344 345 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_READ | 346 (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT)); 347 for (i = VTE_PHY_TIMEOUT; i > 0; i--) { 348 DELAY(5); 349 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_READ) == 0) 350 break; 351 } 352 353 if (i == 0) { 354 aprint_error_dev(sc->vte_dev, "phy read timeout : %d\n", reg); 355 return ETIMEDOUT; 356 } 357 358 *val = CSR_READ_2(sc, VTE_MMRD); 359 return 0; 360 } 361 362 static int 363 vte_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 364 { 365 struct vte_softc *sc = device_private(dev); 366 int i; 367 368 CSR_WRITE_2(sc, VTE_MMWD, val); 369 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE | 370 (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT)); 371 for (i = VTE_PHY_TIMEOUT; i > 0; i--) { 372 DELAY(5); 373 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_WRITE) == 0) 374 break; 375 } 376 377 if (i == 0) { 378 aprint_error_dev(sc->vte_dev, "phy write timeout : %d\n", reg); 379 return ETIMEDOUT; 380 } 381 382 return 0; 383 } 384 385 static void 386 vte_miibus_statchg(struct ifnet *ifp) 387 { 388 struct vte_softc *sc = ifp->if_softc; 389 uint16_t val; 390 391 DPRINTF(("vte_miibus_statchg 0x%x 0x%x\n", 392 sc->vte_mii.mii_media_status, sc->vte_mii.mii_media_active)); 393 394 sc->vte_flags &= ~VTE_FLAG_LINK; 395 if ((sc->vte_mii.mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 396 (IFM_ACTIVE | IFM_AVALID)) { 397 switch (IFM_SUBTYPE(sc->vte_mii.mii_media_active)) { 398 case IFM_10_T: 399 case IFM_100_TX: 400 sc->vte_flags |= VTE_FLAG_LINK; 401 break; 402 default: 403 break; 404 } 405 } 406 407 /* Stop RX/TX MACs. */ 408 vte_stop_mac(sc); 409 /* Program MACs with resolved duplex and flow control. */ 410 if ((sc->vte_flags & VTE_FLAG_LINK) != 0) { 411 /* 412 * Timer waiting time : (63 + TIMER * 64) MII clock. 413 * MII clock : 25MHz(100Mbps) or 2.5MHz(10Mbps). 414 */ 415 if (IFM_SUBTYPE(sc->vte_mii.mii_media_active) == IFM_100_TX) 416 val = 18 << VTE_IM_TIMER_SHIFT; 417 else 418 val = 1 << VTE_IM_TIMER_SHIFT; 419 val |= sc->vte_int_rx_mod << VTE_IM_BUNDLE_SHIFT; 420 /* 48.6us for 100Mbps, 50.8us for 10Mbps */ 421 CSR_WRITE_2(sc, VTE_MRICR, val); 422 423 if (IFM_SUBTYPE(sc->vte_mii.mii_media_active) == IFM_100_TX) 424 val = 18 << VTE_IM_TIMER_SHIFT; 425 else 426 val = 1 << VTE_IM_TIMER_SHIFT; 427 val |= sc->vte_int_tx_mod << VTE_IM_BUNDLE_SHIFT; 428 /* 48.6us for 100Mbps, 50.8us for 10Mbps */ 429 CSR_WRITE_2(sc, VTE_MTICR, val); 430 431 vte_mac_config(sc); 432 vte_start_mac(sc); 433 DPRINTF(("vte_miibus_statchg: link\n")); 434 } 435 } 436 437 static void 438 vte_get_macaddr(struct vte_softc *sc) 439 { 440 uint16_t mid; 441 442 /* 443 * It seems there is no way to reload station address and 444 * it is supposed to be set by BIOS. 445 */ 446 mid = CSR_READ_2(sc, VTE_MID0L); 447 sc->vte_eaddr[0] = (mid >> 0) & 0xFF; 448 sc->vte_eaddr[1] = (mid >> 8) & 0xFF; 449 mid = CSR_READ_2(sc, VTE_MID0M); 450 sc->vte_eaddr[2] = (mid >> 0) & 0xFF; 451 sc->vte_eaddr[3] = (mid >> 8) & 0xFF; 452 mid = CSR_READ_2(sc, VTE_MID0H); 453 sc->vte_eaddr[4] = (mid >> 0) & 0xFF; 454 sc->vte_eaddr[5] = (mid >> 8) & 0xFF; 455 } 456 457 458 static int 459 vte_dma_alloc(struct vte_softc *sc) 460 { 461 struct vte_txdesc *txd; 462 struct vte_rxdesc *rxd; 463 int error, i, rseg; 464 465 /* create DMA map for TX ring */ 466 error = bus_dmamap_create(sc->vte_dmatag, VTE_TX_RING_SZ, 1, 467 VTE_TX_RING_SZ, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 468 &sc->vte_cdata.vte_tx_ring_map); 469 if (error) { 470 aprint_error_dev(sc->vte_dev, 471 "could not create dma map for TX ring (%d)\n", 472 error); 473 goto fail; 474 } 475 /* Allocate and map DMA'able memory and load the DMA map for TX ring. */ 476 error = bus_dmamem_alloc(sc->vte_dmatag, VTE_TX_RING_SZ, 477 VTE_TX_RING_ALIGN, 0, 478 sc->vte_cdata.vte_tx_ring_seg, 1, &rseg, 479 BUS_DMA_NOWAIT); 480 if (error != 0) { 481 aprint_error_dev(sc->vte_dev, 482 "could not allocate DMA'able memory for TX ring (%d).\n", 483 error); 484 goto fail; 485 } 486 KASSERT(rseg == 1); 487 error = bus_dmamem_map(sc->vte_dmatag, 488 sc->vte_cdata.vte_tx_ring_seg, 1, 489 VTE_TX_RING_SZ, (void **)(&sc->vte_cdata.vte_tx_ring), 490 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 491 if (error != 0) { 492 aprint_error_dev(sc->vte_dev, 493 "could not map DMA'able memory for TX ring (%d).\n", 494 error); 495 goto fail; 496 } 497 memset(sc->vte_cdata.vte_tx_ring, 0, VTE_TX_RING_SZ); 498 error = bus_dmamap_load(sc->vte_dmatag, 499 sc->vte_cdata.vte_tx_ring_map, sc->vte_cdata.vte_tx_ring, 500 VTE_TX_RING_SZ, NULL, 501 BUS_DMA_NOWAIT | BUS_DMA_READ | BUS_DMA_WRITE); 502 if (error != 0) { 503 aprint_error_dev(sc->vte_dev, 504 "could not load DMA'able memory for TX ring.\n"); 505 goto fail; 506 } 507 508 /* create DMA map for RX ring */ 509 error = bus_dmamap_create(sc->vte_dmatag, VTE_RX_RING_SZ, 1, 510 VTE_RX_RING_SZ, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 511 &sc->vte_cdata.vte_rx_ring_map); 512 if (error) { 513 aprint_error_dev(sc->vte_dev, 514 "could not create dma map for RX ring (%d)\n", 515 error); 516 goto fail; 517 } 518 /* Allocate and map DMA'able memory and load the DMA map for RX ring. */ 519 error = bus_dmamem_alloc(sc->vte_dmatag, VTE_RX_RING_SZ, 520 VTE_RX_RING_ALIGN, 0, 521 sc->vte_cdata.vte_rx_ring_seg, 1, &rseg, 522 BUS_DMA_NOWAIT); 523 if (error != 0) { 524 aprint_error_dev(sc->vte_dev, 525 "could not allocate DMA'able memory for RX ring (%d).\n", 526 error); 527 goto fail; 528 } 529 KASSERT(rseg == 1); 530 error = bus_dmamem_map(sc->vte_dmatag, 531 sc->vte_cdata.vte_rx_ring_seg, 1, 532 VTE_RX_RING_SZ, (void **)(&sc->vte_cdata.vte_rx_ring), 533 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 534 if (error != 0) { 535 aprint_error_dev(sc->vte_dev, 536 "could not map DMA'able memory for RX ring (%d).\n", 537 error); 538 goto fail; 539 } 540 memset(sc->vte_cdata.vte_rx_ring, 0, VTE_RX_RING_SZ); 541 error = bus_dmamap_load(sc->vte_dmatag, 542 sc->vte_cdata.vte_rx_ring_map, sc->vte_cdata.vte_rx_ring, 543 VTE_RX_RING_SZ, NULL, 544 BUS_DMA_NOWAIT | BUS_DMA_READ | BUS_DMA_WRITE); 545 if (error != 0) { 546 aprint_error_dev(sc->vte_dev, 547 "could not load DMA'able memory for RX ring (%d).\n", 548 error); 549 goto fail; 550 } 551 552 /* Create DMA maps for TX buffers. */ 553 for (i = 0; i < VTE_TX_RING_CNT; i++) { 554 txd = &sc->vte_cdata.vte_txdesc[i]; 555 txd->tx_m = NULL; 556 txd->tx_dmamap = NULL; 557 error = bus_dmamap_create(sc->vte_dmatag, MCLBYTES, 558 1, MCLBYTES, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 559 &txd->tx_dmamap); 560 if (error != 0) { 561 aprint_error_dev(sc->vte_dev, 562 "could not create TX DMA map %d (%d).\n", i, error); 563 goto fail; 564 } 565 } 566 /* Create DMA maps for RX buffers. */ 567 if ((error = bus_dmamap_create(sc->vte_dmatag, MCLBYTES, 568 1, MCLBYTES, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 569 &sc->vte_cdata.vte_rx_sparemap)) != 0) { 570 aprint_error_dev(sc->vte_dev, 571 "could not create spare RX dmamap (%d).\n", error); 572 goto fail; 573 } 574 for (i = 0; i < VTE_RX_RING_CNT; i++) { 575 rxd = &sc->vte_cdata.vte_rxdesc[i]; 576 rxd->rx_m = NULL; 577 rxd->rx_dmamap = NULL; 578 error = bus_dmamap_create(sc->vte_dmatag, MCLBYTES, 579 1, MCLBYTES, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 580 &rxd->rx_dmamap); 581 if (error != 0) { 582 aprint_error_dev(sc->vte_dev, 583 "could not create RX dmamap %d (%d).\n", i, error); 584 goto fail; 585 } 586 } 587 return 0; 588 589 fail: 590 vte_dma_free(sc); 591 return (error); 592 } 593 594 static void 595 vte_dma_free(struct vte_softc *sc) 596 { 597 struct vte_txdesc *txd; 598 struct vte_rxdesc *rxd; 599 int i; 600 601 /* TX buffers. */ 602 for (i = 0; i < VTE_TX_RING_CNT; i++) { 603 txd = &sc->vte_cdata.vte_txdesc[i]; 604 if (txd->tx_dmamap != NULL) { 605 bus_dmamap_destroy(sc->vte_dmatag, txd->tx_dmamap); 606 txd->tx_dmamap = NULL; 607 } 608 } 609 /* RX buffers */ 610 for (i = 0; i < VTE_RX_RING_CNT; i++) { 611 rxd = &sc->vte_cdata.vte_rxdesc[i]; 612 if (rxd->rx_dmamap != NULL) { 613 bus_dmamap_destroy(sc->vte_dmatag, rxd->rx_dmamap); 614 rxd->rx_dmamap = NULL; 615 } 616 } 617 if (sc->vte_cdata.vte_rx_sparemap != NULL) { 618 bus_dmamap_destroy(sc->vte_dmatag, 619 sc->vte_cdata.vte_rx_sparemap); 620 sc->vte_cdata.vte_rx_sparemap = NULL; 621 } 622 /* TX descriptor ring. */ 623 if (sc->vte_cdata.vte_tx_ring_map != NULL) { 624 bus_dmamap_unload(sc->vte_dmatag, 625 sc->vte_cdata.vte_tx_ring_map); 626 bus_dmamap_destroy(sc->vte_dmatag, 627 sc->vte_cdata.vte_tx_ring_map); 628 } 629 if (sc->vte_cdata.vte_tx_ring != NULL) { 630 bus_dmamem_unmap(sc->vte_dmatag, 631 sc->vte_cdata.vte_tx_ring, VTE_TX_RING_SZ); 632 bus_dmamem_free(sc->vte_dmatag, 633 sc->vte_cdata.vte_tx_ring_seg, 1); 634 } 635 sc->vte_cdata.vte_tx_ring = NULL; 636 sc->vte_cdata.vte_tx_ring_map = NULL; 637 /* RX ring. */ 638 if (sc->vte_cdata.vte_rx_ring_map != NULL) { 639 bus_dmamap_unload(sc->vte_dmatag, 640 sc->vte_cdata.vte_rx_ring_map); 641 bus_dmamap_destroy(sc->vte_dmatag, 642 sc->vte_cdata.vte_rx_ring_map); 643 } 644 if (sc->vte_cdata.vte_rx_ring != NULL) { 645 bus_dmamem_unmap(sc->vte_dmatag, 646 sc->vte_cdata.vte_rx_ring, VTE_RX_RING_SZ); 647 bus_dmamem_free(sc->vte_dmatag, 648 sc->vte_cdata.vte_rx_ring_seg, 1); 649 } 650 sc->vte_cdata.vte_rx_ring = NULL; 651 sc->vte_cdata.vte_rx_ring_map = NULL; 652 } 653 654 static bool 655 vte_shutdown(device_t dev, int howto) 656 { 657 658 return (vte_suspend(dev, NULL)); 659 } 660 661 static bool 662 vte_suspend(device_t dev, const pmf_qual_t *qual) 663 { 664 struct vte_softc *sc = device_private(dev); 665 struct ifnet *ifp = &sc->vte_if; 666 667 DPRINTF(("vte_suspend if_flags 0x%x\n", ifp->if_flags)); 668 if ((ifp->if_flags & IFF_RUNNING) != 0) 669 vte_stop(ifp, 1); 670 return (0); 671 } 672 673 static bool 674 vte_resume(device_t dev, const pmf_qual_t *qual) 675 { 676 struct vte_softc *sc = device_private(dev); 677 struct ifnet *ifp; 678 679 ifp = &sc->vte_if; 680 if ((ifp->if_flags & IFF_UP) != 0) { 681 ifp->if_flags &= ~IFF_RUNNING; 682 vte_init(ifp); 683 } 684 685 return (0); 686 } 687 688 static struct vte_txdesc * 689 vte_encap(struct vte_softc *sc, struct mbuf **m_head) 690 { 691 struct vte_txdesc *txd; 692 struct mbuf *m, *n; 693 int copy, error, padlen; 694 695 txd = &sc->vte_cdata.vte_txdesc[sc->vte_cdata.vte_tx_prod]; 696 m = *m_head; 697 /* 698 * Controller doesn't auto-pad, so we have to make sure pad 699 * short frames out to the minimum frame length. 700 */ 701 if (m->m_pkthdr.len < VTE_MIN_FRAMELEN) 702 padlen = VTE_MIN_FRAMELEN - m->m_pkthdr.len; 703 else 704 padlen = 0; 705 706 /* 707 * Controller does not support multi-fragmented TX buffers. 708 * Controller spends most of its TX processing time in 709 * de-fragmenting TX buffers. Either faster CPU or more 710 * advanced controller DMA engine is required to speed up 711 * TX path processing. 712 * To mitigate the de-fragmenting issue, perform deep copy 713 * from fragmented mbuf chains to a pre-allocated mbuf 714 * cluster with extra cost of kernel memory. For frames 715 * that is composed of single TX buffer, the deep copy is 716 * bypassed. 717 */ 718 copy = 0; 719 if (m->m_next != NULL) 720 copy++; 721 if (padlen > 0 && (M_READONLY(m) || 722 padlen > M_TRAILINGSPACE(m))) 723 copy++; 724 if (copy != 0) { 725 n = sc->vte_cdata.vte_txmbufs[sc->vte_cdata.vte_tx_prod]; 726 m_copydata(m, 0, m->m_pkthdr.len, mtod(n, char *)); 727 n->m_pkthdr.len = m->m_pkthdr.len; 728 n->m_len = m->m_pkthdr.len; 729 m = n; 730 txd->tx_flags |= VTE_TXMBUF; 731 } 732 733 if (padlen > 0) { 734 /* Zero out the bytes in the pad area. */ 735 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 736 m->m_pkthdr.len += padlen; 737 m->m_len = m->m_pkthdr.len; 738 } 739 740 error = bus_dmamap_load_mbuf(sc->vte_dmatag, txd->tx_dmamap, m, 741 BUS_DMA_NOWAIT); 742 if (error != 0) { 743 txd->tx_flags &= ~VTE_TXMBUF; 744 return (NULL); 745 } 746 KASSERT(txd->tx_dmamap->dm_nsegs == 1); 747 bus_dmamap_sync(sc->vte_dmatag, txd->tx_dmamap, 0, 748 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 749 750 txd->tx_desc->dtlen = 751 htole16(VTE_TX_LEN(txd->tx_dmamap->dm_segs[0].ds_len)); 752 txd->tx_desc->dtbp = htole32(txd->tx_dmamap->dm_segs[0].ds_addr); 753 sc->vte_cdata.vte_tx_cnt++; 754 /* Update producer index. */ 755 VTE_DESC_INC(sc->vte_cdata.vte_tx_prod, VTE_TX_RING_CNT); 756 757 /* Finally hand over ownership to controller. */ 758 txd->tx_desc->dtst = htole16(VTE_DTST_TX_OWN); 759 txd->tx_m = m; 760 761 return (txd); 762 } 763 764 static void 765 vte_ifstart(struct ifnet *ifp) 766 { 767 struct vte_softc *sc = ifp->if_softc; 768 struct vte_txdesc *txd; 769 struct mbuf *m_head, *m; 770 int enq; 771 772 ifp = &sc->vte_if; 773 774 DPRINTF(("vte_ifstart 0x%x 0x%x\n", ifp->if_flags, sc->vte_flags)); 775 776 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != 777 IFF_RUNNING || (sc->vte_flags & VTE_FLAG_LINK) == 0) 778 return; 779 780 for (enq = 0; !IFQ_IS_EMPTY(&ifp->if_snd); ) { 781 /* Reserve one free TX descriptor. */ 782 if (sc->vte_cdata.vte_tx_cnt >= VTE_TX_RING_CNT - 1) { 783 ifp->if_flags |= IFF_OACTIVE; 784 break; 785 } 786 IFQ_POLL(&ifp->if_snd, m_head); 787 if (m_head == NULL) 788 break; 789 /* 790 * Pack the data into the transmit ring. If we 791 * don't have room, set the OACTIVE flag and wait 792 * for the NIC to drain the ring. 793 */ 794 DPRINTF(("vte_encap:")); 795 if ((txd = vte_encap(sc, &m_head)) == NULL) { 796 DPRINTF((" failed\n")); 797 break; 798 } 799 DPRINTF((" ok\n")); 800 IFQ_DEQUEUE(&ifp->if_snd, m); 801 KASSERT(m == m_head); 802 803 enq++; 804 /* 805 * If there's a BPF listener, bounce a copy of this frame 806 * to him. 807 */ 808 bpf_mtap(ifp, m_head, BPF_D_OUT); 809 /* Free consumed TX frame. */ 810 if ((txd->tx_flags & VTE_TXMBUF) != 0) 811 m_freem(m_head); 812 } 813 814 if (enq > 0) { 815 bus_dmamap_sync(sc->vte_dmatag, 816 sc->vte_cdata.vte_tx_ring_map, 0, 817 sc->vte_cdata.vte_tx_ring_map->dm_mapsize, 818 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 819 CSR_WRITE_2(sc, VTE_TX_POLL, TX_POLL_START); 820 sc->vte_watchdog_timer = VTE_TX_TIMEOUT; 821 } 822 } 823 824 static void 825 vte_ifwatchdog(struct ifnet *ifp) 826 { 827 struct vte_softc *sc = ifp->if_softc; 828 829 if (sc->vte_watchdog_timer == 0 || --sc->vte_watchdog_timer) 830 return; 831 832 aprint_error_dev(sc->vte_dev, "watchdog timeout -- resetting\n"); 833 if_statinc(ifp, if_oerrors); 834 vte_init(ifp); 835 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 836 vte_ifstart(ifp); 837 } 838 839 static int 840 vte_mediachange(struct ifnet *ifp) 841 { 842 int error; 843 struct vte_softc *sc = ifp->if_softc; 844 845 if ((error = mii_mediachg(&sc->vte_mii)) == ENXIO) 846 error = 0; 847 else if (error != 0) { 848 aprint_error_dev(sc->vte_dev, "could not set media\n"); 849 return error; 850 } 851 return 0; 852 853 } 854 855 static int 856 vte_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 857 { 858 struct vte_softc *sc = ifp->if_softc; 859 int error, s; 860 861 s = splnet(); 862 error = ether_ioctl(ifp, cmd, data); 863 if (error == ENETRESET) { 864 DPRINTF(("vte_ifioctl if_flags 0x%x\n", ifp->if_flags)); 865 if (ifp->if_flags & IFF_RUNNING) 866 vte_rxfilter(sc); 867 error = 0; 868 } 869 splx(s); 870 return error; 871 } 872 873 static void 874 vte_mac_config(struct vte_softc *sc) 875 { 876 uint16_t mcr; 877 878 mcr = CSR_READ_2(sc, VTE_MCR0); 879 mcr &= ~(MCR0_FC_ENB | MCR0_FULL_DUPLEX); 880 if ((IFM_OPTIONS(sc->vte_mii.mii_media_active) & IFM_FDX) != 0) { 881 mcr |= MCR0_FULL_DUPLEX; 882 #ifdef notyet 883 if ((IFM_OPTIONS(sc->vte_mii.mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 884 mcr |= MCR0_FC_ENB; 885 /* 886 * The data sheet is not clear whether the controller 887 * honors received pause frames or not. The is no 888 * separate control bit for RX pause frame so just 889 * enable MCR0_FC_ENB bit. 890 */ 891 if ((IFM_OPTIONS(sc->vte_mii.mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 892 mcr |= MCR0_FC_ENB; 893 #endif 894 } 895 CSR_WRITE_2(sc, VTE_MCR0, mcr); 896 } 897 898 static void 899 vte_stats_clear(struct vte_softc *sc) 900 { 901 902 /* Reading counter registers clears its contents. */ 903 CSR_READ_2(sc, VTE_CNT_RX_DONE); 904 CSR_READ_2(sc, VTE_CNT_MECNT0); 905 CSR_READ_2(sc, VTE_CNT_MECNT1); 906 CSR_READ_2(sc, VTE_CNT_MECNT2); 907 CSR_READ_2(sc, VTE_CNT_MECNT3); 908 CSR_READ_2(sc, VTE_CNT_TX_DONE); 909 CSR_READ_2(sc, VTE_CNT_MECNT4); 910 CSR_READ_2(sc, VTE_CNT_PAUSE); 911 } 912 913 static void 914 vte_stats_update(struct vte_softc *sc) 915 { 916 struct vte_hw_stats *stat; 917 struct ifnet *ifp = &sc->vte_if; 918 uint16_t value; 919 920 stat = &sc->vte_stats; 921 922 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 923 924 CSR_READ_2(sc, VTE_MECISR); 925 926 /* RX stats. */ 927 stat->rx_frames += CSR_READ_2(sc, VTE_CNT_RX_DONE); 928 929 value = CSR_READ_2(sc, VTE_CNT_MECNT0); 930 stat->rx_bcast_frames += (value >> 8); 931 stat->rx_mcast_frames += (value & 0xFF); 932 933 value = CSR_READ_2(sc, VTE_CNT_MECNT1); 934 if_statadd_ref(nsr, if_ierrors, 935 (value >> 8) + /* rx_runts */ 936 (value & 0xFF)); /* rx_crcerrs */ 937 938 value = CSR_READ_2(sc, VTE_CNT_MECNT2); 939 if_statadd_ref(nsr, if_ierrors, 940 (value & 0xFF)); /* rx_long_frames */ 941 942 value = CSR_READ_2(sc, VTE_CNT_MECNT3); 943 if_statadd_ref(nsr, if_ierrors, 944 (value >> 8)); /* rx_fifo_full */ 945 stat->rx_desc_unavail += (value & 0xFF); 946 947 /* TX stats. */ 948 if_statadd_ref(nsr, if_opackets, 949 CSR_READ_2(sc, VTE_CNT_TX_DONE)); /* tx_frames */ 950 951 value = CSR_READ_2(sc, VTE_CNT_MECNT4); 952 if_statadd_ref(nsr, if_oerrors, 953 (value >> 8) + /* tx_underruns */ 954 (value & 0xFF)); /* tx_late_colls */ 955 956 /* Pause stats. */ 957 value = CSR_READ_2(sc, VTE_CNT_PAUSE); 958 stat->tx_pause_frames += (value >> 8); 959 stat->rx_pause_frames += (value & 0xFF); 960 961 IF_STAT_PUTREF(ifp); 962 } 963 964 static int 965 vte_intr(void *arg) 966 { 967 struct vte_softc *sc = (struct vte_softc *)arg; 968 struct ifnet *ifp = &sc->vte_if; 969 uint16_t status; 970 int n; 971 972 /* Reading VTE_MISR acknowledges interrupts. */ 973 status = CSR_READ_2(sc, VTE_MISR); 974 DPRINTF(("vte_intr status 0x%x\n", status)); 975 if ((status & VTE_INTRS) == 0) { 976 /* Not ours. */ 977 return 0; 978 } 979 980 /* Disable interrupts. */ 981 CSR_WRITE_2(sc, VTE_MIER, 0); 982 for (n = 8; (status & VTE_INTRS) != 0;) { 983 if ((ifp->if_flags & IFF_RUNNING) == 0) 984 break; 985 if ((status & (MISR_RX_DONE | MISR_RX_DESC_UNAVAIL | 986 MISR_RX_FIFO_FULL)) != 0) 987 vte_rxeof(sc); 988 if ((status & MISR_TX_DONE) != 0) 989 vte_txeof(sc); 990 if ((status & MISR_EVENT_CNT_OFLOW) != 0) 991 vte_stats_update(sc); 992 if_schedule_deferred_start(ifp); 993 if (--n > 0) 994 status = CSR_READ_2(sc, VTE_MISR); 995 else 996 break; 997 } 998 999 if ((ifp->if_flags & IFF_RUNNING) != 0) { 1000 /* Re-enable interrupts. */ 1001 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS); 1002 } 1003 return 1; 1004 } 1005 1006 static void 1007 vte_txeof(struct vte_softc *sc) 1008 { 1009 struct ifnet *ifp; 1010 struct vte_txdesc *txd; 1011 uint16_t status; 1012 int cons, prog; 1013 1014 ifp = &sc->vte_if; 1015 1016 if (sc->vte_cdata.vte_tx_cnt == 0) 1017 return; 1018 bus_dmamap_sync(sc->vte_dmatag, 1019 sc->vte_cdata.vte_tx_ring_map, 0, 1020 sc->vte_cdata.vte_tx_ring_map->dm_mapsize, 1021 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1022 cons = sc->vte_cdata.vte_tx_cons; 1023 /* 1024 * Go through our TX list and free mbufs for those 1025 * frames which have been transmitted. 1026 */ 1027 for (prog = 0; sc->vte_cdata.vte_tx_cnt > 0; prog++) { 1028 txd = &sc->vte_cdata.vte_txdesc[cons]; 1029 status = le16toh(txd->tx_desc->dtst); 1030 if ((status & VTE_DTST_TX_OWN) != 0) 1031 break; 1032 if ((status & VTE_DTST_TX_OK) != 0) 1033 if_statadd(ifp, if_collisions, (status & 0xf)); 1034 sc->vte_cdata.vte_tx_cnt--; 1035 /* Reclaim transmitted mbufs. */ 1036 bus_dmamap_sync(sc->vte_dmatag, txd->tx_dmamap, 0, 1037 txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1038 bus_dmamap_unload(sc->vte_dmatag, txd->tx_dmamap); 1039 if ((txd->tx_flags & VTE_TXMBUF) == 0) 1040 m_freem(txd->tx_m); 1041 txd->tx_flags &= ~VTE_TXMBUF; 1042 txd->tx_m = NULL; 1043 prog++; 1044 VTE_DESC_INC(cons, VTE_TX_RING_CNT); 1045 } 1046 1047 if (prog > 0) { 1048 ifp->if_flags &= ~IFF_OACTIVE; 1049 sc->vte_cdata.vte_tx_cons = cons; 1050 /* 1051 * Unarm watchdog timer only when there is no pending 1052 * frames in TX queue. 1053 */ 1054 if (sc->vte_cdata.vte_tx_cnt == 0) 1055 sc->vte_watchdog_timer = 0; 1056 } 1057 } 1058 1059 static int 1060 vte_newbuf(struct vte_softc *sc, struct vte_rxdesc *rxd) 1061 { 1062 struct mbuf *m; 1063 bus_dmamap_t map; 1064 1065 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1066 if (m == NULL) 1067 return (ENOBUFS); 1068 m->m_len = m->m_pkthdr.len = MCLBYTES; 1069 m_adj(m, sizeof(uint32_t)); 1070 1071 if (bus_dmamap_load_mbuf(sc->vte_dmatag, 1072 sc->vte_cdata.vte_rx_sparemap, m, BUS_DMA_NOWAIT) != 0) { 1073 m_freem(m); 1074 return (ENOBUFS); 1075 } 1076 KASSERT(sc->vte_cdata.vte_rx_sparemap->dm_nsegs == 1); 1077 1078 if (rxd->rx_m != NULL) { 1079 bus_dmamap_sync(sc->vte_dmatag, rxd->rx_dmamap, 1080 0, rxd->rx_dmamap->dm_mapsize, 1081 BUS_DMASYNC_POSTREAD); 1082 bus_dmamap_unload(sc->vte_dmatag, rxd->rx_dmamap); 1083 } 1084 map = rxd->rx_dmamap; 1085 rxd->rx_dmamap = sc->vte_cdata.vte_rx_sparemap; 1086 sc->vte_cdata.vte_rx_sparemap = map; 1087 bus_dmamap_sync(sc->vte_dmatag, rxd->rx_dmamap, 1088 0, rxd->rx_dmamap->dm_mapsize, 1089 BUS_DMASYNC_PREREAD); 1090 rxd->rx_m = m; 1091 rxd->rx_desc->drbp = 1092 htole32(rxd->rx_dmamap->dm_segs[0].ds_addr); 1093 rxd->rx_desc->drlen = htole16( 1094 VTE_RX_LEN(rxd->rx_dmamap->dm_segs[0].ds_len)); 1095 DPRINTF(("rx data %p mbuf %p buf 0x%x/0x%x\n", rxd, m, 1096 (u_int)rxd->rx_dmamap->dm_segs[0].ds_addr, 1097 rxd->rx_dmamap->dm_segs[0].ds_len)); 1098 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1099 1100 return (0); 1101 } 1102 1103 static void 1104 vte_rxeof(struct vte_softc *sc) 1105 { 1106 struct ifnet *ifp; 1107 struct vte_rxdesc *rxd; 1108 struct mbuf *m; 1109 uint16_t status, total_len; 1110 int cons, prog; 1111 1112 bus_dmamap_sync(sc->vte_dmatag, 1113 sc->vte_cdata.vte_rx_ring_map, 0, 1114 sc->vte_cdata.vte_rx_ring_map->dm_mapsize, 1115 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1116 cons = sc->vte_cdata.vte_rx_cons; 1117 ifp = &sc->vte_if; 1118 DPRINTF(("vte_rxeof if_flags 0x%x\n", ifp->if_flags)); 1119 for (prog = 0; (ifp->if_flags & IFF_RUNNING) != 0; prog++, 1120 VTE_DESC_INC(cons, VTE_RX_RING_CNT)) { 1121 rxd = &sc->vte_cdata.vte_rxdesc[cons]; 1122 status = le16toh(rxd->rx_desc->drst); 1123 DPRINTF(("vte_rxoef rxd %d/%p mbuf %p status 0x%x len %d\n", 1124 cons, rxd, rxd->rx_m, status, 1125 VTE_RX_LEN(le16toh(rxd->rx_desc->drlen)))); 1126 if ((status & VTE_DRST_RX_OWN) != 0) 1127 break; 1128 total_len = VTE_RX_LEN(le16toh(rxd->rx_desc->drlen)); 1129 m = rxd->rx_m; 1130 if ((status & VTE_DRST_RX_OK) == 0) { 1131 /* Discard errored frame. */ 1132 rxd->rx_desc->drlen = 1133 htole16(MCLBYTES - sizeof(uint32_t)); 1134 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1135 continue; 1136 } 1137 if (vte_newbuf(sc, rxd) != 0) { 1138 DPRINTF(("vte_rxeof newbuf failed\n")); 1139 if_statinc(ifp, if_ierrors); 1140 rxd->rx_desc->drlen = 1141 htole16(MCLBYTES - sizeof(uint32_t)); 1142 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1143 continue; 1144 } 1145 1146 /* 1147 * It seems there is no way to strip FCS bytes. 1148 */ 1149 m->m_pkthdr.len = m->m_len = total_len - ETHER_CRC_LEN; 1150 m_set_rcvif(m, ifp); 1151 if_percpuq_enqueue(ifp->if_percpuq, m); 1152 } 1153 1154 if (prog > 0) { 1155 /* Update the consumer index. */ 1156 sc->vte_cdata.vte_rx_cons = cons; 1157 /* 1158 * Sync updated RX descriptors such that controller see 1159 * modified RX buffer addresses. 1160 */ 1161 bus_dmamap_sync(sc->vte_dmatag, 1162 sc->vte_cdata.vte_rx_ring_map, 0, 1163 sc->vte_cdata.vte_rx_ring_map->dm_mapsize, 1164 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1165 #ifdef notyet 1166 /* 1167 * Update residue counter. Controller does not 1168 * keep track of number of available RX descriptors 1169 * such that driver should have to update VTE_MRDCR 1170 * to make controller know how many free RX 1171 * descriptors were added to controller. This is 1172 * a similar mechanism used in VIA velocity 1173 * controllers and it indicates controller just 1174 * polls OWN bit of current RX descriptor pointer. 1175 * A couple of severe issues were seen on sample 1176 * board where the controller continuously emits TX 1177 * pause frames once RX pause threshold crossed. 1178 * Once triggered it never recovered form that 1179 * state, I couldn't find a way to make it back to 1180 * work at least. This issue effectively 1181 * disconnected the system from network. Also, the 1182 * controller used 00:00:00:00:00:00 as source 1183 * station address of TX pause frame. Probably this 1184 * is one of reason why vendor recommends not to 1185 * enable flow control on R6040 controller. 1186 */ 1187 CSR_WRITE_2(sc, VTE_MRDCR, prog | 1188 (((VTE_RX_RING_CNT * 2) / 10) << 1189 VTE_MRDCR_RX_PAUSE_THRESH_SHIFT)); 1190 #endif 1191 rnd_add_uint32(&sc->rnd_source, prog); 1192 } 1193 } 1194 1195 static void 1196 vte_tick(void *arg) 1197 { 1198 struct vte_softc *sc; 1199 int s = splnet(); 1200 1201 sc = (struct vte_softc *)arg; 1202 1203 mii_tick(&sc->vte_mii); 1204 vte_stats_update(sc); 1205 vte_txeof(sc); 1206 vte_ifwatchdog(&sc->vte_if); 1207 callout_schedule(&sc->vte_tick_ch, hz); 1208 splx(s); 1209 } 1210 1211 static void 1212 vte_reset(struct vte_softc *sc) 1213 { 1214 uint16_t mcr, mdcsc; 1215 int i; 1216 1217 mdcsc = CSR_READ_2(sc, VTE_MDCSC); 1218 mcr = CSR_READ_2(sc, VTE_MCR1); 1219 CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESET); 1220 for (i = VTE_RESET_TIMEOUT; i > 0; i--) { 1221 DELAY(10); 1222 if ((CSR_READ_2(sc, VTE_MCR1) & MCR1_MAC_RESET) == 0) 1223 break; 1224 } 1225 if (i == 0) 1226 aprint_error_dev(sc->vte_dev, "reset timeout(0x%04x)!\n", mcr); 1227 /* 1228 * Follow the guide of vendor recommended way to reset MAC. 1229 * Vendor confirms relying on MCR1_MAC_RESET of VTE_MCR1 is 1230 * not reliable so manually reset internal state machine. 1231 */ 1232 CSR_WRITE_2(sc, VTE_MACSM, 0x0002); 1233 CSR_WRITE_2(sc, VTE_MACSM, 0); 1234 DELAY(5000); 1235 1236 /* 1237 * On some SoCs (like Vortex86DX3) MDC speed control register value 1238 * needs to be restored to original value instead of default one, 1239 * otherwise some PHY registers may fail to be read. 1240 */ 1241 if (mdcsc != MDCSC_DEFAULT) 1242 CSR_WRITE_2(sc, VTE_MDCSC, mdcsc); 1243 } 1244 1245 1246 static int 1247 vte_init(struct ifnet *ifp) 1248 { 1249 struct vte_softc *sc = ifp->if_softc; 1250 bus_addr_t paddr; 1251 uint8_t eaddr[ETHER_ADDR_LEN]; 1252 int s, error; 1253 1254 s = splnet(); 1255 /* 1256 * Cancel any pending I/O. 1257 */ 1258 vte_stop(ifp, 1); 1259 /* 1260 * Reset the chip to a known state. 1261 */ 1262 vte_reset(sc); 1263 1264 if ((sc->vte_if.if_flags & IFF_UP) == 0) { 1265 splx(s); 1266 return 0; 1267 } 1268 1269 /* Initialize RX descriptors. */ 1270 if (vte_init_rx_ring(sc) != 0) { 1271 aprint_error_dev(sc->vte_dev, "no memory for RX buffers.\n"); 1272 vte_stop(ifp, 1); 1273 splx(s); 1274 return ENOMEM; 1275 } 1276 if (vte_init_tx_ring(sc) != 0) { 1277 aprint_error_dev(sc->vte_dev, "no memory for TX buffers.\n"); 1278 vte_stop(ifp, 1); 1279 splx(s); 1280 return ENOMEM; 1281 } 1282 1283 /* 1284 * Reprogram the station address. Controller supports up 1285 * to 4 different station addresses so driver programs the 1286 * first station address as its own ethernet address and 1287 * configure the remaining three addresses as perfect 1288 * multicast addresses. 1289 */ 1290 memcpy(eaddr, CLLADDR(ifp->if_sadl), ETHER_ADDR_LEN); 1291 CSR_WRITE_2(sc, VTE_MID0L, eaddr[1] << 8 | eaddr[0]); 1292 CSR_WRITE_2(sc, VTE_MID0M, eaddr[3] << 8 | eaddr[2]); 1293 CSR_WRITE_2(sc, VTE_MID0H, eaddr[5] << 8 | eaddr[4]); 1294 1295 /* Set TX descriptor base addresses. */ 1296 paddr = sc->vte_cdata.vte_tx_ring_map->dm_segs[0].ds_addr; 1297 DPRINTF(("tx paddr 0x%x\n", (u_int)paddr)); 1298 CSR_WRITE_2(sc, VTE_MTDSA1, paddr >> 16); 1299 CSR_WRITE_2(sc, VTE_MTDSA0, paddr & 0xFFFF); 1300 1301 /* Set RX descriptor base addresses. */ 1302 paddr = sc->vte_cdata.vte_rx_ring_map->dm_segs[0].ds_addr; 1303 DPRINTF(("rx paddr 0x%x\n", (u_int)paddr)); 1304 CSR_WRITE_2(sc, VTE_MRDSA1, paddr >> 16); 1305 CSR_WRITE_2(sc, VTE_MRDSA0, paddr & 0xFFFF); 1306 /* 1307 * Initialize RX descriptor residue counter and set RX 1308 * pause threshold to 20% of available RX descriptors. 1309 * See comments on vte_rxeof() for details on flow control 1310 * issues. 1311 */ 1312 CSR_WRITE_2(sc, VTE_MRDCR, (VTE_RX_RING_CNT & VTE_MRDCR_RESIDUE_MASK) | 1313 (((VTE_RX_RING_CNT * 2) / 10) << VTE_MRDCR_RX_PAUSE_THRESH_SHIFT)); 1314 1315 /* 1316 * Always use maximum frame size that controller can 1317 * support. Otherwise received frames that has longer 1318 * frame length than vte(4) MTU would be silently dropped 1319 * in controller. This would break path-MTU discovery as 1320 * sender wouldn't get any responses from receiver. The 1321 * RX buffer size should be multiple of 4. 1322 * Note, jumbo frames are silently ignored by controller 1323 * and even MAC counters do not detect them. 1324 */ 1325 CSR_WRITE_2(sc, VTE_MRBSR, VTE_RX_BUF_SIZE_MAX); 1326 1327 /* Configure FIFO. */ 1328 CSR_WRITE_2(sc, VTE_MBCR, MBCR_FIFO_XFER_LENGTH_16 | 1329 MBCR_TX_FIFO_THRESH_64 | MBCR_RX_FIFO_THRESH_16 | 1330 MBCR_SDRAM_BUS_REQ_TIMER_DEFAULT); 1331 1332 /* 1333 * Configure TX/RX MACs. Actual resolved duplex and flow 1334 * control configuration is done after detecting a valid 1335 * link. Note, we don't generate early interrupt here 1336 * as well since FreeBSD does not have interrupt latency 1337 * problems like Windows. 1338 */ 1339 CSR_WRITE_2(sc, VTE_MCR0, MCR0_ACCPT_LONG_PKT); 1340 /* 1341 * We manually keep track of PHY status changes to 1342 * configure resolved duplex and flow control since only 1343 * duplex configuration can be automatically reflected to 1344 * MCR0. 1345 */ 1346 CSR_WRITE_2(sc, VTE_MCR1, MCR1_PKT_LENGTH_1537 | 1347 MCR1_EXCESS_COL_RETRY_16); 1348 1349 /* Initialize RX filter. */ 1350 vte_rxfilter(sc); 1351 1352 /* Disable TX/RX interrupt moderation control. */ 1353 CSR_WRITE_2(sc, VTE_MRICR, 0); 1354 CSR_WRITE_2(sc, VTE_MTICR, 0); 1355 1356 /* Enable MAC event counter interrupts. */ 1357 CSR_WRITE_2(sc, VTE_MECIER, VTE_MECIER_INTRS); 1358 /* Clear MAC statistics. */ 1359 vte_stats_clear(sc); 1360 1361 /* Acknowledge all pending interrupts and clear it. */ 1362 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS); 1363 CSR_WRITE_2(sc, VTE_MISR, 0); 1364 DPRINTF(("before ipend 0x%x 0x%x\n", CSR_READ_2(sc, VTE_MIER), 1365 CSR_READ_2(sc, VTE_MISR))); 1366 1367 sc->vte_flags &= ~VTE_FLAG_LINK; 1368 ifp->if_flags |= IFF_RUNNING; 1369 ifp->if_flags &= ~IFF_OACTIVE; 1370 1371 /* calling mii_mediachg will call back vte_start_mac() */ 1372 if ((error = mii_mediachg(&sc->vte_mii)) == ENXIO) 1373 error = 0; 1374 else if (error != 0) { 1375 aprint_error_dev(sc->vte_dev, "could not set media\n"); 1376 splx(s); 1377 return error; 1378 } 1379 1380 callout_schedule(&sc->vte_tick_ch, hz); 1381 1382 DPRINTF(("ipend 0x%x 0x%x\n", CSR_READ_2(sc, VTE_MIER), 1383 CSR_READ_2(sc, VTE_MISR))); 1384 splx(s); 1385 return 0; 1386 } 1387 1388 static void 1389 vte_stop(struct ifnet *ifp, int disable) 1390 { 1391 struct vte_softc *sc = ifp->if_softc; 1392 struct vte_txdesc *txd; 1393 struct vte_rxdesc *rxd; 1394 int i; 1395 1396 DPRINTF(("vte_stop if_flags 0x%x\n", ifp->if_flags)); 1397 if ((ifp->if_flags & IFF_RUNNING) == 0) 1398 return; 1399 /* 1400 * Mark the interface down and cancel the watchdog timer. 1401 */ 1402 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1403 sc->vte_flags &= ~VTE_FLAG_LINK; 1404 callout_stop(&sc->vte_tick_ch); 1405 sc->vte_watchdog_timer = 0; 1406 vte_stats_update(sc); 1407 /* Disable interrupts. */ 1408 CSR_WRITE_2(sc, VTE_MIER, 0); 1409 CSR_WRITE_2(sc, VTE_MECIER, 0); 1410 /* Stop RX/TX MACs. */ 1411 vte_stop_mac(sc); 1412 /* Clear interrupts. */ 1413 CSR_READ_2(sc, VTE_MISR); 1414 /* 1415 * Free TX/RX mbufs still in the queues. 1416 */ 1417 for (i = 0; i < VTE_RX_RING_CNT; i++) { 1418 rxd = &sc->vte_cdata.vte_rxdesc[i]; 1419 if (rxd->rx_m != NULL) { 1420 bus_dmamap_sync(sc->vte_dmatag, 1421 rxd->rx_dmamap, 0, rxd->rx_dmamap->dm_mapsize, 1422 BUS_DMASYNC_POSTREAD); 1423 bus_dmamap_unload(sc->vte_dmatag, 1424 rxd->rx_dmamap); 1425 m_freem(rxd->rx_m); 1426 rxd->rx_m = NULL; 1427 } 1428 } 1429 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1430 txd = &sc->vte_cdata.vte_txdesc[i]; 1431 if (txd->tx_m != NULL) { 1432 bus_dmamap_sync(sc->vte_dmatag, 1433 txd->tx_dmamap, 0, txd->tx_dmamap->dm_mapsize, 1434 BUS_DMASYNC_POSTWRITE); 1435 bus_dmamap_unload(sc->vte_dmatag, 1436 txd->tx_dmamap); 1437 if ((txd->tx_flags & VTE_TXMBUF) == 0) 1438 m_freem(txd->tx_m); 1439 txd->tx_m = NULL; 1440 txd->tx_flags &= ~VTE_TXMBUF; 1441 } 1442 } 1443 /* Free TX mbuf pools used for deep copy. */ 1444 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1445 if (sc->vte_cdata.vte_txmbufs[i] != NULL) { 1446 m_freem(sc->vte_cdata.vte_txmbufs[i]); 1447 sc->vte_cdata.vte_txmbufs[i] = NULL; 1448 } 1449 } 1450 } 1451 1452 static void 1453 vte_start_mac(struct vte_softc *sc) 1454 { 1455 struct ifnet *ifp = &sc->vte_if; 1456 uint16_t mcr; 1457 int i; 1458 1459 /* Enable RX/TX MACs. */ 1460 mcr = CSR_READ_2(sc, VTE_MCR0); 1461 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) != 1462 (MCR0_RX_ENB | MCR0_TX_ENB) && 1463 (ifp->if_flags & IFF_RUNNING) != 0) { 1464 mcr |= MCR0_RX_ENB | MCR0_TX_ENB; 1465 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1466 for (i = VTE_TIMEOUT; i > 0; i--) { 1467 mcr = CSR_READ_2(sc, VTE_MCR0); 1468 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) == 1469 (MCR0_RX_ENB | MCR0_TX_ENB)) 1470 break; 1471 DELAY(10); 1472 } 1473 if (i == 0) 1474 aprint_error_dev(sc->vte_dev, 1475 "could not enable RX/TX MAC(0x%04x)!\n", mcr); 1476 } 1477 vte_rxfilter(sc); 1478 } 1479 1480 static void 1481 vte_stop_mac(struct vte_softc *sc) 1482 { 1483 uint16_t mcr; 1484 int i; 1485 1486 /* Disable RX/TX MACs. */ 1487 mcr = CSR_READ_2(sc, VTE_MCR0); 1488 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) != 0) { 1489 mcr &= ~(MCR0_RX_ENB | MCR0_TX_ENB); 1490 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1491 for (i = VTE_TIMEOUT; i > 0; i--) { 1492 mcr = CSR_READ_2(sc, VTE_MCR0); 1493 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) == 0) 1494 break; 1495 DELAY(10); 1496 } 1497 if (i == 0) 1498 aprint_error_dev(sc->vte_dev, 1499 "could not disable RX/TX MAC(0x%04x)!\n", mcr); 1500 } 1501 } 1502 1503 static int 1504 vte_init_tx_ring(struct vte_softc *sc) 1505 { 1506 struct vte_tx_desc *desc; 1507 struct vte_txdesc *txd; 1508 bus_addr_t addr; 1509 int i; 1510 1511 sc->vte_cdata.vte_tx_prod = 0; 1512 sc->vte_cdata.vte_tx_cons = 0; 1513 sc->vte_cdata.vte_tx_cnt = 0; 1514 1515 /* Pre-allocate TX mbufs for deep copy. */ 1516 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1517 sc->vte_cdata.vte_txmbufs[i] = m_getcl(M_DONTWAIT, 1518 MT_DATA, M_PKTHDR); 1519 if (sc->vte_cdata.vte_txmbufs[i] == NULL) 1520 return (ENOBUFS); 1521 sc->vte_cdata.vte_txmbufs[i]->m_pkthdr.len = MCLBYTES; 1522 sc->vte_cdata.vte_txmbufs[i]->m_len = MCLBYTES; 1523 } 1524 desc = sc->vte_cdata.vte_tx_ring; 1525 bzero(desc, VTE_TX_RING_SZ); 1526 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1527 txd = &sc->vte_cdata.vte_txdesc[i]; 1528 txd->tx_m = NULL; 1529 if (i != VTE_TX_RING_CNT - 1) 1530 addr = sc->vte_cdata.vte_tx_ring_map->dm_segs[0].ds_addr + 1531 sizeof(struct vte_tx_desc) * (i + 1); 1532 else 1533 addr = sc->vte_cdata.vte_tx_ring_map->dm_segs[0].ds_addr + 1534 sizeof(struct vte_tx_desc) * 0; 1535 desc = &sc->vte_cdata.vte_tx_ring[i]; 1536 desc->dtnp = htole32(addr); 1537 DPRINTF(("tx ring desc %d addr 0x%x\n", i, (u_int)addr)); 1538 txd->tx_desc = desc; 1539 } 1540 1541 bus_dmamap_sync(sc->vte_dmatag, 1542 sc->vte_cdata.vte_tx_ring_map, 0, 1543 sc->vte_cdata.vte_tx_ring_map->dm_mapsize, 1544 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1545 return (0); 1546 } 1547 1548 static int 1549 vte_init_rx_ring(struct vte_softc *sc) 1550 { 1551 struct vte_rx_desc *desc; 1552 struct vte_rxdesc *rxd; 1553 bus_addr_t addr; 1554 int i; 1555 1556 sc->vte_cdata.vte_rx_cons = 0; 1557 desc = sc->vte_cdata.vte_rx_ring; 1558 bzero(desc, VTE_RX_RING_SZ); 1559 for (i = 0; i < VTE_RX_RING_CNT; i++) { 1560 rxd = &sc->vte_cdata.vte_rxdesc[i]; 1561 rxd->rx_m = NULL; 1562 if (i != VTE_RX_RING_CNT - 1) 1563 addr = sc->vte_cdata.vte_rx_ring_map->dm_segs[0].ds_addr 1564 + sizeof(struct vte_rx_desc) * (i + 1); 1565 else 1566 addr = sc->vte_cdata.vte_rx_ring_map->dm_segs[0].ds_addr 1567 + sizeof(struct vte_rx_desc) * 0; 1568 desc = &sc->vte_cdata.vte_rx_ring[i]; 1569 desc->drnp = htole32(addr); 1570 DPRINTF(("rx ring desc %d addr 0x%x\n", i, (u_int)addr)); 1571 rxd->rx_desc = desc; 1572 if (vte_newbuf(sc, rxd) != 0) 1573 return (ENOBUFS); 1574 } 1575 1576 bus_dmamap_sync(sc->vte_dmatag, 1577 sc->vte_cdata.vte_rx_ring_map, 0, 1578 sc->vte_cdata.vte_rx_ring_map->dm_mapsize, 1579 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1580 1581 return (0); 1582 } 1583 1584 static void 1585 vte_rxfilter(struct vte_softc *sc) 1586 { 1587 struct ethercom *ec = &sc->vte_ec; 1588 struct ether_multistep step; 1589 struct ether_multi *enm; 1590 struct ifnet *ifp; 1591 uint8_t *eaddr; 1592 uint32_t crc; 1593 uint16_t rxfilt_perf[VTE_RXFILT_PERFECT_CNT][3]; 1594 uint16_t mchash[4], mcr; 1595 int i, nperf; 1596 1597 ifp = &sc->vte_if; 1598 1599 DPRINTF(("vte_rxfilter\n")); 1600 memset(mchash, 0, sizeof(mchash)); 1601 for (i = 0; i < VTE_RXFILT_PERFECT_CNT; i++) { 1602 rxfilt_perf[i][0] = 0xFFFF; 1603 rxfilt_perf[i][1] = 0xFFFF; 1604 rxfilt_perf[i][2] = 0xFFFF; 1605 } 1606 1607 mcr = CSR_READ_2(sc, VTE_MCR0); 1608 DPRINTF(("vte_rxfilter mcr 0x%x\n", mcr)); 1609 mcr &= ~(MCR0_PROMISC | MCR0_BROADCAST_DIS | MCR0_MULTICAST); 1610 if ((ifp->if_flags & IFF_BROADCAST) == 0) 1611 mcr |= MCR0_BROADCAST_DIS; 1612 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 1613 if ((ifp->if_flags & IFF_PROMISC) != 0) 1614 mcr |= MCR0_PROMISC; 1615 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 1616 mcr |= MCR0_MULTICAST; 1617 mchash[0] = 0xFFFF; 1618 mchash[1] = 0xFFFF; 1619 mchash[2] = 0xFFFF; 1620 mchash[3] = 0xFFFF; 1621 goto chipit; 1622 } 1623 1624 ETHER_LOCK(ec); 1625 ETHER_FIRST_MULTI(step, ec, enm); 1626 nperf = 0; 1627 while (enm != NULL) { 1628 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN) 1629 != 0) { 1630 sc->vte_if.if_flags |= IFF_ALLMULTI; 1631 mcr |= MCR0_MULTICAST; 1632 mchash[0] = 0xFFFF; 1633 mchash[1] = 0xFFFF; 1634 mchash[2] = 0xFFFF; 1635 mchash[3] = 0xFFFF; 1636 ETHER_UNLOCK(ec); 1637 goto chipit; 1638 } 1639 /* 1640 * Program the first 3 multicast groups into 1641 * the perfect filter. For all others, use the 1642 * hash table. 1643 */ 1644 if (nperf < VTE_RXFILT_PERFECT_CNT) { 1645 eaddr = enm->enm_addrlo; 1646 rxfilt_perf[nperf][0] = eaddr[1] << 8 | eaddr[0]; 1647 rxfilt_perf[nperf][1] = eaddr[3] << 8 | eaddr[2]; 1648 rxfilt_perf[nperf][2] = eaddr[5] << 8 | eaddr[4]; 1649 nperf++; 1650 } else { 1651 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1652 mchash[crc >> 30] |= 1 << ((crc >> 26) & 0x0F); 1653 } 1654 ETHER_NEXT_MULTI(step, enm); 1655 } 1656 ETHER_UNLOCK(ec); 1657 if (mchash[0] != 0 || mchash[1] != 0 || mchash[2] != 0 || 1658 mchash[3] != 0) 1659 mcr |= MCR0_MULTICAST; 1660 1661 chipit: 1662 /* Program multicast hash table. */ 1663 DPRINTF(("chipit write multicast\n")); 1664 CSR_WRITE_2(sc, VTE_MAR0, mchash[0]); 1665 CSR_WRITE_2(sc, VTE_MAR1, mchash[1]); 1666 CSR_WRITE_2(sc, VTE_MAR2, mchash[2]); 1667 CSR_WRITE_2(sc, VTE_MAR3, mchash[3]); 1668 /* Program perfect filter table. */ 1669 DPRINTF(("chipit write perfect filter\n")); 1670 for (i = 0; i < VTE_RXFILT_PERFECT_CNT; i++) { 1671 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 0, 1672 rxfilt_perf[i][0]); 1673 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 2, 1674 rxfilt_perf[i][1]); 1675 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 4, 1676 rxfilt_perf[i][2]); 1677 } 1678 DPRINTF(("chipit mcr0 0x%x\n", mcr)); 1679 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1680 DPRINTF(("chipit read mcro\n")); 1681 CSR_READ_2(sc, VTE_MCR0); 1682 DPRINTF(("chipit done\n")); 1683 } 1684 1685 /* 1686 * Set up sysctl(3) MIB, hw.vte.* - Individual controllers will be 1687 * set up in vte_pci_attach() 1688 */ 1689 SYSCTL_SETUP(sysctl_vte, "sysctl vte subtree setup") 1690 { 1691 int rc; 1692 const struct sysctlnode *node; 1693 1694 if ((rc = sysctl_createv(clog, 0, NULL, &node, 1695 0, CTLTYPE_NODE, "vte", 1696 SYSCTL_DESCR("vte interface controls"), 1697 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) { 1698 goto err; 1699 } 1700 1701 vte_root_num = node->sysctl_num; 1702 return; 1703 1704 err: 1705 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc); 1706 } 1707 1708 static int 1709 vte_sysctl_intrxct(SYSCTLFN_ARGS) 1710 { 1711 int error, t; 1712 struct sysctlnode node; 1713 struct vte_softc *sc; 1714 1715 node = *rnode; 1716 sc = node.sysctl_data; 1717 t = sc->vte_int_rx_mod; 1718 node.sysctl_data = &t; 1719 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1720 if (error || newp == NULL) 1721 return error; 1722 if (t < VTE_IM_BUNDLE_MIN || t > VTE_IM_BUNDLE_MAX) 1723 return EINVAL; 1724 1725 sc->vte_int_rx_mod = t; 1726 vte_miibus_statchg(&sc->vte_if); 1727 return 0; 1728 } 1729 1730 static int 1731 vte_sysctl_inttxct(SYSCTLFN_ARGS) 1732 { 1733 int error, t; 1734 struct sysctlnode node; 1735 struct vte_softc *sc; 1736 1737 node = *rnode; 1738 sc = node.sysctl_data; 1739 t = sc->vte_int_tx_mod; 1740 node.sysctl_data = &t; 1741 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 1742 if (error || newp == NULL) 1743 return error; 1744 1745 if (t < VTE_IM_BUNDLE_MIN || t > VTE_IM_BUNDLE_MAX) 1746 return EINVAL; 1747 sc->vte_int_tx_mod = t; 1748 vte_miibus_statchg(&sc->vte_if); 1749 return 0; 1750 } 1751