1 /* $NetBSD: if_vr.c,v 1.75 2005/12/11 12:22:50 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1997, 1998 42 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Bill Paul. 55 * 4. Neither the name of the author nor the names of any co-contributors 56 * may be used to endorse or promote products derived from this software 57 * without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 63 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 64 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 65 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 66 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 67 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 68 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 69 * THE POSSIBILITY OF SUCH DAMAGE. 70 * 71 * $FreeBSD: if_vr.c,v 1.7 1999/01/10 18:51:49 wpaul Exp $ 72 */ 73 74 /* 75 * VIA Rhine fast ethernet PCI NIC driver 76 * 77 * Supports various network adapters based on the VIA Rhine 78 * and Rhine II PCI controllers, including the D-Link DFE530TX. 79 * Datasheets are available at http://www.via.com.tw. 80 * 81 * Written by Bill Paul <wpaul@ctr.columbia.edu> 82 * Electrical Engineering Department 83 * Columbia University, New York City 84 */ 85 86 /* 87 * The VIA Rhine controllers are similar in some respects to the 88 * the DEC tulip chips, except less complicated. The controller 89 * uses an MII bus and an external physical layer interface. The 90 * receiver has a one entry perfect filter and a 64-bit hash table 91 * multicast filter. Transmit and receive descriptors are similar 92 * to the tulip. 93 * 94 * The Rhine has a serious flaw in its transmit DMA mechanism: 95 * transmit buffers must be longword aligned. Unfortunately, 96 * the kernel doesn't guarantee that mbufs will be filled in starting 97 * at longword boundaries, so we have to do a buffer copy before 98 * transmission. 99 * 100 * Apparently, the receive DMA mechanism also has the same flaw. This 101 * means that on systems with struct alignment requirements, incoming 102 * frames must be copied to a new buffer which shifts the data forward 103 * 2 bytes so that the payload is aligned on a 4-byte boundary. 104 */ 105 106 #include <sys/cdefs.h> 107 __KERNEL_RCSID(0, "$NetBSD: if_vr.c,v 1.75 2005/12/11 12:22:50 christos Exp $"); 108 109 #include "rnd.h" 110 111 #include <sys/param.h> 112 #include <sys/systm.h> 113 #include <sys/callout.h> 114 #include <sys/sockio.h> 115 #include <sys/mbuf.h> 116 #include <sys/malloc.h> 117 #include <sys/kernel.h> 118 #include <sys/socket.h> 119 #include <sys/device.h> 120 121 #if NRND > 0 122 #include <sys/rnd.h> 123 #endif 124 125 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 126 127 #include <net/if.h> 128 #include <net/if_arp.h> 129 #include <net/if_dl.h> 130 #include <net/if_media.h> 131 #include <net/if_ether.h> 132 133 #include "bpfilter.h" 134 #if NBPFILTER > 0 135 #include <net/bpf.h> 136 #endif 137 138 #include <machine/bus.h> 139 #include <machine/intr.h> 140 #include <machine/endian.h> 141 142 #include <dev/mii/mii.h> 143 #include <dev/mii/miivar.h> 144 #include <dev/mii/mii_bitbang.h> 145 146 #include <dev/pci/pcireg.h> 147 #include <dev/pci/pcivar.h> 148 #include <dev/pci/pcidevs.h> 149 150 #include <dev/pci/if_vrreg.h> 151 152 #define VR_USEIOSPACE 153 154 /* 155 * Various supported device vendors/types and their names. 156 */ 157 static struct vr_type { 158 pci_vendor_id_t vr_vid; 159 pci_product_id_t vr_did; 160 const char *vr_name; 161 } vr_devs[] = { 162 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT3043, 163 "VIA VT3043 (Rhine) 10/100" }, 164 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6102, 165 "VIA VT6102 (Rhine II) 10/100" }, 166 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6105, 167 "VIA VT6105 (Rhine III) 10/100" }, 168 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT86C100A, 169 "VIA VT86C100A (Rhine-II) 10/100" }, 170 { 0, 0, NULL } 171 }; 172 173 /* 174 * Transmit descriptor list size. 175 */ 176 #define VR_NTXDESC 64 177 #define VR_NTXDESC_MASK (VR_NTXDESC - 1) 178 #define VR_NEXTTX(x) (((x) + 1) & VR_NTXDESC_MASK) 179 180 /* 181 * Receive descriptor list size. 182 */ 183 #define VR_NRXDESC 64 184 #define VR_NRXDESC_MASK (VR_NRXDESC - 1) 185 #define VR_NEXTRX(x) (((x) + 1) & VR_NRXDESC_MASK) 186 187 /* 188 * Control data structres that are DMA'd to the Rhine chip. We allocate 189 * them in a single clump that maps to a single DMA segment to make several 190 * things easier. 191 * 192 * Note that since we always copy outgoing packets to aligned transmit 193 * buffers, we can reduce the transmit descriptors to one per packet. 194 */ 195 struct vr_control_data { 196 struct vr_desc vr_txdescs[VR_NTXDESC]; 197 struct vr_desc vr_rxdescs[VR_NRXDESC]; 198 }; 199 200 #define VR_CDOFF(x) offsetof(struct vr_control_data, x) 201 #define VR_CDTXOFF(x) VR_CDOFF(vr_txdescs[(x)]) 202 #define VR_CDRXOFF(x) VR_CDOFF(vr_rxdescs[(x)]) 203 204 /* 205 * Software state of transmit and receive descriptors. 206 */ 207 struct vr_descsoft { 208 struct mbuf *ds_mbuf; /* head of mbuf chain */ 209 bus_dmamap_t ds_dmamap; /* our DMA map */ 210 }; 211 212 struct vr_softc { 213 struct device vr_dev; /* generic device glue */ 214 void *vr_ih; /* interrupt cookie */ 215 void *vr_ats; /* shutdown hook */ 216 bus_space_tag_t vr_bst; /* bus space tag */ 217 bus_space_handle_t vr_bsh; /* bus space handle */ 218 bus_dma_tag_t vr_dmat; /* bus DMA tag */ 219 pci_chipset_tag_t vr_pc; /* PCI chipset info */ 220 struct ethercom vr_ec; /* Ethernet common info */ 221 u_int8_t vr_enaddr[ETHER_ADDR_LEN]; 222 struct mii_data vr_mii; /* MII/media info */ 223 224 u_int8_t vr_revid; /* Rhine chip revision */ 225 226 struct callout vr_tick_ch; /* tick callout */ 227 228 bus_dmamap_t vr_cddmamap; /* control data DMA map */ 229 #define vr_cddma vr_cddmamap->dm_segs[0].ds_addr 230 231 /* 232 * Software state for transmit and receive descriptors. 233 */ 234 struct vr_descsoft vr_txsoft[VR_NTXDESC]; 235 struct vr_descsoft vr_rxsoft[VR_NRXDESC]; 236 237 /* 238 * Control data structures. 239 */ 240 struct vr_control_data *vr_control_data; 241 242 int vr_txpending; /* number of TX requests pending */ 243 int vr_txdirty; /* first dirty TX descriptor */ 244 int vr_txlast; /* last used TX descriptor */ 245 246 int vr_rxptr; /* next ready RX descriptor */ 247 248 #if NRND > 0 249 rndsource_element_t rnd_source; /* random source */ 250 #endif 251 }; 252 253 #define VR_CDTXADDR(sc, x) ((sc)->vr_cddma + VR_CDTXOFF((x))) 254 #define VR_CDRXADDR(sc, x) ((sc)->vr_cddma + VR_CDRXOFF((x))) 255 256 #define VR_CDTX(sc, x) (&(sc)->vr_control_data->vr_txdescs[(x)]) 257 #define VR_CDRX(sc, x) (&(sc)->vr_control_data->vr_rxdescs[(x)]) 258 259 #define VR_DSTX(sc, x) (&(sc)->vr_txsoft[(x)]) 260 #define VR_DSRX(sc, x) (&(sc)->vr_rxsoft[(x)]) 261 262 #define VR_CDTXSYNC(sc, x, ops) \ 263 bus_dmamap_sync((sc)->vr_dmat, (sc)->vr_cddmamap, \ 264 VR_CDTXOFF((x)), sizeof(struct vr_desc), (ops)) 265 266 #define VR_CDRXSYNC(sc, x, ops) \ 267 bus_dmamap_sync((sc)->vr_dmat, (sc)->vr_cddmamap, \ 268 VR_CDRXOFF((x)), sizeof(struct vr_desc), (ops)) 269 270 /* 271 * Note we rely on MCLBYTES being a power of two below. 272 */ 273 #define VR_INIT_RXDESC(sc, i) \ 274 do { \ 275 struct vr_desc *__d = VR_CDRX((sc), (i)); \ 276 struct vr_descsoft *__ds = VR_DSRX((sc), (i)); \ 277 \ 278 __d->vr_next = htole32(VR_CDRXADDR((sc), VR_NEXTRX((i)))); \ 279 __d->vr_status = htole32(VR_RXSTAT_FIRSTFRAG | \ 280 VR_RXSTAT_LASTFRAG | VR_RXSTAT_OWN); \ 281 __d->vr_data = htole32(__ds->ds_dmamap->dm_segs[0].ds_addr); \ 282 __d->vr_ctl = htole32(VR_RXCTL_CHAIN | VR_RXCTL_RX_INTR | \ 283 ((MCLBYTES - 1) & VR_RXCTL_BUFLEN)); \ 284 VR_CDRXSYNC((sc), (i), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 285 } while (/* CONSTCOND */ 0) 286 287 /* 288 * register space access macros 289 */ 290 #define CSR_WRITE_4(sc, reg, val) \ 291 bus_space_write_4(sc->vr_bst, sc->vr_bsh, reg, val) 292 #define CSR_WRITE_2(sc, reg, val) \ 293 bus_space_write_2(sc->vr_bst, sc->vr_bsh, reg, val) 294 #define CSR_WRITE_1(sc, reg, val) \ 295 bus_space_write_1(sc->vr_bst, sc->vr_bsh, reg, val) 296 297 #define CSR_READ_4(sc, reg) \ 298 bus_space_read_4(sc->vr_bst, sc->vr_bsh, reg) 299 #define CSR_READ_2(sc, reg) \ 300 bus_space_read_2(sc->vr_bst, sc->vr_bsh, reg) 301 #define CSR_READ_1(sc, reg) \ 302 bus_space_read_1(sc->vr_bst, sc->vr_bsh, reg) 303 304 #define VR_TIMEOUT 1000 305 306 static int vr_add_rxbuf(struct vr_softc *, int); 307 308 static void vr_rxeof(struct vr_softc *); 309 static void vr_rxeoc(struct vr_softc *); 310 static void vr_txeof(struct vr_softc *); 311 static int vr_intr(void *); 312 static void vr_start(struct ifnet *); 313 static int vr_ioctl(struct ifnet *, u_long, caddr_t); 314 static int vr_init(struct ifnet *); 315 static void vr_stop(struct ifnet *, int); 316 static void vr_rxdrain(struct vr_softc *); 317 static void vr_watchdog(struct ifnet *); 318 static void vr_tick(void *); 319 320 static int vr_ifmedia_upd(struct ifnet *); 321 static void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *); 322 323 static int vr_mii_readreg(struct device *, int, int); 324 static void vr_mii_writereg(struct device *, int, int, int); 325 static void vr_mii_statchg(struct device *); 326 327 static void vr_setmulti(struct vr_softc *); 328 static void vr_reset(struct vr_softc *); 329 330 int vr_copy_small = 0; 331 332 #define VR_SETBIT(sc, reg, x) \ 333 CSR_WRITE_1(sc, reg, \ 334 CSR_READ_1(sc, reg) | (x)) 335 336 #define VR_CLRBIT(sc, reg, x) \ 337 CSR_WRITE_1(sc, reg, \ 338 CSR_READ_1(sc, reg) & ~(x)) 339 340 #define VR_SETBIT16(sc, reg, x) \ 341 CSR_WRITE_2(sc, reg, \ 342 CSR_READ_2(sc, reg) | (x)) 343 344 #define VR_CLRBIT16(sc, reg, x) \ 345 CSR_WRITE_2(sc, reg, \ 346 CSR_READ_2(sc, reg) & ~(x)) 347 348 #define VR_SETBIT32(sc, reg, x) \ 349 CSR_WRITE_4(sc, reg, \ 350 CSR_READ_4(sc, reg) | (x)) 351 352 #define VR_CLRBIT32(sc, reg, x) \ 353 CSR_WRITE_4(sc, reg, \ 354 CSR_READ_4(sc, reg) & ~(x)) 355 356 /* 357 * MII bit-bang glue. 358 */ 359 static u_int32_t vr_mii_bitbang_read(struct device *); 360 static void vr_mii_bitbang_write(struct device *, u_int32_t); 361 362 static const struct mii_bitbang_ops vr_mii_bitbang_ops = { 363 vr_mii_bitbang_read, 364 vr_mii_bitbang_write, 365 { 366 VR_MIICMD_DATAOUT, /* MII_BIT_MDO */ 367 VR_MIICMD_DATAIN, /* MII_BIT_MDI */ 368 VR_MIICMD_CLK, /* MII_BIT_MDC */ 369 VR_MIICMD_DIR, /* MII_BIT_DIR_HOST_PHY */ 370 0, /* MII_BIT_DIR_PHY_HOST */ 371 } 372 }; 373 374 static u_int32_t 375 vr_mii_bitbang_read(struct device *self) 376 { 377 struct vr_softc *sc = (void *) self; 378 379 return (CSR_READ_1(sc, VR_MIICMD)); 380 } 381 382 static void 383 vr_mii_bitbang_write(struct device *self, u_int32_t val) 384 { 385 struct vr_softc *sc = (void *) self; 386 387 CSR_WRITE_1(sc, VR_MIICMD, (val & 0xff) | VR_MIICMD_DIRECTPGM); 388 } 389 390 /* 391 * Read an PHY register through the MII. 392 */ 393 static int 394 vr_mii_readreg(struct device *self, int phy, int reg) 395 { 396 struct vr_softc *sc = (void *) self; 397 398 CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 399 return (mii_bitbang_readreg(self, &vr_mii_bitbang_ops, phy, reg)); 400 } 401 402 /* 403 * Write to a PHY register through the MII. 404 */ 405 static void 406 vr_mii_writereg(struct device *self, int phy, int reg, int val) 407 { 408 struct vr_softc *sc = (void *) self; 409 410 CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 411 mii_bitbang_writereg(self, &vr_mii_bitbang_ops, phy, reg, val); 412 } 413 414 static void 415 vr_mii_statchg(struct device *self) 416 { 417 struct vr_softc *sc = (struct vr_softc *)self; 418 419 /* 420 * In order to fiddle with the 'full-duplex' bit in the netconfig 421 * register, we first have to put the transmit and/or receive logic 422 * in the idle state. 423 */ 424 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 425 426 if (sc->vr_mii.mii_media_active & IFM_FDX) 427 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 428 else 429 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 430 431 if (sc->vr_ec.ec_if.if_flags & IFF_RUNNING) 432 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 433 } 434 435 #define vr_calchash(addr) \ 436 (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26) 437 438 /* 439 * Program the 64-bit multicast hash filter. 440 */ 441 static void 442 vr_setmulti(struct vr_softc *sc) 443 { 444 struct ifnet *ifp; 445 int h = 0; 446 u_int32_t hashes[2] = { 0, 0 }; 447 struct ether_multistep step; 448 struct ether_multi *enm; 449 int mcnt = 0; 450 u_int8_t rxfilt; 451 452 ifp = &sc->vr_ec.ec_if; 453 454 rxfilt = CSR_READ_1(sc, VR_RXCFG); 455 456 if (ifp->if_flags & IFF_PROMISC) { 457 allmulti: 458 ifp->if_flags |= IFF_ALLMULTI; 459 rxfilt |= VR_RXCFG_RX_MULTI; 460 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 461 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 462 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 463 return; 464 } 465 466 /* first, zot all the existing hash bits */ 467 CSR_WRITE_4(sc, VR_MAR0, 0); 468 CSR_WRITE_4(sc, VR_MAR1, 0); 469 470 /* now program new ones */ 471 ETHER_FIRST_MULTI(step, &sc->vr_ec, enm); 472 while (enm != NULL) { 473 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 474 ETHER_ADDR_LEN) != 0) 475 goto allmulti; 476 477 h = vr_calchash(enm->enm_addrlo); 478 479 if (h < 32) 480 hashes[0] |= (1 << h); 481 else 482 hashes[1] |= (1 << (h - 32)); 483 ETHER_NEXT_MULTI(step, enm); 484 mcnt++; 485 } 486 487 ifp->if_flags &= ~IFF_ALLMULTI; 488 489 if (mcnt) 490 rxfilt |= VR_RXCFG_RX_MULTI; 491 else 492 rxfilt &= ~VR_RXCFG_RX_MULTI; 493 494 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 495 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 496 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 497 } 498 499 static void 500 vr_reset(struct vr_softc *sc) 501 { 502 int i; 503 504 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 505 506 for (i = 0; i < VR_TIMEOUT; i++) { 507 DELAY(10); 508 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 509 break; 510 } 511 if (i == VR_TIMEOUT) { 512 if (sc->vr_revid < REV_ID_VT3065_A) { 513 printf("%s: reset never completed!\n", 514 sc->vr_dev.dv_xname); 515 } else { 516 /* Use newer force reset command */ 517 printf("%s: using force reset command.\n", 518 sc->vr_dev.dv_xname); 519 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 520 } 521 } 522 523 /* Wait a little while for the chip to get its brains in order. */ 524 DELAY(1000); 525 } 526 527 /* 528 * Initialize an RX descriptor and attach an MBUF cluster. 529 * Note: the length fields are only 11 bits wide, which means the 530 * largest size we can specify is 2047. This is important because 531 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 532 * overflow the field and make a mess. 533 */ 534 static int 535 vr_add_rxbuf(struct vr_softc *sc, int i) 536 { 537 struct vr_descsoft *ds = VR_DSRX(sc, i); 538 struct mbuf *m_new; 539 int error; 540 541 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 542 if (m_new == NULL) 543 return (ENOBUFS); 544 545 MCLGET(m_new, M_DONTWAIT); 546 if ((m_new->m_flags & M_EXT) == 0) { 547 m_freem(m_new); 548 return (ENOBUFS); 549 } 550 551 if (ds->ds_mbuf != NULL) 552 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 553 554 ds->ds_mbuf = m_new; 555 556 error = bus_dmamap_load(sc->vr_dmat, ds->ds_dmamap, 557 m_new->m_ext.ext_buf, m_new->m_ext.ext_size, NULL, 558 BUS_DMA_READ|BUS_DMA_NOWAIT); 559 if (error) { 560 printf("%s: unable to load rx DMA map %d, error = %d\n", 561 sc->vr_dev.dv_xname, i, error); 562 panic("vr_add_rxbuf"); /* XXX */ 563 } 564 565 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 566 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 567 568 VR_INIT_RXDESC(sc, i); 569 570 return (0); 571 } 572 573 /* 574 * A frame has been uploaded: pass the resulting mbuf chain up to 575 * the higher level protocols. 576 */ 577 static void 578 vr_rxeof(struct vr_softc *sc) 579 { 580 struct mbuf *m; 581 struct ifnet *ifp; 582 struct vr_desc *d; 583 struct vr_descsoft *ds; 584 int i, total_len; 585 u_int32_t rxstat; 586 587 ifp = &sc->vr_ec.ec_if; 588 589 for (i = sc->vr_rxptr;; i = VR_NEXTRX(i)) { 590 d = VR_CDRX(sc, i); 591 ds = VR_DSRX(sc, i); 592 593 VR_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 594 595 rxstat = le32toh(d->vr_status); 596 597 if (rxstat & VR_RXSTAT_OWN) { 598 /* 599 * We have processed all of the receive buffers. 600 */ 601 break; 602 } 603 604 /* 605 * If an error occurs, update stats, clear the 606 * status word and leave the mbuf cluster in place: 607 * it should simply get re-used next time this descriptor 608 * comes up in the ring. 609 */ 610 if (rxstat & VR_RXSTAT_RXERR) { 611 const char *errstr; 612 613 ifp->if_ierrors++; 614 switch (rxstat & 0x000000FF) { 615 case VR_RXSTAT_CRCERR: 616 errstr = "crc error"; 617 break; 618 case VR_RXSTAT_FRAMEALIGNERR: 619 errstr = "frame alignment error"; 620 break; 621 case VR_RXSTAT_FIFOOFLOW: 622 errstr = "FIFO overflow"; 623 break; 624 case VR_RXSTAT_GIANT: 625 errstr = "received giant packet"; 626 break; 627 case VR_RXSTAT_RUNT: 628 errstr = "received runt packet"; 629 break; 630 case VR_RXSTAT_BUSERR: 631 errstr = "system bus error"; 632 break; 633 case VR_RXSTAT_BUFFERR: 634 errstr = "rx buffer error"; 635 break; 636 default: 637 errstr = "unknown rx error"; 638 break; 639 } 640 printf("%s: receive error: %s\n", sc->vr_dev.dv_xname, 641 errstr); 642 643 VR_INIT_RXDESC(sc, i); 644 645 continue; 646 } else if (!(rxstat & VR_RXSTAT_FIRSTFRAG) || 647 !(rxstat & VR_RXSTAT_LASTFRAG)) { 648 /* 649 * This driver expects to receive whole packets every 650 * time. In case we receive a fragment that is not 651 * a complete packet, we discard it. 652 */ 653 ifp->if_ierrors++; 654 655 printf("%s: receive error: incomplete frame; " 656 "size = %d, status = 0x%x\n", 657 sc->vr_dev.dv_xname, 658 VR_RXBYTES(le32toh(d->vr_status)), rxstat); 659 660 VR_INIT_RXDESC(sc, i); 661 662 continue; 663 } 664 665 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 666 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 667 668 /* No errors; receive the packet. */ 669 total_len = VR_RXBYTES(le32toh(d->vr_status)); 670 #ifdef DIAGNOSTIC 671 if (total_len == 0) { 672 /* 673 * If we receive a zero-length packet, we probably 674 * missed to handle an error condition above. 675 * Discard it to avoid a later crash. 676 */ 677 ifp->if_ierrors++; 678 679 printf("%s: receive error: zero-length packet; " 680 "status = 0x%x\n", 681 sc->vr_dev.dv_xname, rxstat); 682 683 VR_INIT_RXDESC(sc, i); 684 685 continue; 686 } 687 #endif 688 689 /* 690 * The Rhine chip includes the CRC with every packet. 691 * Trim it off here. 692 */ 693 total_len -= ETHER_CRC_LEN; 694 695 #ifdef __NO_STRICT_ALIGNMENT 696 /* 697 * If the packet is small enough to fit in a 698 * single header mbuf, allocate one and copy 699 * the data into it. This greatly reduces 700 * memory consumption when we receive lots 701 * of small packets. 702 * 703 * Otherwise, we add a new buffer to the receive 704 * chain. If this fails, we drop the packet and 705 * recycle the old buffer. 706 */ 707 if (vr_copy_small != 0 && total_len <= MHLEN) { 708 MGETHDR(m, M_DONTWAIT, MT_DATA); 709 if (m == NULL) 710 goto dropit; 711 memcpy(mtod(m, caddr_t), 712 mtod(ds->ds_mbuf, caddr_t), total_len); 713 VR_INIT_RXDESC(sc, i); 714 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 715 ds->ds_dmamap->dm_mapsize, 716 BUS_DMASYNC_PREREAD); 717 } else { 718 m = ds->ds_mbuf; 719 if (vr_add_rxbuf(sc, i) == ENOBUFS) { 720 dropit: 721 ifp->if_ierrors++; 722 VR_INIT_RXDESC(sc, i); 723 bus_dmamap_sync(sc->vr_dmat, 724 ds->ds_dmamap, 0, 725 ds->ds_dmamap->dm_mapsize, 726 BUS_DMASYNC_PREREAD); 727 continue; 728 } 729 } 730 #else 731 /* 732 * The Rhine's packet buffers must be 4-byte aligned. 733 * But this means that the data after the Ethernet header 734 * is misaligned. We must allocate a new buffer and 735 * copy the data, shifted forward 2 bytes. 736 */ 737 MGETHDR(m, M_DONTWAIT, MT_DATA); 738 if (m == NULL) { 739 dropit: 740 ifp->if_ierrors++; 741 VR_INIT_RXDESC(sc, i); 742 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 743 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 744 continue; 745 } 746 if (total_len > (MHLEN - 2)) { 747 MCLGET(m, M_DONTWAIT); 748 if ((m->m_flags & M_EXT) == 0) { 749 m_freem(m); 750 goto dropit; 751 } 752 } 753 m->m_data += 2; 754 755 /* 756 * Note that we use clusters for incoming frames, so the 757 * buffer is virtually contiguous. 758 */ 759 memcpy(mtod(m, caddr_t), mtod(ds->ds_mbuf, caddr_t), 760 total_len); 761 762 /* Allow the receive descriptor to continue using its mbuf. */ 763 VR_INIT_RXDESC(sc, i); 764 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 765 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 766 #endif /* __NO_STRICT_ALIGNMENT */ 767 768 ifp->if_ipackets++; 769 m->m_pkthdr.rcvif = ifp; 770 m->m_pkthdr.len = m->m_len = total_len; 771 #if NBPFILTER > 0 772 /* 773 * Handle BPF listeners. Let the BPF user see the packet, but 774 * don't pass it up to the ether_input() layer unless it's 775 * a broadcast packet, multicast packet, matches our ethernet 776 * address or the interface is in promiscuous mode. 777 */ 778 if (ifp->if_bpf) 779 bpf_mtap(ifp->if_bpf, m); 780 #endif 781 /* Pass it on. */ 782 (*ifp->if_input)(ifp, m); 783 } 784 785 /* Update the receive pointer. */ 786 sc->vr_rxptr = i; 787 } 788 789 void 790 vr_rxeoc(struct vr_softc *sc) 791 { 792 793 vr_rxeof(sc); 794 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 795 CSR_WRITE_4(sc, VR_RXADDR, VR_CDRXADDR(sc, sc->vr_rxptr)); 796 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 797 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 798 } 799 800 /* 801 * A frame was downloaded to the chip. It's safe for us to clean up 802 * the list buffers. 803 */ 804 static void 805 vr_txeof(struct vr_softc *sc) 806 { 807 struct ifnet *ifp = &sc->vr_ec.ec_if; 808 struct vr_desc *d; 809 struct vr_descsoft *ds; 810 u_int32_t txstat; 811 int i; 812 813 ifp->if_flags &= ~IFF_OACTIVE; 814 815 /* 816 * Go through our tx list and free mbufs for those 817 * frames that have been transmitted. 818 */ 819 for (i = sc->vr_txdirty; sc->vr_txpending != 0; 820 i = VR_NEXTTX(i), sc->vr_txpending--) { 821 d = VR_CDTX(sc, i); 822 ds = VR_DSTX(sc, i); 823 824 VR_CDTXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 825 826 txstat = le32toh(d->vr_status); 827 if (txstat & VR_TXSTAT_OWN) 828 break; 829 830 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 831 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 832 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 833 m_freem(ds->ds_mbuf); 834 ds->ds_mbuf = NULL; 835 836 if (txstat & VR_TXSTAT_ERRSUM) { 837 ifp->if_oerrors++; 838 if (txstat & VR_TXSTAT_DEFER) 839 ifp->if_collisions++; 840 if (txstat & VR_TXSTAT_LATECOLL) 841 ifp->if_collisions++; 842 } 843 844 ifp->if_collisions += (txstat & VR_TXSTAT_COLLCNT) >> 3; 845 ifp->if_opackets++; 846 } 847 848 /* Update the dirty transmit buffer pointer. */ 849 sc->vr_txdirty = i; 850 851 /* 852 * Cancel the watchdog timer if there are no pending 853 * transmissions. 854 */ 855 if (sc->vr_txpending == 0) 856 ifp->if_timer = 0; 857 } 858 859 static int 860 vr_intr(void *arg) 861 { 862 struct vr_softc *sc; 863 struct ifnet *ifp; 864 u_int16_t status; 865 int handled = 0, dotx = 0; 866 867 sc = arg; 868 ifp = &sc->vr_ec.ec_if; 869 870 /* Suppress unwanted interrupts. */ 871 if ((ifp->if_flags & IFF_UP) == 0) { 872 vr_stop(ifp, 1); 873 return (0); 874 } 875 876 /* Disable interrupts. */ 877 CSR_WRITE_2(sc, VR_IMR, 0x0000); 878 879 for (;;) { 880 status = CSR_READ_2(sc, VR_ISR); 881 if (status) 882 CSR_WRITE_2(sc, VR_ISR, status); 883 884 if ((status & VR_INTRS) == 0) 885 break; 886 887 handled = 1; 888 889 #if NRND > 0 890 if (RND_ENABLED(&sc->rnd_source)) 891 rnd_add_uint32(&sc->rnd_source, status); 892 #endif 893 894 if (status & VR_ISR_RX_OK) 895 vr_rxeof(sc); 896 897 if (status & 898 (VR_ISR_RX_ERR | VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW | 899 VR_ISR_RX_DROPPED)) 900 vr_rxeoc(sc); 901 902 if (status & VR_ISR_TX_OK) { 903 dotx = 1; 904 vr_txeof(sc); 905 } 906 907 if (status & (VR_ISR_TX_UNDERRUN | VR_ISR_TX_ABRT)) { 908 if (status & VR_ISR_TX_UNDERRUN) 909 printf("%s: transmit underrun\n", 910 sc->vr_dev.dv_xname); 911 if (status & VR_ISR_TX_ABRT) 912 printf("%s: transmit aborted\n", 913 sc->vr_dev.dv_xname); 914 ifp->if_oerrors++; 915 dotx = 1; 916 vr_txeof(sc); 917 if (sc->vr_txpending) { 918 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 919 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 920 } 921 /* 922 * Unfortunately many cards get stuck after 923 * aborted transmits, so we reset them. 924 */ 925 if (status & VR_ISR_TX_ABRT) { 926 printf("%s: restarting\n", sc->vr_dev.dv_xname); 927 dotx = 0; 928 (void) vr_init(ifp); 929 } 930 } 931 932 if (status & VR_ISR_BUSERR) { 933 printf("%s: PCI bus error\n", sc->vr_dev.dv_xname); 934 /* vr_init() calls vr_start() */ 935 dotx = 0; 936 (void) vr_init(ifp); 937 } 938 } 939 940 /* Re-enable interrupts. */ 941 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 942 943 if (dotx) 944 vr_start(ifp); 945 946 return (handled); 947 } 948 949 /* 950 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 951 * to the mbuf data regions directly in the transmit lists. We also save a 952 * copy of the pointers since the transmit list fragment pointers are 953 * physical addresses. 954 */ 955 static void 956 vr_start(struct ifnet *ifp) 957 { 958 struct vr_softc *sc = ifp->if_softc; 959 struct mbuf *m0, *m; 960 struct vr_desc *d; 961 struct vr_descsoft *ds; 962 int error, firsttx, nexttx, opending; 963 964 /* 965 * Remember the previous txpending and the first transmit 966 * descriptor we use. 967 */ 968 opending = sc->vr_txpending; 969 firsttx = VR_NEXTTX(sc->vr_txlast); 970 971 /* 972 * Loop through the send queue, setting up transmit descriptors 973 * until we drain the queue, or use up all available transmit 974 * descriptors. 975 */ 976 while (sc->vr_txpending < VR_NTXDESC) { 977 /* 978 * Grab a packet off the queue. 979 */ 980 IFQ_POLL(&ifp->if_snd, m0); 981 if (m0 == NULL) 982 break; 983 m = NULL; 984 985 /* 986 * Get the next available transmit descriptor. 987 */ 988 nexttx = VR_NEXTTX(sc->vr_txlast); 989 d = VR_CDTX(sc, nexttx); 990 ds = VR_DSTX(sc, nexttx); 991 992 /* 993 * Load the DMA map. If this fails, the packet didn't 994 * fit in one DMA segment, and we need to copy. Note, 995 * the packet must also be aligned. 996 * if the packet is too small, copy it too, so we're sure 997 * we have enough room for the pad buffer. 998 */ 999 if ((mtod(m0, uintptr_t) & 3) != 0 || 1000 m0->m_pkthdr.len < VR_MIN_FRAMELEN || 1001 bus_dmamap_load_mbuf(sc->vr_dmat, ds->ds_dmamap, m0, 1002 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1003 MGETHDR(m, M_DONTWAIT, MT_DATA); 1004 if (m == NULL) { 1005 printf("%s: unable to allocate Tx mbuf\n", 1006 sc->vr_dev.dv_xname); 1007 break; 1008 } 1009 if (m0->m_pkthdr.len > MHLEN) { 1010 MCLGET(m, M_DONTWAIT); 1011 if ((m->m_flags & M_EXT) == 0) { 1012 printf("%s: unable to allocate Tx " 1013 "cluster\n", sc->vr_dev.dv_xname); 1014 m_freem(m); 1015 break; 1016 } 1017 } 1018 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1019 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1020 /* 1021 * The Rhine doesn't auto-pad, so we have to do this 1022 * ourselves. 1023 */ 1024 if (m0->m_pkthdr.len < VR_MIN_FRAMELEN) { 1025 memset(mtod(m, caddr_t) + m0->m_pkthdr.len, 1026 0, VR_MIN_FRAMELEN - m0->m_pkthdr.len); 1027 m->m_pkthdr.len = m->m_len = VR_MIN_FRAMELEN; 1028 } 1029 error = bus_dmamap_load_mbuf(sc->vr_dmat, 1030 ds->ds_dmamap, m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1031 if (error) { 1032 m_freem(m); 1033 printf("%s: unable to load Tx buffer, " 1034 "error = %d\n", sc->vr_dev.dv_xname, error); 1035 break; 1036 } 1037 } 1038 1039 IFQ_DEQUEUE(&ifp->if_snd, m0); 1040 if (m != NULL) { 1041 m_freem(m0); 1042 m0 = m; 1043 } 1044 1045 /* Sync the DMA map. */ 1046 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 1047 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1048 1049 /* 1050 * Store a pointer to the packet so we can free it later. 1051 */ 1052 ds->ds_mbuf = m0; 1053 1054 #if NBPFILTER > 0 1055 /* 1056 * If there's a BPF listener, bounce a copy of this frame 1057 * to him. 1058 */ 1059 if (ifp->if_bpf) 1060 bpf_mtap(ifp->if_bpf, m0); 1061 #endif 1062 1063 /* 1064 * Fill in the transmit descriptor. 1065 */ 1066 d->vr_data = htole32(ds->ds_dmamap->dm_segs[0].ds_addr); 1067 d->vr_ctl = htole32(m0->m_pkthdr.len); 1068 d->vr_ctl |= htole32(VR_TXCTL_FIRSTFRAG | VR_TXCTL_LASTFRAG); 1069 1070 /* 1071 * If this is the first descriptor we're enqueuing, 1072 * don't give it to the Rhine yet. That could cause 1073 * a race condition. We'll do it below. 1074 */ 1075 if (nexttx == firsttx) 1076 d->vr_status = 0; 1077 else 1078 d->vr_status = htole32(VR_TXSTAT_OWN); 1079 1080 VR_CDTXSYNC(sc, nexttx, 1081 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1082 1083 /* Advance the tx pointer. */ 1084 sc->vr_txpending++; 1085 sc->vr_txlast = nexttx; 1086 } 1087 1088 if (sc->vr_txpending == VR_NTXDESC) { 1089 /* No more slots left; notify upper layer. */ 1090 ifp->if_flags |= IFF_OACTIVE; 1091 } 1092 1093 if (sc->vr_txpending != opending) { 1094 /* 1095 * We enqueued packets. If the transmitter was idle, 1096 * reset the txdirty pointer. 1097 */ 1098 if (opending == 0) 1099 sc->vr_txdirty = firsttx; 1100 1101 /* 1102 * Cause a transmit interrupt to happen on the 1103 * last packet we enqueued. 1104 */ 1105 VR_CDTX(sc, sc->vr_txlast)->vr_ctl |= htole32(VR_TXCTL_FINT); 1106 VR_CDTXSYNC(sc, sc->vr_txlast, 1107 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1108 1109 /* 1110 * The entire packet chain is set up. Give the 1111 * first descriptor to the Rhine now. 1112 */ 1113 VR_CDTX(sc, firsttx)->vr_status = htole32(VR_TXSTAT_OWN); 1114 VR_CDTXSYNC(sc, firsttx, 1115 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1116 1117 /* Start the transmitter. */ 1118 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1119 1120 /* Set the watchdog timer in case the chip flakes out. */ 1121 ifp->if_timer = 5; 1122 } 1123 } 1124 1125 /* 1126 * Initialize the interface. Must be called at splnet. 1127 */ 1128 static int 1129 vr_init(struct ifnet *ifp) 1130 { 1131 struct vr_softc *sc = ifp->if_softc; 1132 struct vr_desc *d; 1133 struct vr_descsoft *ds; 1134 int i, error = 0; 1135 1136 /* Cancel pending I/O. */ 1137 vr_stop(ifp, 0); 1138 1139 /* Reset the Rhine to a known state. */ 1140 vr_reset(sc); 1141 1142 /* set DMA length in BCR0 and BCR1 */ 1143 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1144 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1145 1146 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1147 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTH_128BYTES); 1148 1149 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1150 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTH_STORENFWD); 1151 1152 /* set DMA threshold length in RXCFG and TXCFG */ 1153 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1154 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1155 1156 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1157 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1158 1159 /* 1160 * Initialize the transmit descriptor ring. txlast is initialized 1161 * to the end of the list so that it will wrap around to the first 1162 * descriptor when the first packet is transmitted. 1163 */ 1164 for (i = 0; i < VR_NTXDESC; i++) { 1165 d = VR_CDTX(sc, i); 1166 memset(d, 0, sizeof(struct vr_desc)); 1167 d->vr_next = htole32(VR_CDTXADDR(sc, VR_NEXTTX(i))); 1168 VR_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1169 } 1170 sc->vr_txpending = 0; 1171 sc->vr_txdirty = 0; 1172 sc->vr_txlast = VR_NTXDESC - 1; 1173 1174 /* 1175 * Initialize the receive descriptor ring. 1176 */ 1177 for (i = 0; i < VR_NRXDESC; i++) { 1178 ds = VR_DSRX(sc, i); 1179 if (ds->ds_mbuf == NULL) { 1180 if ((error = vr_add_rxbuf(sc, i)) != 0) { 1181 printf("%s: unable to allocate or map rx " 1182 "buffer %d, error = %d\n", 1183 sc->vr_dev.dv_xname, i, error); 1184 /* 1185 * XXX Should attempt to run with fewer receive 1186 * XXX buffers instead of just failing. 1187 */ 1188 vr_rxdrain(sc); 1189 goto out; 1190 } 1191 } else 1192 VR_INIT_RXDESC(sc, i); 1193 } 1194 sc->vr_rxptr = 0; 1195 1196 /* If we want promiscuous mode, set the allframes bit. */ 1197 if (ifp->if_flags & IFF_PROMISC) 1198 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1199 else 1200 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1201 1202 /* Set capture broadcast bit to capture broadcast frames. */ 1203 if (ifp->if_flags & IFF_BROADCAST) 1204 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1205 else 1206 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1207 1208 /* Program the multicast filter, if necessary. */ 1209 vr_setmulti(sc); 1210 1211 /* Give the transmit and receive rings to the Rhine. */ 1212 CSR_WRITE_4(sc, VR_RXADDR, VR_CDRXADDR(sc, sc->vr_rxptr)); 1213 CSR_WRITE_4(sc, VR_TXADDR, VR_CDTXADDR(sc, VR_NEXTTX(sc->vr_txlast))); 1214 1215 /* Set current media. */ 1216 mii_mediachg(&sc->vr_mii); 1217 1218 /* Enable receiver and transmitter. */ 1219 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1220 VR_CMD_TX_ON|VR_CMD_RX_ON| 1221 VR_CMD_RX_GO); 1222 1223 /* Enable interrupts. */ 1224 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1225 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1226 1227 ifp->if_flags |= IFF_RUNNING; 1228 ifp->if_flags &= ~IFF_OACTIVE; 1229 1230 /* Start one second timer. */ 1231 callout_reset(&sc->vr_tick_ch, hz, vr_tick, sc); 1232 1233 /* Attempt to start output on the interface. */ 1234 vr_start(ifp); 1235 1236 out: 1237 if (error) 1238 printf("%s: interface not running\n", sc->vr_dev.dv_xname); 1239 return (error); 1240 } 1241 1242 /* 1243 * Set media options. 1244 */ 1245 static int 1246 vr_ifmedia_upd(struct ifnet *ifp) 1247 { 1248 struct vr_softc *sc = ifp->if_softc; 1249 1250 if (ifp->if_flags & IFF_UP) 1251 mii_mediachg(&sc->vr_mii); 1252 return (0); 1253 } 1254 1255 /* 1256 * Report current media status. 1257 */ 1258 static void 1259 vr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1260 { 1261 struct vr_softc *sc = ifp->if_softc; 1262 1263 mii_pollstat(&sc->vr_mii); 1264 ifmr->ifm_status = sc->vr_mii.mii_media_status; 1265 ifmr->ifm_active = sc->vr_mii.mii_media_active; 1266 } 1267 1268 static int 1269 vr_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1270 { 1271 struct vr_softc *sc = ifp->if_softc; 1272 struct ifreq *ifr = (struct ifreq *)data; 1273 int s, error = 0; 1274 1275 s = splnet(); 1276 1277 switch (command) { 1278 case SIOCGIFMEDIA: 1279 case SIOCSIFMEDIA: 1280 error = ifmedia_ioctl(ifp, ifr, &sc->vr_mii.mii_media, command); 1281 break; 1282 1283 default: 1284 error = ether_ioctl(ifp, command, data); 1285 if (error == ENETRESET) { 1286 /* 1287 * Multicast list has changed; set the hardware filter 1288 * accordingly. 1289 */ 1290 if (ifp->if_flags & IFF_RUNNING) 1291 vr_setmulti(sc); 1292 error = 0; 1293 } 1294 break; 1295 } 1296 1297 splx(s); 1298 return (error); 1299 } 1300 1301 static void 1302 vr_watchdog(struct ifnet *ifp) 1303 { 1304 struct vr_softc *sc = ifp->if_softc; 1305 1306 printf("%s: device timeout\n", sc->vr_dev.dv_xname); 1307 ifp->if_oerrors++; 1308 1309 (void) vr_init(ifp); 1310 } 1311 1312 /* 1313 * One second timer, used to tick MII. 1314 */ 1315 static void 1316 vr_tick(void *arg) 1317 { 1318 struct vr_softc *sc = arg; 1319 int s; 1320 1321 s = splnet(); 1322 mii_tick(&sc->vr_mii); 1323 splx(s); 1324 1325 callout_reset(&sc->vr_tick_ch, hz, vr_tick, sc); 1326 } 1327 1328 /* 1329 * Drain the receive queue. 1330 */ 1331 static void 1332 vr_rxdrain(struct vr_softc *sc) 1333 { 1334 struct vr_descsoft *ds; 1335 int i; 1336 1337 for (i = 0; i < VR_NRXDESC; i++) { 1338 ds = VR_DSRX(sc, i); 1339 if (ds->ds_mbuf != NULL) { 1340 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 1341 m_freem(ds->ds_mbuf); 1342 ds->ds_mbuf = NULL; 1343 } 1344 } 1345 } 1346 1347 /* 1348 * Stop the adapter and free any mbufs allocated to the 1349 * transmit lists. 1350 */ 1351 static void 1352 vr_stop(struct ifnet *ifp, int disable) 1353 { 1354 struct vr_softc *sc = ifp->if_softc; 1355 struct vr_descsoft *ds; 1356 int i; 1357 1358 /* Cancel one second timer. */ 1359 callout_stop(&sc->vr_tick_ch); 1360 1361 /* Down the MII. */ 1362 mii_down(&sc->vr_mii); 1363 1364 ifp = &sc->vr_ec.ec_if; 1365 ifp->if_timer = 0; 1366 1367 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1368 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1369 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1370 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1371 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1372 1373 /* 1374 * Release any queued transmit buffers. 1375 */ 1376 for (i = 0; i < VR_NTXDESC; i++) { 1377 ds = VR_DSTX(sc, i); 1378 if (ds->ds_mbuf != NULL) { 1379 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 1380 m_freem(ds->ds_mbuf); 1381 ds->ds_mbuf = NULL; 1382 } 1383 } 1384 1385 if (disable) 1386 vr_rxdrain(sc); 1387 1388 /* 1389 * Mark the interface down and cancel the watchdog timer. 1390 */ 1391 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1392 ifp->if_timer = 0; 1393 } 1394 1395 static int vr_probe(struct device *, struct cfdata *, void *); 1396 static void vr_attach(struct device *, struct device *, void *); 1397 static void vr_shutdown(void *); 1398 1399 CFATTACH_DECL(vr, sizeof (struct vr_softc), 1400 vr_probe, vr_attach, NULL, NULL); 1401 1402 static struct vr_type * 1403 vr_lookup(struct pci_attach_args *pa) 1404 { 1405 struct vr_type *vrt; 1406 1407 for (vrt = vr_devs; vrt->vr_name != NULL; vrt++) { 1408 if (PCI_VENDOR(pa->pa_id) == vrt->vr_vid && 1409 PCI_PRODUCT(pa->pa_id) == vrt->vr_did) 1410 return (vrt); 1411 } 1412 return (NULL); 1413 } 1414 1415 static int 1416 vr_probe(struct device *parent, struct cfdata *match, void *aux) 1417 { 1418 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1419 1420 if (vr_lookup(pa) != NULL) 1421 return (1); 1422 1423 return (0); 1424 } 1425 1426 /* 1427 * Stop all chip I/O so that the kernel's probe routines don't 1428 * get confused by errant DMAs when rebooting. 1429 */ 1430 static void 1431 vr_shutdown(void *arg) 1432 { 1433 struct vr_softc *sc = (struct vr_softc *)arg; 1434 1435 vr_stop(&sc->vr_ec.ec_if, 1); 1436 } 1437 1438 /* 1439 * Attach the interface. Allocate softc structures, do ifmedia 1440 * setup and ethernet/BPF attach. 1441 */ 1442 static void 1443 vr_attach(struct device *parent, struct device *self, void *aux) 1444 { 1445 struct vr_softc *sc = (struct vr_softc *) self; 1446 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 1447 bus_dma_segment_t seg; 1448 struct vr_type *vrt; 1449 u_int32_t pmreg, reg; 1450 struct ifnet *ifp; 1451 u_char eaddr[ETHER_ADDR_LEN]; 1452 int i, rseg, error; 1453 1454 #define PCI_CONF_WRITE(r, v) pci_conf_write(pa->pa_pc, pa->pa_tag, (r), (v)) 1455 #define PCI_CONF_READ(r) pci_conf_read(pa->pa_pc, pa->pa_tag, (r)) 1456 1457 callout_init(&sc->vr_tick_ch); 1458 1459 vrt = vr_lookup(pa); 1460 if (vrt == NULL) { 1461 printf("\n"); 1462 panic("vr_attach: impossible"); 1463 } 1464 1465 printf(": %s Ethernet\n", vrt->vr_name); 1466 1467 /* 1468 * Handle power management nonsense. 1469 */ 1470 1471 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 1472 PCI_CAP_PWRMGMT, &pmreg, 0)) { 1473 reg = PCI_CONF_READ(pmreg + PCI_PMCSR); 1474 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 1475 u_int32_t iobase, membase, irq; 1476 1477 /* Save important PCI config data. */ 1478 iobase = PCI_CONF_READ(VR_PCI_LOIO); 1479 membase = PCI_CONF_READ(VR_PCI_LOMEM); 1480 irq = PCI_CONF_READ(PCI_INTERRUPT_REG); 1481 1482 /* Reset the power state. */ 1483 printf("%s: chip is in D%d power mode " 1484 "-- setting to D0\n", 1485 sc->vr_dev.dv_xname, reg & PCI_PMCSR_STATE_MASK); 1486 reg = (reg & ~PCI_PMCSR_STATE_MASK) | 1487 PCI_PMCSR_STATE_D0; 1488 PCI_CONF_WRITE(pmreg + PCI_PMCSR, reg); 1489 1490 /* Restore PCI config data. */ 1491 PCI_CONF_WRITE(VR_PCI_LOIO, iobase); 1492 PCI_CONF_WRITE(VR_PCI_LOMEM, membase); 1493 PCI_CONF_WRITE(PCI_INTERRUPT_REG, irq); 1494 } 1495 } 1496 1497 /* Make sure bus mastering is enabled. */ 1498 reg = PCI_CONF_READ(PCI_COMMAND_STATUS_REG); 1499 reg |= PCI_COMMAND_MASTER_ENABLE; 1500 PCI_CONF_WRITE(PCI_COMMAND_STATUS_REG, reg); 1501 1502 /* Get revision */ 1503 sc->vr_revid = PCI_REVISION(pa->pa_class); 1504 1505 /* 1506 * Map control/status registers. 1507 */ 1508 { 1509 bus_space_tag_t iot, memt; 1510 bus_space_handle_t ioh, memh; 1511 int ioh_valid, memh_valid; 1512 pci_intr_handle_t intrhandle; 1513 const char *intrstr; 1514 1515 ioh_valid = (pci_mapreg_map(pa, VR_PCI_LOIO, 1516 PCI_MAPREG_TYPE_IO, 0, 1517 &iot, &ioh, NULL, NULL) == 0); 1518 memh_valid = (pci_mapreg_map(pa, VR_PCI_LOMEM, 1519 PCI_MAPREG_TYPE_MEM | 1520 PCI_MAPREG_MEM_TYPE_32BIT, 1521 0, &memt, &memh, NULL, NULL) == 0); 1522 #if defined(VR_USEIOSPACE) 1523 if (ioh_valid) { 1524 sc->vr_bst = iot; 1525 sc->vr_bsh = ioh; 1526 } else if (memh_valid) { 1527 sc->vr_bst = memt; 1528 sc->vr_bsh = memh; 1529 } 1530 #else 1531 if (memh_valid) { 1532 sc->vr_bst = memt; 1533 sc->vr_bsh = memh; 1534 } else if (ioh_valid) { 1535 sc->vr_bst = iot; 1536 sc->vr_bsh = ioh; 1537 } 1538 #endif 1539 else { 1540 printf(": unable to map device registers\n"); 1541 return; 1542 } 1543 1544 /* Allocate interrupt */ 1545 if (pci_intr_map(pa, &intrhandle)) { 1546 printf("%s: couldn't map interrupt\n", 1547 sc->vr_dev.dv_xname); 1548 return; 1549 } 1550 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 1551 sc->vr_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 1552 vr_intr, sc); 1553 if (sc->vr_ih == NULL) { 1554 printf("%s: couldn't establish interrupt", 1555 sc->vr_dev.dv_xname); 1556 if (intrstr != NULL) 1557 printf(" at %s", intrstr); 1558 printf("\n"); 1559 } 1560 printf("%s: interrupting at %s\n", 1561 sc->vr_dev.dv_xname, intrstr); 1562 } 1563 1564 /* 1565 * Windows may put the chip in suspend mode when it 1566 * shuts down. Be sure to kick it in the head to wake it 1567 * up again. 1568 */ 1569 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 1570 1571 /* Reset the adapter. */ 1572 vr_reset(sc); 1573 1574 /* 1575 * Get station address. The way the Rhine chips work, 1576 * you're not allowed to directly access the EEPROM once 1577 * they've been programmed a special way. Consequently, 1578 * we need to read the node address from the PAR0 and PAR1 1579 * registers. 1580 * 1581 * XXXSCW: On the Rhine III, setting VR_EECSR_LOAD forces a reload 1582 * of the *whole* EEPROM, not just the MAC address. This is 1583 * pretty pointless since the chip does this automatically 1584 * at powerup/reset. 1585 * I suspect the same thing applies to the other Rhine 1586 * variants, but in the absence of a data sheet for those 1587 * (and the lack of anyone else noticing the problems this 1588 * causes) I'm going to retain the old behaviour for the 1589 * other parts. 1590 */ 1591 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT6105 && 1592 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT6102) { 1593 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 1594 DELAY(200); 1595 } 1596 for (i = 0; i < ETHER_ADDR_LEN; i++) 1597 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 1598 1599 /* 1600 * A Rhine chip was detected. Inform the world. 1601 */ 1602 printf("%s: Ethernet address: %s\n", 1603 sc->vr_dev.dv_xname, ether_sprintf(eaddr)); 1604 1605 memcpy(sc->vr_enaddr, eaddr, ETHER_ADDR_LEN); 1606 1607 sc->vr_dmat = pa->pa_dmat; 1608 1609 /* 1610 * Allocate the control data structures, and create and load 1611 * the DMA map for it. 1612 */ 1613 if ((error = bus_dmamem_alloc(sc->vr_dmat, 1614 sizeof(struct vr_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 1615 0)) != 0) { 1616 printf("%s: unable to allocate control data, error = %d\n", 1617 sc->vr_dev.dv_xname, error); 1618 goto fail_0; 1619 } 1620 1621 if ((error = bus_dmamem_map(sc->vr_dmat, &seg, rseg, 1622 sizeof(struct vr_control_data), (caddr_t *)&sc->vr_control_data, 1623 BUS_DMA_COHERENT)) != 0) { 1624 printf("%s: unable to map control data, error = %d\n", 1625 sc->vr_dev.dv_xname, error); 1626 goto fail_1; 1627 } 1628 1629 if ((error = bus_dmamap_create(sc->vr_dmat, 1630 sizeof(struct vr_control_data), 1, 1631 sizeof(struct vr_control_data), 0, 0, 1632 &sc->vr_cddmamap)) != 0) { 1633 printf("%s: unable to create control data DMA map, " 1634 "error = %d\n", sc->vr_dev.dv_xname, error); 1635 goto fail_2; 1636 } 1637 1638 if ((error = bus_dmamap_load(sc->vr_dmat, sc->vr_cddmamap, 1639 sc->vr_control_data, sizeof(struct vr_control_data), NULL, 1640 0)) != 0) { 1641 printf("%s: unable to load control data DMA map, error = %d\n", 1642 sc->vr_dev.dv_xname, error); 1643 goto fail_3; 1644 } 1645 1646 /* 1647 * Create the transmit buffer DMA maps. 1648 */ 1649 for (i = 0; i < VR_NTXDESC; i++) { 1650 if ((error = bus_dmamap_create(sc->vr_dmat, MCLBYTES, 1651 1, MCLBYTES, 0, 0, 1652 &VR_DSTX(sc, i)->ds_dmamap)) != 0) { 1653 printf("%s: unable to create tx DMA map %d, " 1654 "error = %d\n", sc->vr_dev.dv_xname, i, error); 1655 goto fail_4; 1656 } 1657 } 1658 1659 /* 1660 * Create the receive buffer DMA maps. 1661 */ 1662 for (i = 0; i < VR_NRXDESC; i++) { 1663 if ((error = bus_dmamap_create(sc->vr_dmat, MCLBYTES, 1, 1664 MCLBYTES, 0, 0, 1665 &VR_DSRX(sc, i)->ds_dmamap)) != 0) { 1666 printf("%s: unable to create rx DMA map %d, " 1667 "error = %d\n", sc->vr_dev.dv_xname, i, error); 1668 goto fail_5; 1669 } 1670 VR_DSRX(sc, i)->ds_mbuf = NULL; 1671 } 1672 1673 ifp = &sc->vr_ec.ec_if; 1674 ifp->if_softc = sc; 1675 ifp->if_mtu = ETHERMTU; 1676 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1677 ifp->if_ioctl = vr_ioctl; 1678 ifp->if_start = vr_start; 1679 ifp->if_watchdog = vr_watchdog; 1680 ifp->if_init = vr_init; 1681 ifp->if_stop = vr_stop; 1682 IFQ_SET_READY(&ifp->if_snd); 1683 1684 strcpy(ifp->if_xname, sc->vr_dev.dv_xname); 1685 1686 /* 1687 * Initialize MII/media info. 1688 */ 1689 sc->vr_mii.mii_ifp = ifp; 1690 sc->vr_mii.mii_readreg = vr_mii_readreg; 1691 sc->vr_mii.mii_writereg = vr_mii_writereg; 1692 sc->vr_mii.mii_statchg = vr_mii_statchg; 1693 ifmedia_init(&sc->vr_mii.mii_media, IFM_IMASK, vr_ifmedia_upd, 1694 vr_ifmedia_sts); 1695 mii_attach(&sc->vr_dev, &sc->vr_mii, 0xffffffff, MII_PHY_ANY, 1696 MII_OFFSET_ANY, MIIF_FORCEANEG); 1697 if (LIST_FIRST(&sc->vr_mii.mii_phys) == NULL) { 1698 ifmedia_add(&sc->vr_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1699 ifmedia_set(&sc->vr_mii.mii_media, IFM_ETHER|IFM_NONE); 1700 } else 1701 ifmedia_set(&sc->vr_mii.mii_media, IFM_ETHER|IFM_AUTO); 1702 1703 /* 1704 * Call MI attach routines. 1705 */ 1706 if_attach(ifp); 1707 ether_ifattach(ifp, sc->vr_enaddr); 1708 #if NRND > 0 1709 rnd_attach_source(&sc->rnd_source, sc->vr_dev.dv_xname, 1710 RND_TYPE_NET, 0); 1711 #endif 1712 1713 sc->vr_ats = shutdownhook_establish(vr_shutdown, sc); 1714 if (sc->vr_ats == NULL) 1715 printf("%s: warning: couldn't establish shutdown hook\n", 1716 sc->vr_dev.dv_xname); 1717 return; 1718 1719 fail_5: 1720 for (i = 0; i < VR_NRXDESC; i++) { 1721 if (sc->vr_rxsoft[i].ds_dmamap != NULL) 1722 bus_dmamap_destroy(sc->vr_dmat, 1723 sc->vr_rxsoft[i].ds_dmamap); 1724 } 1725 fail_4: 1726 for (i = 0; i < VR_NTXDESC; i++) { 1727 if (sc->vr_txsoft[i].ds_dmamap != NULL) 1728 bus_dmamap_destroy(sc->vr_dmat, 1729 sc->vr_txsoft[i].ds_dmamap); 1730 } 1731 bus_dmamap_unload(sc->vr_dmat, sc->vr_cddmamap); 1732 fail_3: 1733 bus_dmamap_destroy(sc->vr_dmat, sc->vr_cddmamap); 1734 fail_2: 1735 bus_dmamem_unmap(sc->vr_dmat, (caddr_t)sc->vr_control_data, 1736 sizeof(struct vr_control_data)); 1737 fail_1: 1738 bus_dmamem_free(sc->vr_dmat, &seg, rseg); 1739 fail_0: 1740 return; 1741 } 1742