1 /* $NetBSD: if_vr.c,v 1.97 2009/08/23 16:11:48 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1997, 1998 35 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Bill Paul. 48 * 4. Neither the name of the author nor the names of any co-contributors 49 * may be used to endorse or promote products derived from this software 50 * without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 56 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 57 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 58 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 59 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 60 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 61 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 62 * THE POSSIBILITY OF SUCH DAMAGE. 63 * 64 * $FreeBSD: if_vr.c,v 1.7 1999/01/10 18:51:49 wpaul Exp $ 65 */ 66 67 /* 68 * VIA Rhine fast ethernet PCI NIC driver 69 * 70 * Supports various network adapters based on the VIA Rhine 71 * and Rhine II PCI controllers, including the D-Link DFE530TX. 72 * Datasheets are available at http://www.via.com.tw. 73 * 74 * Written by Bill Paul <wpaul@ctr.columbia.edu> 75 * Electrical Engineering Department 76 * Columbia University, New York City 77 */ 78 79 /* 80 * The VIA Rhine controllers are similar in some respects to the 81 * the DEC tulip chips, except less complicated. The controller 82 * uses an MII bus and an external physical layer interface. The 83 * receiver has a one entry perfect filter and a 64-bit hash table 84 * multicast filter. Transmit and receive descriptors are similar 85 * to the tulip. 86 * 87 * The Rhine has a serious flaw in its transmit DMA mechanism: 88 * transmit buffers must be longword aligned. Unfortunately, 89 * the kernel doesn't guarantee that mbufs will be filled in starting 90 * at longword boundaries, so we have to do a buffer copy before 91 * transmission. 92 * 93 * Apparently, the receive DMA mechanism also has the same flaw. This 94 * means that on systems with struct alignment requirements, incoming 95 * frames must be copied to a new buffer which shifts the data forward 96 * 2 bytes so that the payload is aligned on a 4-byte boundary. 97 */ 98 99 #include <sys/cdefs.h> 100 __KERNEL_RCSID(0, "$NetBSD: if_vr.c,v 1.97 2009/08/23 16:11:48 jmcneill Exp $"); 101 102 #include "rnd.h" 103 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/callout.h> 107 #include <sys/sockio.h> 108 #include <sys/mbuf.h> 109 #include <sys/malloc.h> 110 #include <sys/kernel.h> 111 #include <sys/socket.h> 112 #include <sys/device.h> 113 114 #if NRND > 0 115 #include <sys/rnd.h> 116 #endif 117 118 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 119 120 #include <net/if.h> 121 #include <net/if_arp.h> 122 #include <net/if_dl.h> 123 #include <net/if_media.h> 124 #include <net/if_ether.h> 125 126 #include "bpfilter.h" 127 #if NBPFILTER > 0 128 #include <net/bpf.h> 129 #endif 130 131 #include <sys/bus.h> 132 #include <sys/intr.h> 133 #include <machine/endian.h> 134 135 #include <dev/mii/mii.h> 136 #include <dev/mii/miivar.h> 137 #include <dev/mii/mii_bitbang.h> 138 139 #include <dev/pci/pcireg.h> 140 #include <dev/pci/pcivar.h> 141 #include <dev/pci/pcidevs.h> 142 143 #include <dev/pci/if_vrreg.h> 144 145 #define VR_USEIOSPACE 146 147 /* 148 * Various supported device vendors/types and their names. 149 */ 150 static const struct vr_type { 151 pci_vendor_id_t vr_vid; 152 pci_product_id_t vr_did; 153 } vr_devs[] = { 154 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT3043 }, 155 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6102 }, 156 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6105 }, 157 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6105M }, 158 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT86C100A } 159 }; 160 161 /* 162 * Transmit descriptor list size. 163 */ 164 #define VR_NTXDESC 64 165 #define VR_NTXDESC_MASK (VR_NTXDESC - 1) 166 #define VR_NEXTTX(x) (((x) + 1) & VR_NTXDESC_MASK) 167 168 /* 169 * Receive descriptor list size. 170 */ 171 #define VR_NRXDESC 64 172 #define VR_NRXDESC_MASK (VR_NRXDESC - 1) 173 #define VR_NEXTRX(x) (((x) + 1) & VR_NRXDESC_MASK) 174 175 /* 176 * Control data structres that are DMA'd to the Rhine chip. We allocate 177 * them in a single clump that maps to a single DMA segment to make several 178 * things easier. 179 * 180 * Note that since we always copy outgoing packets to aligned transmit 181 * buffers, we can reduce the transmit descriptors to one per packet. 182 */ 183 struct vr_control_data { 184 struct vr_desc vr_txdescs[VR_NTXDESC]; 185 struct vr_desc vr_rxdescs[VR_NRXDESC]; 186 }; 187 188 #define VR_CDOFF(x) offsetof(struct vr_control_data, x) 189 #define VR_CDTXOFF(x) VR_CDOFF(vr_txdescs[(x)]) 190 #define VR_CDRXOFF(x) VR_CDOFF(vr_rxdescs[(x)]) 191 192 /* 193 * Software state of transmit and receive descriptors. 194 */ 195 struct vr_descsoft { 196 struct mbuf *ds_mbuf; /* head of mbuf chain */ 197 bus_dmamap_t ds_dmamap; /* our DMA map */ 198 }; 199 200 struct vr_softc { 201 device_t vr_dev; 202 void *vr_ih; /* interrupt cookie */ 203 void *vr_ats; /* shutdown hook */ 204 bus_space_tag_t vr_bst; /* bus space tag */ 205 bus_space_handle_t vr_bsh; /* bus space handle */ 206 bus_dma_tag_t vr_dmat; /* bus DMA tag */ 207 pci_chipset_tag_t vr_pc; /* PCI chipset info */ 208 pcitag_t vr_tag; /* PCI tag */ 209 struct ethercom vr_ec; /* Ethernet common info */ 210 uint8_t vr_enaddr[ETHER_ADDR_LEN]; 211 struct mii_data vr_mii; /* MII/media info */ 212 213 uint8_t vr_revid; /* Rhine chip revision */ 214 215 callout_t vr_tick_ch; /* tick callout */ 216 217 bus_dmamap_t vr_cddmamap; /* control data DMA map */ 218 #define vr_cddma vr_cddmamap->dm_segs[0].ds_addr 219 220 /* 221 * Software state for transmit and receive descriptors. 222 */ 223 struct vr_descsoft vr_txsoft[VR_NTXDESC]; 224 struct vr_descsoft vr_rxsoft[VR_NRXDESC]; 225 226 /* 227 * Control data structures. 228 */ 229 struct vr_control_data *vr_control_data; 230 231 int vr_txpending; /* number of TX requests pending */ 232 int vr_txdirty; /* first dirty TX descriptor */ 233 int vr_txlast; /* last used TX descriptor */ 234 235 int vr_rxptr; /* next ready RX descriptor */ 236 237 uint32_t vr_save_iobase; 238 uint32_t vr_save_membase; 239 uint32_t vr_save_irq; 240 241 #if NRND > 0 242 rndsource_element_t rnd_source; /* random source */ 243 #endif 244 }; 245 246 #define VR_CDTXADDR(sc, x) ((sc)->vr_cddma + VR_CDTXOFF((x))) 247 #define VR_CDRXADDR(sc, x) ((sc)->vr_cddma + VR_CDRXOFF((x))) 248 249 #define VR_CDTX(sc, x) (&(sc)->vr_control_data->vr_txdescs[(x)]) 250 #define VR_CDRX(sc, x) (&(sc)->vr_control_data->vr_rxdescs[(x)]) 251 252 #define VR_DSTX(sc, x) (&(sc)->vr_txsoft[(x)]) 253 #define VR_DSRX(sc, x) (&(sc)->vr_rxsoft[(x)]) 254 255 #define VR_CDTXSYNC(sc, x, ops) \ 256 bus_dmamap_sync((sc)->vr_dmat, (sc)->vr_cddmamap, \ 257 VR_CDTXOFF((x)), sizeof(struct vr_desc), (ops)) 258 259 #define VR_CDRXSYNC(sc, x, ops) \ 260 bus_dmamap_sync((sc)->vr_dmat, (sc)->vr_cddmamap, \ 261 VR_CDRXOFF((x)), sizeof(struct vr_desc), (ops)) 262 263 /* 264 * Note we rely on MCLBYTES being a power of two below. 265 */ 266 #define VR_INIT_RXDESC(sc, i) \ 267 do { \ 268 struct vr_desc *__d = VR_CDRX((sc), (i)); \ 269 struct vr_descsoft *__ds = VR_DSRX((sc), (i)); \ 270 \ 271 __d->vr_next = htole32(VR_CDRXADDR((sc), VR_NEXTRX((i)))); \ 272 __d->vr_data = htole32(__ds->ds_dmamap->dm_segs[0].ds_addr); \ 273 __d->vr_ctl = htole32(VR_RXCTL_CHAIN | VR_RXCTL_RX_INTR | \ 274 ((MCLBYTES - 1) & VR_RXCTL_BUFLEN)); \ 275 __d->vr_status = htole32(VR_RXSTAT_FIRSTFRAG | \ 276 VR_RXSTAT_LASTFRAG | VR_RXSTAT_OWN); \ 277 VR_CDRXSYNC((sc), (i), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 278 } while (/* CONSTCOND */ 0) 279 280 /* 281 * register space access macros 282 */ 283 #define CSR_WRITE_4(sc, reg, val) \ 284 bus_space_write_4(sc->vr_bst, sc->vr_bsh, reg, val) 285 #define CSR_WRITE_2(sc, reg, val) \ 286 bus_space_write_2(sc->vr_bst, sc->vr_bsh, reg, val) 287 #define CSR_WRITE_1(sc, reg, val) \ 288 bus_space_write_1(sc->vr_bst, sc->vr_bsh, reg, val) 289 290 #define CSR_READ_4(sc, reg) \ 291 bus_space_read_4(sc->vr_bst, sc->vr_bsh, reg) 292 #define CSR_READ_2(sc, reg) \ 293 bus_space_read_2(sc->vr_bst, sc->vr_bsh, reg) 294 #define CSR_READ_1(sc, reg) \ 295 bus_space_read_1(sc->vr_bst, sc->vr_bsh, reg) 296 297 #define VR_TIMEOUT 1000 298 299 static int vr_add_rxbuf(struct vr_softc *, int); 300 301 static void vr_rxeof(struct vr_softc *); 302 static void vr_rxeoc(struct vr_softc *); 303 static void vr_txeof(struct vr_softc *); 304 static int vr_intr(void *); 305 static void vr_start(struct ifnet *); 306 static int vr_ioctl(struct ifnet *, u_long, void *); 307 static int vr_init(struct ifnet *); 308 static void vr_stop(struct ifnet *, int); 309 static void vr_rxdrain(struct vr_softc *); 310 static void vr_watchdog(struct ifnet *); 311 static void vr_tick(void *); 312 313 static int vr_mii_readreg(device_t, int, int); 314 static void vr_mii_writereg(device_t, int, int, int); 315 static void vr_mii_statchg(device_t); 316 317 static void vr_setmulti(struct vr_softc *); 318 static void vr_reset(struct vr_softc *); 319 static int vr_restore_state(pci_chipset_tag_t, pcitag_t, device_t, 320 pcireg_t); 321 322 int vr_copy_small = 0; 323 324 #define VR_SETBIT(sc, reg, x) \ 325 CSR_WRITE_1(sc, reg, \ 326 CSR_READ_1(sc, reg) | (x)) 327 328 #define VR_CLRBIT(sc, reg, x) \ 329 CSR_WRITE_1(sc, reg, \ 330 CSR_READ_1(sc, reg) & ~(x)) 331 332 #define VR_SETBIT16(sc, reg, x) \ 333 CSR_WRITE_2(sc, reg, \ 334 CSR_READ_2(sc, reg) | (x)) 335 336 #define VR_CLRBIT16(sc, reg, x) \ 337 CSR_WRITE_2(sc, reg, \ 338 CSR_READ_2(sc, reg) & ~(x)) 339 340 #define VR_SETBIT32(sc, reg, x) \ 341 CSR_WRITE_4(sc, reg, \ 342 CSR_READ_4(sc, reg) | (x)) 343 344 #define VR_CLRBIT32(sc, reg, x) \ 345 CSR_WRITE_4(sc, reg, \ 346 CSR_READ_4(sc, reg) & ~(x)) 347 348 /* 349 * MII bit-bang glue. 350 */ 351 static uint32_t vr_mii_bitbang_read(device_t); 352 static void vr_mii_bitbang_write(device_t, uint32_t); 353 354 static const struct mii_bitbang_ops vr_mii_bitbang_ops = { 355 vr_mii_bitbang_read, 356 vr_mii_bitbang_write, 357 { 358 VR_MIICMD_DATAOUT, /* MII_BIT_MDO */ 359 VR_MIICMD_DATAIN, /* MII_BIT_MDI */ 360 VR_MIICMD_CLK, /* MII_BIT_MDC */ 361 VR_MIICMD_DIR, /* MII_BIT_DIR_HOST_PHY */ 362 0, /* MII_BIT_DIR_PHY_HOST */ 363 } 364 }; 365 366 static uint32_t 367 vr_mii_bitbang_read(device_t self) 368 { 369 struct vr_softc *sc = device_private(self); 370 371 return (CSR_READ_1(sc, VR_MIICMD)); 372 } 373 374 static void 375 vr_mii_bitbang_write(device_t self, uint32_t val) 376 { 377 struct vr_softc *sc = device_private(self); 378 379 CSR_WRITE_1(sc, VR_MIICMD, (val & 0xff) | VR_MIICMD_DIRECTPGM); 380 } 381 382 /* 383 * Read an PHY register through the MII. 384 */ 385 static int 386 vr_mii_readreg(device_t self, int phy, int reg) 387 { 388 struct vr_softc *sc = device_private(self); 389 390 CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 391 return (mii_bitbang_readreg(self, &vr_mii_bitbang_ops, phy, reg)); 392 } 393 394 /* 395 * Write to a PHY register through the MII. 396 */ 397 static void 398 vr_mii_writereg(device_t self, int phy, int reg, int val) 399 { 400 struct vr_softc *sc = device_private(self); 401 402 CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 403 mii_bitbang_writereg(self, &vr_mii_bitbang_ops, phy, reg, val); 404 } 405 406 static void 407 vr_mii_statchg(device_t self) 408 { 409 struct vr_softc *sc = device_private(self); 410 411 /* 412 * In order to fiddle with the 'full-duplex' bit in the netconfig 413 * register, we first have to put the transmit and/or receive logic 414 * in the idle state. 415 */ 416 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 417 418 if (sc->vr_mii.mii_media_active & IFM_FDX) 419 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 420 else 421 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 422 423 if (sc->vr_ec.ec_if.if_flags & IFF_RUNNING) 424 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 425 } 426 427 #define vr_calchash(addr) \ 428 (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26) 429 430 /* 431 * Program the 64-bit multicast hash filter. 432 */ 433 static void 434 vr_setmulti(struct vr_softc *sc) 435 { 436 struct ifnet *ifp; 437 int h = 0; 438 uint32_t hashes[2] = { 0, 0 }; 439 struct ether_multistep step; 440 struct ether_multi *enm; 441 int mcnt = 0; 442 uint8_t rxfilt; 443 444 ifp = &sc->vr_ec.ec_if; 445 446 rxfilt = CSR_READ_1(sc, VR_RXCFG); 447 448 if (ifp->if_flags & IFF_PROMISC) { 449 allmulti: 450 ifp->if_flags |= IFF_ALLMULTI; 451 rxfilt |= VR_RXCFG_RX_MULTI; 452 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 453 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 454 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 455 return; 456 } 457 458 /* first, zot all the existing hash bits */ 459 CSR_WRITE_4(sc, VR_MAR0, 0); 460 CSR_WRITE_4(sc, VR_MAR1, 0); 461 462 /* now program new ones */ 463 ETHER_FIRST_MULTI(step, &sc->vr_ec, enm); 464 while (enm != NULL) { 465 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 466 ETHER_ADDR_LEN) != 0) 467 goto allmulti; 468 469 h = vr_calchash(enm->enm_addrlo); 470 471 if (h < 32) 472 hashes[0] |= (1 << h); 473 else 474 hashes[1] |= (1 << (h - 32)); 475 ETHER_NEXT_MULTI(step, enm); 476 mcnt++; 477 } 478 479 ifp->if_flags &= ~IFF_ALLMULTI; 480 481 if (mcnt) 482 rxfilt |= VR_RXCFG_RX_MULTI; 483 else 484 rxfilt &= ~VR_RXCFG_RX_MULTI; 485 486 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 487 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 488 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 489 } 490 491 static void 492 vr_reset(struct vr_softc *sc) 493 { 494 int i; 495 496 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 497 498 for (i = 0; i < VR_TIMEOUT; i++) { 499 DELAY(10); 500 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 501 break; 502 } 503 if (i == VR_TIMEOUT) { 504 if (sc->vr_revid < REV_ID_VT3065_A) { 505 printf("%s: reset never completed!\n", 506 device_xname(sc->vr_dev)); 507 } else { 508 /* Use newer force reset command */ 509 printf("%s: using force reset command.\n", 510 device_xname(sc->vr_dev)); 511 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 512 } 513 } 514 515 /* Wait a little while for the chip to get its brains in order. */ 516 DELAY(1000); 517 } 518 519 /* 520 * Initialize an RX descriptor and attach an MBUF cluster. 521 * Note: the length fields are only 11 bits wide, which means the 522 * largest size we can specify is 2047. This is important because 523 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 524 * overflow the field and make a mess. 525 */ 526 static int 527 vr_add_rxbuf(struct vr_softc *sc, int i) 528 { 529 struct vr_descsoft *ds = VR_DSRX(sc, i); 530 struct mbuf *m_new; 531 int error; 532 533 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 534 if (m_new == NULL) 535 return (ENOBUFS); 536 537 MCLGET(m_new, M_DONTWAIT); 538 if ((m_new->m_flags & M_EXT) == 0) { 539 m_freem(m_new); 540 return (ENOBUFS); 541 } 542 543 if (ds->ds_mbuf != NULL) 544 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 545 546 ds->ds_mbuf = m_new; 547 548 error = bus_dmamap_load(sc->vr_dmat, ds->ds_dmamap, 549 m_new->m_ext.ext_buf, m_new->m_ext.ext_size, NULL, 550 BUS_DMA_READ|BUS_DMA_NOWAIT); 551 if (error) { 552 aprint_error_dev(sc->vr_dev, "unable to load rx DMA map %d, error = %d\n", 553 i, error); 554 panic("vr_add_rxbuf"); /* XXX */ 555 } 556 557 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 558 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 559 560 VR_INIT_RXDESC(sc, i); 561 562 return (0); 563 } 564 565 /* 566 * A frame has been uploaded: pass the resulting mbuf chain up to 567 * the higher level protocols. 568 */ 569 static void 570 vr_rxeof(struct vr_softc *sc) 571 { 572 struct mbuf *m; 573 struct ifnet *ifp; 574 struct vr_desc *d; 575 struct vr_descsoft *ds; 576 int i, total_len; 577 uint32_t rxstat; 578 579 ifp = &sc->vr_ec.ec_if; 580 581 for (i = sc->vr_rxptr;; i = VR_NEXTRX(i)) { 582 d = VR_CDRX(sc, i); 583 ds = VR_DSRX(sc, i); 584 585 VR_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 586 587 rxstat = le32toh(d->vr_status); 588 589 if (rxstat & VR_RXSTAT_OWN) { 590 /* 591 * We have processed all of the receive buffers. 592 */ 593 break; 594 } 595 596 /* 597 * If an error occurs, update stats, clear the 598 * status word and leave the mbuf cluster in place: 599 * it should simply get re-used next time this descriptor 600 * comes up in the ring. 601 */ 602 if (rxstat & VR_RXSTAT_RXERR) { 603 const char *errstr; 604 605 ifp->if_ierrors++; 606 switch (rxstat & 0x000000FF) { 607 case VR_RXSTAT_CRCERR: 608 errstr = "crc error"; 609 break; 610 case VR_RXSTAT_FRAMEALIGNERR: 611 errstr = "frame alignment error"; 612 break; 613 case VR_RXSTAT_FIFOOFLOW: 614 errstr = "FIFO overflow"; 615 break; 616 case VR_RXSTAT_GIANT: 617 errstr = "received giant packet"; 618 break; 619 case VR_RXSTAT_RUNT: 620 errstr = "received runt packet"; 621 break; 622 case VR_RXSTAT_BUSERR: 623 errstr = "system bus error"; 624 break; 625 case VR_RXSTAT_BUFFERR: 626 errstr = "rx buffer error"; 627 break; 628 default: 629 errstr = "unknown rx error"; 630 break; 631 } 632 printf("%s: receive error: %s\n", device_xname(sc->vr_dev), 633 errstr); 634 635 VR_INIT_RXDESC(sc, i); 636 637 continue; 638 } else if (!(rxstat & VR_RXSTAT_FIRSTFRAG) || 639 !(rxstat & VR_RXSTAT_LASTFRAG)) { 640 /* 641 * This driver expects to receive whole packets every 642 * time. In case we receive a fragment that is not 643 * a complete packet, we discard it. 644 */ 645 ifp->if_ierrors++; 646 647 printf("%s: receive error: incomplete frame; " 648 "size = %d, status = 0x%x\n", 649 device_xname(sc->vr_dev), 650 VR_RXBYTES(le32toh(d->vr_status)), rxstat); 651 652 VR_INIT_RXDESC(sc, i); 653 654 continue; 655 } 656 657 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 658 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 659 660 /* No errors; receive the packet. */ 661 total_len = VR_RXBYTES(le32toh(d->vr_status)); 662 #ifdef DIAGNOSTIC 663 if (total_len == 0) { 664 /* 665 * If we receive a zero-length packet, we probably 666 * missed to handle an error condition above. 667 * Discard it to avoid a later crash. 668 */ 669 ifp->if_ierrors++; 670 671 printf("%s: receive error: zero-length packet; " 672 "status = 0x%x\n", 673 device_xname(sc->vr_dev), rxstat); 674 675 VR_INIT_RXDESC(sc, i); 676 677 continue; 678 } 679 #endif 680 681 /* 682 * The Rhine chip includes the CRC with every packet. 683 * Trim it off here. 684 */ 685 total_len -= ETHER_CRC_LEN; 686 687 #ifdef __NO_STRICT_ALIGNMENT 688 /* 689 * If the packet is small enough to fit in a 690 * single header mbuf, allocate one and copy 691 * the data into it. This greatly reduces 692 * memory consumption when we receive lots 693 * of small packets. 694 * 695 * Otherwise, we add a new buffer to the receive 696 * chain. If this fails, we drop the packet and 697 * recycle the old buffer. 698 */ 699 if (vr_copy_small != 0 && total_len <= MHLEN) { 700 MGETHDR(m, M_DONTWAIT, MT_DATA); 701 if (m == NULL) 702 goto dropit; 703 memcpy(mtod(m, void *), 704 mtod(ds->ds_mbuf, void *), total_len); 705 VR_INIT_RXDESC(sc, i); 706 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 707 ds->ds_dmamap->dm_mapsize, 708 BUS_DMASYNC_PREREAD); 709 } else { 710 m = ds->ds_mbuf; 711 if (vr_add_rxbuf(sc, i) == ENOBUFS) { 712 dropit: 713 ifp->if_ierrors++; 714 VR_INIT_RXDESC(sc, i); 715 bus_dmamap_sync(sc->vr_dmat, 716 ds->ds_dmamap, 0, 717 ds->ds_dmamap->dm_mapsize, 718 BUS_DMASYNC_PREREAD); 719 continue; 720 } 721 } 722 #else 723 /* 724 * The Rhine's packet buffers must be 4-byte aligned. 725 * But this means that the data after the Ethernet header 726 * is misaligned. We must allocate a new buffer and 727 * copy the data, shifted forward 2 bytes. 728 */ 729 MGETHDR(m, M_DONTWAIT, MT_DATA); 730 if (m == NULL) { 731 dropit: 732 ifp->if_ierrors++; 733 VR_INIT_RXDESC(sc, i); 734 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 735 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 736 continue; 737 } 738 if (total_len > (MHLEN - 2)) { 739 MCLGET(m, M_DONTWAIT); 740 if ((m->m_flags & M_EXT) == 0) { 741 m_freem(m); 742 goto dropit; 743 } 744 } 745 m->m_data += 2; 746 747 /* 748 * Note that we use clusters for incoming frames, so the 749 * buffer is virtually contiguous. 750 */ 751 memcpy(mtod(m, void *), mtod(ds->ds_mbuf, void *), 752 total_len); 753 754 /* Allow the receive descriptor to continue using its mbuf. */ 755 VR_INIT_RXDESC(sc, i); 756 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 757 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 758 #endif /* __NO_STRICT_ALIGNMENT */ 759 760 ifp->if_ipackets++; 761 m->m_pkthdr.rcvif = ifp; 762 m->m_pkthdr.len = m->m_len = total_len; 763 #if NBPFILTER > 0 764 /* 765 * Handle BPF listeners. Let the BPF user see the packet, but 766 * don't pass it up to the ether_input() layer unless it's 767 * a broadcast packet, multicast packet, matches our ethernet 768 * address or the interface is in promiscuous mode. 769 */ 770 if (ifp->if_bpf) 771 bpf_mtap(ifp->if_bpf, m); 772 #endif 773 /* Pass it on. */ 774 (*ifp->if_input)(ifp, m); 775 } 776 777 /* Update the receive pointer. */ 778 sc->vr_rxptr = i; 779 } 780 781 void 782 vr_rxeoc(struct vr_softc *sc) 783 { 784 struct ifnet *ifp; 785 int i; 786 787 ifp = &sc->vr_ec.ec_if; 788 789 ifp->if_ierrors++; 790 791 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 792 for (i = 0; i < VR_TIMEOUT; i++) { 793 DELAY(10); 794 if ((CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON) == 0) 795 break; 796 } 797 if (i == VR_TIMEOUT) { 798 /* XXX need reset? */ 799 printf("%s: RX shutdown never complete\n", 800 device_xname(sc->vr_dev)); 801 } 802 803 vr_rxeof(sc); 804 805 CSR_WRITE_4(sc, VR_RXADDR, VR_CDRXADDR(sc, sc->vr_rxptr)); 806 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 807 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 808 } 809 810 /* 811 * A frame was downloaded to the chip. It's safe for us to clean up 812 * the list buffers. 813 */ 814 static void 815 vr_txeof(struct vr_softc *sc) 816 { 817 struct ifnet *ifp = &sc->vr_ec.ec_if; 818 struct vr_desc *d; 819 struct vr_descsoft *ds; 820 uint32_t txstat; 821 int i, j; 822 823 ifp->if_flags &= ~IFF_OACTIVE; 824 825 /* 826 * Go through our tx list and free mbufs for those 827 * frames that have been transmitted. 828 */ 829 for (i = sc->vr_txdirty; sc->vr_txpending != 0; 830 i = VR_NEXTTX(i), sc->vr_txpending--) { 831 d = VR_CDTX(sc, i); 832 ds = VR_DSTX(sc, i); 833 834 VR_CDTXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 835 836 txstat = le32toh(d->vr_status); 837 838 if (txstat & (VR_TXSTAT_ABRT | VR_TXSTAT_UDF)) { 839 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 840 for (j = 0; j < VR_TIMEOUT; j++) { 841 DELAY(10); 842 if ((CSR_READ_2(sc, VR_COMMAND) & 843 VR_CMD_TX_ON) == 0) 844 break; 845 } 846 if (j == VR_TIMEOUT) { 847 /* XXX need reset? */ 848 printf("%s: TX shutdown never complete\n", 849 device_xname(sc->vr_dev)); 850 } 851 d->vr_status = htole32(VR_TXSTAT_OWN); 852 CSR_WRITE_4(sc, VR_TXADDR, VR_CDTXADDR(sc, i)); 853 break; 854 } 855 856 if (txstat & VR_TXSTAT_OWN) 857 break; 858 859 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 860 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 861 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 862 m_freem(ds->ds_mbuf); 863 ds->ds_mbuf = NULL; 864 865 if (txstat & VR_TXSTAT_ERRSUM) { 866 ifp->if_oerrors++; 867 if (txstat & VR_TXSTAT_DEFER) 868 ifp->if_collisions++; 869 if (txstat & VR_TXSTAT_LATECOLL) 870 ifp->if_collisions++; 871 } 872 873 ifp->if_collisions += (txstat & VR_TXSTAT_COLLCNT) >> 3; 874 ifp->if_opackets++; 875 } 876 877 /* Update the dirty transmit buffer pointer. */ 878 sc->vr_txdirty = i; 879 880 /* 881 * Cancel the watchdog timer if there are no pending 882 * transmissions. 883 */ 884 if (sc->vr_txpending == 0) 885 ifp->if_timer = 0; 886 } 887 888 static int 889 vr_intr(void *arg) 890 { 891 struct vr_softc *sc; 892 struct ifnet *ifp; 893 uint16_t status; 894 int handled = 0, dotx = 0; 895 896 sc = arg; 897 ifp = &sc->vr_ec.ec_if; 898 899 /* Suppress unwanted interrupts. */ 900 if ((ifp->if_flags & IFF_UP) == 0) { 901 vr_stop(ifp, 1); 902 return (0); 903 } 904 905 /* Disable interrupts. */ 906 CSR_WRITE_2(sc, VR_IMR, 0x0000); 907 908 for (;;) { 909 status = CSR_READ_2(sc, VR_ISR); 910 if (status) 911 CSR_WRITE_2(sc, VR_ISR, status); 912 913 if ((status & VR_INTRS) == 0) 914 break; 915 916 handled = 1; 917 918 #if NRND > 0 919 if (RND_ENABLED(&sc->rnd_source)) 920 rnd_add_uint32(&sc->rnd_source, status); 921 #endif 922 923 if (status & VR_ISR_RX_OK) 924 vr_rxeof(sc); 925 926 if (status & VR_ISR_RX_DROPPED) { 927 printf("%s: rx packet lost\n", device_xname(sc->vr_dev)); 928 ifp->if_ierrors++; 929 } 930 931 if (status & 932 (VR_ISR_RX_ERR | VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW)) 933 vr_rxeoc(sc); 934 935 936 if (status & (VR_ISR_BUSERR | VR_ISR_TX_UNDERRUN)) { 937 if (status & VR_ISR_BUSERR) 938 printf("%s: PCI bus error\n", 939 device_xname(sc->vr_dev)); 940 if (status & VR_ISR_TX_UNDERRUN) 941 printf("%s: transmit underrun\n", 942 device_xname(sc->vr_dev)); 943 /* vr_init() calls vr_start() */ 944 dotx = 0; 945 (void)vr_init(ifp); 946 947 } 948 949 if (status & VR_ISR_TX_OK) { 950 dotx = 1; 951 vr_txeof(sc); 952 } 953 954 if (status & 955 (VR_ISR_TX_ABRT | VR_ISR_TX_ABRT2 | VR_ISR_TX_UDFI)) { 956 if (status & (VR_ISR_TX_ABRT | VR_ISR_TX_ABRT2)) 957 printf("%s: transmit aborted\n", 958 device_xname(sc->vr_dev)); 959 if (status & VR_ISR_TX_UDFI) 960 printf("%s: transmit underflow\n", 961 device_xname(sc->vr_dev)); 962 ifp->if_oerrors++; 963 dotx = 1; 964 vr_txeof(sc); 965 if (sc->vr_txpending) { 966 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 967 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 968 } 969 } 970 } 971 972 /* Re-enable interrupts. */ 973 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 974 975 if (dotx) 976 vr_start(ifp); 977 978 return (handled); 979 } 980 981 /* 982 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 983 * to the mbuf data regions directly in the transmit lists. We also save a 984 * copy of the pointers since the transmit list fragment pointers are 985 * physical addresses. 986 */ 987 static void 988 vr_start(struct ifnet *ifp) 989 { 990 struct vr_softc *sc = ifp->if_softc; 991 struct mbuf *m0, *m; 992 struct vr_desc *d; 993 struct vr_descsoft *ds; 994 int error, firsttx, nexttx, opending; 995 996 /* 997 * Remember the previous txpending and the first transmit 998 * descriptor we use. 999 */ 1000 opending = sc->vr_txpending; 1001 firsttx = VR_NEXTTX(sc->vr_txlast); 1002 1003 /* 1004 * Loop through the send queue, setting up transmit descriptors 1005 * until we drain the queue, or use up all available transmit 1006 * descriptors. 1007 */ 1008 while (sc->vr_txpending < VR_NTXDESC) { 1009 /* 1010 * Grab a packet off the queue. 1011 */ 1012 IFQ_POLL(&ifp->if_snd, m0); 1013 if (m0 == NULL) 1014 break; 1015 m = NULL; 1016 1017 /* 1018 * Get the next available transmit descriptor. 1019 */ 1020 nexttx = VR_NEXTTX(sc->vr_txlast); 1021 d = VR_CDTX(sc, nexttx); 1022 ds = VR_DSTX(sc, nexttx); 1023 1024 /* 1025 * Load the DMA map. If this fails, the packet didn't 1026 * fit in one DMA segment, and we need to copy. Note, 1027 * the packet must also be aligned. 1028 * if the packet is too small, copy it too, so we're sure 1029 * we have enough room for the pad buffer. 1030 */ 1031 if ((mtod(m0, uintptr_t) & 3) != 0 || 1032 m0->m_pkthdr.len < VR_MIN_FRAMELEN || 1033 bus_dmamap_load_mbuf(sc->vr_dmat, ds->ds_dmamap, m0, 1034 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1035 MGETHDR(m, M_DONTWAIT, MT_DATA); 1036 if (m == NULL) { 1037 printf("%s: unable to allocate Tx mbuf\n", 1038 device_xname(sc->vr_dev)); 1039 break; 1040 } 1041 if (m0->m_pkthdr.len > MHLEN) { 1042 MCLGET(m, M_DONTWAIT); 1043 if ((m->m_flags & M_EXT) == 0) { 1044 printf("%s: unable to allocate Tx " 1045 "cluster\n", device_xname(sc->vr_dev)); 1046 m_freem(m); 1047 break; 1048 } 1049 } 1050 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1051 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1052 /* 1053 * The Rhine doesn't auto-pad, so we have to do this 1054 * ourselves. 1055 */ 1056 if (m0->m_pkthdr.len < VR_MIN_FRAMELEN) { 1057 memset(mtod(m, char *) + m0->m_pkthdr.len, 1058 0, VR_MIN_FRAMELEN - m0->m_pkthdr.len); 1059 m->m_pkthdr.len = m->m_len = VR_MIN_FRAMELEN; 1060 } 1061 error = bus_dmamap_load_mbuf(sc->vr_dmat, 1062 ds->ds_dmamap, m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1063 if (error) { 1064 m_freem(m); 1065 printf("%s: unable to load Tx buffer, " 1066 "error = %d\n", device_xname(sc->vr_dev), error); 1067 break; 1068 } 1069 } 1070 1071 IFQ_DEQUEUE(&ifp->if_snd, m0); 1072 if (m != NULL) { 1073 m_freem(m0); 1074 m0 = m; 1075 } 1076 1077 /* Sync the DMA map. */ 1078 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 1079 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1080 1081 /* 1082 * Store a pointer to the packet so we can free it later. 1083 */ 1084 ds->ds_mbuf = m0; 1085 1086 #if NBPFILTER > 0 1087 /* 1088 * If there's a BPF listener, bounce a copy of this frame 1089 * to him. 1090 */ 1091 if (ifp->if_bpf) 1092 bpf_mtap(ifp->if_bpf, m0); 1093 #endif 1094 1095 /* 1096 * Fill in the transmit descriptor. 1097 */ 1098 d->vr_data = htole32(ds->ds_dmamap->dm_segs[0].ds_addr); 1099 d->vr_ctl = htole32(m0->m_pkthdr.len); 1100 d->vr_ctl |= htole32(VR_TXCTL_FIRSTFRAG | VR_TXCTL_LASTFRAG); 1101 1102 /* 1103 * If this is the first descriptor we're enqueuing, 1104 * don't give it to the Rhine yet. That could cause 1105 * a race condition. We'll do it below. 1106 */ 1107 if (nexttx == firsttx) 1108 d->vr_status = 0; 1109 else 1110 d->vr_status = htole32(VR_TXSTAT_OWN); 1111 1112 VR_CDTXSYNC(sc, nexttx, 1113 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1114 1115 /* Advance the tx pointer. */ 1116 sc->vr_txpending++; 1117 sc->vr_txlast = nexttx; 1118 } 1119 1120 if (sc->vr_txpending == VR_NTXDESC) { 1121 /* No more slots left; notify upper layer. */ 1122 ifp->if_flags |= IFF_OACTIVE; 1123 } 1124 1125 if (sc->vr_txpending != opending) { 1126 /* 1127 * We enqueued packets. If the transmitter was idle, 1128 * reset the txdirty pointer. 1129 */ 1130 if (opending == 0) 1131 sc->vr_txdirty = firsttx; 1132 1133 /* 1134 * Cause a transmit interrupt to happen on the 1135 * last packet we enqueued. 1136 */ 1137 VR_CDTX(sc, sc->vr_txlast)->vr_ctl |= htole32(VR_TXCTL_FINT); 1138 VR_CDTXSYNC(sc, sc->vr_txlast, 1139 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1140 1141 /* 1142 * The entire packet chain is set up. Give the 1143 * first descriptor to the Rhine now. 1144 */ 1145 VR_CDTX(sc, firsttx)->vr_status = htole32(VR_TXSTAT_OWN); 1146 VR_CDTXSYNC(sc, firsttx, 1147 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1148 1149 /* Start the transmitter. */ 1150 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1151 1152 /* Set the watchdog timer in case the chip flakes out. */ 1153 ifp->if_timer = 5; 1154 } 1155 } 1156 1157 /* 1158 * Initialize the interface. Must be called at splnet. 1159 */ 1160 static int 1161 vr_init(struct ifnet *ifp) 1162 { 1163 struct vr_softc *sc = ifp->if_softc; 1164 struct vr_desc *d; 1165 struct vr_descsoft *ds; 1166 int i, error = 0; 1167 1168 /* Cancel pending I/O. */ 1169 vr_stop(ifp, 0); 1170 1171 /* Reset the Rhine to a known state. */ 1172 vr_reset(sc); 1173 1174 /* set DMA length in BCR0 and BCR1 */ 1175 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1176 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1177 1178 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1179 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTH_128BYTES); 1180 1181 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1182 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTH_STORENFWD); 1183 1184 /* set DMA threshold length in RXCFG and TXCFG */ 1185 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1186 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1187 1188 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1189 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1190 1191 /* 1192 * Initialize the transmit descriptor ring. txlast is initialized 1193 * to the end of the list so that it will wrap around to the first 1194 * descriptor when the first packet is transmitted. 1195 */ 1196 for (i = 0; i < VR_NTXDESC; i++) { 1197 d = VR_CDTX(sc, i); 1198 memset(d, 0, sizeof(struct vr_desc)); 1199 d->vr_next = htole32(VR_CDTXADDR(sc, VR_NEXTTX(i))); 1200 VR_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1201 } 1202 sc->vr_txpending = 0; 1203 sc->vr_txdirty = 0; 1204 sc->vr_txlast = VR_NTXDESC - 1; 1205 1206 /* 1207 * Initialize the receive descriptor ring. 1208 */ 1209 for (i = 0; i < VR_NRXDESC; i++) { 1210 ds = VR_DSRX(sc, i); 1211 if (ds->ds_mbuf == NULL) { 1212 if ((error = vr_add_rxbuf(sc, i)) != 0) { 1213 printf("%s: unable to allocate or map rx " 1214 "buffer %d, error = %d\n", 1215 device_xname(sc->vr_dev), i, error); 1216 /* 1217 * XXX Should attempt to run with fewer receive 1218 * XXX buffers instead of just failing. 1219 */ 1220 vr_rxdrain(sc); 1221 goto out; 1222 } 1223 } else 1224 VR_INIT_RXDESC(sc, i); 1225 } 1226 sc->vr_rxptr = 0; 1227 1228 /* If we want promiscuous mode, set the allframes bit. */ 1229 if (ifp->if_flags & IFF_PROMISC) 1230 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1231 else 1232 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1233 1234 /* Set capture broadcast bit to capture broadcast frames. */ 1235 if (ifp->if_flags & IFF_BROADCAST) 1236 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1237 else 1238 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1239 1240 /* Program the multicast filter, if necessary. */ 1241 vr_setmulti(sc); 1242 1243 /* Give the transmit and receive rings to the Rhine. */ 1244 CSR_WRITE_4(sc, VR_RXADDR, VR_CDRXADDR(sc, sc->vr_rxptr)); 1245 CSR_WRITE_4(sc, VR_TXADDR, VR_CDTXADDR(sc, VR_NEXTTX(sc->vr_txlast))); 1246 1247 /* Set current media. */ 1248 if ((error = ether_mediachange(ifp)) != 0) 1249 goto out; 1250 1251 /* Enable receiver and transmitter. */ 1252 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1253 VR_CMD_TX_ON|VR_CMD_RX_ON| 1254 VR_CMD_RX_GO); 1255 1256 /* Enable interrupts. */ 1257 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1258 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1259 1260 ifp->if_flags |= IFF_RUNNING; 1261 ifp->if_flags &= ~IFF_OACTIVE; 1262 1263 /* Start one second timer. */ 1264 callout_reset(&sc->vr_tick_ch, hz, vr_tick, sc); 1265 1266 /* Attempt to start output on the interface. */ 1267 vr_start(ifp); 1268 1269 out: 1270 if (error) 1271 printf("%s: interface not running\n", device_xname(sc->vr_dev)); 1272 return (error); 1273 } 1274 1275 static int 1276 vr_ioctl(struct ifnet *ifp, u_long command, void *data) 1277 { 1278 struct vr_softc *sc = ifp->if_softc; 1279 int s, error = 0; 1280 1281 s = splnet(); 1282 1283 error = ether_ioctl(ifp, command, data); 1284 if (error == ENETRESET) { 1285 /* 1286 * Multicast list has changed; set the hardware filter 1287 * accordingly. 1288 */ 1289 if (ifp->if_flags & IFF_RUNNING) 1290 vr_setmulti(sc); 1291 error = 0; 1292 } 1293 1294 splx(s); 1295 return (error); 1296 } 1297 1298 static void 1299 vr_watchdog(struct ifnet *ifp) 1300 { 1301 struct vr_softc *sc = ifp->if_softc; 1302 1303 printf("%s: device timeout\n", device_xname(sc->vr_dev)); 1304 ifp->if_oerrors++; 1305 1306 (void) vr_init(ifp); 1307 } 1308 1309 /* 1310 * One second timer, used to tick MII. 1311 */ 1312 static void 1313 vr_tick(void *arg) 1314 { 1315 struct vr_softc *sc = arg; 1316 int s; 1317 1318 s = splnet(); 1319 mii_tick(&sc->vr_mii); 1320 splx(s); 1321 1322 callout_reset(&sc->vr_tick_ch, hz, vr_tick, sc); 1323 } 1324 1325 /* 1326 * Drain the receive queue. 1327 */ 1328 static void 1329 vr_rxdrain(struct vr_softc *sc) 1330 { 1331 struct vr_descsoft *ds; 1332 int i; 1333 1334 for (i = 0; i < VR_NRXDESC; i++) { 1335 ds = VR_DSRX(sc, i); 1336 if (ds->ds_mbuf != NULL) { 1337 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 1338 m_freem(ds->ds_mbuf); 1339 ds->ds_mbuf = NULL; 1340 } 1341 } 1342 } 1343 1344 /* 1345 * Stop the adapter and free any mbufs allocated to the 1346 * transmit lists. 1347 */ 1348 static void 1349 vr_stop(struct ifnet *ifp, int disable) 1350 { 1351 struct vr_softc *sc = ifp->if_softc; 1352 struct vr_descsoft *ds; 1353 int i; 1354 1355 /* Cancel one second timer. */ 1356 callout_stop(&sc->vr_tick_ch); 1357 1358 /* Down the MII. */ 1359 mii_down(&sc->vr_mii); 1360 1361 ifp = &sc->vr_ec.ec_if; 1362 ifp->if_timer = 0; 1363 1364 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1365 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1366 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1367 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1368 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1369 1370 /* 1371 * Release any queued transmit buffers. 1372 */ 1373 for (i = 0; i < VR_NTXDESC; i++) { 1374 ds = VR_DSTX(sc, i); 1375 if (ds->ds_mbuf != NULL) { 1376 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 1377 m_freem(ds->ds_mbuf); 1378 ds->ds_mbuf = NULL; 1379 } 1380 } 1381 1382 /* 1383 * Mark the interface down and cancel the watchdog timer. 1384 */ 1385 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1386 ifp->if_timer = 0; 1387 1388 if (disable) 1389 vr_rxdrain(sc); 1390 } 1391 1392 static int vr_probe(device_t, cfdata_t, void *); 1393 static void vr_attach(device_t, device_t, void *); 1394 static void vr_shutdown(void *); 1395 1396 CFATTACH_DECL_NEW(vr, sizeof (struct vr_softc), 1397 vr_probe, vr_attach, NULL, NULL); 1398 1399 static const struct vr_type * 1400 vr_lookup(struct pci_attach_args *pa) 1401 { 1402 const struct vr_type *vrt; 1403 int i; 1404 1405 for (i = 0; i < __arraycount(vr_devs); i++) { 1406 vrt = &vr_devs[i]; 1407 if (PCI_VENDOR(pa->pa_id) == vrt->vr_vid && 1408 PCI_PRODUCT(pa->pa_id) == vrt->vr_did) 1409 return (vrt); 1410 } 1411 return (NULL); 1412 } 1413 1414 static int 1415 vr_probe(device_t parent, cfdata_t match, void *aux) 1416 { 1417 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1418 1419 if (vr_lookup(pa) != NULL) 1420 return (1); 1421 1422 return (0); 1423 } 1424 1425 /* 1426 * Stop all chip I/O so that the kernel's probe routines don't 1427 * get confused by errant DMAs when rebooting. 1428 */ 1429 static void 1430 vr_shutdown(void *arg) 1431 { 1432 struct vr_softc *sc = (struct vr_softc *)arg; 1433 1434 vr_stop(&sc->vr_ec.ec_if, 1); 1435 } 1436 1437 /* 1438 * Attach the interface. Allocate softc structures, do ifmedia 1439 * setup and ethernet/BPF attach. 1440 */ 1441 static void 1442 vr_attach(device_t parent, device_t self, void *aux) 1443 { 1444 struct vr_softc *sc = device_private(self); 1445 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 1446 bus_dma_segment_t seg; 1447 uint32_t reg; 1448 struct ifnet *ifp; 1449 uint8_t eaddr[ETHER_ADDR_LEN], mac; 1450 int i, rseg, error; 1451 char devinfo[256]; 1452 1453 #define PCI_CONF_WRITE(r, v) pci_conf_write(sc->vr_pc, sc->vr_tag, (r), (v)) 1454 #define PCI_CONF_READ(r) pci_conf_read(sc->vr_pc, sc->vr_tag, (r)) 1455 1456 sc->vr_dev = self; 1457 sc->vr_pc = pa->pa_pc; 1458 sc->vr_tag = pa->pa_tag; 1459 callout_init(&sc->vr_tick_ch, 0); 1460 1461 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 1462 aprint_naive("\n"); 1463 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 1464 PCI_REVISION(pa->pa_class)); 1465 1466 /* 1467 * Handle power management nonsense. 1468 */ 1469 1470 sc->vr_save_iobase = PCI_CONF_READ(VR_PCI_LOIO); 1471 sc->vr_save_membase = PCI_CONF_READ(VR_PCI_LOMEM); 1472 sc->vr_save_irq = PCI_CONF_READ(PCI_INTERRUPT_REG); 1473 1474 /* power up chip */ 1475 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 1476 vr_restore_state)) && error != EOPNOTSUPP) { 1477 aprint_error_dev(self, "cannot activate %d\n", 1478 error); 1479 return; 1480 } 1481 1482 /* Make sure bus mastering is enabled. */ 1483 reg = PCI_CONF_READ(PCI_COMMAND_STATUS_REG); 1484 reg |= PCI_COMMAND_MASTER_ENABLE; 1485 PCI_CONF_WRITE(PCI_COMMAND_STATUS_REG, reg); 1486 1487 /* Get revision */ 1488 sc->vr_revid = PCI_REVISION(pa->pa_class); 1489 1490 /* 1491 * Map control/status registers. 1492 */ 1493 { 1494 bus_space_tag_t iot, memt; 1495 bus_space_handle_t ioh, memh; 1496 int ioh_valid, memh_valid; 1497 pci_intr_handle_t intrhandle; 1498 const char *intrstr; 1499 1500 ioh_valid = (pci_mapreg_map(pa, VR_PCI_LOIO, 1501 PCI_MAPREG_TYPE_IO, 0, 1502 &iot, &ioh, NULL, NULL) == 0); 1503 memh_valid = (pci_mapreg_map(pa, VR_PCI_LOMEM, 1504 PCI_MAPREG_TYPE_MEM | 1505 PCI_MAPREG_MEM_TYPE_32BIT, 1506 0, &memt, &memh, NULL, NULL) == 0); 1507 #if defined(VR_USEIOSPACE) 1508 if (ioh_valid) { 1509 sc->vr_bst = iot; 1510 sc->vr_bsh = ioh; 1511 } else if (memh_valid) { 1512 sc->vr_bst = memt; 1513 sc->vr_bsh = memh; 1514 } 1515 #else 1516 if (memh_valid) { 1517 sc->vr_bst = memt; 1518 sc->vr_bsh = memh; 1519 } else if (ioh_valid) { 1520 sc->vr_bst = iot; 1521 sc->vr_bsh = ioh; 1522 } 1523 #endif 1524 else { 1525 printf(": unable to map device registers\n"); 1526 return; 1527 } 1528 1529 /* Allocate interrupt */ 1530 if (pci_intr_map(pa, &intrhandle)) { 1531 aprint_error_dev(self, "couldn't map interrupt\n"); 1532 return; 1533 } 1534 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 1535 sc->vr_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 1536 vr_intr, sc); 1537 if (sc->vr_ih == NULL) { 1538 aprint_error_dev(self, "couldn't establish interrupt"); 1539 if (intrstr != NULL) 1540 printf(" at %s", intrstr); 1541 printf("\n"); 1542 } 1543 printf("%s: interrupting at %s\n", 1544 device_xname(self), intrstr); 1545 } 1546 1547 /* 1548 * Windows may put the chip in suspend mode when it 1549 * shuts down. Be sure to kick it in the head to wake it 1550 * up again. 1551 * 1552 * Don't touch this register on VT3043 since it causes 1553 * kernel MCHK trap on macppc. 1554 * (Note some VT86C100A chip returns a product ID of VT3043) 1555 */ 1556 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT3043) 1557 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 1558 1559 /* Reset the adapter. */ 1560 vr_reset(sc); 1561 1562 /* 1563 * Get station address. The way the Rhine chips work, 1564 * you're not allowed to directly access the EEPROM once 1565 * they've been programmed a special way. Consequently, 1566 * we need to read the node address from the PAR0 and PAR1 1567 * registers. 1568 * 1569 * XXXSCW: On the Rhine III, setting VR_EECSR_LOAD forces a reload 1570 * of the *whole* EEPROM, not just the MAC address. This is 1571 * pretty pointless since the chip does this automatically 1572 * at powerup/reset. 1573 * I suspect the same thing applies to the other Rhine 1574 * variants, but in the absence of a data sheet for those 1575 * (and the lack of anyone else noticing the problems this 1576 * causes) I'm going to retain the old behaviour for the 1577 * other parts. 1578 * In some cases, the chip really does startup without having 1579 * read the EEPROM (kern/34812). To handle this case, we force 1580 * a reload if we see an all-zeroes MAC address. 1581 */ 1582 for (mac = 0, i = 0; i < ETHER_ADDR_LEN; i++) 1583 mac |= (eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i)); 1584 1585 if (mac == 0 || (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT6105 && 1586 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT6102)) { 1587 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 1588 DELAY(200); 1589 for (i = 0; i < ETHER_ADDR_LEN; i++) 1590 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 1591 } 1592 1593 /* 1594 * A Rhine chip was detected. Inform the world. 1595 */ 1596 printf("%s: Ethernet address: %s\n", 1597 device_xname(self), ether_sprintf(eaddr)); 1598 1599 memcpy(sc->vr_enaddr, eaddr, ETHER_ADDR_LEN); 1600 1601 sc->vr_dmat = pa->pa_dmat; 1602 1603 /* 1604 * Allocate the control data structures, and create and load 1605 * the DMA map for it. 1606 */ 1607 if ((error = bus_dmamem_alloc(sc->vr_dmat, 1608 sizeof(struct vr_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 1609 0)) != 0) { 1610 aprint_error_dev(self, "unable to allocate control data, error = %d\n", error); 1611 goto fail_0; 1612 } 1613 1614 if ((error = bus_dmamem_map(sc->vr_dmat, &seg, rseg, 1615 sizeof(struct vr_control_data), (void **)&sc->vr_control_data, 1616 BUS_DMA_COHERENT)) != 0) { 1617 aprint_error_dev(self, "unable to map control data, error = %d\n", error); 1618 goto fail_1; 1619 } 1620 1621 if ((error = bus_dmamap_create(sc->vr_dmat, 1622 sizeof(struct vr_control_data), 1, 1623 sizeof(struct vr_control_data), 0, 0, 1624 &sc->vr_cddmamap)) != 0) { 1625 aprint_error_dev(self, "unable to create control data DMA map, " 1626 "error = %d\n", error); 1627 goto fail_2; 1628 } 1629 1630 if ((error = bus_dmamap_load(sc->vr_dmat, sc->vr_cddmamap, 1631 sc->vr_control_data, sizeof(struct vr_control_data), NULL, 1632 0)) != 0) { 1633 aprint_error_dev(self, "unable to load control data DMA map, error = %d\n", 1634 error); 1635 goto fail_3; 1636 } 1637 1638 /* 1639 * Create the transmit buffer DMA maps. 1640 */ 1641 for (i = 0; i < VR_NTXDESC; i++) { 1642 if ((error = bus_dmamap_create(sc->vr_dmat, MCLBYTES, 1643 1, MCLBYTES, 0, 0, 1644 &VR_DSTX(sc, i)->ds_dmamap)) != 0) { 1645 aprint_error_dev(self, "unable to create tx DMA map %d, " 1646 "error = %d\n", i, error); 1647 goto fail_4; 1648 } 1649 } 1650 1651 /* 1652 * Create the receive buffer DMA maps. 1653 */ 1654 for (i = 0; i < VR_NRXDESC; i++) { 1655 if ((error = bus_dmamap_create(sc->vr_dmat, MCLBYTES, 1, 1656 MCLBYTES, 0, 0, 1657 &VR_DSRX(sc, i)->ds_dmamap)) != 0) { 1658 aprint_error_dev(self, "unable to create rx DMA map %d, " 1659 "error = %d\n", i, error); 1660 goto fail_5; 1661 } 1662 VR_DSRX(sc, i)->ds_mbuf = NULL; 1663 } 1664 1665 ifp = &sc->vr_ec.ec_if; 1666 ifp->if_softc = sc; 1667 ifp->if_mtu = ETHERMTU; 1668 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1669 ifp->if_ioctl = vr_ioctl; 1670 ifp->if_start = vr_start; 1671 ifp->if_watchdog = vr_watchdog; 1672 ifp->if_init = vr_init; 1673 ifp->if_stop = vr_stop; 1674 IFQ_SET_READY(&ifp->if_snd); 1675 1676 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 1677 1678 /* 1679 * Initialize MII/media info. 1680 */ 1681 sc->vr_mii.mii_ifp = ifp; 1682 sc->vr_mii.mii_readreg = vr_mii_readreg; 1683 sc->vr_mii.mii_writereg = vr_mii_writereg; 1684 sc->vr_mii.mii_statchg = vr_mii_statchg; 1685 1686 sc->vr_ec.ec_mii = &sc->vr_mii; 1687 ifmedia_init(&sc->vr_mii.mii_media, IFM_IMASK, ether_mediachange, 1688 ether_mediastatus); 1689 mii_attach(self, &sc->vr_mii, 0xffffffff, MII_PHY_ANY, 1690 MII_OFFSET_ANY, MIIF_FORCEANEG); 1691 if (LIST_FIRST(&sc->vr_mii.mii_phys) == NULL) { 1692 ifmedia_add(&sc->vr_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1693 ifmedia_set(&sc->vr_mii.mii_media, IFM_ETHER|IFM_NONE); 1694 } else 1695 ifmedia_set(&sc->vr_mii.mii_media, IFM_ETHER|IFM_AUTO); 1696 1697 /* 1698 * Call MI attach routines. 1699 */ 1700 if_attach(ifp); 1701 ether_ifattach(ifp, sc->vr_enaddr); 1702 #if NRND > 0 1703 rnd_attach_source(&sc->rnd_source, device_xname(self), 1704 RND_TYPE_NET, 0); 1705 #endif 1706 1707 sc->vr_ats = shutdownhook_establish(vr_shutdown, sc); 1708 if (sc->vr_ats == NULL) 1709 aprint_error_dev(self, "warning: couldn't establish shutdown hook\n"); 1710 return; 1711 1712 fail_5: 1713 for (i = 0; i < VR_NRXDESC; i++) { 1714 if (sc->vr_rxsoft[i].ds_dmamap != NULL) 1715 bus_dmamap_destroy(sc->vr_dmat, 1716 sc->vr_rxsoft[i].ds_dmamap); 1717 } 1718 fail_4: 1719 for (i = 0; i < VR_NTXDESC; i++) { 1720 if (sc->vr_txsoft[i].ds_dmamap != NULL) 1721 bus_dmamap_destroy(sc->vr_dmat, 1722 sc->vr_txsoft[i].ds_dmamap); 1723 } 1724 bus_dmamap_unload(sc->vr_dmat, sc->vr_cddmamap); 1725 fail_3: 1726 bus_dmamap_destroy(sc->vr_dmat, sc->vr_cddmamap); 1727 fail_2: 1728 bus_dmamem_unmap(sc->vr_dmat, (void *)sc->vr_control_data, 1729 sizeof(struct vr_control_data)); 1730 fail_1: 1731 bus_dmamem_free(sc->vr_dmat, &seg, rseg); 1732 fail_0: 1733 return; 1734 } 1735 1736 static int 1737 vr_restore_state(pci_chipset_tag_t pc, pcitag_t tag, device_t self, 1738 pcireg_t state) 1739 { 1740 struct vr_softc *sc = device_private(self); 1741 int error; 1742 1743 if (state == PCI_PMCSR_STATE_D0) 1744 return 0; 1745 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 1746 return error; 1747 1748 /* Restore PCI config data. */ 1749 PCI_CONF_WRITE(VR_PCI_LOIO, sc->vr_save_iobase); 1750 PCI_CONF_WRITE(VR_PCI_LOMEM, sc->vr_save_membase); 1751 PCI_CONF_WRITE(PCI_INTERRUPT_REG, sc->vr_save_irq); 1752 return 0; 1753 } 1754