1 /* $NetBSD: if_vr.c,v 1.76 2006/06/17 23:34:27 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1997, 1998 42 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Bill Paul. 55 * 4. Neither the name of the author nor the names of any co-contributors 56 * may be used to endorse or promote products derived from this software 57 * without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 63 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 64 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 65 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 66 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 67 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 68 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 69 * THE POSSIBILITY OF SUCH DAMAGE. 70 * 71 * $FreeBSD: if_vr.c,v 1.7 1999/01/10 18:51:49 wpaul Exp $ 72 */ 73 74 /* 75 * VIA Rhine fast ethernet PCI NIC driver 76 * 77 * Supports various network adapters based on the VIA Rhine 78 * and Rhine II PCI controllers, including the D-Link DFE530TX. 79 * Datasheets are available at http://www.via.com.tw. 80 * 81 * Written by Bill Paul <wpaul@ctr.columbia.edu> 82 * Electrical Engineering Department 83 * Columbia University, New York City 84 */ 85 86 /* 87 * The VIA Rhine controllers are similar in some respects to the 88 * the DEC tulip chips, except less complicated. The controller 89 * uses an MII bus and an external physical layer interface. The 90 * receiver has a one entry perfect filter and a 64-bit hash table 91 * multicast filter. Transmit and receive descriptors are similar 92 * to the tulip. 93 * 94 * The Rhine has a serious flaw in its transmit DMA mechanism: 95 * transmit buffers must be longword aligned. Unfortunately, 96 * the kernel doesn't guarantee that mbufs will be filled in starting 97 * at longword boundaries, so we have to do a buffer copy before 98 * transmission. 99 * 100 * Apparently, the receive DMA mechanism also has the same flaw. This 101 * means that on systems with struct alignment requirements, incoming 102 * frames must be copied to a new buffer which shifts the data forward 103 * 2 bytes so that the payload is aligned on a 4-byte boundary. 104 */ 105 106 #include <sys/cdefs.h> 107 __KERNEL_RCSID(0, "$NetBSD: if_vr.c,v 1.76 2006/06/17 23:34:27 christos Exp $"); 108 109 #include "rnd.h" 110 111 #include <sys/param.h> 112 #include <sys/systm.h> 113 #include <sys/callout.h> 114 #include <sys/sockio.h> 115 #include <sys/mbuf.h> 116 #include <sys/malloc.h> 117 #include <sys/kernel.h> 118 #include <sys/socket.h> 119 #include <sys/device.h> 120 121 #if NRND > 0 122 #include <sys/rnd.h> 123 #endif 124 125 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 126 127 #include <net/if.h> 128 #include <net/if_arp.h> 129 #include <net/if_dl.h> 130 #include <net/if_media.h> 131 #include <net/if_ether.h> 132 133 #include "bpfilter.h" 134 #if NBPFILTER > 0 135 #include <net/bpf.h> 136 #endif 137 138 #include <machine/bus.h> 139 #include <machine/intr.h> 140 #include <machine/endian.h> 141 142 #include <dev/mii/mii.h> 143 #include <dev/mii/miivar.h> 144 #include <dev/mii/mii_bitbang.h> 145 146 #include <dev/pci/pcireg.h> 147 #include <dev/pci/pcivar.h> 148 #include <dev/pci/pcidevs.h> 149 150 #include <dev/pci/if_vrreg.h> 151 152 #define VR_USEIOSPACE 153 154 /* 155 * Various supported device vendors/types and their names. 156 */ 157 static struct vr_type { 158 pci_vendor_id_t vr_vid; 159 pci_product_id_t vr_did; 160 const char *vr_name; 161 } vr_devs[] = { 162 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT3043, 163 "VIA VT3043 (Rhine) 10/100" }, 164 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6102, 165 "VIA VT6102 (Rhine II) 10/100" }, 166 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6105, 167 "VIA VT6105 (Rhine III) 10/100" }, 168 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT86C100A, 169 "VIA VT86C100A (Rhine-II) 10/100" }, 170 { 0, 0, NULL } 171 }; 172 173 /* 174 * Transmit descriptor list size. 175 */ 176 #define VR_NTXDESC 64 177 #define VR_NTXDESC_MASK (VR_NTXDESC - 1) 178 #define VR_NEXTTX(x) (((x) + 1) & VR_NTXDESC_MASK) 179 180 /* 181 * Receive descriptor list size. 182 */ 183 #define VR_NRXDESC 64 184 #define VR_NRXDESC_MASK (VR_NRXDESC - 1) 185 #define VR_NEXTRX(x) (((x) + 1) & VR_NRXDESC_MASK) 186 187 /* 188 * Control data structres that are DMA'd to the Rhine chip. We allocate 189 * them in a single clump that maps to a single DMA segment to make several 190 * things easier. 191 * 192 * Note that since we always copy outgoing packets to aligned transmit 193 * buffers, we can reduce the transmit descriptors to one per packet. 194 */ 195 struct vr_control_data { 196 struct vr_desc vr_txdescs[VR_NTXDESC]; 197 struct vr_desc vr_rxdescs[VR_NRXDESC]; 198 }; 199 200 #define VR_CDOFF(x) offsetof(struct vr_control_data, x) 201 #define VR_CDTXOFF(x) VR_CDOFF(vr_txdescs[(x)]) 202 #define VR_CDRXOFF(x) VR_CDOFF(vr_rxdescs[(x)]) 203 204 /* 205 * Software state of transmit and receive descriptors. 206 */ 207 struct vr_descsoft { 208 struct mbuf *ds_mbuf; /* head of mbuf chain */ 209 bus_dmamap_t ds_dmamap; /* our DMA map */ 210 }; 211 212 struct vr_softc { 213 struct device vr_dev; /* generic device glue */ 214 void *vr_ih; /* interrupt cookie */ 215 void *vr_ats; /* shutdown hook */ 216 bus_space_tag_t vr_bst; /* bus space tag */ 217 bus_space_handle_t vr_bsh; /* bus space handle */ 218 bus_dma_tag_t vr_dmat; /* bus DMA tag */ 219 pci_chipset_tag_t vr_pc; /* PCI chipset info */ 220 pcitag_t vr_tag; /* PCI tag */ 221 struct ethercom vr_ec; /* Ethernet common info */ 222 u_int8_t vr_enaddr[ETHER_ADDR_LEN]; 223 struct mii_data vr_mii; /* MII/media info */ 224 225 u_int8_t vr_revid; /* Rhine chip revision */ 226 227 struct callout vr_tick_ch; /* tick callout */ 228 229 bus_dmamap_t vr_cddmamap; /* control data DMA map */ 230 #define vr_cddma vr_cddmamap->dm_segs[0].ds_addr 231 232 /* 233 * Software state for transmit and receive descriptors. 234 */ 235 struct vr_descsoft vr_txsoft[VR_NTXDESC]; 236 struct vr_descsoft vr_rxsoft[VR_NRXDESC]; 237 238 /* 239 * Control data structures. 240 */ 241 struct vr_control_data *vr_control_data; 242 243 int vr_txpending; /* number of TX requests pending */ 244 int vr_txdirty; /* first dirty TX descriptor */ 245 int vr_txlast; /* last used TX descriptor */ 246 247 int vr_rxptr; /* next ready RX descriptor */ 248 249 u_int32_t vr_save_iobase; 250 u_int32_t vr_save_membase; 251 u_int32_t vr_save_irq; 252 253 #if NRND > 0 254 rndsource_element_t rnd_source; /* random source */ 255 #endif 256 }; 257 258 #define VR_CDTXADDR(sc, x) ((sc)->vr_cddma + VR_CDTXOFF((x))) 259 #define VR_CDRXADDR(sc, x) ((sc)->vr_cddma + VR_CDRXOFF((x))) 260 261 #define VR_CDTX(sc, x) (&(sc)->vr_control_data->vr_txdescs[(x)]) 262 #define VR_CDRX(sc, x) (&(sc)->vr_control_data->vr_rxdescs[(x)]) 263 264 #define VR_DSTX(sc, x) (&(sc)->vr_txsoft[(x)]) 265 #define VR_DSRX(sc, x) (&(sc)->vr_rxsoft[(x)]) 266 267 #define VR_CDTXSYNC(sc, x, ops) \ 268 bus_dmamap_sync((sc)->vr_dmat, (sc)->vr_cddmamap, \ 269 VR_CDTXOFF((x)), sizeof(struct vr_desc), (ops)) 270 271 #define VR_CDRXSYNC(sc, x, ops) \ 272 bus_dmamap_sync((sc)->vr_dmat, (sc)->vr_cddmamap, \ 273 VR_CDRXOFF((x)), sizeof(struct vr_desc), (ops)) 274 275 /* 276 * Note we rely on MCLBYTES being a power of two below. 277 */ 278 #define VR_INIT_RXDESC(sc, i) \ 279 do { \ 280 struct vr_desc *__d = VR_CDRX((sc), (i)); \ 281 struct vr_descsoft *__ds = VR_DSRX((sc), (i)); \ 282 \ 283 __d->vr_next = htole32(VR_CDRXADDR((sc), VR_NEXTRX((i)))); \ 284 __d->vr_status = htole32(VR_RXSTAT_FIRSTFRAG | \ 285 VR_RXSTAT_LASTFRAG | VR_RXSTAT_OWN); \ 286 __d->vr_data = htole32(__ds->ds_dmamap->dm_segs[0].ds_addr); \ 287 __d->vr_ctl = htole32(VR_RXCTL_CHAIN | VR_RXCTL_RX_INTR | \ 288 ((MCLBYTES - 1) & VR_RXCTL_BUFLEN)); \ 289 VR_CDRXSYNC((sc), (i), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 290 } while (/* CONSTCOND */ 0) 291 292 /* 293 * register space access macros 294 */ 295 #define CSR_WRITE_4(sc, reg, val) \ 296 bus_space_write_4(sc->vr_bst, sc->vr_bsh, reg, val) 297 #define CSR_WRITE_2(sc, reg, val) \ 298 bus_space_write_2(sc->vr_bst, sc->vr_bsh, reg, val) 299 #define CSR_WRITE_1(sc, reg, val) \ 300 bus_space_write_1(sc->vr_bst, sc->vr_bsh, reg, val) 301 302 #define CSR_READ_4(sc, reg) \ 303 bus_space_read_4(sc->vr_bst, sc->vr_bsh, reg) 304 #define CSR_READ_2(sc, reg) \ 305 bus_space_read_2(sc->vr_bst, sc->vr_bsh, reg) 306 #define CSR_READ_1(sc, reg) \ 307 bus_space_read_1(sc->vr_bst, sc->vr_bsh, reg) 308 309 #define VR_TIMEOUT 1000 310 311 static int vr_add_rxbuf(struct vr_softc *, int); 312 313 static void vr_rxeof(struct vr_softc *); 314 static void vr_rxeoc(struct vr_softc *); 315 static void vr_txeof(struct vr_softc *); 316 static int vr_intr(void *); 317 static void vr_start(struct ifnet *); 318 static int vr_ioctl(struct ifnet *, u_long, caddr_t); 319 static int vr_init(struct ifnet *); 320 static void vr_stop(struct ifnet *, int); 321 static void vr_rxdrain(struct vr_softc *); 322 static void vr_watchdog(struct ifnet *); 323 static void vr_tick(void *); 324 325 static int vr_ifmedia_upd(struct ifnet *); 326 static void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *); 327 328 static int vr_mii_readreg(struct device *, int, int); 329 static void vr_mii_writereg(struct device *, int, int, int); 330 static void vr_mii_statchg(struct device *); 331 332 static void vr_setmulti(struct vr_softc *); 333 static void vr_reset(struct vr_softc *); 334 static int vr_restore_state(pci_chipset_tag_t, pcitag_t, void *, pcireg_t); 335 336 int vr_copy_small = 0; 337 338 #define VR_SETBIT(sc, reg, x) \ 339 CSR_WRITE_1(sc, reg, \ 340 CSR_READ_1(sc, reg) | (x)) 341 342 #define VR_CLRBIT(sc, reg, x) \ 343 CSR_WRITE_1(sc, reg, \ 344 CSR_READ_1(sc, reg) & ~(x)) 345 346 #define VR_SETBIT16(sc, reg, x) \ 347 CSR_WRITE_2(sc, reg, \ 348 CSR_READ_2(sc, reg) | (x)) 349 350 #define VR_CLRBIT16(sc, reg, x) \ 351 CSR_WRITE_2(sc, reg, \ 352 CSR_READ_2(sc, reg) & ~(x)) 353 354 #define VR_SETBIT32(sc, reg, x) \ 355 CSR_WRITE_4(sc, reg, \ 356 CSR_READ_4(sc, reg) | (x)) 357 358 #define VR_CLRBIT32(sc, reg, x) \ 359 CSR_WRITE_4(sc, reg, \ 360 CSR_READ_4(sc, reg) & ~(x)) 361 362 /* 363 * MII bit-bang glue. 364 */ 365 static u_int32_t vr_mii_bitbang_read(struct device *); 366 static void vr_mii_bitbang_write(struct device *, u_int32_t); 367 368 static const struct mii_bitbang_ops vr_mii_bitbang_ops = { 369 vr_mii_bitbang_read, 370 vr_mii_bitbang_write, 371 { 372 VR_MIICMD_DATAOUT, /* MII_BIT_MDO */ 373 VR_MIICMD_DATAIN, /* MII_BIT_MDI */ 374 VR_MIICMD_CLK, /* MII_BIT_MDC */ 375 VR_MIICMD_DIR, /* MII_BIT_DIR_HOST_PHY */ 376 0, /* MII_BIT_DIR_PHY_HOST */ 377 } 378 }; 379 380 static u_int32_t 381 vr_mii_bitbang_read(struct device *self) 382 { 383 struct vr_softc *sc = (void *) self; 384 385 return (CSR_READ_1(sc, VR_MIICMD)); 386 } 387 388 static void 389 vr_mii_bitbang_write(struct device *self, u_int32_t val) 390 { 391 struct vr_softc *sc = (void *) self; 392 393 CSR_WRITE_1(sc, VR_MIICMD, (val & 0xff) | VR_MIICMD_DIRECTPGM); 394 } 395 396 /* 397 * Read an PHY register through the MII. 398 */ 399 static int 400 vr_mii_readreg(struct device *self, int phy, int reg) 401 { 402 struct vr_softc *sc = (void *) self; 403 404 CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 405 return (mii_bitbang_readreg(self, &vr_mii_bitbang_ops, phy, reg)); 406 } 407 408 /* 409 * Write to a PHY register through the MII. 410 */ 411 static void 412 vr_mii_writereg(struct device *self, int phy, int reg, int val) 413 { 414 struct vr_softc *sc = (void *) self; 415 416 CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 417 mii_bitbang_writereg(self, &vr_mii_bitbang_ops, phy, reg, val); 418 } 419 420 static void 421 vr_mii_statchg(struct device *self) 422 { 423 struct vr_softc *sc = (struct vr_softc *)self; 424 425 /* 426 * In order to fiddle with the 'full-duplex' bit in the netconfig 427 * register, we first have to put the transmit and/or receive logic 428 * in the idle state. 429 */ 430 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 431 432 if (sc->vr_mii.mii_media_active & IFM_FDX) 433 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 434 else 435 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 436 437 if (sc->vr_ec.ec_if.if_flags & IFF_RUNNING) 438 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 439 } 440 441 #define vr_calchash(addr) \ 442 (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26) 443 444 /* 445 * Program the 64-bit multicast hash filter. 446 */ 447 static void 448 vr_setmulti(struct vr_softc *sc) 449 { 450 struct ifnet *ifp; 451 int h = 0; 452 u_int32_t hashes[2] = { 0, 0 }; 453 struct ether_multistep step; 454 struct ether_multi *enm; 455 int mcnt = 0; 456 u_int8_t rxfilt; 457 458 ifp = &sc->vr_ec.ec_if; 459 460 rxfilt = CSR_READ_1(sc, VR_RXCFG); 461 462 if (ifp->if_flags & IFF_PROMISC) { 463 allmulti: 464 ifp->if_flags |= IFF_ALLMULTI; 465 rxfilt |= VR_RXCFG_RX_MULTI; 466 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 467 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 468 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 469 return; 470 } 471 472 /* first, zot all the existing hash bits */ 473 CSR_WRITE_4(sc, VR_MAR0, 0); 474 CSR_WRITE_4(sc, VR_MAR1, 0); 475 476 /* now program new ones */ 477 ETHER_FIRST_MULTI(step, &sc->vr_ec, enm); 478 while (enm != NULL) { 479 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 480 ETHER_ADDR_LEN) != 0) 481 goto allmulti; 482 483 h = vr_calchash(enm->enm_addrlo); 484 485 if (h < 32) 486 hashes[0] |= (1 << h); 487 else 488 hashes[1] |= (1 << (h - 32)); 489 ETHER_NEXT_MULTI(step, enm); 490 mcnt++; 491 } 492 493 ifp->if_flags &= ~IFF_ALLMULTI; 494 495 if (mcnt) 496 rxfilt |= VR_RXCFG_RX_MULTI; 497 else 498 rxfilt &= ~VR_RXCFG_RX_MULTI; 499 500 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 501 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 502 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 503 } 504 505 static void 506 vr_reset(struct vr_softc *sc) 507 { 508 int i; 509 510 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 511 512 for (i = 0; i < VR_TIMEOUT; i++) { 513 DELAY(10); 514 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 515 break; 516 } 517 if (i == VR_TIMEOUT) { 518 if (sc->vr_revid < REV_ID_VT3065_A) { 519 printf("%s: reset never completed!\n", 520 sc->vr_dev.dv_xname); 521 } else { 522 /* Use newer force reset command */ 523 printf("%s: using force reset command.\n", 524 sc->vr_dev.dv_xname); 525 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 526 } 527 } 528 529 /* Wait a little while for the chip to get its brains in order. */ 530 DELAY(1000); 531 } 532 533 /* 534 * Initialize an RX descriptor and attach an MBUF cluster. 535 * Note: the length fields are only 11 bits wide, which means the 536 * largest size we can specify is 2047. This is important because 537 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 538 * overflow the field and make a mess. 539 */ 540 static int 541 vr_add_rxbuf(struct vr_softc *sc, int i) 542 { 543 struct vr_descsoft *ds = VR_DSRX(sc, i); 544 struct mbuf *m_new; 545 int error; 546 547 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 548 if (m_new == NULL) 549 return (ENOBUFS); 550 551 MCLGET(m_new, M_DONTWAIT); 552 if ((m_new->m_flags & M_EXT) == 0) { 553 m_freem(m_new); 554 return (ENOBUFS); 555 } 556 557 if (ds->ds_mbuf != NULL) 558 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 559 560 ds->ds_mbuf = m_new; 561 562 error = bus_dmamap_load(sc->vr_dmat, ds->ds_dmamap, 563 m_new->m_ext.ext_buf, m_new->m_ext.ext_size, NULL, 564 BUS_DMA_READ|BUS_DMA_NOWAIT); 565 if (error) { 566 printf("%s: unable to load rx DMA map %d, error = %d\n", 567 sc->vr_dev.dv_xname, i, error); 568 panic("vr_add_rxbuf"); /* XXX */ 569 } 570 571 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 572 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 573 574 VR_INIT_RXDESC(sc, i); 575 576 return (0); 577 } 578 579 /* 580 * A frame has been uploaded: pass the resulting mbuf chain up to 581 * the higher level protocols. 582 */ 583 static void 584 vr_rxeof(struct vr_softc *sc) 585 { 586 struct mbuf *m; 587 struct ifnet *ifp; 588 struct vr_desc *d; 589 struct vr_descsoft *ds; 590 int i, total_len; 591 u_int32_t rxstat; 592 593 ifp = &sc->vr_ec.ec_if; 594 595 for (i = sc->vr_rxptr;; i = VR_NEXTRX(i)) { 596 d = VR_CDRX(sc, i); 597 ds = VR_DSRX(sc, i); 598 599 VR_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 600 601 rxstat = le32toh(d->vr_status); 602 603 if (rxstat & VR_RXSTAT_OWN) { 604 /* 605 * We have processed all of the receive buffers. 606 */ 607 break; 608 } 609 610 /* 611 * If an error occurs, update stats, clear the 612 * status word and leave the mbuf cluster in place: 613 * it should simply get re-used next time this descriptor 614 * comes up in the ring. 615 */ 616 if (rxstat & VR_RXSTAT_RXERR) { 617 const char *errstr; 618 619 ifp->if_ierrors++; 620 switch (rxstat & 0x000000FF) { 621 case VR_RXSTAT_CRCERR: 622 errstr = "crc error"; 623 break; 624 case VR_RXSTAT_FRAMEALIGNERR: 625 errstr = "frame alignment error"; 626 break; 627 case VR_RXSTAT_FIFOOFLOW: 628 errstr = "FIFO overflow"; 629 break; 630 case VR_RXSTAT_GIANT: 631 errstr = "received giant packet"; 632 break; 633 case VR_RXSTAT_RUNT: 634 errstr = "received runt packet"; 635 break; 636 case VR_RXSTAT_BUSERR: 637 errstr = "system bus error"; 638 break; 639 case VR_RXSTAT_BUFFERR: 640 errstr = "rx buffer error"; 641 break; 642 default: 643 errstr = "unknown rx error"; 644 break; 645 } 646 printf("%s: receive error: %s\n", sc->vr_dev.dv_xname, 647 errstr); 648 649 VR_INIT_RXDESC(sc, i); 650 651 continue; 652 } else if (!(rxstat & VR_RXSTAT_FIRSTFRAG) || 653 !(rxstat & VR_RXSTAT_LASTFRAG)) { 654 /* 655 * This driver expects to receive whole packets every 656 * time. In case we receive a fragment that is not 657 * a complete packet, we discard it. 658 */ 659 ifp->if_ierrors++; 660 661 printf("%s: receive error: incomplete frame; " 662 "size = %d, status = 0x%x\n", 663 sc->vr_dev.dv_xname, 664 VR_RXBYTES(le32toh(d->vr_status)), rxstat); 665 666 VR_INIT_RXDESC(sc, i); 667 668 continue; 669 } 670 671 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 672 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 673 674 /* No errors; receive the packet. */ 675 total_len = VR_RXBYTES(le32toh(d->vr_status)); 676 #ifdef DIAGNOSTIC 677 if (total_len == 0) { 678 /* 679 * If we receive a zero-length packet, we probably 680 * missed to handle an error condition above. 681 * Discard it to avoid a later crash. 682 */ 683 ifp->if_ierrors++; 684 685 printf("%s: receive error: zero-length packet; " 686 "status = 0x%x\n", 687 sc->vr_dev.dv_xname, rxstat); 688 689 VR_INIT_RXDESC(sc, i); 690 691 continue; 692 } 693 #endif 694 695 /* 696 * The Rhine chip includes the CRC with every packet. 697 * Trim it off here. 698 */ 699 total_len -= ETHER_CRC_LEN; 700 701 #ifdef __NO_STRICT_ALIGNMENT 702 /* 703 * If the packet is small enough to fit in a 704 * single header mbuf, allocate one and copy 705 * the data into it. This greatly reduces 706 * memory consumption when we receive lots 707 * of small packets. 708 * 709 * Otherwise, we add a new buffer to the receive 710 * chain. If this fails, we drop the packet and 711 * recycle the old buffer. 712 */ 713 if (vr_copy_small != 0 && total_len <= MHLEN) { 714 MGETHDR(m, M_DONTWAIT, MT_DATA); 715 if (m == NULL) 716 goto dropit; 717 memcpy(mtod(m, caddr_t), 718 mtod(ds->ds_mbuf, caddr_t), total_len); 719 VR_INIT_RXDESC(sc, i); 720 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 721 ds->ds_dmamap->dm_mapsize, 722 BUS_DMASYNC_PREREAD); 723 } else { 724 m = ds->ds_mbuf; 725 if (vr_add_rxbuf(sc, i) == ENOBUFS) { 726 dropit: 727 ifp->if_ierrors++; 728 VR_INIT_RXDESC(sc, i); 729 bus_dmamap_sync(sc->vr_dmat, 730 ds->ds_dmamap, 0, 731 ds->ds_dmamap->dm_mapsize, 732 BUS_DMASYNC_PREREAD); 733 continue; 734 } 735 } 736 #else 737 /* 738 * The Rhine's packet buffers must be 4-byte aligned. 739 * But this means that the data after the Ethernet header 740 * is misaligned. We must allocate a new buffer and 741 * copy the data, shifted forward 2 bytes. 742 */ 743 MGETHDR(m, M_DONTWAIT, MT_DATA); 744 if (m == NULL) { 745 dropit: 746 ifp->if_ierrors++; 747 VR_INIT_RXDESC(sc, i); 748 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 749 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 750 continue; 751 } 752 if (total_len > (MHLEN - 2)) { 753 MCLGET(m, M_DONTWAIT); 754 if ((m->m_flags & M_EXT) == 0) { 755 m_freem(m); 756 goto dropit; 757 } 758 } 759 m->m_data += 2; 760 761 /* 762 * Note that we use clusters for incoming frames, so the 763 * buffer is virtually contiguous. 764 */ 765 memcpy(mtod(m, caddr_t), mtod(ds->ds_mbuf, caddr_t), 766 total_len); 767 768 /* Allow the receive descriptor to continue using its mbuf. */ 769 VR_INIT_RXDESC(sc, i); 770 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 771 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 772 #endif /* __NO_STRICT_ALIGNMENT */ 773 774 ifp->if_ipackets++; 775 m->m_pkthdr.rcvif = ifp; 776 m->m_pkthdr.len = m->m_len = total_len; 777 #if NBPFILTER > 0 778 /* 779 * Handle BPF listeners. Let the BPF user see the packet, but 780 * don't pass it up to the ether_input() layer unless it's 781 * a broadcast packet, multicast packet, matches our ethernet 782 * address or the interface is in promiscuous mode. 783 */ 784 if (ifp->if_bpf) 785 bpf_mtap(ifp->if_bpf, m); 786 #endif 787 /* Pass it on. */ 788 (*ifp->if_input)(ifp, m); 789 } 790 791 /* Update the receive pointer. */ 792 sc->vr_rxptr = i; 793 } 794 795 void 796 vr_rxeoc(struct vr_softc *sc) 797 { 798 799 vr_rxeof(sc); 800 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 801 CSR_WRITE_4(sc, VR_RXADDR, VR_CDRXADDR(sc, sc->vr_rxptr)); 802 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 803 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 804 } 805 806 /* 807 * A frame was downloaded to the chip. It's safe for us to clean up 808 * the list buffers. 809 */ 810 static void 811 vr_txeof(struct vr_softc *sc) 812 { 813 struct ifnet *ifp = &sc->vr_ec.ec_if; 814 struct vr_desc *d; 815 struct vr_descsoft *ds; 816 u_int32_t txstat; 817 int i; 818 819 ifp->if_flags &= ~IFF_OACTIVE; 820 821 /* 822 * Go through our tx list and free mbufs for those 823 * frames that have been transmitted. 824 */ 825 for (i = sc->vr_txdirty; sc->vr_txpending != 0; 826 i = VR_NEXTTX(i), sc->vr_txpending--) { 827 d = VR_CDTX(sc, i); 828 ds = VR_DSTX(sc, i); 829 830 VR_CDTXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 831 832 txstat = le32toh(d->vr_status); 833 if (txstat & VR_TXSTAT_OWN) 834 break; 835 836 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 837 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 838 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 839 m_freem(ds->ds_mbuf); 840 ds->ds_mbuf = NULL; 841 842 if (txstat & VR_TXSTAT_ERRSUM) { 843 ifp->if_oerrors++; 844 if (txstat & VR_TXSTAT_DEFER) 845 ifp->if_collisions++; 846 if (txstat & VR_TXSTAT_LATECOLL) 847 ifp->if_collisions++; 848 } 849 850 ifp->if_collisions += (txstat & VR_TXSTAT_COLLCNT) >> 3; 851 ifp->if_opackets++; 852 } 853 854 /* Update the dirty transmit buffer pointer. */ 855 sc->vr_txdirty = i; 856 857 /* 858 * Cancel the watchdog timer if there are no pending 859 * transmissions. 860 */ 861 if (sc->vr_txpending == 0) 862 ifp->if_timer = 0; 863 } 864 865 static int 866 vr_intr(void *arg) 867 { 868 struct vr_softc *sc; 869 struct ifnet *ifp; 870 u_int16_t status; 871 int handled = 0, dotx = 0; 872 873 sc = arg; 874 ifp = &sc->vr_ec.ec_if; 875 876 /* Suppress unwanted interrupts. */ 877 if ((ifp->if_flags & IFF_UP) == 0) { 878 vr_stop(ifp, 1); 879 return (0); 880 } 881 882 /* Disable interrupts. */ 883 CSR_WRITE_2(sc, VR_IMR, 0x0000); 884 885 for (;;) { 886 status = CSR_READ_2(sc, VR_ISR); 887 if (status) 888 CSR_WRITE_2(sc, VR_ISR, status); 889 890 if ((status & VR_INTRS) == 0) 891 break; 892 893 handled = 1; 894 895 #if NRND > 0 896 if (RND_ENABLED(&sc->rnd_source)) 897 rnd_add_uint32(&sc->rnd_source, status); 898 #endif 899 900 if (status & VR_ISR_RX_OK) 901 vr_rxeof(sc); 902 903 if (status & 904 (VR_ISR_RX_ERR | VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW | 905 VR_ISR_RX_DROPPED)) 906 vr_rxeoc(sc); 907 908 if (status & VR_ISR_TX_OK) { 909 dotx = 1; 910 vr_txeof(sc); 911 } 912 913 if (status & (VR_ISR_TX_UNDERRUN | VR_ISR_TX_ABRT)) { 914 if (status & VR_ISR_TX_UNDERRUN) 915 printf("%s: transmit underrun\n", 916 sc->vr_dev.dv_xname); 917 if (status & VR_ISR_TX_ABRT) 918 printf("%s: transmit aborted\n", 919 sc->vr_dev.dv_xname); 920 ifp->if_oerrors++; 921 dotx = 1; 922 vr_txeof(sc); 923 if (sc->vr_txpending) { 924 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 925 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 926 } 927 /* 928 * Unfortunately many cards get stuck after 929 * aborted transmits, so we reset them. 930 */ 931 if (status & VR_ISR_TX_ABRT) { 932 printf("%s: restarting\n", sc->vr_dev.dv_xname); 933 dotx = 0; 934 (void) vr_init(ifp); 935 } 936 } 937 938 if (status & VR_ISR_BUSERR) { 939 printf("%s: PCI bus error\n", sc->vr_dev.dv_xname); 940 /* vr_init() calls vr_start() */ 941 dotx = 0; 942 (void) vr_init(ifp); 943 } 944 } 945 946 /* Re-enable interrupts. */ 947 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 948 949 if (dotx) 950 vr_start(ifp); 951 952 return (handled); 953 } 954 955 /* 956 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 957 * to the mbuf data regions directly in the transmit lists. We also save a 958 * copy of the pointers since the transmit list fragment pointers are 959 * physical addresses. 960 */ 961 static void 962 vr_start(struct ifnet *ifp) 963 { 964 struct vr_softc *sc = ifp->if_softc; 965 struct mbuf *m0, *m; 966 struct vr_desc *d; 967 struct vr_descsoft *ds; 968 int error, firsttx, nexttx, opending; 969 970 /* 971 * Remember the previous txpending and the first transmit 972 * descriptor we use. 973 */ 974 opending = sc->vr_txpending; 975 firsttx = VR_NEXTTX(sc->vr_txlast); 976 977 /* 978 * Loop through the send queue, setting up transmit descriptors 979 * until we drain the queue, or use up all available transmit 980 * descriptors. 981 */ 982 while (sc->vr_txpending < VR_NTXDESC) { 983 /* 984 * Grab a packet off the queue. 985 */ 986 IFQ_POLL(&ifp->if_snd, m0); 987 if (m0 == NULL) 988 break; 989 m = NULL; 990 991 /* 992 * Get the next available transmit descriptor. 993 */ 994 nexttx = VR_NEXTTX(sc->vr_txlast); 995 d = VR_CDTX(sc, nexttx); 996 ds = VR_DSTX(sc, nexttx); 997 998 /* 999 * Load the DMA map. If this fails, the packet didn't 1000 * fit in one DMA segment, and we need to copy. Note, 1001 * the packet must also be aligned. 1002 * if the packet is too small, copy it too, so we're sure 1003 * we have enough room for the pad buffer. 1004 */ 1005 if ((mtod(m0, uintptr_t) & 3) != 0 || 1006 m0->m_pkthdr.len < VR_MIN_FRAMELEN || 1007 bus_dmamap_load_mbuf(sc->vr_dmat, ds->ds_dmamap, m0, 1008 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1009 MGETHDR(m, M_DONTWAIT, MT_DATA); 1010 if (m == NULL) { 1011 printf("%s: unable to allocate Tx mbuf\n", 1012 sc->vr_dev.dv_xname); 1013 break; 1014 } 1015 if (m0->m_pkthdr.len > MHLEN) { 1016 MCLGET(m, M_DONTWAIT); 1017 if ((m->m_flags & M_EXT) == 0) { 1018 printf("%s: unable to allocate Tx " 1019 "cluster\n", sc->vr_dev.dv_xname); 1020 m_freem(m); 1021 break; 1022 } 1023 } 1024 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1025 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1026 /* 1027 * The Rhine doesn't auto-pad, so we have to do this 1028 * ourselves. 1029 */ 1030 if (m0->m_pkthdr.len < VR_MIN_FRAMELEN) { 1031 memset(mtod(m, caddr_t) + m0->m_pkthdr.len, 1032 0, VR_MIN_FRAMELEN - m0->m_pkthdr.len); 1033 m->m_pkthdr.len = m->m_len = VR_MIN_FRAMELEN; 1034 } 1035 error = bus_dmamap_load_mbuf(sc->vr_dmat, 1036 ds->ds_dmamap, m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1037 if (error) { 1038 m_freem(m); 1039 printf("%s: unable to load Tx buffer, " 1040 "error = %d\n", sc->vr_dev.dv_xname, error); 1041 break; 1042 } 1043 } 1044 1045 IFQ_DEQUEUE(&ifp->if_snd, m0); 1046 if (m != NULL) { 1047 m_freem(m0); 1048 m0 = m; 1049 } 1050 1051 /* Sync the DMA map. */ 1052 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 1053 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1054 1055 /* 1056 * Store a pointer to the packet so we can free it later. 1057 */ 1058 ds->ds_mbuf = m0; 1059 1060 #if NBPFILTER > 0 1061 /* 1062 * If there's a BPF listener, bounce a copy of this frame 1063 * to him. 1064 */ 1065 if (ifp->if_bpf) 1066 bpf_mtap(ifp->if_bpf, m0); 1067 #endif 1068 1069 /* 1070 * Fill in the transmit descriptor. 1071 */ 1072 d->vr_data = htole32(ds->ds_dmamap->dm_segs[0].ds_addr); 1073 d->vr_ctl = htole32(m0->m_pkthdr.len); 1074 d->vr_ctl |= htole32(VR_TXCTL_FIRSTFRAG | VR_TXCTL_LASTFRAG); 1075 1076 /* 1077 * If this is the first descriptor we're enqueuing, 1078 * don't give it to the Rhine yet. That could cause 1079 * a race condition. We'll do it below. 1080 */ 1081 if (nexttx == firsttx) 1082 d->vr_status = 0; 1083 else 1084 d->vr_status = htole32(VR_TXSTAT_OWN); 1085 1086 VR_CDTXSYNC(sc, nexttx, 1087 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1088 1089 /* Advance the tx pointer. */ 1090 sc->vr_txpending++; 1091 sc->vr_txlast = nexttx; 1092 } 1093 1094 if (sc->vr_txpending == VR_NTXDESC) { 1095 /* No more slots left; notify upper layer. */ 1096 ifp->if_flags |= IFF_OACTIVE; 1097 } 1098 1099 if (sc->vr_txpending != opending) { 1100 /* 1101 * We enqueued packets. If the transmitter was idle, 1102 * reset the txdirty pointer. 1103 */ 1104 if (opending == 0) 1105 sc->vr_txdirty = firsttx; 1106 1107 /* 1108 * Cause a transmit interrupt to happen on the 1109 * last packet we enqueued. 1110 */ 1111 VR_CDTX(sc, sc->vr_txlast)->vr_ctl |= htole32(VR_TXCTL_FINT); 1112 VR_CDTXSYNC(sc, sc->vr_txlast, 1113 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1114 1115 /* 1116 * The entire packet chain is set up. Give the 1117 * first descriptor to the Rhine now. 1118 */ 1119 VR_CDTX(sc, firsttx)->vr_status = htole32(VR_TXSTAT_OWN); 1120 VR_CDTXSYNC(sc, firsttx, 1121 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1122 1123 /* Start the transmitter. */ 1124 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1125 1126 /* Set the watchdog timer in case the chip flakes out. */ 1127 ifp->if_timer = 5; 1128 } 1129 } 1130 1131 /* 1132 * Initialize the interface. Must be called at splnet. 1133 */ 1134 static int 1135 vr_init(struct ifnet *ifp) 1136 { 1137 struct vr_softc *sc = ifp->if_softc; 1138 struct vr_desc *d; 1139 struct vr_descsoft *ds; 1140 int i, error = 0; 1141 1142 /* Cancel pending I/O. */ 1143 vr_stop(ifp, 0); 1144 1145 /* Reset the Rhine to a known state. */ 1146 vr_reset(sc); 1147 1148 /* set DMA length in BCR0 and BCR1 */ 1149 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1150 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1151 1152 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1153 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTH_128BYTES); 1154 1155 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1156 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTH_STORENFWD); 1157 1158 /* set DMA threshold length in RXCFG and TXCFG */ 1159 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1160 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1161 1162 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1163 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1164 1165 /* 1166 * Initialize the transmit descriptor ring. txlast is initialized 1167 * to the end of the list so that it will wrap around to the first 1168 * descriptor when the first packet is transmitted. 1169 */ 1170 for (i = 0; i < VR_NTXDESC; i++) { 1171 d = VR_CDTX(sc, i); 1172 memset(d, 0, sizeof(struct vr_desc)); 1173 d->vr_next = htole32(VR_CDTXADDR(sc, VR_NEXTTX(i))); 1174 VR_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1175 } 1176 sc->vr_txpending = 0; 1177 sc->vr_txdirty = 0; 1178 sc->vr_txlast = VR_NTXDESC - 1; 1179 1180 /* 1181 * Initialize the receive descriptor ring. 1182 */ 1183 for (i = 0; i < VR_NRXDESC; i++) { 1184 ds = VR_DSRX(sc, i); 1185 if (ds->ds_mbuf == NULL) { 1186 if ((error = vr_add_rxbuf(sc, i)) != 0) { 1187 printf("%s: unable to allocate or map rx " 1188 "buffer %d, error = %d\n", 1189 sc->vr_dev.dv_xname, i, error); 1190 /* 1191 * XXX Should attempt to run with fewer receive 1192 * XXX buffers instead of just failing. 1193 */ 1194 vr_rxdrain(sc); 1195 goto out; 1196 } 1197 } else 1198 VR_INIT_RXDESC(sc, i); 1199 } 1200 sc->vr_rxptr = 0; 1201 1202 /* If we want promiscuous mode, set the allframes bit. */ 1203 if (ifp->if_flags & IFF_PROMISC) 1204 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1205 else 1206 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1207 1208 /* Set capture broadcast bit to capture broadcast frames. */ 1209 if (ifp->if_flags & IFF_BROADCAST) 1210 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1211 else 1212 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1213 1214 /* Program the multicast filter, if necessary. */ 1215 vr_setmulti(sc); 1216 1217 /* Give the transmit and receive rings to the Rhine. */ 1218 CSR_WRITE_4(sc, VR_RXADDR, VR_CDRXADDR(sc, sc->vr_rxptr)); 1219 CSR_WRITE_4(sc, VR_TXADDR, VR_CDTXADDR(sc, VR_NEXTTX(sc->vr_txlast))); 1220 1221 /* Set current media. */ 1222 mii_mediachg(&sc->vr_mii); 1223 1224 /* Enable receiver and transmitter. */ 1225 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1226 VR_CMD_TX_ON|VR_CMD_RX_ON| 1227 VR_CMD_RX_GO); 1228 1229 /* Enable interrupts. */ 1230 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1231 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1232 1233 ifp->if_flags |= IFF_RUNNING; 1234 ifp->if_flags &= ~IFF_OACTIVE; 1235 1236 /* Start one second timer. */ 1237 callout_reset(&sc->vr_tick_ch, hz, vr_tick, sc); 1238 1239 /* Attempt to start output on the interface. */ 1240 vr_start(ifp); 1241 1242 out: 1243 if (error) 1244 printf("%s: interface not running\n", sc->vr_dev.dv_xname); 1245 return (error); 1246 } 1247 1248 /* 1249 * Set media options. 1250 */ 1251 static int 1252 vr_ifmedia_upd(struct ifnet *ifp) 1253 { 1254 struct vr_softc *sc = ifp->if_softc; 1255 1256 if (ifp->if_flags & IFF_UP) 1257 mii_mediachg(&sc->vr_mii); 1258 return (0); 1259 } 1260 1261 /* 1262 * Report current media status. 1263 */ 1264 static void 1265 vr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1266 { 1267 struct vr_softc *sc = ifp->if_softc; 1268 1269 mii_pollstat(&sc->vr_mii); 1270 ifmr->ifm_status = sc->vr_mii.mii_media_status; 1271 ifmr->ifm_active = sc->vr_mii.mii_media_active; 1272 } 1273 1274 static int 1275 vr_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1276 { 1277 struct vr_softc *sc = ifp->if_softc; 1278 struct ifreq *ifr = (struct ifreq *)data; 1279 int s, error = 0; 1280 1281 s = splnet(); 1282 1283 switch (command) { 1284 case SIOCGIFMEDIA: 1285 case SIOCSIFMEDIA: 1286 error = ifmedia_ioctl(ifp, ifr, &sc->vr_mii.mii_media, command); 1287 break; 1288 1289 default: 1290 error = ether_ioctl(ifp, command, data); 1291 if (error == ENETRESET) { 1292 /* 1293 * Multicast list has changed; set the hardware filter 1294 * accordingly. 1295 */ 1296 if (ifp->if_flags & IFF_RUNNING) 1297 vr_setmulti(sc); 1298 error = 0; 1299 } 1300 break; 1301 } 1302 1303 splx(s); 1304 return (error); 1305 } 1306 1307 static void 1308 vr_watchdog(struct ifnet *ifp) 1309 { 1310 struct vr_softc *sc = ifp->if_softc; 1311 1312 printf("%s: device timeout\n", sc->vr_dev.dv_xname); 1313 ifp->if_oerrors++; 1314 1315 (void) vr_init(ifp); 1316 } 1317 1318 /* 1319 * One second timer, used to tick MII. 1320 */ 1321 static void 1322 vr_tick(void *arg) 1323 { 1324 struct vr_softc *sc = arg; 1325 int s; 1326 1327 s = splnet(); 1328 mii_tick(&sc->vr_mii); 1329 splx(s); 1330 1331 callout_reset(&sc->vr_tick_ch, hz, vr_tick, sc); 1332 } 1333 1334 /* 1335 * Drain the receive queue. 1336 */ 1337 static void 1338 vr_rxdrain(struct vr_softc *sc) 1339 { 1340 struct vr_descsoft *ds; 1341 int i; 1342 1343 for (i = 0; i < VR_NRXDESC; i++) { 1344 ds = VR_DSRX(sc, i); 1345 if (ds->ds_mbuf != NULL) { 1346 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 1347 m_freem(ds->ds_mbuf); 1348 ds->ds_mbuf = NULL; 1349 } 1350 } 1351 } 1352 1353 /* 1354 * Stop the adapter and free any mbufs allocated to the 1355 * transmit lists. 1356 */ 1357 static void 1358 vr_stop(struct ifnet *ifp, int disable) 1359 { 1360 struct vr_softc *sc = ifp->if_softc; 1361 struct vr_descsoft *ds; 1362 int i; 1363 1364 /* Cancel one second timer. */ 1365 callout_stop(&sc->vr_tick_ch); 1366 1367 /* Down the MII. */ 1368 mii_down(&sc->vr_mii); 1369 1370 ifp = &sc->vr_ec.ec_if; 1371 ifp->if_timer = 0; 1372 1373 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1374 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1375 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1376 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1377 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1378 1379 /* 1380 * Release any queued transmit buffers. 1381 */ 1382 for (i = 0; i < VR_NTXDESC; i++) { 1383 ds = VR_DSTX(sc, i); 1384 if (ds->ds_mbuf != NULL) { 1385 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 1386 m_freem(ds->ds_mbuf); 1387 ds->ds_mbuf = NULL; 1388 } 1389 } 1390 1391 if (disable) 1392 vr_rxdrain(sc); 1393 1394 /* 1395 * Mark the interface down and cancel the watchdog timer. 1396 */ 1397 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1398 ifp->if_timer = 0; 1399 } 1400 1401 static int vr_probe(struct device *, struct cfdata *, void *); 1402 static void vr_attach(struct device *, struct device *, void *); 1403 static void vr_shutdown(void *); 1404 1405 CFATTACH_DECL(vr, sizeof (struct vr_softc), 1406 vr_probe, vr_attach, NULL, NULL); 1407 1408 static struct vr_type * 1409 vr_lookup(struct pci_attach_args *pa) 1410 { 1411 struct vr_type *vrt; 1412 1413 for (vrt = vr_devs; vrt->vr_name != NULL; vrt++) { 1414 if (PCI_VENDOR(pa->pa_id) == vrt->vr_vid && 1415 PCI_PRODUCT(pa->pa_id) == vrt->vr_did) 1416 return (vrt); 1417 } 1418 return (NULL); 1419 } 1420 1421 static int 1422 vr_probe(struct device *parent, struct cfdata *match, void *aux) 1423 { 1424 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1425 1426 if (vr_lookup(pa) != NULL) 1427 return (1); 1428 1429 return (0); 1430 } 1431 1432 /* 1433 * Stop all chip I/O so that the kernel's probe routines don't 1434 * get confused by errant DMAs when rebooting. 1435 */ 1436 static void 1437 vr_shutdown(void *arg) 1438 { 1439 struct vr_softc *sc = (struct vr_softc *)arg; 1440 1441 vr_stop(&sc->vr_ec.ec_if, 1); 1442 } 1443 1444 /* 1445 * Attach the interface. Allocate softc structures, do ifmedia 1446 * setup and ethernet/BPF attach. 1447 */ 1448 static void 1449 vr_attach(struct device *parent, struct device *self, void *aux) 1450 { 1451 struct vr_softc *sc = (struct vr_softc *) self; 1452 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 1453 bus_dma_segment_t seg; 1454 struct vr_type *vrt; 1455 u_int32_t reg; 1456 struct ifnet *ifp; 1457 u_char eaddr[ETHER_ADDR_LEN]; 1458 int i, rseg, error; 1459 1460 #define PCI_CONF_WRITE(r, v) pci_conf_write(sc->vr_pc, sc->vr_tag, (r), (v)) 1461 #define PCI_CONF_READ(r) pci_conf_read(sc->vr_pc, sc->vr_tag, (r)) 1462 1463 sc->vr_pc = pa->pa_pc; 1464 sc->vr_tag = pa->pa_tag; 1465 callout_init(&sc->vr_tick_ch); 1466 1467 vrt = vr_lookup(pa); 1468 if (vrt == NULL) { 1469 printf("\n"); 1470 panic("vr_attach: impossible"); 1471 } 1472 1473 printf(": %s Ethernet\n", vrt->vr_name); 1474 1475 /* 1476 * Handle power management nonsense. 1477 */ 1478 1479 sc->vr_save_iobase = PCI_CONF_READ(VR_PCI_LOIO); 1480 sc->vr_save_membase = PCI_CONF_READ(VR_PCI_LOMEM); 1481 sc->vr_save_irq = PCI_CONF_READ(PCI_INTERRUPT_REG); 1482 1483 /* power up chip */ 1484 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 1485 vr_restore_state)) && error != EOPNOTSUPP) { 1486 aprint_error("%s: cannot activate %d\n", sc->vr_dev.dv_xname, 1487 error); 1488 return; 1489 } 1490 1491 /* Make sure bus mastering is enabled. */ 1492 reg = PCI_CONF_READ(PCI_COMMAND_STATUS_REG); 1493 reg |= PCI_COMMAND_MASTER_ENABLE; 1494 PCI_CONF_WRITE(PCI_COMMAND_STATUS_REG, reg); 1495 1496 /* Get revision */ 1497 sc->vr_revid = PCI_REVISION(pa->pa_class); 1498 1499 /* 1500 * Map control/status registers. 1501 */ 1502 { 1503 bus_space_tag_t iot, memt; 1504 bus_space_handle_t ioh, memh; 1505 int ioh_valid, memh_valid; 1506 pci_intr_handle_t intrhandle; 1507 const char *intrstr; 1508 1509 ioh_valid = (pci_mapreg_map(pa, VR_PCI_LOIO, 1510 PCI_MAPREG_TYPE_IO, 0, 1511 &iot, &ioh, NULL, NULL) == 0); 1512 memh_valid = (pci_mapreg_map(pa, VR_PCI_LOMEM, 1513 PCI_MAPREG_TYPE_MEM | 1514 PCI_MAPREG_MEM_TYPE_32BIT, 1515 0, &memt, &memh, NULL, NULL) == 0); 1516 #if defined(VR_USEIOSPACE) 1517 if (ioh_valid) { 1518 sc->vr_bst = iot; 1519 sc->vr_bsh = ioh; 1520 } else if (memh_valid) { 1521 sc->vr_bst = memt; 1522 sc->vr_bsh = memh; 1523 } 1524 #else 1525 if (memh_valid) { 1526 sc->vr_bst = memt; 1527 sc->vr_bsh = memh; 1528 } else if (ioh_valid) { 1529 sc->vr_bst = iot; 1530 sc->vr_bsh = ioh; 1531 } 1532 #endif 1533 else { 1534 printf(": unable to map device registers\n"); 1535 return; 1536 } 1537 1538 /* Allocate interrupt */ 1539 if (pci_intr_map(pa, &intrhandle)) { 1540 printf("%s: couldn't map interrupt\n", 1541 sc->vr_dev.dv_xname); 1542 return; 1543 } 1544 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 1545 sc->vr_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 1546 vr_intr, sc); 1547 if (sc->vr_ih == NULL) { 1548 printf("%s: couldn't establish interrupt", 1549 sc->vr_dev.dv_xname); 1550 if (intrstr != NULL) 1551 printf(" at %s", intrstr); 1552 printf("\n"); 1553 } 1554 printf("%s: interrupting at %s\n", 1555 sc->vr_dev.dv_xname, intrstr); 1556 } 1557 1558 /* 1559 * Windows may put the chip in suspend mode when it 1560 * shuts down. Be sure to kick it in the head to wake it 1561 * up again. 1562 */ 1563 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 1564 1565 /* Reset the adapter. */ 1566 vr_reset(sc); 1567 1568 /* 1569 * Get station address. The way the Rhine chips work, 1570 * you're not allowed to directly access the EEPROM once 1571 * they've been programmed a special way. Consequently, 1572 * we need to read the node address from the PAR0 and PAR1 1573 * registers. 1574 * 1575 * XXXSCW: On the Rhine III, setting VR_EECSR_LOAD forces a reload 1576 * of the *whole* EEPROM, not just the MAC address. This is 1577 * pretty pointless since the chip does this automatically 1578 * at powerup/reset. 1579 * I suspect the same thing applies to the other Rhine 1580 * variants, but in the absence of a data sheet for those 1581 * (and the lack of anyone else noticing the problems this 1582 * causes) I'm going to retain the old behaviour for the 1583 * other parts. 1584 */ 1585 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT6105 && 1586 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT6102) { 1587 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 1588 DELAY(200); 1589 } 1590 for (i = 0; i < ETHER_ADDR_LEN; i++) 1591 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 1592 1593 /* 1594 * A Rhine chip was detected. Inform the world. 1595 */ 1596 printf("%s: Ethernet address: %s\n", 1597 sc->vr_dev.dv_xname, ether_sprintf(eaddr)); 1598 1599 memcpy(sc->vr_enaddr, eaddr, ETHER_ADDR_LEN); 1600 1601 sc->vr_dmat = pa->pa_dmat; 1602 1603 /* 1604 * Allocate the control data structures, and create and load 1605 * the DMA map for it. 1606 */ 1607 if ((error = bus_dmamem_alloc(sc->vr_dmat, 1608 sizeof(struct vr_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 1609 0)) != 0) { 1610 printf("%s: unable to allocate control data, error = %d\n", 1611 sc->vr_dev.dv_xname, error); 1612 goto fail_0; 1613 } 1614 1615 if ((error = bus_dmamem_map(sc->vr_dmat, &seg, rseg, 1616 sizeof(struct vr_control_data), (caddr_t *)&sc->vr_control_data, 1617 BUS_DMA_COHERENT)) != 0) { 1618 printf("%s: unable to map control data, error = %d\n", 1619 sc->vr_dev.dv_xname, error); 1620 goto fail_1; 1621 } 1622 1623 if ((error = bus_dmamap_create(sc->vr_dmat, 1624 sizeof(struct vr_control_data), 1, 1625 sizeof(struct vr_control_data), 0, 0, 1626 &sc->vr_cddmamap)) != 0) { 1627 printf("%s: unable to create control data DMA map, " 1628 "error = %d\n", sc->vr_dev.dv_xname, error); 1629 goto fail_2; 1630 } 1631 1632 if ((error = bus_dmamap_load(sc->vr_dmat, sc->vr_cddmamap, 1633 sc->vr_control_data, sizeof(struct vr_control_data), NULL, 1634 0)) != 0) { 1635 printf("%s: unable to load control data DMA map, error = %d\n", 1636 sc->vr_dev.dv_xname, error); 1637 goto fail_3; 1638 } 1639 1640 /* 1641 * Create the transmit buffer DMA maps. 1642 */ 1643 for (i = 0; i < VR_NTXDESC; i++) { 1644 if ((error = bus_dmamap_create(sc->vr_dmat, MCLBYTES, 1645 1, MCLBYTES, 0, 0, 1646 &VR_DSTX(sc, i)->ds_dmamap)) != 0) { 1647 printf("%s: unable to create tx DMA map %d, " 1648 "error = %d\n", sc->vr_dev.dv_xname, i, error); 1649 goto fail_4; 1650 } 1651 } 1652 1653 /* 1654 * Create the receive buffer DMA maps. 1655 */ 1656 for (i = 0; i < VR_NRXDESC; i++) { 1657 if ((error = bus_dmamap_create(sc->vr_dmat, MCLBYTES, 1, 1658 MCLBYTES, 0, 0, 1659 &VR_DSRX(sc, i)->ds_dmamap)) != 0) { 1660 printf("%s: unable to create rx DMA map %d, " 1661 "error = %d\n", sc->vr_dev.dv_xname, i, error); 1662 goto fail_5; 1663 } 1664 VR_DSRX(sc, i)->ds_mbuf = NULL; 1665 } 1666 1667 ifp = &sc->vr_ec.ec_if; 1668 ifp->if_softc = sc; 1669 ifp->if_mtu = ETHERMTU; 1670 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1671 ifp->if_ioctl = vr_ioctl; 1672 ifp->if_start = vr_start; 1673 ifp->if_watchdog = vr_watchdog; 1674 ifp->if_init = vr_init; 1675 ifp->if_stop = vr_stop; 1676 IFQ_SET_READY(&ifp->if_snd); 1677 1678 strcpy(ifp->if_xname, sc->vr_dev.dv_xname); 1679 1680 /* 1681 * Initialize MII/media info. 1682 */ 1683 sc->vr_mii.mii_ifp = ifp; 1684 sc->vr_mii.mii_readreg = vr_mii_readreg; 1685 sc->vr_mii.mii_writereg = vr_mii_writereg; 1686 sc->vr_mii.mii_statchg = vr_mii_statchg; 1687 ifmedia_init(&sc->vr_mii.mii_media, IFM_IMASK, vr_ifmedia_upd, 1688 vr_ifmedia_sts); 1689 mii_attach(&sc->vr_dev, &sc->vr_mii, 0xffffffff, MII_PHY_ANY, 1690 MII_OFFSET_ANY, MIIF_FORCEANEG); 1691 if (LIST_FIRST(&sc->vr_mii.mii_phys) == NULL) { 1692 ifmedia_add(&sc->vr_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1693 ifmedia_set(&sc->vr_mii.mii_media, IFM_ETHER|IFM_NONE); 1694 } else 1695 ifmedia_set(&sc->vr_mii.mii_media, IFM_ETHER|IFM_AUTO); 1696 1697 /* 1698 * Call MI attach routines. 1699 */ 1700 if_attach(ifp); 1701 ether_ifattach(ifp, sc->vr_enaddr); 1702 #if NRND > 0 1703 rnd_attach_source(&sc->rnd_source, sc->vr_dev.dv_xname, 1704 RND_TYPE_NET, 0); 1705 #endif 1706 1707 sc->vr_ats = shutdownhook_establish(vr_shutdown, sc); 1708 if (sc->vr_ats == NULL) 1709 printf("%s: warning: couldn't establish shutdown hook\n", 1710 sc->vr_dev.dv_xname); 1711 return; 1712 1713 fail_5: 1714 for (i = 0; i < VR_NRXDESC; i++) { 1715 if (sc->vr_rxsoft[i].ds_dmamap != NULL) 1716 bus_dmamap_destroy(sc->vr_dmat, 1717 sc->vr_rxsoft[i].ds_dmamap); 1718 } 1719 fail_4: 1720 for (i = 0; i < VR_NTXDESC; i++) { 1721 if (sc->vr_txsoft[i].ds_dmamap != NULL) 1722 bus_dmamap_destroy(sc->vr_dmat, 1723 sc->vr_txsoft[i].ds_dmamap); 1724 } 1725 bus_dmamap_unload(sc->vr_dmat, sc->vr_cddmamap); 1726 fail_3: 1727 bus_dmamap_destroy(sc->vr_dmat, sc->vr_cddmamap); 1728 fail_2: 1729 bus_dmamem_unmap(sc->vr_dmat, (caddr_t)sc->vr_control_data, 1730 sizeof(struct vr_control_data)); 1731 fail_1: 1732 bus_dmamem_free(sc->vr_dmat, &seg, rseg); 1733 fail_0: 1734 return; 1735 } 1736 1737 static int 1738 vr_restore_state(pci_chipset_tag_t pc, pcitag_t tag, void *ssc, pcireg_t state) 1739 { 1740 struct vr_softc *sc = ssc; 1741 int error; 1742 1743 if (state == PCI_PMCSR_STATE_D0) 1744 return 0; 1745 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 1746 return error; 1747 1748 /* Restore PCI config data. */ 1749 PCI_CONF_WRITE(VR_PCI_LOIO, sc->vr_save_iobase); 1750 PCI_CONF_WRITE(VR_PCI_LOMEM, sc->vr_save_membase); 1751 PCI_CONF_WRITE(PCI_INTERRUPT_REG, sc->vr_save_irq); 1752 return 0; 1753 } 1754