1 /* $NetBSD: if_vr.c,v 1.107 2010/12/16 17:07:44 jakllsch Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1997, 1998 35 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Bill Paul. 48 * 4. Neither the name of the author nor the names of any co-contributors 49 * may be used to endorse or promote products derived from this software 50 * without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 56 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 57 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 58 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 59 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 60 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 61 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 62 * THE POSSIBILITY OF SUCH DAMAGE. 63 * 64 * $FreeBSD: if_vr.c,v 1.7 1999/01/10 18:51:49 wpaul Exp $ 65 */ 66 67 /* 68 * VIA Rhine fast ethernet PCI NIC driver 69 * 70 * Supports various network adapters based on the VIA Rhine 71 * and Rhine II PCI controllers, including the D-Link DFE530TX. 72 * Datasheets are available at http://www.via.com.tw. 73 * 74 * Written by Bill Paul <wpaul@ctr.columbia.edu> 75 * Electrical Engineering Department 76 * Columbia University, New York City 77 */ 78 79 /* 80 * The VIA Rhine controllers are similar in some respects to the 81 * the DEC tulip chips, except less complicated. The controller 82 * uses an MII bus and an external physical layer interface. The 83 * receiver has a one entry perfect filter and a 64-bit hash table 84 * multicast filter. Transmit and receive descriptors are similar 85 * to the tulip. 86 * 87 * The Rhine has a serious flaw in its transmit DMA mechanism: 88 * transmit buffers must be longword aligned. Unfortunately, 89 * the kernel doesn't guarantee that mbufs will be filled in starting 90 * at longword boundaries, so we have to do a buffer copy before 91 * transmission. 92 * 93 * Apparently, the receive DMA mechanism also has the same flaw. This 94 * means that on systems with struct alignment requirements, incoming 95 * frames must be copied to a new buffer which shifts the data forward 96 * 2 bytes so that the payload is aligned on a 4-byte boundary. 97 */ 98 99 #include <sys/cdefs.h> 100 __KERNEL_RCSID(0, "$NetBSD: if_vr.c,v 1.107 2010/12/16 17:07:44 jakllsch Exp $"); 101 102 #include "rnd.h" 103 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/callout.h> 107 #include <sys/sockio.h> 108 #include <sys/mbuf.h> 109 #include <sys/malloc.h> 110 #include <sys/kernel.h> 111 #include <sys/socket.h> 112 #include <sys/device.h> 113 114 #if NRND > 0 115 #include <sys/rnd.h> 116 #endif 117 118 #include <net/if.h> 119 #include <net/if_arp.h> 120 #include <net/if_dl.h> 121 #include <net/if_media.h> 122 #include <net/if_ether.h> 123 124 #include <net/bpf.h> 125 126 #include <sys/bus.h> 127 #include <sys/intr.h> 128 #include <machine/endian.h> 129 130 #include <dev/mii/mii.h> 131 #include <dev/mii/miivar.h> 132 #include <dev/mii/mii_bitbang.h> 133 134 #include <dev/pci/pcireg.h> 135 #include <dev/pci/pcivar.h> 136 #include <dev/pci/pcidevs.h> 137 138 #include <dev/pci/if_vrreg.h> 139 140 #define VR_USEIOSPACE 141 142 /* 143 * Various supported device vendors/types and their names. 144 */ 145 static const struct vr_type { 146 pci_vendor_id_t vr_vid; 147 pci_product_id_t vr_did; 148 } vr_devs[] = { 149 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT3043 }, 150 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6102 }, 151 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6105 }, 152 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6105M }, 153 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT86C100A } 154 }; 155 156 /* 157 * Transmit descriptor list size. 158 */ 159 #define VR_NTXDESC 64 160 #define VR_NTXDESC_MASK (VR_NTXDESC - 1) 161 #define VR_NEXTTX(x) (((x) + 1) & VR_NTXDESC_MASK) 162 163 /* 164 * Receive descriptor list size. 165 */ 166 #define VR_NRXDESC 64 167 #define VR_NRXDESC_MASK (VR_NRXDESC - 1) 168 #define VR_NEXTRX(x) (((x) + 1) & VR_NRXDESC_MASK) 169 170 /* 171 * Control data structres that are DMA'd to the Rhine chip. We allocate 172 * them in a single clump that maps to a single DMA segment to make several 173 * things easier. 174 * 175 * Note that since we always copy outgoing packets to aligned transmit 176 * buffers, we can reduce the transmit descriptors to one per packet. 177 */ 178 struct vr_control_data { 179 struct vr_desc vr_txdescs[VR_NTXDESC]; 180 struct vr_desc vr_rxdescs[VR_NRXDESC]; 181 }; 182 183 #define VR_CDOFF(x) offsetof(struct vr_control_data, x) 184 #define VR_CDTXOFF(x) VR_CDOFF(vr_txdescs[(x)]) 185 #define VR_CDRXOFF(x) VR_CDOFF(vr_rxdescs[(x)]) 186 187 /* 188 * Software state of transmit and receive descriptors. 189 */ 190 struct vr_descsoft { 191 struct mbuf *ds_mbuf; /* head of mbuf chain */ 192 bus_dmamap_t ds_dmamap; /* our DMA map */ 193 }; 194 195 struct vr_softc { 196 device_t vr_dev; 197 void *vr_ih; /* interrupt cookie */ 198 bus_space_tag_t vr_bst; /* bus space tag */ 199 bus_space_handle_t vr_bsh; /* bus space handle */ 200 bus_dma_tag_t vr_dmat; /* bus DMA tag */ 201 pci_chipset_tag_t vr_pc; /* PCI chipset info */ 202 pcitag_t vr_tag; /* PCI tag */ 203 struct ethercom vr_ec; /* Ethernet common info */ 204 uint8_t vr_enaddr[ETHER_ADDR_LEN]; 205 struct mii_data vr_mii; /* MII/media info */ 206 207 pcireg_t vr_id; /* vendor/product ID */ 208 uint8_t vr_revid; /* Rhine chip revision */ 209 210 callout_t vr_tick_ch; /* tick callout */ 211 212 bus_dmamap_t vr_cddmamap; /* control data DMA map */ 213 #define vr_cddma vr_cddmamap->dm_segs[0].ds_addr 214 215 /* 216 * Software state for transmit and receive descriptors. 217 */ 218 struct vr_descsoft vr_txsoft[VR_NTXDESC]; 219 struct vr_descsoft vr_rxsoft[VR_NRXDESC]; 220 221 /* 222 * Control data structures. 223 */ 224 struct vr_control_data *vr_control_data; 225 226 int vr_txpending; /* number of TX requests pending */ 227 int vr_txdirty; /* first dirty TX descriptor */ 228 int vr_txlast; /* last used TX descriptor */ 229 230 int vr_rxptr; /* next ready RX descriptor */ 231 232 uint32_t vr_save_iobase; 233 uint32_t vr_save_membase; 234 uint32_t vr_save_irq; 235 236 #if NRND > 0 237 rndsource_element_t rnd_source; /* random source */ 238 #endif 239 }; 240 241 #define VR_CDTXADDR(sc, x) ((sc)->vr_cddma + VR_CDTXOFF((x))) 242 #define VR_CDRXADDR(sc, x) ((sc)->vr_cddma + VR_CDRXOFF((x))) 243 244 #define VR_CDTX(sc, x) (&(sc)->vr_control_data->vr_txdescs[(x)]) 245 #define VR_CDRX(sc, x) (&(sc)->vr_control_data->vr_rxdescs[(x)]) 246 247 #define VR_DSTX(sc, x) (&(sc)->vr_txsoft[(x)]) 248 #define VR_DSRX(sc, x) (&(sc)->vr_rxsoft[(x)]) 249 250 #define VR_CDTXSYNC(sc, x, ops) \ 251 bus_dmamap_sync((sc)->vr_dmat, (sc)->vr_cddmamap, \ 252 VR_CDTXOFF((x)), sizeof(struct vr_desc), (ops)) 253 254 #define VR_CDRXSYNC(sc, x, ops) \ 255 bus_dmamap_sync((sc)->vr_dmat, (sc)->vr_cddmamap, \ 256 VR_CDRXOFF((x)), sizeof(struct vr_desc), (ops)) 257 258 /* 259 * Note we rely on MCLBYTES being a power of two below. 260 */ 261 #define VR_INIT_RXDESC(sc, i) \ 262 do { \ 263 struct vr_desc *__d = VR_CDRX((sc), (i)); \ 264 struct vr_descsoft *__ds = VR_DSRX((sc), (i)); \ 265 \ 266 __d->vr_next = htole32(VR_CDRXADDR((sc), VR_NEXTRX((i)))); \ 267 __d->vr_data = htole32(__ds->ds_dmamap->dm_segs[0].ds_addr); \ 268 __d->vr_ctl = htole32(VR_RXCTL_CHAIN | VR_RXCTL_RX_INTR | \ 269 ((MCLBYTES - 1) & VR_RXCTL_BUFLEN)); \ 270 __d->vr_status = htole32(VR_RXSTAT_FIRSTFRAG | \ 271 VR_RXSTAT_LASTFRAG | VR_RXSTAT_OWN); \ 272 VR_CDRXSYNC((sc), (i), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 273 } while (/* CONSTCOND */ 0) 274 275 /* 276 * register space access macros 277 */ 278 #define CSR_WRITE_4(sc, reg, val) \ 279 bus_space_write_4(sc->vr_bst, sc->vr_bsh, reg, val) 280 #define CSR_WRITE_2(sc, reg, val) \ 281 bus_space_write_2(sc->vr_bst, sc->vr_bsh, reg, val) 282 #define CSR_WRITE_1(sc, reg, val) \ 283 bus_space_write_1(sc->vr_bst, sc->vr_bsh, reg, val) 284 285 #define CSR_READ_4(sc, reg) \ 286 bus_space_read_4(sc->vr_bst, sc->vr_bsh, reg) 287 #define CSR_READ_2(sc, reg) \ 288 bus_space_read_2(sc->vr_bst, sc->vr_bsh, reg) 289 #define CSR_READ_1(sc, reg) \ 290 bus_space_read_1(sc->vr_bst, sc->vr_bsh, reg) 291 292 #define VR_TIMEOUT 1000 293 294 static int vr_add_rxbuf(struct vr_softc *, int); 295 296 static void vr_rxeof(struct vr_softc *); 297 static void vr_rxeoc(struct vr_softc *); 298 static void vr_txeof(struct vr_softc *); 299 static int vr_intr(void *); 300 static void vr_start(struct ifnet *); 301 static int vr_ioctl(struct ifnet *, u_long, void *); 302 static int vr_init(struct ifnet *); 303 static void vr_stop(struct ifnet *, int); 304 static void vr_rxdrain(struct vr_softc *); 305 static void vr_watchdog(struct ifnet *); 306 static void vr_tick(void *); 307 308 static int vr_mii_readreg(device_t, int, int); 309 static void vr_mii_writereg(device_t, int, int, int); 310 static void vr_mii_statchg(device_t); 311 312 static void vr_setmulti(struct vr_softc *); 313 static void vr_reset(struct vr_softc *); 314 static int vr_restore_state(pci_chipset_tag_t, pcitag_t, device_t, 315 pcireg_t); 316 static bool vr_resume(device_t, const pmf_qual_t *); 317 318 int vr_copy_small = 0; 319 320 #define VR_SETBIT(sc, reg, x) \ 321 CSR_WRITE_1(sc, reg, \ 322 CSR_READ_1(sc, reg) | (x)) 323 324 #define VR_CLRBIT(sc, reg, x) \ 325 CSR_WRITE_1(sc, reg, \ 326 CSR_READ_1(sc, reg) & ~(x)) 327 328 #define VR_SETBIT16(sc, reg, x) \ 329 CSR_WRITE_2(sc, reg, \ 330 CSR_READ_2(sc, reg) | (x)) 331 332 #define VR_CLRBIT16(sc, reg, x) \ 333 CSR_WRITE_2(sc, reg, \ 334 CSR_READ_2(sc, reg) & ~(x)) 335 336 #define VR_SETBIT32(sc, reg, x) \ 337 CSR_WRITE_4(sc, reg, \ 338 CSR_READ_4(sc, reg) | (x)) 339 340 #define VR_CLRBIT32(sc, reg, x) \ 341 CSR_WRITE_4(sc, reg, \ 342 CSR_READ_4(sc, reg) & ~(x)) 343 344 /* 345 * MII bit-bang glue. 346 */ 347 static uint32_t vr_mii_bitbang_read(device_t); 348 static void vr_mii_bitbang_write(device_t, uint32_t); 349 350 static const struct mii_bitbang_ops vr_mii_bitbang_ops = { 351 vr_mii_bitbang_read, 352 vr_mii_bitbang_write, 353 { 354 VR_MIICMD_DATAOUT, /* MII_BIT_MDO */ 355 VR_MIICMD_DATAIN, /* MII_BIT_MDI */ 356 VR_MIICMD_CLK, /* MII_BIT_MDC */ 357 VR_MIICMD_DIR, /* MII_BIT_DIR_HOST_PHY */ 358 0, /* MII_BIT_DIR_PHY_HOST */ 359 } 360 }; 361 362 static uint32_t 363 vr_mii_bitbang_read(device_t self) 364 { 365 struct vr_softc *sc = device_private(self); 366 367 return (CSR_READ_1(sc, VR_MIICMD)); 368 } 369 370 static void 371 vr_mii_bitbang_write(device_t self, uint32_t val) 372 { 373 struct vr_softc *sc = device_private(self); 374 375 CSR_WRITE_1(sc, VR_MIICMD, (val & 0xff) | VR_MIICMD_DIRECTPGM); 376 } 377 378 /* 379 * Read an PHY register through the MII. 380 */ 381 static int 382 vr_mii_readreg(device_t self, int phy, int reg) 383 { 384 struct vr_softc *sc = device_private(self); 385 386 CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 387 return (mii_bitbang_readreg(self, &vr_mii_bitbang_ops, phy, reg)); 388 } 389 390 /* 391 * Write to a PHY register through the MII. 392 */ 393 static void 394 vr_mii_writereg(device_t self, int phy, int reg, int val) 395 { 396 struct vr_softc *sc = device_private(self); 397 398 CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 399 mii_bitbang_writereg(self, &vr_mii_bitbang_ops, phy, reg, val); 400 } 401 402 static void 403 vr_mii_statchg(device_t self) 404 { 405 struct vr_softc *sc = device_private(self); 406 407 /* 408 * In order to fiddle with the 'full-duplex' bit in the netconfig 409 * register, we first have to put the transmit and/or receive logic 410 * in the idle state. 411 */ 412 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 413 414 if (sc->vr_mii.mii_media_active & IFM_FDX) 415 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 416 else 417 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 418 419 if (sc->vr_ec.ec_if.if_flags & IFF_RUNNING) 420 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 421 } 422 423 #define vr_calchash(addr) \ 424 (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26) 425 426 /* 427 * Program the 64-bit multicast hash filter. 428 */ 429 static void 430 vr_setmulti(struct vr_softc *sc) 431 { 432 struct ifnet *ifp; 433 int h = 0; 434 uint32_t hashes[2] = { 0, 0 }; 435 struct ether_multistep step; 436 struct ether_multi *enm; 437 int mcnt = 0; 438 uint8_t rxfilt; 439 440 ifp = &sc->vr_ec.ec_if; 441 442 rxfilt = CSR_READ_1(sc, VR_RXCFG); 443 444 if (ifp->if_flags & IFF_PROMISC) { 445 allmulti: 446 ifp->if_flags |= IFF_ALLMULTI; 447 rxfilt |= VR_RXCFG_RX_MULTI; 448 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 449 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 450 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 451 return; 452 } 453 454 /* first, zot all the existing hash bits */ 455 CSR_WRITE_4(sc, VR_MAR0, 0); 456 CSR_WRITE_4(sc, VR_MAR1, 0); 457 458 /* now program new ones */ 459 ETHER_FIRST_MULTI(step, &sc->vr_ec, enm); 460 while (enm != NULL) { 461 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 462 ETHER_ADDR_LEN) != 0) 463 goto allmulti; 464 465 h = vr_calchash(enm->enm_addrlo); 466 467 if (h < 32) 468 hashes[0] |= (1 << h); 469 else 470 hashes[1] |= (1 << (h - 32)); 471 ETHER_NEXT_MULTI(step, enm); 472 mcnt++; 473 } 474 475 ifp->if_flags &= ~IFF_ALLMULTI; 476 477 if (mcnt) 478 rxfilt |= VR_RXCFG_RX_MULTI; 479 else 480 rxfilt &= ~VR_RXCFG_RX_MULTI; 481 482 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 483 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 484 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 485 } 486 487 static void 488 vr_reset(struct vr_softc *sc) 489 { 490 int i; 491 492 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 493 494 for (i = 0; i < VR_TIMEOUT; i++) { 495 DELAY(10); 496 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 497 break; 498 } 499 if (i == VR_TIMEOUT) { 500 if (sc->vr_revid < REV_ID_VT3065_A) { 501 printf("%s: reset never completed!\n", 502 device_xname(sc->vr_dev)); 503 } else { 504 /* Use newer force reset command */ 505 printf("%s: using force reset command.\n", 506 device_xname(sc->vr_dev)); 507 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 508 } 509 } 510 511 /* Wait a little while for the chip to get its brains in order. */ 512 DELAY(1000); 513 } 514 515 /* 516 * Initialize an RX descriptor and attach an MBUF cluster. 517 * Note: the length fields are only 11 bits wide, which means the 518 * largest size we can specify is 2047. This is important because 519 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 520 * overflow the field and make a mess. 521 */ 522 static int 523 vr_add_rxbuf(struct vr_softc *sc, int i) 524 { 525 struct vr_descsoft *ds = VR_DSRX(sc, i); 526 struct mbuf *m_new; 527 int error; 528 529 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 530 if (m_new == NULL) 531 return (ENOBUFS); 532 533 MCLGET(m_new, M_DONTWAIT); 534 if ((m_new->m_flags & M_EXT) == 0) { 535 m_freem(m_new); 536 return (ENOBUFS); 537 } 538 539 if (ds->ds_mbuf != NULL) 540 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 541 542 ds->ds_mbuf = m_new; 543 544 error = bus_dmamap_load(sc->vr_dmat, ds->ds_dmamap, 545 m_new->m_ext.ext_buf, m_new->m_ext.ext_size, NULL, 546 BUS_DMA_READ|BUS_DMA_NOWAIT); 547 if (error) { 548 aprint_error_dev(sc->vr_dev, "unable to load rx DMA map %d, error = %d\n", 549 i, error); 550 panic("vr_add_rxbuf"); /* XXX */ 551 } 552 553 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 554 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 555 556 VR_INIT_RXDESC(sc, i); 557 558 return (0); 559 } 560 561 /* 562 * A frame has been uploaded: pass the resulting mbuf chain up to 563 * the higher level protocols. 564 */ 565 static void 566 vr_rxeof(struct vr_softc *sc) 567 { 568 struct mbuf *m; 569 struct ifnet *ifp; 570 struct vr_desc *d; 571 struct vr_descsoft *ds; 572 int i, total_len; 573 uint32_t rxstat; 574 575 ifp = &sc->vr_ec.ec_if; 576 577 for (i = sc->vr_rxptr;; i = VR_NEXTRX(i)) { 578 d = VR_CDRX(sc, i); 579 ds = VR_DSRX(sc, i); 580 581 VR_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 582 583 rxstat = le32toh(d->vr_status); 584 585 if (rxstat & VR_RXSTAT_OWN) { 586 /* 587 * We have processed all of the receive buffers. 588 */ 589 break; 590 } 591 592 /* 593 * If an error occurs, update stats, clear the 594 * status word and leave the mbuf cluster in place: 595 * it should simply get re-used next time this descriptor 596 * comes up in the ring. 597 */ 598 if (rxstat & VR_RXSTAT_RXERR) { 599 const char *errstr; 600 601 ifp->if_ierrors++; 602 switch (rxstat & 0x000000FF) { 603 case VR_RXSTAT_CRCERR: 604 errstr = "crc error"; 605 break; 606 case VR_RXSTAT_FRAMEALIGNERR: 607 errstr = "frame alignment error"; 608 break; 609 case VR_RXSTAT_FIFOOFLOW: 610 errstr = "FIFO overflow"; 611 break; 612 case VR_RXSTAT_GIANT: 613 errstr = "received giant packet"; 614 break; 615 case VR_RXSTAT_RUNT: 616 errstr = "received runt packet"; 617 break; 618 case VR_RXSTAT_BUSERR: 619 errstr = "system bus error"; 620 break; 621 case VR_RXSTAT_BUFFERR: 622 errstr = "rx buffer error"; 623 break; 624 default: 625 errstr = "unknown rx error"; 626 break; 627 } 628 printf("%s: receive error: %s\n", device_xname(sc->vr_dev), 629 errstr); 630 631 VR_INIT_RXDESC(sc, i); 632 633 continue; 634 } else if (!(rxstat & VR_RXSTAT_FIRSTFRAG) || 635 !(rxstat & VR_RXSTAT_LASTFRAG)) { 636 /* 637 * This driver expects to receive whole packets every 638 * time. In case we receive a fragment that is not 639 * a complete packet, we discard it. 640 */ 641 ifp->if_ierrors++; 642 643 printf("%s: receive error: incomplete frame; " 644 "size = %d, status = 0x%x\n", 645 device_xname(sc->vr_dev), 646 VR_RXBYTES(le32toh(d->vr_status)), rxstat); 647 648 VR_INIT_RXDESC(sc, i); 649 650 continue; 651 } 652 653 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 654 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 655 656 /* No errors; receive the packet. */ 657 total_len = VR_RXBYTES(le32toh(d->vr_status)); 658 #ifdef DIAGNOSTIC 659 if (total_len == 0) { 660 /* 661 * If we receive a zero-length packet, we probably 662 * missed to handle an error condition above. 663 * Discard it to avoid a later crash. 664 */ 665 ifp->if_ierrors++; 666 667 printf("%s: receive error: zero-length packet; " 668 "status = 0x%x\n", 669 device_xname(sc->vr_dev), rxstat); 670 671 VR_INIT_RXDESC(sc, i); 672 673 continue; 674 } 675 #endif 676 677 /* 678 * The Rhine chip includes the CRC with every packet. 679 * Trim it off here. 680 */ 681 total_len -= ETHER_CRC_LEN; 682 683 #ifdef __NO_STRICT_ALIGNMENT 684 /* 685 * If the packet is small enough to fit in a 686 * single header mbuf, allocate one and copy 687 * the data into it. This greatly reduces 688 * memory consumption when we receive lots 689 * of small packets. 690 * 691 * Otherwise, we add a new buffer to the receive 692 * chain. If this fails, we drop the packet and 693 * recycle the old buffer. 694 */ 695 if (vr_copy_small != 0 && total_len <= MHLEN) { 696 MGETHDR(m, M_DONTWAIT, MT_DATA); 697 if (m == NULL) 698 goto dropit; 699 memcpy(mtod(m, void *), 700 mtod(ds->ds_mbuf, void *), total_len); 701 VR_INIT_RXDESC(sc, i); 702 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 703 ds->ds_dmamap->dm_mapsize, 704 BUS_DMASYNC_PREREAD); 705 } else { 706 m = ds->ds_mbuf; 707 if (vr_add_rxbuf(sc, i) == ENOBUFS) { 708 dropit: 709 ifp->if_ierrors++; 710 VR_INIT_RXDESC(sc, i); 711 bus_dmamap_sync(sc->vr_dmat, 712 ds->ds_dmamap, 0, 713 ds->ds_dmamap->dm_mapsize, 714 BUS_DMASYNC_PREREAD); 715 continue; 716 } 717 } 718 #else 719 /* 720 * The Rhine's packet buffers must be 4-byte aligned. 721 * But this means that the data after the Ethernet header 722 * is misaligned. We must allocate a new buffer and 723 * copy the data, shifted forward 2 bytes. 724 */ 725 MGETHDR(m, M_DONTWAIT, MT_DATA); 726 if (m == NULL) { 727 dropit: 728 ifp->if_ierrors++; 729 VR_INIT_RXDESC(sc, i); 730 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 731 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 732 continue; 733 } 734 if (total_len > (MHLEN - 2)) { 735 MCLGET(m, M_DONTWAIT); 736 if ((m->m_flags & M_EXT) == 0) { 737 m_freem(m); 738 goto dropit; 739 } 740 } 741 m->m_data += 2; 742 743 /* 744 * Note that we use clusters for incoming frames, so the 745 * buffer is virtually contiguous. 746 */ 747 memcpy(mtod(m, void *), mtod(ds->ds_mbuf, void *), 748 total_len); 749 750 /* Allow the receive descriptor to continue using its mbuf. */ 751 VR_INIT_RXDESC(sc, i); 752 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 753 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 754 #endif /* __NO_STRICT_ALIGNMENT */ 755 756 ifp->if_ipackets++; 757 m->m_pkthdr.rcvif = ifp; 758 m->m_pkthdr.len = m->m_len = total_len; 759 /* 760 * Handle BPF listeners. Let the BPF user see the packet, but 761 * don't pass it up to the ether_input() layer unless it's 762 * a broadcast packet, multicast packet, matches our ethernet 763 * address or the interface is in promiscuous mode. 764 */ 765 bpf_mtap(ifp, m); 766 /* Pass it on. */ 767 (*ifp->if_input)(ifp, m); 768 } 769 770 /* Update the receive pointer. */ 771 sc->vr_rxptr = i; 772 } 773 774 void 775 vr_rxeoc(struct vr_softc *sc) 776 { 777 struct ifnet *ifp; 778 int i; 779 780 ifp = &sc->vr_ec.ec_if; 781 782 ifp->if_ierrors++; 783 784 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 785 for (i = 0; i < VR_TIMEOUT; i++) { 786 DELAY(10); 787 if ((CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON) == 0) 788 break; 789 } 790 if (i == VR_TIMEOUT) { 791 /* XXX need reset? */ 792 printf("%s: RX shutdown never complete\n", 793 device_xname(sc->vr_dev)); 794 } 795 796 vr_rxeof(sc); 797 798 CSR_WRITE_4(sc, VR_RXADDR, VR_CDRXADDR(sc, sc->vr_rxptr)); 799 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 800 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 801 } 802 803 /* 804 * A frame was downloaded to the chip. It's safe for us to clean up 805 * the list buffers. 806 */ 807 static void 808 vr_txeof(struct vr_softc *sc) 809 { 810 struct ifnet *ifp = &sc->vr_ec.ec_if; 811 struct vr_desc *d; 812 struct vr_descsoft *ds; 813 uint32_t txstat; 814 int i, j; 815 816 ifp->if_flags &= ~IFF_OACTIVE; 817 818 /* 819 * Go through our tx list and free mbufs for those 820 * frames that have been transmitted. 821 */ 822 for (i = sc->vr_txdirty; sc->vr_txpending != 0; 823 i = VR_NEXTTX(i), sc->vr_txpending--) { 824 d = VR_CDTX(sc, i); 825 ds = VR_DSTX(sc, i); 826 827 VR_CDTXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 828 829 txstat = le32toh(d->vr_status); 830 831 if (txstat & (VR_TXSTAT_ABRT | VR_TXSTAT_UDF)) { 832 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 833 for (j = 0; j < VR_TIMEOUT; j++) { 834 DELAY(10); 835 if ((CSR_READ_2(sc, VR_COMMAND) & 836 VR_CMD_TX_ON) == 0) 837 break; 838 } 839 if (j == VR_TIMEOUT) { 840 /* XXX need reset? */ 841 printf("%s: TX shutdown never complete\n", 842 device_xname(sc->vr_dev)); 843 } 844 d->vr_status = htole32(VR_TXSTAT_OWN); 845 CSR_WRITE_4(sc, VR_TXADDR, VR_CDTXADDR(sc, i)); 846 break; 847 } 848 849 if (txstat & VR_TXSTAT_OWN) 850 break; 851 852 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 853 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 854 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 855 m_freem(ds->ds_mbuf); 856 ds->ds_mbuf = NULL; 857 858 if (txstat & VR_TXSTAT_ERRSUM) { 859 ifp->if_oerrors++; 860 if (txstat & VR_TXSTAT_DEFER) 861 ifp->if_collisions++; 862 if (txstat & VR_TXSTAT_LATECOLL) 863 ifp->if_collisions++; 864 } 865 866 ifp->if_collisions += (txstat & VR_TXSTAT_COLLCNT) >> 3; 867 ifp->if_opackets++; 868 } 869 870 /* Update the dirty transmit buffer pointer. */ 871 sc->vr_txdirty = i; 872 873 /* 874 * Cancel the watchdog timer if there are no pending 875 * transmissions. 876 */ 877 if (sc->vr_txpending == 0) 878 ifp->if_timer = 0; 879 } 880 881 static int 882 vr_intr(void *arg) 883 { 884 struct vr_softc *sc; 885 struct ifnet *ifp; 886 uint16_t status; 887 int handled = 0, dotx = 0; 888 889 sc = arg; 890 ifp = &sc->vr_ec.ec_if; 891 892 /* Suppress unwanted interrupts. */ 893 if ((ifp->if_flags & IFF_UP) == 0) { 894 vr_stop(ifp, 1); 895 return (0); 896 } 897 898 /* Disable interrupts. */ 899 CSR_WRITE_2(sc, VR_IMR, 0x0000); 900 901 for (;;) { 902 status = CSR_READ_2(sc, VR_ISR); 903 if (status) 904 CSR_WRITE_2(sc, VR_ISR, status); 905 906 if ((status & VR_INTRS) == 0) 907 break; 908 909 handled = 1; 910 911 #if NRND > 0 912 if (RND_ENABLED(&sc->rnd_source)) 913 rnd_add_uint32(&sc->rnd_source, status); 914 #endif 915 916 if (status & VR_ISR_RX_OK) 917 vr_rxeof(sc); 918 919 if (status & VR_ISR_RX_DROPPED) { 920 printf("%s: rx packet lost\n", device_xname(sc->vr_dev)); 921 ifp->if_ierrors++; 922 } 923 924 if (status & 925 (VR_ISR_RX_ERR | VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW)) 926 vr_rxeoc(sc); 927 928 929 if (status & (VR_ISR_BUSERR | VR_ISR_TX_UNDERRUN)) { 930 if (status & VR_ISR_BUSERR) 931 printf("%s: PCI bus error\n", 932 device_xname(sc->vr_dev)); 933 if (status & VR_ISR_TX_UNDERRUN) 934 printf("%s: transmit underrun\n", 935 device_xname(sc->vr_dev)); 936 /* vr_init() calls vr_start() */ 937 dotx = 0; 938 (void)vr_init(ifp); 939 940 } 941 942 if (status & VR_ISR_TX_OK) { 943 dotx = 1; 944 vr_txeof(sc); 945 } 946 947 if (status & 948 (VR_ISR_TX_ABRT | VR_ISR_TX_ABRT2 | VR_ISR_TX_UDFI)) { 949 if (status & (VR_ISR_TX_ABRT | VR_ISR_TX_ABRT2)) 950 printf("%s: transmit aborted\n", 951 device_xname(sc->vr_dev)); 952 if (status & VR_ISR_TX_UDFI) 953 printf("%s: transmit underflow\n", 954 device_xname(sc->vr_dev)); 955 ifp->if_oerrors++; 956 dotx = 1; 957 vr_txeof(sc); 958 if (sc->vr_txpending) { 959 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 960 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 961 } 962 } 963 } 964 965 /* Re-enable interrupts. */ 966 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 967 968 if (dotx) 969 vr_start(ifp); 970 971 return (handled); 972 } 973 974 /* 975 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 976 * to the mbuf data regions directly in the transmit lists. We also save a 977 * copy of the pointers since the transmit list fragment pointers are 978 * physical addresses. 979 */ 980 static void 981 vr_start(struct ifnet *ifp) 982 { 983 struct vr_softc *sc = ifp->if_softc; 984 struct mbuf *m0, *m; 985 struct vr_desc *d; 986 struct vr_descsoft *ds; 987 int error, firsttx, nexttx, opending; 988 989 /* 990 * Remember the previous txpending and the first transmit 991 * descriptor we use. 992 */ 993 opending = sc->vr_txpending; 994 firsttx = VR_NEXTTX(sc->vr_txlast); 995 996 /* 997 * Loop through the send queue, setting up transmit descriptors 998 * until we drain the queue, or use up all available transmit 999 * descriptors. 1000 */ 1001 while (sc->vr_txpending < VR_NTXDESC) { 1002 /* 1003 * Grab a packet off the queue. 1004 */ 1005 IFQ_POLL(&ifp->if_snd, m0); 1006 if (m0 == NULL) 1007 break; 1008 m = NULL; 1009 1010 /* 1011 * Get the next available transmit descriptor. 1012 */ 1013 nexttx = VR_NEXTTX(sc->vr_txlast); 1014 d = VR_CDTX(sc, nexttx); 1015 ds = VR_DSTX(sc, nexttx); 1016 1017 /* 1018 * Load the DMA map. If this fails, the packet didn't 1019 * fit in one DMA segment, and we need to copy. Note, 1020 * the packet must also be aligned. 1021 * if the packet is too small, copy it too, so we're sure 1022 * we have enough room for the pad buffer. 1023 */ 1024 if ((mtod(m0, uintptr_t) & 3) != 0 || 1025 m0->m_pkthdr.len < VR_MIN_FRAMELEN || 1026 bus_dmamap_load_mbuf(sc->vr_dmat, ds->ds_dmamap, m0, 1027 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1028 MGETHDR(m, M_DONTWAIT, MT_DATA); 1029 if (m == NULL) { 1030 printf("%s: unable to allocate Tx mbuf\n", 1031 device_xname(sc->vr_dev)); 1032 break; 1033 } 1034 if (m0->m_pkthdr.len > MHLEN) { 1035 MCLGET(m, M_DONTWAIT); 1036 if ((m->m_flags & M_EXT) == 0) { 1037 printf("%s: unable to allocate Tx " 1038 "cluster\n", device_xname(sc->vr_dev)); 1039 m_freem(m); 1040 break; 1041 } 1042 } 1043 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1044 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1045 /* 1046 * The Rhine doesn't auto-pad, so we have to do this 1047 * ourselves. 1048 */ 1049 if (m0->m_pkthdr.len < VR_MIN_FRAMELEN) { 1050 memset(mtod(m, char *) + m0->m_pkthdr.len, 1051 0, VR_MIN_FRAMELEN - m0->m_pkthdr.len); 1052 m->m_pkthdr.len = m->m_len = VR_MIN_FRAMELEN; 1053 } 1054 error = bus_dmamap_load_mbuf(sc->vr_dmat, 1055 ds->ds_dmamap, m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1056 if (error) { 1057 m_freem(m); 1058 printf("%s: unable to load Tx buffer, " 1059 "error = %d\n", device_xname(sc->vr_dev), error); 1060 break; 1061 } 1062 } 1063 1064 IFQ_DEQUEUE(&ifp->if_snd, m0); 1065 if (m != NULL) { 1066 m_freem(m0); 1067 m0 = m; 1068 } 1069 1070 /* Sync the DMA map. */ 1071 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 1072 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1073 1074 /* 1075 * Store a pointer to the packet so we can free it later. 1076 */ 1077 ds->ds_mbuf = m0; 1078 1079 /* 1080 * If there's a BPF listener, bounce a copy of this frame 1081 * to him. 1082 */ 1083 bpf_mtap(ifp, m0); 1084 1085 /* 1086 * Fill in the transmit descriptor. 1087 */ 1088 d->vr_data = htole32(ds->ds_dmamap->dm_segs[0].ds_addr); 1089 d->vr_ctl = htole32(m0->m_pkthdr.len); 1090 d->vr_ctl |= htole32(VR_TXCTL_FIRSTFRAG | VR_TXCTL_LASTFRAG); 1091 1092 /* 1093 * If this is the first descriptor we're enqueuing, 1094 * don't give it to the Rhine yet. That could cause 1095 * a race condition. We'll do it below. 1096 */ 1097 if (nexttx == firsttx) 1098 d->vr_status = 0; 1099 else 1100 d->vr_status = htole32(VR_TXSTAT_OWN); 1101 1102 VR_CDTXSYNC(sc, nexttx, 1103 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1104 1105 /* Advance the tx pointer. */ 1106 sc->vr_txpending++; 1107 sc->vr_txlast = nexttx; 1108 } 1109 1110 if (sc->vr_txpending == VR_NTXDESC) { 1111 /* No more slots left; notify upper layer. */ 1112 ifp->if_flags |= IFF_OACTIVE; 1113 } 1114 1115 if (sc->vr_txpending != opending) { 1116 /* 1117 * We enqueued packets. If the transmitter was idle, 1118 * reset the txdirty pointer. 1119 */ 1120 if (opending == 0) 1121 sc->vr_txdirty = firsttx; 1122 1123 /* 1124 * Cause a transmit interrupt to happen on the 1125 * last packet we enqueued. 1126 */ 1127 VR_CDTX(sc, sc->vr_txlast)->vr_ctl |= htole32(VR_TXCTL_FINT); 1128 VR_CDTXSYNC(sc, sc->vr_txlast, 1129 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1130 1131 /* 1132 * The entire packet chain is set up. Give the 1133 * first descriptor to the Rhine now. 1134 */ 1135 VR_CDTX(sc, firsttx)->vr_status = htole32(VR_TXSTAT_OWN); 1136 VR_CDTXSYNC(sc, firsttx, 1137 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1138 1139 /* Start the transmitter. */ 1140 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1141 1142 /* Set the watchdog timer in case the chip flakes out. */ 1143 ifp->if_timer = 5; 1144 } 1145 } 1146 1147 /* 1148 * Initialize the interface. Must be called at splnet. 1149 */ 1150 static int 1151 vr_init(struct ifnet *ifp) 1152 { 1153 struct vr_softc *sc = ifp->if_softc; 1154 struct vr_desc *d; 1155 struct vr_descsoft *ds; 1156 int i, error = 0; 1157 1158 /* Cancel pending I/O. */ 1159 vr_stop(ifp, 0); 1160 1161 /* Reset the Rhine to a known state. */ 1162 vr_reset(sc); 1163 1164 /* set DMA length in BCR0 and BCR1 */ 1165 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1166 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1167 1168 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1169 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTH_128BYTES); 1170 1171 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1172 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTH_STORENFWD); 1173 1174 /* set DMA threshold length in RXCFG and TXCFG */ 1175 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1176 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1177 1178 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1179 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1180 1181 /* 1182 * Initialize the transmit descriptor ring. txlast is initialized 1183 * to the end of the list so that it will wrap around to the first 1184 * descriptor when the first packet is transmitted. 1185 */ 1186 for (i = 0; i < VR_NTXDESC; i++) { 1187 d = VR_CDTX(sc, i); 1188 memset(d, 0, sizeof(struct vr_desc)); 1189 d->vr_next = htole32(VR_CDTXADDR(sc, VR_NEXTTX(i))); 1190 VR_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1191 } 1192 sc->vr_txpending = 0; 1193 sc->vr_txdirty = 0; 1194 sc->vr_txlast = VR_NTXDESC - 1; 1195 1196 /* 1197 * Initialize the receive descriptor ring. 1198 */ 1199 for (i = 0; i < VR_NRXDESC; i++) { 1200 ds = VR_DSRX(sc, i); 1201 if (ds->ds_mbuf == NULL) { 1202 if ((error = vr_add_rxbuf(sc, i)) != 0) { 1203 printf("%s: unable to allocate or map rx " 1204 "buffer %d, error = %d\n", 1205 device_xname(sc->vr_dev), i, error); 1206 /* 1207 * XXX Should attempt to run with fewer receive 1208 * XXX buffers instead of just failing. 1209 */ 1210 vr_rxdrain(sc); 1211 goto out; 1212 } 1213 } else 1214 VR_INIT_RXDESC(sc, i); 1215 } 1216 sc->vr_rxptr = 0; 1217 1218 /* If we want promiscuous mode, set the allframes bit. */ 1219 if (ifp->if_flags & IFF_PROMISC) 1220 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1221 else 1222 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1223 1224 /* Set capture broadcast bit to capture broadcast frames. */ 1225 if (ifp->if_flags & IFF_BROADCAST) 1226 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1227 else 1228 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1229 1230 /* Program the multicast filter, if necessary. */ 1231 vr_setmulti(sc); 1232 1233 /* Give the transmit and receive rings to the Rhine. */ 1234 CSR_WRITE_4(sc, VR_RXADDR, VR_CDRXADDR(sc, sc->vr_rxptr)); 1235 CSR_WRITE_4(sc, VR_TXADDR, VR_CDTXADDR(sc, VR_NEXTTX(sc->vr_txlast))); 1236 1237 /* Set current media. */ 1238 if ((error = ether_mediachange(ifp)) != 0) 1239 goto out; 1240 1241 /* Enable receiver and transmitter. */ 1242 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1243 VR_CMD_TX_ON|VR_CMD_RX_ON| 1244 VR_CMD_RX_GO); 1245 1246 /* Enable interrupts. */ 1247 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1248 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1249 1250 ifp->if_flags |= IFF_RUNNING; 1251 ifp->if_flags &= ~IFF_OACTIVE; 1252 1253 /* Start one second timer. */ 1254 callout_reset(&sc->vr_tick_ch, hz, vr_tick, sc); 1255 1256 /* Attempt to start output on the interface. */ 1257 vr_start(ifp); 1258 1259 out: 1260 if (error) 1261 printf("%s: interface not running\n", device_xname(sc->vr_dev)); 1262 return (error); 1263 } 1264 1265 static int 1266 vr_ioctl(struct ifnet *ifp, u_long command, void *data) 1267 { 1268 struct vr_softc *sc = ifp->if_softc; 1269 int s, error = 0; 1270 1271 s = splnet(); 1272 1273 error = ether_ioctl(ifp, command, data); 1274 if (error == ENETRESET) { 1275 /* 1276 * Multicast list has changed; set the hardware filter 1277 * accordingly. 1278 */ 1279 if (ifp->if_flags & IFF_RUNNING) 1280 vr_setmulti(sc); 1281 error = 0; 1282 } 1283 1284 splx(s); 1285 return (error); 1286 } 1287 1288 static void 1289 vr_watchdog(struct ifnet *ifp) 1290 { 1291 struct vr_softc *sc = ifp->if_softc; 1292 1293 printf("%s: device timeout\n", device_xname(sc->vr_dev)); 1294 ifp->if_oerrors++; 1295 1296 (void) vr_init(ifp); 1297 } 1298 1299 /* 1300 * One second timer, used to tick MII. 1301 */ 1302 static void 1303 vr_tick(void *arg) 1304 { 1305 struct vr_softc *sc = arg; 1306 int s; 1307 1308 s = splnet(); 1309 mii_tick(&sc->vr_mii); 1310 splx(s); 1311 1312 callout_reset(&sc->vr_tick_ch, hz, vr_tick, sc); 1313 } 1314 1315 /* 1316 * Drain the receive queue. 1317 */ 1318 static void 1319 vr_rxdrain(struct vr_softc *sc) 1320 { 1321 struct vr_descsoft *ds; 1322 int i; 1323 1324 for (i = 0; i < VR_NRXDESC; i++) { 1325 ds = VR_DSRX(sc, i); 1326 if (ds->ds_mbuf != NULL) { 1327 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 1328 m_freem(ds->ds_mbuf); 1329 ds->ds_mbuf = NULL; 1330 } 1331 } 1332 } 1333 1334 /* 1335 * Stop the adapter and free any mbufs allocated to the 1336 * transmit lists. 1337 */ 1338 static void 1339 vr_stop(struct ifnet *ifp, int disable) 1340 { 1341 struct vr_softc *sc = ifp->if_softc; 1342 struct vr_descsoft *ds; 1343 int i; 1344 1345 /* Cancel one second timer. */ 1346 callout_stop(&sc->vr_tick_ch); 1347 1348 /* Down the MII. */ 1349 mii_down(&sc->vr_mii); 1350 1351 ifp = &sc->vr_ec.ec_if; 1352 ifp->if_timer = 0; 1353 1354 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1355 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1356 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1357 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1358 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1359 1360 /* 1361 * Release any queued transmit buffers. 1362 */ 1363 for (i = 0; i < VR_NTXDESC; i++) { 1364 ds = VR_DSTX(sc, i); 1365 if (ds->ds_mbuf != NULL) { 1366 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 1367 m_freem(ds->ds_mbuf); 1368 ds->ds_mbuf = NULL; 1369 } 1370 } 1371 1372 /* 1373 * Mark the interface down and cancel the watchdog timer. 1374 */ 1375 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1376 ifp->if_timer = 0; 1377 1378 if (disable) 1379 vr_rxdrain(sc); 1380 } 1381 1382 static int vr_probe(device_t, cfdata_t, void *); 1383 static void vr_attach(device_t, device_t, void *); 1384 static bool vr_shutdown(device_t, int); 1385 1386 CFATTACH_DECL_NEW(vr, sizeof (struct vr_softc), 1387 vr_probe, vr_attach, NULL, NULL); 1388 1389 static const struct vr_type * 1390 vr_lookup(struct pci_attach_args *pa) 1391 { 1392 const struct vr_type *vrt; 1393 int i; 1394 1395 for (i = 0; i < __arraycount(vr_devs); i++) { 1396 vrt = &vr_devs[i]; 1397 if (PCI_VENDOR(pa->pa_id) == vrt->vr_vid && 1398 PCI_PRODUCT(pa->pa_id) == vrt->vr_did) 1399 return (vrt); 1400 } 1401 return (NULL); 1402 } 1403 1404 static int 1405 vr_probe(device_t parent, cfdata_t match, void *aux) 1406 { 1407 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1408 1409 if (vr_lookup(pa) != NULL) 1410 return (1); 1411 1412 return (0); 1413 } 1414 1415 /* 1416 * Stop all chip I/O so that the kernel's probe routines don't 1417 * get confused by errant DMAs when rebooting. 1418 */ 1419 static bool 1420 vr_shutdown(device_t self, int howto) 1421 { 1422 struct vr_softc *sc = device_private(self); 1423 1424 vr_stop(&sc->vr_ec.ec_if, 1); 1425 1426 return true; 1427 } 1428 1429 /* 1430 * Attach the interface. Allocate softc structures, do ifmedia 1431 * setup and ethernet/BPF attach. 1432 */ 1433 static void 1434 vr_attach(device_t parent, device_t self, void *aux) 1435 { 1436 struct vr_softc *sc = device_private(self); 1437 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 1438 bus_dma_segment_t seg; 1439 uint32_t reg; 1440 struct ifnet *ifp; 1441 uint8_t eaddr[ETHER_ADDR_LEN], mac; 1442 int i, rseg, error; 1443 char devinfo[256]; 1444 1445 #define PCI_CONF_WRITE(r, v) pci_conf_write(sc->vr_pc, sc->vr_tag, (r), (v)) 1446 #define PCI_CONF_READ(r) pci_conf_read(sc->vr_pc, sc->vr_tag, (r)) 1447 1448 sc->vr_dev = self; 1449 sc->vr_pc = pa->pa_pc; 1450 sc->vr_tag = pa->pa_tag; 1451 sc->vr_id = pa->pa_id; 1452 callout_init(&sc->vr_tick_ch, 0); 1453 1454 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 1455 aprint_naive("\n"); 1456 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 1457 PCI_REVISION(pa->pa_class)); 1458 1459 /* 1460 * Handle power management nonsense. 1461 */ 1462 1463 sc->vr_save_iobase = PCI_CONF_READ(VR_PCI_LOIO); 1464 sc->vr_save_membase = PCI_CONF_READ(VR_PCI_LOMEM); 1465 sc->vr_save_irq = PCI_CONF_READ(PCI_INTERRUPT_REG); 1466 1467 /* power up chip */ 1468 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 1469 vr_restore_state)) && error != EOPNOTSUPP) { 1470 aprint_error_dev(self, "cannot activate %d\n", 1471 error); 1472 return; 1473 } 1474 1475 /* Make sure bus mastering is enabled. */ 1476 reg = PCI_CONF_READ(PCI_COMMAND_STATUS_REG); 1477 reg |= PCI_COMMAND_MASTER_ENABLE; 1478 PCI_CONF_WRITE(PCI_COMMAND_STATUS_REG, reg); 1479 1480 /* Get revision */ 1481 sc->vr_revid = PCI_REVISION(pa->pa_class); 1482 1483 /* 1484 * Map control/status registers. 1485 */ 1486 { 1487 bus_space_tag_t iot, memt; 1488 bus_space_handle_t ioh, memh; 1489 int ioh_valid, memh_valid; 1490 pci_intr_handle_t intrhandle; 1491 const char *intrstr; 1492 1493 ioh_valid = (pci_mapreg_map(pa, VR_PCI_LOIO, 1494 PCI_MAPREG_TYPE_IO, 0, 1495 &iot, &ioh, NULL, NULL) == 0); 1496 memh_valid = (pci_mapreg_map(pa, VR_PCI_LOMEM, 1497 PCI_MAPREG_TYPE_MEM | 1498 PCI_MAPREG_MEM_TYPE_32BIT, 1499 0, &memt, &memh, NULL, NULL) == 0); 1500 #if defined(VR_USEIOSPACE) 1501 if (ioh_valid) { 1502 sc->vr_bst = iot; 1503 sc->vr_bsh = ioh; 1504 } else if (memh_valid) { 1505 sc->vr_bst = memt; 1506 sc->vr_bsh = memh; 1507 } 1508 #else 1509 if (memh_valid) { 1510 sc->vr_bst = memt; 1511 sc->vr_bsh = memh; 1512 } else if (ioh_valid) { 1513 sc->vr_bst = iot; 1514 sc->vr_bsh = ioh; 1515 } 1516 #endif 1517 else { 1518 printf(": unable to map device registers\n"); 1519 return; 1520 } 1521 1522 /* Allocate interrupt */ 1523 if (pci_intr_map(pa, &intrhandle)) { 1524 aprint_error_dev(self, "couldn't map interrupt\n"); 1525 return; 1526 } 1527 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 1528 sc->vr_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 1529 vr_intr, sc); 1530 if (sc->vr_ih == NULL) { 1531 aprint_error_dev(self, "couldn't establish interrupt"); 1532 if (intrstr != NULL) 1533 aprint_error(" at %s", intrstr); 1534 aprint_error("\n"); 1535 } 1536 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 1537 } 1538 1539 /* 1540 * Windows may put the chip in suspend mode when it 1541 * shuts down. Be sure to kick it in the head to wake it 1542 * up again. 1543 * 1544 * Don't touch this register on VT3043 since it causes 1545 * kernel MCHK trap on macppc. 1546 * (Note some VT86C100A chip returns a product ID of VT3043) 1547 */ 1548 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT3043) 1549 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 1550 1551 /* Reset the adapter. */ 1552 vr_reset(sc); 1553 1554 /* 1555 * Get station address. The way the Rhine chips work, 1556 * you're not allowed to directly access the EEPROM once 1557 * they've been programmed a special way. Consequently, 1558 * we need to read the node address from the PAR0 and PAR1 1559 * registers. 1560 * 1561 * XXXSCW: On the Rhine III, setting VR_EECSR_LOAD forces a reload 1562 * of the *whole* EEPROM, not just the MAC address. This is 1563 * pretty pointless since the chip does this automatically 1564 * at powerup/reset. 1565 * I suspect the same thing applies to the other Rhine 1566 * variants, but in the absence of a data sheet for those 1567 * (and the lack of anyone else noticing the problems this 1568 * causes) I'm going to retain the old behaviour for the 1569 * other parts. 1570 * In some cases, the chip really does startup without having 1571 * read the EEPROM (kern/34812). To handle this case, we force 1572 * a reload if we see an all-zeroes MAC address. 1573 */ 1574 for (mac = 0, i = 0; i < ETHER_ADDR_LEN; i++) 1575 mac |= (eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i)); 1576 1577 if (mac == 0 || (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT6105 && 1578 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT6102)) { 1579 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 1580 DELAY(200); 1581 for (i = 0; i < ETHER_ADDR_LEN; i++) 1582 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 1583 } 1584 1585 /* 1586 * A Rhine chip was detected. Inform the world. 1587 */ 1588 aprint_normal("%s: Ethernet address: %s\n", 1589 device_xname(self), ether_sprintf(eaddr)); 1590 1591 memcpy(sc->vr_enaddr, eaddr, ETHER_ADDR_LEN); 1592 1593 sc->vr_dmat = pa->pa_dmat; 1594 1595 /* 1596 * Allocate the control data structures, and create and load 1597 * the DMA map for it. 1598 */ 1599 if ((error = bus_dmamem_alloc(sc->vr_dmat, 1600 sizeof(struct vr_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 1601 0)) != 0) { 1602 aprint_error_dev(self, "unable to allocate control data, error = %d\n", error); 1603 goto fail_0; 1604 } 1605 1606 if ((error = bus_dmamem_map(sc->vr_dmat, &seg, rseg, 1607 sizeof(struct vr_control_data), (void **)&sc->vr_control_data, 1608 BUS_DMA_COHERENT)) != 0) { 1609 aprint_error_dev(self, "unable to map control data, error = %d\n", error); 1610 goto fail_1; 1611 } 1612 1613 if ((error = bus_dmamap_create(sc->vr_dmat, 1614 sizeof(struct vr_control_data), 1, 1615 sizeof(struct vr_control_data), 0, 0, 1616 &sc->vr_cddmamap)) != 0) { 1617 aprint_error_dev(self, "unable to create control data DMA map, " 1618 "error = %d\n", error); 1619 goto fail_2; 1620 } 1621 1622 if ((error = bus_dmamap_load(sc->vr_dmat, sc->vr_cddmamap, 1623 sc->vr_control_data, sizeof(struct vr_control_data), NULL, 1624 0)) != 0) { 1625 aprint_error_dev(self, "unable to load control data DMA map, error = %d\n", 1626 error); 1627 goto fail_3; 1628 } 1629 1630 /* 1631 * Create the transmit buffer DMA maps. 1632 */ 1633 for (i = 0; i < VR_NTXDESC; i++) { 1634 if ((error = bus_dmamap_create(sc->vr_dmat, MCLBYTES, 1635 1, MCLBYTES, 0, 0, 1636 &VR_DSTX(sc, i)->ds_dmamap)) != 0) { 1637 aprint_error_dev(self, "unable to create tx DMA map %d, " 1638 "error = %d\n", i, error); 1639 goto fail_4; 1640 } 1641 } 1642 1643 /* 1644 * Create the receive buffer DMA maps. 1645 */ 1646 for (i = 0; i < VR_NRXDESC; i++) { 1647 if ((error = bus_dmamap_create(sc->vr_dmat, MCLBYTES, 1, 1648 MCLBYTES, 0, 0, 1649 &VR_DSRX(sc, i)->ds_dmamap)) != 0) { 1650 aprint_error_dev(self, "unable to create rx DMA map %d, " 1651 "error = %d\n", i, error); 1652 goto fail_5; 1653 } 1654 VR_DSRX(sc, i)->ds_mbuf = NULL; 1655 } 1656 1657 ifp = &sc->vr_ec.ec_if; 1658 ifp->if_softc = sc; 1659 ifp->if_mtu = ETHERMTU; 1660 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1661 ifp->if_ioctl = vr_ioctl; 1662 ifp->if_start = vr_start; 1663 ifp->if_watchdog = vr_watchdog; 1664 ifp->if_init = vr_init; 1665 ifp->if_stop = vr_stop; 1666 IFQ_SET_READY(&ifp->if_snd); 1667 1668 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 1669 1670 /* 1671 * Initialize MII/media info. 1672 */ 1673 sc->vr_mii.mii_ifp = ifp; 1674 sc->vr_mii.mii_readreg = vr_mii_readreg; 1675 sc->vr_mii.mii_writereg = vr_mii_writereg; 1676 sc->vr_mii.mii_statchg = vr_mii_statchg; 1677 1678 sc->vr_ec.ec_mii = &sc->vr_mii; 1679 ifmedia_init(&sc->vr_mii.mii_media, IFM_IMASK, ether_mediachange, 1680 ether_mediastatus); 1681 mii_attach(self, &sc->vr_mii, 0xffffffff, MII_PHY_ANY, 1682 MII_OFFSET_ANY, MIIF_FORCEANEG); 1683 if (LIST_FIRST(&sc->vr_mii.mii_phys) == NULL) { 1684 ifmedia_add(&sc->vr_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1685 ifmedia_set(&sc->vr_mii.mii_media, IFM_ETHER|IFM_NONE); 1686 } else 1687 ifmedia_set(&sc->vr_mii.mii_media, IFM_ETHER|IFM_AUTO); 1688 1689 sc->vr_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 1690 1691 /* 1692 * Call MI attach routines. 1693 */ 1694 if_attach(ifp); 1695 ether_ifattach(ifp, sc->vr_enaddr); 1696 #if NRND > 0 1697 rnd_attach_source(&sc->rnd_source, device_xname(self), 1698 RND_TYPE_NET, 0); 1699 #endif 1700 1701 if (pmf_device_register1(self, NULL, vr_resume, vr_shutdown)) 1702 pmf_class_network_register(self, ifp); 1703 else 1704 aprint_error_dev(self, "couldn't establish power handler\n"); 1705 1706 return; 1707 1708 fail_5: 1709 for (i = 0; i < VR_NRXDESC; i++) { 1710 if (sc->vr_rxsoft[i].ds_dmamap != NULL) 1711 bus_dmamap_destroy(sc->vr_dmat, 1712 sc->vr_rxsoft[i].ds_dmamap); 1713 } 1714 fail_4: 1715 for (i = 0; i < VR_NTXDESC; i++) { 1716 if (sc->vr_txsoft[i].ds_dmamap != NULL) 1717 bus_dmamap_destroy(sc->vr_dmat, 1718 sc->vr_txsoft[i].ds_dmamap); 1719 } 1720 bus_dmamap_unload(sc->vr_dmat, sc->vr_cddmamap); 1721 fail_3: 1722 bus_dmamap_destroy(sc->vr_dmat, sc->vr_cddmamap); 1723 fail_2: 1724 bus_dmamem_unmap(sc->vr_dmat, (void *)sc->vr_control_data, 1725 sizeof(struct vr_control_data)); 1726 fail_1: 1727 bus_dmamem_free(sc->vr_dmat, &seg, rseg); 1728 fail_0: 1729 return; 1730 } 1731 1732 static int 1733 vr_restore_state(pci_chipset_tag_t pc, pcitag_t tag, device_t self, 1734 pcireg_t state) 1735 { 1736 struct vr_softc *sc = device_private(self); 1737 int error; 1738 1739 if (state == PCI_PMCSR_STATE_D0) 1740 return 0; 1741 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 1742 return error; 1743 1744 /* Restore PCI config data. */ 1745 PCI_CONF_WRITE(VR_PCI_LOIO, sc->vr_save_iobase); 1746 PCI_CONF_WRITE(VR_PCI_LOMEM, sc->vr_save_membase); 1747 PCI_CONF_WRITE(PCI_INTERRUPT_REG, sc->vr_save_irq); 1748 return 0; 1749 } 1750 1751 static bool 1752 vr_resume(device_t self, const pmf_qual_t *qual) 1753 { 1754 struct vr_softc *sc = device_private(self); 1755 1756 if (PCI_PRODUCT(sc->vr_id) != PCI_PRODUCT_VIATECH_VT3043) 1757 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 1758 1759 return true; 1760 } 1761