1 /* $NetBSD: if_vr.c,v 1.124 2018/06/26 06:48:01 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1997, 1998 35 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Bill Paul. 48 * 4. Neither the name of the author nor the names of any co-contributors 49 * may be used to endorse or promote products derived from this software 50 * without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 56 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 57 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 58 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 59 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 60 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 61 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 62 * THE POSSIBILITY OF SUCH DAMAGE. 63 * 64 * $FreeBSD: if_vr.c,v 1.7 1999/01/10 18:51:49 wpaul Exp $ 65 */ 66 67 /* 68 * VIA Rhine fast ethernet PCI NIC driver 69 * 70 * Supports various network adapters based on the VIA Rhine 71 * and Rhine II PCI controllers, including the D-Link DFE530TX. 72 * Datasheets are available at http://www.via.com.tw. 73 * 74 * Written by Bill Paul <wpaul@ctr.columbia.edu> 75 * Electrical Engineering Department 76 * Columbia University, New York City 77 */ 78 79 /* 80 * The VIA Rhine controllers are similar in some respects to the 81 * the DEC tulip chips, except less complicated. The controller 82 * uses an MII bus and an external physical layer interface. The 83 * receiver has a one entry perfect filter and a 64-bit hash table 84 * multicast filter. Transmit and receive descriptors are similar 85 * to the tulip. 86 * 87 * The Rhine has a serious flaw in its transmit DMA mechanism: 88 * transmit buffers must be longword aligned. Unfortunately, 89 * the kernel doesn't guarantee that mbufs will be filled in starting 90 * at longword boundaries, so we have to do a buffer copy before 91 * transmission. 92 * 93 * Apparently, the receive DMA mechanism also has the same flaw. This 94 * means that on systems with struct alignment requirements, incoming 95 * frames must be copied to a new buffer which shifts the data forward 96 * 2 bytes so that the payload is aligned on a 4-byte boundary. 97 */ 98 99 #include <sys/cdefs.h> 100 __KERNEL_RCSID(0, "$NetBSD: if_vr.c,v 1.124 2018/06/26 06:48:01 msaitoh Exp $"); 101 102 103 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/callout.h> 107 #include <sys/sockio.h> 108 #include <sys/mbuf.h> 109 #include <sys/malloc.h> 110 #include <sys/kernel.h> 111 #include <sys/socket.h> 112 #include <sys/device.h> 113 114 #include <sys/rndsource.h> 115 116 #include <net/if.h> 117 #include <net/if_arp.h> 118 #include <net/if_dl.h> 119 #include <net/if_media.h> 120 #include <net/if_ether.h> 121 122 #include <net/bpf.h> 123 124 #include <sys/bus.h> 125 #include <sys/intr.h> 126 #include <machine/endian.h> 127 128 #include <dev/mii/mii.h> 129 #include <dev/mii/miivar.h> 130 #include <dev/mii/mii_bitbang.h> 131 132 #include <dev/pci/pcireg.h> 133 #include <dev/pci/pcivar.h> 134 #include <dev/pci/pcidevs.h> 135 136 #include <dev/pci/if_vrreg.h> 137 138 #define VR_USEIOSPACE 139 140 /* 141 * Various supported device vendors/types and their names. 142 */ 143 static const struct vr_type { 144 pci_vendor_id_t vr_vid; 145 pci_product_id_t vr_did; 146 } vr_devs[] = { 147 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT3043 }, 148 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6102 }, 149 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6105 }, 150 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6105M }, 151 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT86C100A } 152 }; 153 154 /* 155 * Transmit descriptor list size. 156 */ 157 #define VR_NTXDESC 64 158 #define VR_NTXDESC_MASK (VR_NTXDESC - 1) 159 #define VR_NEXTTX(x) (((x) + 1) & VR_NTXDESC_MASK) 160 161 /* 162 * Receive descriptor list size. 163 */ 164 #define VR_NRXDESC 64 165 #define VR_NRXDESC_MASK (VR_NRXDESC - 1) 166 #define VR_NEXTRX(x) (((x) + 1) & VR_NRXDESC_MASK) 167 168 /* 169 * Control data structres that are DMA'd to the Rhine chip. We allocate 170 * them in a single clump that maps to a single DMA segment to make several 171 * things easier. 172 * 173 * Note that since we always copy outgoing packets to aligned transmit 174 * buffers, we can reduce the transmit descriptors to one per packet. 175 */ 176 struct vr_control_data { 177 struct vr_desc vr_txdescs[VR_NTXDESC]; 178 struct vr_desc vr_rxdescs[VR_NRXDESC]; 179 }; 180 181 #define VR_CDOFF(x) offsetof(struct vr_control_data, x) 182 #define VR_CDTXOFF(x) VR_CDOFF(vr_txdescs[(x)]) 183 #define VR_CDRXOFF(x) VR_CDOFF(vr_rxdescs[(x)]) 184 185 /* 186 * Software state of transmit and receive descriptors. 187 */ 188 struct vr_descsoft { 189 struct mbuf *ds_mbuf; /* head of mbuf chain */ 190 bus_dmamap_t ds_dmamap; /* our DMA map */ 191 }; 192 193 struct vr_softc { 194 device_t vr_dev; 195 void *vr_ih; /* interrupt cookie */ 196 bus_space_tag_t vr_bst; /* bus space tag */ 197 bus_space_handle_t vr_bsh; /* bus space handle */ 198 bus_dma_tag_t vr_dmat; /* bus DMA tag */ 199 pci_chipset_tag_t vr_pc; /* PCI chipset info */ 200 pcitag_t vr_tag; /* PCI tag */ 201 struct ethercom vr_ec; /* Ethernet common info */ 202 uint8_t vr_enaddr[ETHER_ADDR_LEN]; 203 struct mii_data vr_mii; /* MII/media info */ 204 205 pcireg_t vr_id; /* vendor/product ID */ 206 uint8_t vr_revid; /* Rhine chip revision */ 207 208 callout_t vr_tick_ch; /* tick callout */ 209 210 bus_dmamap_t vr_cddmamap; /* control data DMA map */ 211 #define vr_cddma vr_cddmamap->dm_segs[0].ds_addr 212 213 /* 214 * Software state for transmit and receive descriptors. 215 */ 216 struct vr_descsoft vr_txsoft[VR_NTXDESC]; 217 struct vr_descsoft vr_rxsoft[VR_NRXDESC]; 218 219 /* 220 * Control data structures. 221 */ 222 struct vr_control_data *vr_control_data; 223 224 int vr_txpending; /* number of TX requests pending */ 225 int vr_txdirty; /* first dirty TX descriptor */ 226 int vr_txlast; /* last used TX descriptor */ 227 228 int vr_rxptr; /* next ready RX descriptor */ 229 230 uint32_t vr_save_iobase; 231 uint32_t vr_save_membase; 232 uint32_t vr_save_irq; 233 234 bool vr_link; 235 int vr_flags; 236 #define VR_F_RESTART 0x1 /* restart on next tick */ 237 int vr_if_flags; 238 239 krndsource_t rnd_source; /* random source */ 240 }; 241 242 #define VR_CDTXADDR(sc, x) ((sc)->vr_cddma + VR_CDTXOFF((x))) 243 #define VR_CDRXADDR(sc, x) ((sc)->vr_cddma + VR_CDRXOFF((x))) 244 245 #define VR_CDTX(sc, x) (&(sc)->vr_control_data->vr_txdescs[(x)]) 246 #define VR_CDRX(sc, x) (&(sc)->vr_control_data->vr_rxdescs[(x)]) 247 248 #define VR_DSTX(sc, x) (&(sc)->vr_txsoft[(x)]) 249 #define VR_DSRX(sc, x) (&(sc)->vr_rxsoft[(x)]) 250 251 #define VR_CDTXSYNC(sc, x, ops) \ 252 bus_dmamap_sync((sc)->vr_dmat, (sc)->vr_cddmamap, \ 253 VR_CDTXOFF((x)), sizeof(struct vr_desc), (ops)) 254 255 #define VR_CDRXSYNC(sc, x, ops) \ 256 bus_dmamap_sync((sc)->vr_dmat, (sc)->vr_cddmamap, \ 257 VR_CDRXOFF((x)), sizeof(struct vr_desc), (ops)) 258 259 /* 260 * Note we rely on MCLBYTES being a power of two below. 261 */ 262 #define VR_INIT_RXDESC(sc, i) \ 263 do { \ 264 struct vr_desc *__d = VR_CDRX((sc), (i)); \ 265 struct vr_descsoft *__ds = VR_DSRX((sc), (i)); \ 266 \ 267 __d->vr_next = htole32(VR_CDRXADDR((sc), VR_NEXTRX((i)))); \ 268 __d->vr_data = htole32(__ds->ds_dmamap->dm_segs[0].ds_addr); \ 269 __d->vr_ctl = htole32(VR_RXCTL_CHAIN | VR_RXCTL_RX_INTR | \ 270 ((MCLBYTES - 1) & VR_RXCTL_BUFLEN)); \ 271 __d->vr_status = htole32(VR_RXSTAT_FIRSTFRAG | \ 272 VR_RXSTAT_LASTFRAG | VR_RXSTAT_OWN); \ 273 VR_CDRXSYNC((sc), (i), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 274 } while (/* CONSTCOND */ 0) 275 276 /* 277 * register space access macros 278 */ 279 #define CSR_WRITE_4(sc, reg, val) \ 280 bus_space_write_4(sc->vr_bst, sc->vr_bsh, reg, val) 281 #define CSR_WRITE_2(sc, reg, val) \ 282 bus_space_write_2(sc->vr_bst, sc->vr_bsh, reg, val) 283 #define CSR_WRITE_1(sc, reg, val) \ 284 bus_space_write_1(sc->vr_bst, sc->vr_bsh, reg, val) 285 286 #define CSR_READ_4(sc, reg) \ 287 bus_space_read_4(sc->vr_bst, sc->vr_bsh, reg) 288 #define CSR_READ_2(sc, reg) \ 289 bus_space_read_2(sc->vr_bst, sc->vr_bsh, reg) 290 #define CSR_READ_1(sc, reg) \ 291 bus_space_read_1(sc->vr_bst, sc->vr_bsh, reg) 292 293 #define VR_TIMEOUT 1000 294 295 static int vr_add_rxbuf(struct vr_softc *, int); 296 297 static void vr_rxeof(struct vr_softc *); 298 static void vr_rxeoc(struct vr_softc *); 299 static void vr_txeof(struct vr_softc *); 300 static int vr_intr(void *); 301 static void vr_start(struct ifnet *); 302 static int vr_ioctl(struct ifnet *, u_long, void *); 303 static int vr_init(struct ifnet *); 304 static void vr_stop(struct ifnet *, int); 305 static void vr_rxdrain(struct vr_softc *); 306 static void vr_watchdog(struct ifnet *); 307 static void vr_tick(void *); 308 309 static int vr_mii_readreg(device_t, int, int); 310 static void vr_mii_writereg(device_t, int, int, int); 311 static void vr_mii_statchg(struct ifnet *); 312 313 static void vr_setmulti(struct vr_softc *); 314 static void vr_reset(struct vr_softc *); 315 static int vr_restore_state(pci_chipset_tag_t, pcitag_t, device_t, 316 pcireg_t); 317 static bool vr_resume(device_t, const pmf_qual_t *); 318 319 int vr_copy_small = 0; 320 321 #define VR_SETBIT(sc, reg, x) \ 322 CSR_WRITE_1(sc, reg, \ 323 CSR_READ_1(sc, reg) | (x)) 324 325 #define VR_CLRBIT(sc, reg, x) \ 326 CSR_WRITE_1(sc, reg, \ 327 CSR_READ_1(sc, reg) & ~(x)) 328 329 #define VR_SETBIT16(sc, reg, x) \ 330 CSR_WRITE_2(sc, reg, \ 331 CSR_READ_2(sc, reg) | (x)) 332 333 #define VR_CLRBIT16(sc, reg, x) \ 334 CSR_WRITE_2(sc, reg, \ 335 CSR_READ_2(sc, reg) & ~(x)) 336 337 #define VR_SETBIT32(sc, reg, x) \ 338 CSR_WRITE_4(sc, reg, \ 339 CSR_READ_4(sc, reg) | (x)) 340 341 #define VR_CLRBIT32(sc, reg, x) \ 342 CSR_WRITE_4(sc, reg, \ 343 CSR_READ_4(sc, reg) & ~(x)) 344 345 /* 346 * MII bit-bang glue. 347 */ 348 static uint32_t vr_mii_bitbang_read(device_t); 349 static void vr_mii_bitbang_write(device_t, uint32_t); 350 351 static const struct mii_bitbang_ops vr_mii_bitbang_ops = { 352 vr_mii_bitbang_read, 353 vr_mii_bitbang_write, 354 { 355 VR_MIICMD_DATAOUT, /* MII_BIT_MDO */ 356 VR_MIICMD_DATAIN, /* MII_BIT_MDI */ 357 VR_MIICMD_CLK, /* MII_BIT_MDC */ 358 VR_MIICMD_DIR, /* MII_BIT_DIR_HOST_PHY */ 359 0, /* MII_BIT_DIR_PHY_HOST */ 360 } 361 }; 362 363 static uint32_t 364 vr_mii_bitbang_read(device_t self) 365 { 366 struct vr_softc *sc = device_private(self); 367 368 return (CSR_READ_1(sc, VR_MIICMD)); 369 } 370 371 static void 372 vr_mii_bitbang_write(device_t self, uint32_t val) 373 { 374 struct vr_softc *sc = device_private(self); 375 376 CSR_WRITE_1(sc, VR_MIICMD, (val & 0xff) | VR_MIICMD_DIRECTPGM); 377 } 378 379 /* 380 * Read an PHY register through the MII. 381 */ 382 static int 383 vr_mii_readreg(device_t self, int phy, int reg) 384 { 385 struct vr_softc *sc = device_private(self); 386 387 CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 388 return (mii_bitbang_readreg(self, &vr_mii_bitbang_ops, phy, reg)); 389 } 390 391 /* 392 * Write to a PHY register through the MII. 393 */ 394 static void 395 vr_mii_writereg(device_t self, int phy, int reg, int val) 396 { 397 struct vr_softc *sc = device_private(self); 398 399 CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 400 mii_bitbang_writereg(self, &vr_mii_bitbang_ops, phy, reg, val); 401 } 402 403 static void 404 vr_mii_statchg(struct ifnet *ifp) 405 { 406 struct vr_softc *sc = ifp->if_softc; 407 int i; 408 409 /* 410 * In order to fiddle with the 'full-duplex' bit in the netconfig 411 * register, we first have to put the transmit and/or receive logic 412 * in the idle state. 413 */ 414 if ((sc->vr_mii.mii_media_status & IFM_ACTIVE) && 415 IFM_SUBTYPE(sc->vr_mii.mii_media_active) != IFM_NONE) { 416 sc->vr_link = true; 417 418 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) 419 VR_CLRBIT16(sc, VR_COMMAND, 420 (VR_CMD_TX_ON|VR_CMD_RX_ON)); 421 422 if (sc->vr_mii.mii_media_active & IFM_FDX) 423 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 424 else 425 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 426 427 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 428 } else { 429 sc->vr_link = false; 430 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 431 for (i = VR_TIMEOUT; i > 0; i--) { 432 delay(10); 433 if (!(CSR_READ_2(sc, VR_COMMAND) & 434 (VR_CMD_TX_ON|VR_CMD_RX_ON))) 435 break; 436 } 437 if (i == 0) { 438 #ifdef VR_DEBUG 439 aprint_error_dev(sc->vr_dev, "rx shutdown error!\n"); 440 #endif 441 sc->vr_flags |= VR_F_RESTART; 442 } 443 } 444 } 445 446 #define vr_calchash(addr) \ 447 (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26) 448 449 /* 450 * Program the 64-bit multicast hash filter. 451 */ 452 static void 453 vr_setmulti(struct vr_softc *sc) 454 { 455 struct ifnet *ifp; 456 int h = 0; 457 uint32_t hashes[2] = { 0, 0 }; 458 struct ether_multistep step; 459 struct ether_multi *enm; 460 int mcnt = 0; 461 uint8_t rxfilt; 462 463 ifp = &sc->vr_ec.ec_if; 464 465 rxfilt = CSR_READ_1(sc, VR_RXCFG); 466 467 if (ifp->if_flags & IFF_PROMISC) { 468 allmulti: 469 ifp->if_flags |= IFF_ALLMULTI; 470 rxfilt |= VR_RXCFG_RX_MULTI; 471 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 472 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 473 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 474 return; 475 } 476 477 /* first, zot all the existing hash bits */ 478 CSR_WRITE_4(sc, VR_MAR0, 0); 479 CSR_WRITE_4(sc, VR_MAR1, 0); 480 481 /* now program new ones */ 482 ETHER_FIRST_MULTI(step, &sc->vr_ec, enm); 483 while (enm != NULL) { 484 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 485 ETHER_ADDR_LEN) != 0) 486 goto allmulti; 487 488 h = vr_calchash(enm->enm_addrlo); 489 490 if (h < 32) 491 hashes[0] |= (1 << h); 492 else 493 hashes[1] |= (1 << (h - 32)); 494 ETHER_NEXT_MULTI(step, enm); 495 mcnt++; 496 } 497 498 ifp->if_flags &= ~IFF_ALLMULTI; 499 500 if (mcnt) 501 rxfilt |= VR_RXCFG_RX_MULTI; 502 else 503 rxfilt &= ~VR_RXCFG_RX_MULTI; 504 505 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 506 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 507 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 508 } 509 510 static void 511 vr_reset(struct vr_softc *sc) 512 { 513 int i; 514 515 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 516 517 for (i = 0; i < VR_TIMEOUT; i++) { 518 DELAY(10); 519 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 520 break; 521 } 522 if (i == VR_TIMEOUT) { 523 if (sc->vr_revid < REV_ID_VT3065_A) { 524 aprint_error_dev(sc->vr_dev, 525 "reset never completed!\n"); 526 } else { 527 /* Use newer force reset command */ 528 aprint_normal_dev(sc->vr_dev, 529 "using force reset command.\n"); 530 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 531 } 532 } 533 534 /* Wait a little while for the chip to get its brains in order. */ 535 DELAY(1000); 536 } 537 538 /* 539 * Initialize an RX descriptor and attach an MBUF cluster. 540 * Note: the length fields are only 11 bits wide, which means the 541 * largest size we can specify is 2047. This is important because 542 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 543 * overflow the field and make a mess. 544 */ 545 static int 546 vr_add_rxbuf(struct vr_softc *sc, int i) 547 { 548 struct vr_descsoft *ds = VR_DSRX(sc, i); 549 struct mbuf *m_new; 550 int error; 551 552 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 553 if (m_new == NULL) 554 return (ENOBUFS); 555 556 MCLGET(m_new, M_DONTWAIT); 557 if ((m_new->m_flags & M_EXT) == 0) { 558 m_freem(m_new); 559 return (ENOBUFS); 560 } 561 562 if (ds->ds_mbuf != NULL) 563 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 564 565 ds->ds_mbuf = m_new; 566 567 error = bus_dmamap_load(sc->vr_dmat, ds->ds_dmamap, 568 m_new->m_ext.ext_buf, m_new->m_ext.ext_size, NULL, 569 BUS_DMA_READ|BUS_DMA_NOWAIT); 570 if (error) { 571 aprint_error_dev(sc->vr_dev, 572 "unable to load rx DMA map %d, error = %d\n", i, error); 573 panic("vr_add_rxbuf"); /* XXX */ 574 } 575 576 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 577 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 578 579 VR_INIT_RXDESC(sc, i); 580 581 return (0); 582 } 583 584 /* 585 * A frame has been uploaded: pass the resulting mbuf chain up to 586 * the higher level protocols. 587 */ 588 static void 589 vr_rxeof(struct vr_softc *sc) 590 { 591 struct mbuf *m; 592 struct ifnet *ifp; 593 struct vr_desc *d; 594 struct vr_descsoft *ds; 595 int i, total_len; 596 uint32_t rxstat; 597 598 ifp = &sc->vr_ec.ec_if; 599 600 for (i = sc->vr_rxptr;; i = VR_NEXTRX(i)) { 601 d = VR_CDRX(sc, i); 602 ds = VR_DSRX(sc, i); 603 604 VR_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 605 606 rxstat = le32toh(d->vr_status); 607 608 if (rxstat & VR_RXSTAT_OWN) { 609 /* 610 * We have processed all of the receive buffers. 611 */ 612 break; 613 } 614 615 /* 616 * If an error occurs, update stats, clear the 617 * status word and leave the mbuf cluster in place: 618 * it should simply get re-used next time this descriptor 619 * comes up in the ring. 620 */ 621 if (rxstat & VR_RXSTAT_RXERR) { 622 const char *errstr; 623 624 ifp->if_ierrors++; 625 switch (rxstat & 0x000000FF) { 626 case VR_RXSTAT_CRCERR: 627 errstr = "crc error"; 628 break; 629 case VR_RXSTAT_FRAMEALIGNERR: 630 errstr = "frame alignment error"; 631 break; 632 case VR_RXSTAT_FIFOOFLOW: 633 errstr = "FIFO overflow"; 634 break; 635 case VR_RXSTAT_GIANT: 636 errstr = "received giant packet"; 637 break; 638 case VR_RXSTAT_RUNT: 639 errstr = "received runt packet"; 640 break; 641 case VR_RXSTAT_BUSERR: 642 errstr = "system bus error"; 643 break; 644 case VR_RXSTAT_BUFFERR: 645 errstr = "rx buffer error"; 646 break; 647 default: 648 errstr = "unknown rx error"; 649 break; 650 } 651 aprint_error_dev(sc->vr_dev, "receive error: %s\n", 652 errstr); 653 654 VR_INIT_RXDESC(sc, i); 655 656 continue; 657 } else if (!(rxstat & VR_RXSTAT_FIRSTFRAG) || 658 !(rxstat & VR_RXSTAT_LASTFRAG)) { 659 /* 660 * This driver expects to receive whole packets every 661 * time. In case we receive a fragment that is not 662 * a complete packet, we discard it. 663 */ 664 ifp->if_ierrors++; 665 666 aprint_error_dev(sc->vr_dev, 667 "receive error: incomplete frame; " 668 "size = %d, status = 0x%x\n", 669 VR_RXBYTES(le32toh(d->vr_status)), rxstat); 670 671 VR_INIT_RXDESC(sc, i); 672 673 continue; 674 } 675 676 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 677 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 678 679 /* No errors; receive the packet. */ 680 total_len = VR_RXBYTES(le32toh(d->vr_status)); 681 #ifdef DIAGNOSTIC 682 if (total_len == 0) { 683 /* 684 * If we receive a zero-length packet, we probably 685 * missed to handle an error condition above. 686 * Discard it to avoid a later crash. 687 */ 688 ifp->if_ierrors++; 689 690 aprint_error_dev(sc->vr_dev, 691 "receive error: zero-length packet; " 692 "status = 0x%x\n", rxstat); 693 694 VR_INIT_RXDESC(sc, i); 695 696 continue; 697 } 698 #endif 699 700 /* 701 * The Rhine chip includes the CRC with every packet. 702 * Trim it off here. 703 */ 704 total_len -= ETHER_CRC_LEN; 705 706 #ifdef __NO_STRICT_ALIGNMENT 707 /* 708 * If the packet is small enough to fit in a 709 * single header mbuf, allocate one and copy 710 * the data into it. This greatly reduces 711 * memory consumption when we receive lots 712 * of small packets. 713 * 714 * Otherwise, we add a new buffer to the receive 715 * chain. If this fails, we drop the packet and 716 * recycle the old buffer. 717 */ 718 if (vr_copy_small != 0 && total_len <= MHLEN) { 719 MGETHDR(m, M_DONTWAIT, MT_DATA); 720 if (m == NULL) 721 goto dropit; 722 memcpy(mtod(m, void *), 723 mtod(ds->ds_mbuf, void *), total_len); 724 VR_INIT_RXDESC(sc, i); 725 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 726 ds->ds_dmamap->dm_mapsize, 727 BUS_DMASYNC_PREREAD); 728 } else { 729 m = ds->ds_mbuf; 730 if (vr_add_rxbuf(sc, i) == ENOBUFS) { 731 dropit: 732 ifp->if_ierrors++; 733 VR_INIT_RXDESC(sc, i); 734 bus_dmamap_sync(sc->vr_dmat, 735 ds->ds_dmamap, 0, 736 ds->ds_dmamap->dm_mapsize, 737 BUS_DMASYNC_PREREAD); 738 continue; 739 } 740 } 741 #else 742 /* 743 * The Rhine's packet buffers must be 4-byte aligned. 744 * But this means that the data after the Ethernet header 745 * is misaligned. We must allocate a new buffer and 746 * copy the data, shifted forward 2 bytes. 747 */ 748 MGETHDR(m, M_DONTWAIT, MT_DATA); 749 if (m == NULL) { 750 dropit: 751 ifp->if_ierrors++; 752 VR_INIT_RXDESC(sc, i); 753 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 754 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 755 continue; 756 } 757 if (total_len > (MHLEN - 2)) { 758 MCLGET(m, M_DONTWAIT); 759 if ((m->m_flags & M_EXT) == 0) { 760 m_freem(m); 761 goto dropit; 762 } 763 } 764 m->m_data += 2; 765 766 /* 767 * Note that we use clusters for incoming frames, so the 768 * buffer is virtually contiguous. 769 */ 770 memcpy(mtod(m, void *), mtod(ds->ds_mbuf, void *), 771 total_len); 772 773 /* Allow the receive descriptor to continue using its mbuf. */ 774 VR_INIT_RXDESC(sc, i); 775 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 776 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 777 #endif /* __NO_STRICT_ALIGNMENT */ 778 779 m_set_rcvif(m, ifp); 780 m->m_pkthdr.len = m->m_len = total_len; 781 /* Pass it on. */ 782 if_percpuq_enqueue(ifp->if_percpuq, m); 783 } 784 785 /* Update the receive pointer. */ 786 sc->vr_rxptr = i; 787 } 788 789 void 790 vr_rxeoc(struct vr_softc *sc) 791 { 792 struct ifnet *ifp; 793 int i; 794 795 ifp = &sc->vr_ec.ec_if; 796 797 ifp->if_ierrors++; 798 799 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 800 for (i = 0; i < VR_TIMEOUT; i++) { 801 DELAY(10); 802 if ((CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON) == 0) 803 break; 804 } 805 if (i == VR_TIMEOUT) { 806 /* XXX need reset? */ 807 aprint_error_dev(sc->vr_dev, "RX shutdown never completed\n"); 808 } 809 810 vr_rxeof(sc); 811 812 CSR_WRITE_4(sc, VR_RXADDR, VR_CDRXADDR(sc, sc->vr_rxptr)); 813 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 814 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 815 } 816 817 /* 818 * A frame was downloaded to the chip. It's safe for us to clean up 819 * the list buffers. 820 */ 821 static void 822 vr_txeof(struct vr_softc *sc) 823 { 824 struct ifnet *ifp = &sc->vr_ec.ec_if; 825 struct vr_desc *d; 826 struct vr_descsoft *ds; 827 uint32_t txstat; 828 int i, j; 829 830 ifp->if_flags &= ~IFF_OACTIVE; 831 832 /* 833 * Go through our tx list and free mbufs for those 834 * frames that have been transmitted. 835 */ 836 for (i = sc->vr_txdirty; sc->vr_txpending != 0; 837 i = VR_NEXTTX(i), sc->vr_txpending--) { 838 d = VR_CDTX(sc, i); 839 ds = VR_DSTX(sc, i); 840 841 VR_CDTXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 842 843 txstat = le32toh(d->vr_status); 844 845 if (txstat & (VR_TXSTAT_ABRT | VR_TXSTAT_UDF)) { 846 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 847 for (j = 0; j < VR_TIMEOUT; j++) { 848 DELAY(10); 849 if ((CSR_READ_2(sc, VR_COMMAND) & 850 VR_CMD_TX_ON) == 0) 851 break; 852 } 853 if (j == VR_TIMEOUT) { 854 /* XXX need reset? */ 855 aprint_error_dev(sc->vr_dev, 856 "TX shutdown never completed\n"); 857 } 858 d->vr_status = htole32(VR_TXSTAT_OWN); 859 CSR_WRITE_4(sc, VR_TXADDR, VR_CDTXADDR(sc, i)); 860 break; 861 } 862 863 if (txstat & VR_TXSTAT_OWN) 864 break; 865 866 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 867 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 868 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 869 m_freem(ds->ds_mbuf); 870 ds->ds_mbuf = NULL; 871 872 if (txstat & VR_TXSTAT_ERRSUM) { 873 ifp->if_oerrors++; 874 if (txstat & VR_TXSTAT_DEFER) 875 ifp->if_collisions++; 876 if (txstat & VR_TXSTAT_LATECOLL) 877 ifp->if_collisions++; 878 } 879 880 ifp->if_collisions += (txstat & VR_TXSTAT_COLLCNT) >> 3; 881 ifp->if_opackets++; 882 } 883 884 /* Update the dirty transmit buffer pointer. */ 885 sc->vr_txdirty = i; 886 887 /* 888 * Cancel the watchdog timer if there are no pending 889 * transmissions. 890 */ 891 if (sc->vr_txpending == 0) 892 ifp->if_timer = 0; 893 } 894 895 static int 896 vr_intr(void *arg) 897 { 898 struct vr_softc *sc; 899 struct ifnet *ifp; 900 uint16_t status; 901 int handled = 0, dotx = 0; 902 903 sc = arg; 904 ifp = &sc->vr_ec.ec_if; 905 906 /* Suppress unwanted interrupts. */ 907 if ((ifp->if_flags & IFF_UP) == 0) { 908 vr_stop(ifp, 1); 909 return (0); 910 } 911 912 /* Disable interrupts. */ 913 CSR_WRITE_2(sc, VR_IMR, 0x0000); 914 915 for (;;) { 916 status = CSR_READ_2(sc, VR_ISR); 917 if (status) 918 CSR_WRITE_2(sc, VR_ISR, status); 919 920 if ((status & VR_INTRS) == 0) 921 break; 922 923 handled = 1; 924 925 rnd_add_uint32(&sc->rnd_source, status); 926 927 if (status & VR_ISR_RX_OK) 928 vr_rxeof(sc); 929 930 if (status & VR_ISR_RX_DROPPED) { 931 aprint_error_dev(sc->vr_dev, "rx packet lost\n"); 932 ifp->if_ierrors++; 933 } 934 935 if (status & 936 (VR_ISR_RX_ERR | VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW)) 937 vr_rxeoc(sc); 938 939 940 if (status & (VR_ISR_BUSERR | VR_ISR_TX_UNDERRUN)) { 941 if (status & VR_ISR_BUSERR) 942 aprint_error_dev(sc->vr_dev, "PCI bus error\n"); 943 if (status & VR_ISR_TX_UNDERRUN) 944 aprint_error_dev(sc->vr_dev, 945 "transmit underrun\n"); 946 /* vr_init() calls vr_start() */ 947 dotx = 0; 948 (void)vr_init(ifp); 949 950 } 951 952 if (status & VR_ISR_TX_OK) { 953 dotx = 1; 954 vr_txeof(sc); 955 } 956 957 if (status & 958 (VR_ISR_TX_ABRT | VR_ISR_TX_ABRT2 | VR_ISR_TX_UDFI)) { 959 if (status & (VR_ISR_TX_ABRT | VR_ISR_TX_ABRT2)) 960 aprint_error_dev(sc->vr_dev, 961 "transmit aborted\n"); 962 if (status & VR_ISR_TX_UDFI) 963 aprint_error_dev(sc->vr_dev, 964 "transmit underflow\n"); 965 ifp->if_oerrors++; 966 dotx = 1; 967 vr_txeof(sc); 968 if (sc->vr_txpending) { 969 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 970 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 971 } 972 } 973 } 974 975 /* Re-enable interrupts. */ 976 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 977 978 if (dotx) 979 if_schedule_deferred_start(ifp); 980 981 return (handled); 982 } 983 984 /* 985 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 986 * to the mbuf data regions directly in the transmit lists. We also save a 987 * copy of the pointers since the transmit list fragment pointers are 988 * physical addresses. 989 */ 990 static void 991 vr_start(struct ifnet *ifp) 992 { 993 struct vr_softc *sc = ifp->if_softc; 994 struct mbuf *m0, *m; 995 struct vr_desc *d; 996 struct vr_descsoft *ds; 997 int error, firsttx, nexttx, opending; 998 999 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1000 return; 1001 if (sc->vr_link == false) 1002 return; 1003 1004 /* 1005 * Remember the previous txpending and the first transmit 1006 * descriptor we use. 1007 */ 1008 opending = sc->vr_txpending; 1009 firsttx = VR_NEXTTX(sc->vr_txlast); 1010 1011 /* 1012 * Loop through the send queue, setting up transmit descriptors 1013 * until we drain the queue, or use up all available transmit 1014 * descriptors. 1015 */ 1016 while (sc->vr_txpending < VR_NTXDESC) { 1017 /* 1018 * Grab a packet off the queue. 1019 */ 1020 IFQ_POLL(&ifp->if_snd, m0); 1021 if (m0 == NULL) 1022 break; 1023 m = NULL; 1024 1025 /* 1026 * Get the next available transmit descriptor. 1027 */ 1028 nexttx = VR_NEXTTX(sc->vr_txlast); 1029 d = VR_CDTX(sc, nexttx); 1030 ds = VR_DSTX(sc, nexttx); 1031 1032 /* 1033 * Load the DMA map. If this fails, the packet didn't 1034 * fit in one DMA segment, and we need to copy. Note, 1035 * the packet must also be aligned. 1036 * if the packet is too small, copy it too, so we're sure 1037 * we have enough room for the pad buffer. 1038 */ 1039 if ((mtod(m0, uintptr_t) & 3) != 0 || 1040 m0->m_pkthdr.len < VR_MIN_FRAMELEN || 1041 bus_dmamap_load_mbuf(sc->vr_dmat, ds->ds_dmamap, m0, 1042 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1043 MGETHDR(m, M_DONTWAIT, MT_DATA); 1044 if (m == NULL) { 1045 aprint_error_dev(sc->vr_dev, 1046 "unable to allocate Tx mbuf\n"); 1047 break; 1048 } 1049 if (m0->m_pkthdr.len > MHLEN) { 1050 MCLGET(m, M_DONTWAIT); 1051 if ((m->m_flags & M_EXT) == 0) { 1052 aprint_error_dev(sc->vr_dev, 1053 "unable to allocate Tx cluster\n"); 1054 m_freem(m); 1055 break; 1056 } 1057 } 1058 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1059 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1060 /* 1061 * The Rhine doesn't auto-pad, so we have to do this 1062 * ourselves. 1063 */ 1064 if (m0->m_pkthdr.len < VR_MIN_FRAMELEN) { 1065 memset(mtod(m, char *) + m0->m_pkthdr.len, 1066 0, VR_MIN_FRAMELEN - m0->m_pkthdr.len); 1067 m->m_pkthdr.len = m->m_len = VR_MIN_FRAMELEN; 1068 } 1069 error = bus_dmamap_load_mbuf(sc->vr_dmat, 1070 ds->ds_dmamap, m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1071 if (error) { 1072 m_freem(m); 1073 aprint_error_dev(sc->vr_dev, "unable to load " 1074 "Tx buffer, error = %d\n", error); 1075 break; 1076 } 1077 } 1078 1079 IFQ_DEQUEUE(&ifp->if_snd, m0); 1080 if (m != NULL) { 1081 m_freem(m0); 1082 m0 = m; 1083 } 1084 1085 /* Sync the DMA map. */ 1086 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 1087 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1088 1089 /* 1090 * Store a pointer to the packet so we can free it later. 1091 */ 1092 ds->ds_mbuf = m0; 1093 1094 /* 1095 * If there's a BPF listener, bounce a copy of this frame 1096 * to him. 1097 */ 1098 bpf_mtap(ifp, m0, BPF_D_OUT); 1099 1100 /* 1101 * Fill in the transmit descriptor. 1102 */ 1103 d->vr_data = htole32(ds->ds_dmamap->dm_segs[0].ds_addr); 1104 d->vr_ctl = htole32(m0->m_pkthdr.len); 1105 d->vr_ctl |= htole32(VR_TXCTL_FIRSTFRAG | VR_TXCTL_LASTFRAG); 1106 1107 /* 1108 * If this is the first descriptor we're enqueuing, 1109 * don't give it to the Rhine yet. That could cause 1110 * a race condition. We'll do it below. 1111 */ 1112 if (nexttx == firsttx) 1113 d->vr_status = 0; 1114 else 1115 d->vr_status = htole32(VR_TXSTAT_OWN); 1116 1117 VR_CDTXSYNC(sc, nexttx, 1118 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1119 1120 /* Advance the tx pointer. */ 1121 sc->vr_txpending++; 1122 sc->vr_txlast = nexttx; 1123 } 1124 1125 if (sc->vr_txpending == VR_NTXDESC) { 1126 /* No more slots left; notify upper layer. */ 1127 ifp->if_flags |= IFF_OACTIVE; 1128 } 1129 1130 if (sc->vr_txpending != opending) { 1131 /* 1132 * We enqueued packets. If the transmitter was idle, 1133 * reset the txdirty pointer. 1134 */ 1135 if (opending == 0) 1136 sc->vr_txdirty = firsttx; 1137 1138 /* 1139 * Cause a transmit interrupt to happen on the 1140 * last packet we enqueued. 1141 */ 1142 VR_CDTX(sc, sc->vr_txlast)->vr_ctl |= htole32(VR_TXCTL_FINT); 1143 VR_CDTXSYNC(sc, sc->vr_txlast, 1144 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1145 1146 /* 1147 * The entire packet chain is set up. Give the 1148 * first descriptor to the Rhine now. 1149 */ 1150 VR_CDTX(sc, firsttx)->vr_status = htole32(VR_TXSTAT_OWN); 1151 VR_CDTXSYNC(sc, firsttx, 1152 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1153 1154 /* Start the transmitter. */ 1155 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1156 1157 /* Set the watchdog timer in case the chip flakes out. */ 1158 ifp->if_timer = 5; 1159 } 1160 } 1161 1162 /* 1163 * Initialize the interface. Must be called at splnet. 1164 */ 1165 static int 1166 vr_init(struct ifnet *ifp) 1167 { 1168 struct vr_softc *sc = ifp->if_softc; 1169 struct vr_desc *d; 1170 struct vr_descsoft *ds; 1171 int i, error = 0; 1172 1173 /* Cancel pending I/O. */ 1174 vr_stop(ifp, 0); 1175 1176 /* Reset the Rhine to a known state. */ 1177 vr_reset(sc); 1178 1179 /* set DMA length in BCR0 and BCR1 */ 1180 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1181 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1182 1183 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1184 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTH_128BYTES); 1185 1186 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1187 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTH_STORENFWD); 1188 1189 /* set DMA threshold length in RXCFG and TXCFG */ 1190 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1191 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1192 1193 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1194 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1195 1196 /* 1197 * Initialize the transmit descriptor ring. txlast is initialized 1198 * to the end of the list so that it will wrap around to the first 1199 * descriptor when the first packet is transmitted. 1200 */ 1201 for (i = 0; i < VR_NTXDESC; i++) { 1202 d = VR_CDTX(sc, i); 1203 memset(d, 0, sizeof(struct vr_desc)); 1204 d->vr_next = htole32(VR_CDTXADDR(sc, VR_NEXTTX(i))); 1205 VR_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1206 } 1207 sc->vr_txpending = 0; 1208 sc->vr_txdirty = 0; 1209 sc->vr_txlast = VR_NTXDESC - 1; 1210 1211 /* 1212 * Initialize the receive descriptor ring. 1213 */ 1214 for (i = 0; i < VR_NRXDESC; i++) { 1215 ds = VR_DSRX(sc, i); 1216 if (ds->ds_mbuf == NULL) { 1217 if ((error = vr_add_rxbuf(sc, i)) != 0) { 1218 aprint_error_dev(sc->vr_dev, 1219 "unable to allocate or map rx buffer %d, " 1220 "error = %d\n", i, error); 1221 /* 1222 * XXX Should attempt to run with fewer receive 1223 * XXX buffers instead of just failing. 1224 */ 1225 vr_rxdrain(sc); 1226 goto out; 1227 } 1228 } else 1229 VR_INIT_RXDESC(sc, i); 1230 } 1231 sc->vr_rxptr = 0; 1232 1233 /* If we want promiscuous mode, set the allframes bit. */ 1234 if (ifp->if_flags & IFF_PROMISC) 1235 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1236 else 1237 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1238 1239 /* Set capture broadcast bit to capture broadcast frames. */ 1240 if (ifp->if_flags & IFF_BROADCAST) 1241 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1242 else 1243 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1244 1245 /* Program the multicast filter, if necessary. */ 1246 vr_setmulti(sc); 1247 1248 /* Give the transmit and receive rings to the Rhine. */ 1249 CSR_WRITE_4(sc, VR_RXADDR, VR_CDRXADDR(sc, sc->vr_rxptr)); 1250 CSR_WRITE_4(sc, VR_TXADDR, VR_CDTXADDR(sc, VR_NEXTTX(sc->vr_txlast))); 1251 1252 /* Set current media. */ 1253 sc->vr_link = true; 1254 if ((error = ether_mediachange(ifp)) != 0) 1255 goto out; 1256 1257 /* Enable receiver and transmitter. */ 1258 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1259 VR_CMD_TX_ON|VR_CMD_RX_ON| 1260 VR_CMD_RX_GO); 1261 1262 /* Enable interrupts. */ 1263 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1264 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1265 1266 ifp->if_flags |= IFF_RUNNING; 1267 ifp->if_flags &= ~IFF_OACTIVE; 1268 1269 /* Start one second timer. */ 1270 callout_reset(&sc->vr_tick_ch, hz, vr_tick, sc); 1271 1272 /* Attempt to start output on the interface. */ 1273 vr_start(ifp); 1274 1275 out: 1276 if (error) 1277 aprint_error_dev(sc->vr_dev, "interface not running\n"); 1278 return (error); 1279 } 1280 1281 static int 1282 vr_ioctl(struct ifnet *ifp, u_long command, void *data) 1283 { 1284 struct vr_softc *sc = ifp->if_softc; 1285 int s, error = 0; 1286 1287 s = splnet(); 1288 1289 switch (command) { 1290 case SIOCSIFFLAGS: 1291 if ((error = ifioctl_common(ifp, command, data)) != 0) 1292 break; 1293 1294 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 1295 case IFF_RUNNING: 1296 vr_stop(ifp, 1); 1297 break; 1298 case IFF_UP: 1299 vr_init(ifp); 1300 break; 1301 case IFF_UP | IFF_RUNNING: 1302 if ((ifp->if_flags ^ sc->vr_if_flags) == IFF_PROMISC) 1303 vr_setmulti(sc); 1304 else 1305 vr_init(ifp); 1306 break; 1307 } 1308 sc->vr_if_flags = ifp->if_flags; 1309 break; 1310 default: 1311 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1312 break; 1313 error = 0; 1314 if (command == SIOCADDMULTI || command == SIOCDELMULTI) 1315 vr_setmulti(sc); 1316 } 1317 splx(s); 1318 1319 return error; 1320 } 1321 1322 static void 1323 vr_watchdog(struct ifnet *ifp) 1324 { 1325 struct vr_softc *sc = ifp->if_softc; 1326 1327 aprint_error_dev(sc->vr_dev, "device timeout\n"); 1328 ifp->if_oerrors++; 1329 1330 (void) vr_init(ifp); 1331 } 1332 1333 /* 1334 * One second timer, used to tick MII. 1335 */ 1336 static void 1337 vr_tick(void *arg) 1338 { 1339 struct vr_softc *sc = arg; 1340 int s; 1341 1342 s = splnet(); 1343 if (sc->vr_flags & VR_F_RESTART) { 1344 aprint_normal_dev(sc->vr_dev, "restarting\n"); 1345 vr_init(&sc->vr_ec.ec_if); 1346 sc->vr_flags &= ~VR_F_RESTART; 1347 } 1348 mii_tick(&sc->vr_mii); 1349 splx(s); 1350 1351 callout_reset(&sc->vr_tick_ch, hz, vr_tick, sc); 1352 } 1353 1354 /* 1355 * Drain the receive queue. 1356 */ 1357 static void 1358 vr_rxdrain(struct vr_softc *sc) 1359 { 1360 struct vr_descsoft *ds; 1361 int i; 1362 1363 for (i = 0; i < VR_NRXDESC; i++) { 1364 ds = VR_DSRX(sc, i); 1365 if (ds->ds_mbuf != NULL) { 1366 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 1367 m_freem(ds->ds_mbuf); 1368 ds->ds_mbuf = NULL; 1369 } 1370 } 1371 } 1372 1373 /* 1374 * Stop the adapter and free any mbufs allocated to the 1375 * transmit lists. 1376 */ 1377 static void 1378 vr_stop(struct ifnet *ifp, int disable) 1379 { 1380 struct vr_softc *sc = ifp->if_softc; 1381 struct vr_descsoft *ds; 1382 int i; 1383 1384 /* Cancel one second timer. */ 1385 callout_stop(&sc->vr_tick_ch); 1386 1387 /* Down the MII. */ 1388 mii_down(&sc->vr_mii); 1389 1390 ifp = &sc->vr_ec.ec_if; 1391 ifp->if_timer = 0; 1392 1393 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1394 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1395 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1396 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1397 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1398 1399 /* 1400 * Release any queued transmit buffers. 1401 */ 1402 for (i = 0; i < VR_NTXDESC; i++) { 1403 ds = VR_DSTX(sc, i); 1404 if (ds->ds_mbuf != NULL) { 1405 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 1406 m_freem(ds->ds_mbuf); 1407 ds->ds_mbuf = NULL; 1408 } 1409 } 1410 1411 /* 1412 * Mark the interface down and cancel the watchdog timer. 1413 */ 1414 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1415 ifp->if_timer = 0; 1416 1417 if (disable) 1418 vr_rxdrain(sc); 1419 } 1420 1421 static int vr_probe(device_t, cfdata_t, void *); 1422 static void vr_attach(device_t, device_t, void *); 1423 static bool vr_shutdown(device_t, int); 1424 1425 CFATTACH_DECL_NEW(vr, sizeof (struct vr_softc), 1426 vr_probe, vr_attach, NULL, NULL); 1427 1428 static const struct vr_type * 1429 vr_lookup(struct pci_attach_args *pa) 1430 { 1431 const struct vr_type *vrt; 1432 int i; 1433 1434 for (i = 0; i < __arraycount(vr_devs); i++) { 1435 vrt = &vr_devs[i]; 1436 if (PCI_VENDOR(pa->pa_id) == vrt->vr_vid && 1437 PCI_PRODUCT(pa->pa_id) == vrt->vr_did) 1438 return (vrt); 1439 } 1440 return (NULL); 1441 } 1442 1443 static int 1444 vr_probe(device_t parent, cfdata_t match, void *aux) 1445 { 1446 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1447 1448 if (vr_lookup(pa) != NULL) 1449 return (1); 1450 1451 return (0); 1452 } 1453 1454 /* 1455 * Stop all chip I/O so that the kernel's probe routines don't 1456 * get confused by errant DMAs when rebooting. 1457 */ 1458 static bool 1459 vr_shutdown(device_t self, int howto) 1460 { 1461 struct vr_softc *sc = device_private(self); 1462 1463 vr_stop(&sc->vr_ec.ec_if, 1); 1464 1465 return true; 1466 } 1467 1468 /* 1469 * Attach the interface. Allocate softc structures, do ifmedia 1470 * setup and ethernet/BPF attach. 1471 */ 1472 static void 1473 vr_attach(device_t parent, device_t self, void *aux) 1474 { 1475 struct vr_softc *sc = device_private(self); 1476 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 1477 bus_dma_segment_t seg; 1478 uint32_t reg; 1479 struct ifnet *ifp; 1480 uint8_t eaddr[ETHER_ADDR_LEN], mac; 1481 int i, rseg, error; 1482 char intrbuf[PCI_INTRSTR_LEN]; 1483 1484 #define PCI_CONF_WRITE(r, v) pci_conf_write(sc->vr_pc, sc->vr_tag, (r), (v)) 1485 #define PCI_CONF_READ(r) pci_conf_read(sc->vr_pc, sc->vr_tag, (r)) 1486 1487 sc->vr_dev = self; 1488 sc->vr_pc = pa->pa_pc; 1489 sc->vr_tag = pa->pa_tag; 1490 sc->vr_id = pa->pa_id; 1491 callout_init(&sc->vr_tick_ch, 0); 1492 1493 pci_aprint_devinfo(pa, NULL); 1494 1495 /* 1496 * Handle power management nonsense. 1497 */ 1498 1499 sc->vr_save_iobase = PCI_CONF_READ(VR_PCI_LOIO); 1500 sc->vr_save_membase = PCI_CONF_READ(VR_PCI_LOMEM); 1501 sc->vr_save_irq = PCI_CONF_READ(PCI_INTERRUPT_REG); 1502 1503 /* power up chip */ 1504 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 1505 vr_restore_state)) && error != EOPNOTSUPP) { 1506 aprint_error_dev(self, "cannot activate %d\n", error); 1507 return; 1508 } 1509 1510 /* Make sure bus mastering is enabled. */ 1511 reg = PCI_CONF_READ(PCI_COMMAND_STATUS_REG); 1512 reg |= PCI_COMMAND_MASTER_ENABLE; 1513 PCI_CONF_WRITE(PCI_COMMAND_STATUS_REG, reg); 1514 1515 /* Get revision */ 1516 sc->vr_revid = PCI_REVISION(pa->pa_class); 1517 1518 /* 1519 * Map control/status registers. 1520 */ 1521 { 1522 bus_space_tag_t iot, memt; 1523 bus_space_handle_t ioh, memh; 1524 int ioh_valid, memh_valid; 1525 pci_intr_handle_t intrhandle; 1526 const char *intrstr; 1527 1528 ioh_valid = (pci_mapreg_map(pa, VR_PCI_LOIO, 1529 PCI_MAPREG_TYPE_IO, 0, 1530 &iot, &ioh, NULL, NULL) == 0); 1531 memh_valid = (pci_mapreg_map(pa, VR_PCI_LOMEM, 1532 PCI_MAPREG_TYPE_MEM | 1533 PCI_MAPREG_MEM_TYPE_32BIT, 1534 0, &memt, &memh, NULL, NULL) == 0); 1535 #if defined(VR_USEIOSPACE) 1536 if (ioh_valid) { 1537 sc->vr_bst = iot; 1538 sc->vr_bsh = ioh; 1539 } else if (memh_valid) { 1540 sc->vr_bst = memt; 1541 sc->vr_bsh = memh; 1542 } 1543 #else 1544 if (memh_valid) { 1545 sc->vr_bst = memt; 1546 sc->vr_bsh = memh; 1547 } else if (ioh_valid) { 1548 sc->vr_bst = iot; 1549 sc->vr_bsh = ioh; 1550 } 1551 #endif 1552 else { 1553 aprint_error_dev(self, 1554 "unable to map device registers\n"); 1555 return; 1556 } 1557 1558 /* Allocate interrupt */ 1559 if (pci_intr_map(pa, &intrhandle)) { 1560 aprint_error_dev(self, "couldn't map interrupt\n"); 1561 return; 1562 } 1563 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, 1564 sizeof(intrbuf)); 1565 sc->vr_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 1566 vr_intr, sc); 1567 if (sc->vr_ih == NULL) { 1568 aprint_error_dev(self, "couldn't establish interrupt"); 1569 if (intrstr != NULL) 1570 aprint_error(" at %s", intrstr); 1571 aprint_error("\n"); 1572 return; 1573 } 1574 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 1575 } 1576 1577 /* 1578 * Windows may put the chip in suspend mode when it 1579 * shuts down. Be sure to kick it in the head to wake it 1580 * up again. 1581 * 1582 * Don't touch this register on VT3043 since it causes 1583 * kernel MCHK trap on macppc. 1584 * (Note some VT86C100A chip returns a product ID of VT3043) 1585 */ 1586 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT3043) 1587 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 1588 1589 /* Reset the adapter. */ 1590 vr_reset(sc); 1591 1592 /* 1593 * Get station address. The way the Rhine chips work, 1594 * you're not allowed to directly access the EEPROM once 1595 * they've been programmed a special way. Consequently, 1596 * we need to read the node address from the PAR registers. 1597 * 1598 * XXXSCW: On the Rhine III, setting VR_EECSR_LOAD forces a reload 1599 * of the *whole* EEPROM, not just the MAC address. This is 1600 * pretty pointless since the chip does this automatically 1601 * at powerup/reset. 1602 * I suspect the same thing applies to the other Rhine 1603 * variants, but in the absence of a data sheet for those 1604 * (and the lack of anyone else noticing the problems this 1605 * causes) I'm going to retain the old behaviour for the 1606 * other parts. 1607 * In some cases, the chip really does startup without having 1608 * read the EEPROM (kern/34812). To handle this case, we force 1609 * a reload if we see an all-zeroes MAC address. 1610 */ 1611 for (mac = 0, i = 0; i < ETHER_ADDR_LEN; i++) 1612 mac |= (eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i)); 1613 1614 if (mac == 0 || (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT6105 && 1615 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT6102)) { 1616 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 1617 DELAY(200); 1618 for (i = 0; i < ETHER_ADDR_LEN; i++) 1619 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 1620 } 1621 1622 /* 1623 * A Rhine chip was detected. Inform the world. 1624 */ 1625 aprint_normal_dev(self, "Ethernet address: %s\n", ether_sprintf(eaddr)); 1626 1627 memcpy(sc->vr_enaddr, eaddr, ETHER_ADDR_LEN); 1628 1629 sc->vr_dmat = pa->pa_dmat; 1630 1631 /* 1632 * Allocate the control data structures, and create and load 1633 * the DMA map for it. 1634 */ 1635 if ((error = bus_dmamem_alloc(sc->vr_dmat, 1636 sizeof(struct vr_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 1637 0)) != 0) { 1638 aprint_error_dev(self, 1639 "unable to allocate control data, error = %d\n", error); 1640 goto fail_0; 1641 } 1642 1643 if ((error = bus_dmamem_map(sc->vr_dmat, &seg, rseg, 1644 sizeof(struct vr_control_data), (void **)&sc->vr_control_data, 1645 BUS_DMA_COHERENT)) != 0) { 1646 aprint_error_dev(self, 1647 "unable to map control data, error = %d\n", error); 1648 goto fail_1; 1649 } 1650 1651 if ((error = bus_dmamap_create(sc->vr_dmat, 1652 sizeof(struct vr_control_data), 1, 1653 sizeof(struct vr_control_data), 0, 0, 1654 &sc->vr_cddmamap)) != 0) { 1655 aprint_error_dev(self, 1656 "unable to create control data DMA map, error = %d\n", 1657 error); 1658 goto fail_2; 1659 } 1660 1661 if ((error = bus_dmamap_load(sc->vr_dmat, sc->vr_cddmamap, 1662 sc->vr_control_data, sizeof(struct vr_control_data), NULL, 1663 0)) != 0) { 1664 aprint_error_dev(self, 1665 "unable to load control data DMA map, error = %d\n", 1666 error); 1667 goto fail_3; 1668 } 1669 1670 /* 1671 * Create the transmit buffer DMA maps. 1672 */ 1673 for (i = 0; i < VR_NTXDESC; i++) { 1674 if ((error = bus_dmamap_create(sc->vr_dmat, MCLBYTES, 1675 1, MCLBYTES, 0, 0, 1676 &VR_DSTX(sc, i)->ds_dmamap)) != 0) { 1677 aprint_error_dev(self, 1678 "unable to create tx DMA map %d, error = %d\n", i, 1679 error); 1680 goto fail_4; 1681 } 1682 } 1683 1684 /* 1685 * Create the receive buffer DMA maps. 1686 */ 1687 for (i = 0; i < VR_NRXDESC; i++) { 1688 if ((error = bus_dmamap_create(sc->vr_dmat, MCLBYTES, 1, 1689 MCLBYTES, 0, 0, 1690 &VR_DSRX(sc, i)->ds_dmamap)) != 0) { 1691 aprint_error_dev(self, 1692 "unable to create rx DMA map %d, error = %d\n", i, 1693 error); 1694 goto fail_5; 1695 } 1696 VR_DSRX(sc, i)->ds_mbuf = NULL; 1697 } 1698 1699 ifp = &sc->vr_ec.ec_if; 1700 ifp->if_softc = sc; 1701 ifp->if_mtu = ETHERMTU; 1702 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1703 ifp->if_ioctl = vr_ioctl; 1704 ifp->if_start = vr_start; 1705 ifp->if_watchdog = vr_watchdog; 1706 ifp->if_init = vr_init; 1707 ifp->if_stop = vr_stop; 1708 IFQ_SET_READY(&ifp->if_snd); 1709 1710 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 1711 1712 /* 1713 * Initialize MII/media info. 1714 */ 1715 sc->vr_mii.mii_ifp = ifp; 1716 sc->vr_mii.mii_readreg = vr_mii_readreg; 1717 sc->vr_mii.mii_writereg = vr_mii_writereg; 1718 sc->vr_mii.mii_statchg = vr_mii_statchg; 1719 1720 sc->vr_ec.ec_mii = &sc->vr_mii; 1721 ifmedia_init(&sc->vr_mii.mii_media, IFM_IMASK, ether_mediachange, 1722 ether_mediastatus); 1723 mii_attach(self, &sc->vr_mii, 0xffffffff, MII_PHY_ANY, 1724 MII_OFFSET_ANY, MIIF_FORCEANEG); 1725 if (LIST_FIRST(&sc->vr_mii.mii_phys) == NULL) { 1726 ifmedia_add(&sc->vr_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1727 ifmedia_set(&sc->vr_mii.mii_media, IFM_ETHER|IFM_NONE); 1728 } else 1729 ifmedia_set(&sc->vr_mii.mii_media, IFM_ETHER|IFM_AUTO); 1730 1731 sc->vr_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 1732 1733 /* 1734 * Call MI attach routines. 1735 */ 1736 if_attach(ifp); 1737 if_deferred_start_init(ifp, NULL); 1738 ether_ifattach(ifp, sc->vr_enaddr); 1739 1740 rnd_attach_source(&sc->rnd_source, device_xname(self), 1741 RND_TYPE_NET, RND_FLAG_DEFAULT); 1742 1743 if (pmf_device_register1(self, NULL, vr_resume, vr_shutdown)) 1744 pmf_class_network_register(self, ifp); 1745 else 1746 aprint_error_dev(self, "couldn't establish power handler\n"); 1747 1748 return; 1749 1750 fail_5: 1751 for (i = 0; i < VR_NRXDESC; i++) { 1752 if (sc->vr_rxsoft[i].ds_dmamap != NULL) 1753 bus_dmamap_destroy(sc->vr_dmat, 1754 sc->vr_rxsoft[i].ds_dmamap); 1755 } 1756 fail_4: 1757 for (i = 0; i < VR_NTXDESC; i++) { 1758 if (sc->vr_txsoft[i].ds_dmamap != NULL) 1759 bus_dmamap_destroy(sc->vr_dmat, 1760 sc->vr_txsoft[i].ds_dmamap); 1761 } 1762 bus_dmamap_unload(sc->vr_dmat, sc->vr_cddmamap); 1763 fail_3: 1764 bus_dmamap_destroy(sc->vr_dmat, sc->vr_cddmamap); 1765 fail_2: 1766 bus_dmamem_unmap(sc->vr_dmat, (void *)sc->vr_control_data, 1767 sizeof(struct vr_control_data)); 1768 fail_1: 1769 bus_dmamem_free(sc->vr_dmat, &seg, rseg); 1770 fail_0: 1771 return; 1772 } 1773 1774 static int 1775 vr_restore_state(pci_chipset_tag_t pc, pcitag_t tag, device_t self, 1776 pcireg_t state) 1777 { 1778 struct vr_softc *sc = device_private(self); 1779 int error; 1780 1781 if (state == PCI_PMCSR_STATE_D0) 1782 return 0; 1783 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 1784 return error; 1785 1786 /* Restore PCI config data. */ 1787 PCI_CONF_WRITE(VR_PCI_LOIO, sc->vr_save_iobase); 1788 PCI_CONF_WRITE(VR_PCI_LOMEM, sc->vr_save_membase); 1789 PCI_CONF_WRITE(PCI_INTERRUPT_REG, sc->vr_save_irq); 1790 return 0; 1791 } 1792 1793 static bool 1794 vr_resume(device_t self, const pmf_qual_t *qual) 1795 { 1796 struct vr_softc *sc = device_private(self); 1797 1798 if (PCI_PRODUCT(sc->vr_id) != PCI_PRODUCT_VIATECH_VT3043) 1799 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 1800 1801 return true; 1802 } 1803