1 /* $NetBSD: if_vr.c,v 1.110 2012/02/02 19:43:05 tls Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1997, 1998 35 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Bill Paul. 48 * 4. Neither the name of the author nor the names of any co-contributors 49 * may be used to endorse or promote products derived from this software 50 * without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 56 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 57 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 58 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 59 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 60 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 61 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 62 * THE POSSIBILITY OF SUCH DAMAGE. 63 * 64 * $FreeBSD: if_vr.c,v 1.7 1999/01/10 18:51:49 wpaul Exp $ 65 */ 66 67 /* 68 * VIA Rhine fast ethernet PCI NIC driver 69 * 70 * Supports various network adapters based on the VIA Rhine 71 * and Rhine II PCI controllers, including the D-Link DFE530TX. 72 * Datasheets are available at http://www.via.com.tw. 73 * 74 * Written by Bill Paul <wpaul@ctr.columbia.edu> 75 * Electrical Engineering Department 76 * Columbia University, New York City 77 */ 78 79 /* 80 * The VIA Rhine controllers are similar in some respects to the 81 * the DEC tulip chips, except less complicated. The controller 82 * uses an MII bus and an external physical layer interface. The 83 * receiver has a one entry perfect filter and a 64-bit hash table 84 * multicast filter. Transmit and receive descriptors are similar 85 * to the tulip. 86 * 87 * The Rhine has a serious flaw in its transmit DMA mechanism: 88 * transmit buffers must be longword aligned. Unfortunately, 89 * the kernel doesn't guarantee that mbufs will be filled in starting 90 * at longword boundaries, so we have to do a buffer copy before 91 * transmission. 92 * 93 * Apparently, the receive DMA mechanism also has the same flaw. This 94 * means that on systems with struct alignment requirements, incoming 95 * frames must be copied to a new buffer which shifts the data forward 96 * 2 bytes so that the payload is aligned on a 4-byte boundary. 97 */ 98 99 #include <sys/cdefs.h> 100 __KERNEL_RCSID(0, "$NetBSD: if_vr.c,v 1.110 2012/02/02 19:43:05 tls Exp $"); 101 102 103 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/callout.h> 107 #include <sys/sockio.h> 108 #include <sys/mbuf.h> 109 #include <sys/malloc.h> 110 #include <sys/kernel.h> 111 #include <sys/socket.h> 112 #include <sys/device.h> 113 114 #include <sys/rnd.h> 115 116 #include <net/if.h> 117 #include <net/if_arp.h> 118 #include <net/if_dl.h> 119 #include <net/if_media.h> 120 #include <net/if_ether.h> 121 122 #include <net/bpf.h> 123 124 #include <sys/bus.h> 125 #include <sys/intr.h> 126 #include <machine/endian.h> 127 128 #include <dev/mii/mii.h> 129 #include <dev/mii/miivar.h> 130 #include <dev/mii/mii_bitbang.h> 131 132 #include <dev/pci/pcireg.h> 133 #include <dev/pci/pcivar.h> 134 #include <dev/pci/pcidevs.h> 135 136 #include <dev/pci/if_vrreg.h> 137 138 #define VR_USEIOSPACE 139 140 /* 141 * Various supported device vendors/types and their names. 142 */ 143 static const struct vr_type { 144 pci_vendor_id_t vr_vid; 145 pci_product_id_t vr_did; 146 } vr_devs[] = { 147 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT3043 }, 148 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6102 }, 149 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6105 }, 150 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6105M }, 151 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT86C100A } 152 }; 153 154 /* 155 * Transmit descriptor list size. 156 */ 157 #define VR_NTXDESC 64 158 #define VR_NTXDESC_MASK (VR_NTXDESC - 1) 159 #define VR_NEXTTX(x) (((x) + 1) & VR_NTXDESC_MASK) 160 161 /* 162 * Receive descriptor list size. 163 */ 164 #define VR_NRXDESC 64 165 #define VR_NRXDESC_MASK (VR_NRXDESC - 1) 166 #define VR_NEXTRX(x) (((x) + 1) & VR_NRXDESC_MASK) 167 168 /* 169 * Control data structres that are DMA'd to the Rhine chip. We allocate 170 * them in a single clump that maps to a single DMA segment to make several 171 * things easier. 172 * 173 * Note that since we always copy outgoing packets to aligned transmit 174 * buffers, we can reduce the transmit descriptors to one per packet. 175 */ 176 struct vr_control_data { 177 struct vr_desc vr_txdescs[VR_NTXDESC]; 178 struct vr_desc vr_rxdescs[VR_NRXDESC]; 179 }; 180 181 #define VR_CDOFF(x) offsetof(struct vr_control_data, x) 182 #define VR_CDTXOFF(x) VR_CDOFF(vr_txdescs[(x)]) 183 #define VR_CDRXOFF(x) VR_CDOFF(vr_rxdescs[(x)]) 184 185 /* 186 * Software state of transmit and receive descriptors. 187 */ 188 struct vr_descsoft { 189 struct mbuf *ds_mbuf; /* head of mbuf chain */ 190 bus_dmamap_t ds_dmamap; /* our DMA map */ 191 }; 192 193 struct vr_softc { 194 device_t vr_dev; 195 void *vr_ih; /* interrupt cookie */ 196 bus_space_tag_t vr_bst; /* bus space tag */ 197 bus_space_handle_t vr_bsh; /* bus space handle */ 198 bus_dma_tag_t vr_dmat; /* bus DMA tag */ 199 pci_chipset_tag_t vr_pc; /* PCI chipset info */ 200 pcitag_t vr_tag; /* PCI tag */ 201 struct ethercom vr_ec; /* Ethernet common info */ 202 uint8_t vr_enaddr[ETHER_ADDR_LEN]; 203 struct mii_data vr_mii; /* MII/media info */ 204 205 pcireg_t vr_id; /* vendor/product ID */ 206 uint8_t vr_revid; /* Rhine chip revision */ 207 208 callout_t vr_tick_ch; /* tick callout */ 209 210 bus_dmamap_t vr_cddmamap; /* control data DMA map */ 211 #define vr_cddma vr_cddmamap->dm_segs[0].ds_addr 212 213 /* 214 * Software state for transmit and receive descriptors. 215 */ 216 struct vr_descsoft vr_txsoft[VR_NTXDESC]; 217 struct vr_descsoft vr_rxsoft[VR_NRXDESC]; 218 219 /* 220 * Control data structures. 221 */ 222 struct vr_control_data *vr_control_data; 223 224 int vr_txpending; /* number of TX requests pending */ 225 int vr_txdirty; /* first dirty TX descriptor */ 226 int vr_txlast; /* last used TX descriptor */ 227 228 int vr_rxptr; /* next ready RX descriptor */ 229 230 uint32_t vr_save_iobase; 231 uint32_t vr_save_membase; 232 uint32_t vr_save_irq; 233 234 krndsource_t rnd_source; /* random source */ 235 }; 236 237 #define VR_CDTXADDR(sc, x) ((sc)->vr_cddma + VR_CDTXOFF((x))) 238 #define VR_CDRXADDR(sc, x) ((sc)->vr_cddma + VR_CDRXOFF((x))) 239 240 #define VR_CDTX(sc, x) (&(sc)->vr_control_data->vr_txdescs[(x)]) 241 #define VR_CDRX(sc, x) (&(sc)->vr_control_data->vr_rxdescs[(x)]) 242 243 #define VR_DSTX(sc, x) (&(sc)->vr_txsoft[(x)]) 244 #define VR_DSRX(sc, x) (&(sc)->vr_rxsoft[(x)]) 245 246 #define VR_CDTXSYNC(sc, x, ops) \ 247 bus_dmamap_sync((sc)->vr_dmat, (sc)->vr_cddmamap, \ 248 VR_CDTXOFF((x)), sizeof(struct vr_desc), (ops)) 249 250 #define VR_CDRXSYNC(sc, x, ops) \ 251 bus_dmamap_sync((sc)->vr_dmat, (sc)->vr_cddmamap, \ 252 VR_CDRXOFF((x)), sizeof(struct vr_desc), (ops)) 253 254 /* 255 * Note we rely on MCLBYTES being a power of two below. 256 */ 257 #define VR_INIT_RXDESC(sc, i) \ 258 do { \ 259 struct vr_desc *__d = VR_CDRX((sc), (i)); \ 260 struct vr_descsoft *__ds = VR_DSRX((sc), (i)); \ 261 \ 262 __d->vr_next = htole32(VR_CDRXADDR((sc), VR_NEXTRX((i)))); \ 263 __d->vr_data = htole32(__ds->ds_dmamap->dm_segs[0].ds_addr); \ 264 __d->vr_ctl = htole32(VR_RXCTL_CHAIN | VR_RXCTL_RX_INTR | \ 265 ((MCLBYTES - 1) & VR_RXCTL_BUFLEN)); \ 266 __d->vr_status = htole32(VR_RXSTAT_FIRSTFRAG | \ 267 VR_RXSTAT_LASTFRAG | VR_RXSTAT_OWN); \ 268 VR_CDRXSYNC((sc), (i), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 269 } while (/* CONSTCOND */ 0) 270 271 /* 272 * register space access macros 273 */ 274 #define CSR_WRITE_4(sc, reg, val) \ 275 bus_space_write_4(sc->vr_bst, sc->vr_bsh, reg, val) 276 #define CSR_WRITE_2(sc, reg, val) \ 277 bus_space_write_2(sc->vr_bst, sc->vr_bsh, reg, val) 278 #define CSR_WRITE_1(sc, reg, val) \ 279 bus_space_write_1(sc->vr_bst, sc->vr_bsh, reg, val) 280 281 #define CSR_READ_4(sc, reg) \ 282 bus_space_read_4(sc->vr_bst, sc->vr_bsh, reg) 283 #define CSR_READ_2(sc, reg) \ 284 bus_space_read_2(sc->vr_bst, sc->vr_bsh, reg) 285 #define CSR_READ_1(sc, reg) \ 286 bus_space_read_1(sc->vr_bst, sc->vr_bsh, reg) 287 288 #define VR_TIMEOUT 1000 289 290 static int vr_add_rxbuf(struct vr_softc *, int); 291 292 static void vr_rxeof(struct vr_softc *); 293 static void vr_rxeoc(struct vr_softc *); 294 static void vr_txeof(struct vr_softc *); 295 static int vr_intr(void *); 296 static void vr_start(struct ifnet *); 297 static int vr_ioctl(struct ifnet *, u_long, void *); 298 static int vr_init(struct ifnet *); 299 static void vr_stop(struct ifnet *, int); 300 static void vr_rxdrain(struct vr_softc *); 301 static void vr_watchdog(struct ifnet *); 302 static void vr_tick(void *); 303 304 static int vr_mii_readreg(device_t, int, int); 305 static void vr_mii_writereg(device_t, int, int, int); 306 static void vr_mii_statchg(device_t); 307 308 static void vr_setmulti(struct vr_softc *); 309 static void vr_reset(struct vr_softc *); 310 static int vr_restore_state(pci_chipset_tag_t, pcitag_t, device_t, 311 pcireg_t); 312 static bool vr_resume(device_t, const pmf_qual_t *); 313 314 int vr_copy_small = 0; 315 316 #define VR_SETBIT(sc, reg, x) \ 317 CSR_WRITE_1(sc, reg, \ 318 CSR_READ_1(sc, reg) | (x)) 319 320 #define VR_CLRBIT(sc, reg, x) \ 321 CSR_WRITE_1(sc, reg, \ 322 CSR_READ_1(sc, reg) & ~(x)) 323 324 #define VR_SETBIT16(sc, reg, x) \ 325 CSR_WRITE_2(sc, reg, \ 326 CSR_READ_2(sc, reg) | (x)) 327 328 #define VR_CLRBIT16(sc, reg, x) \ 329 CSR_WRITE_2(sc, reg, \ 330 CSR_READ_2(sc, reg) & ~(x)) 331 332 #define VR_SETBIT32(sc, reg, x) \ 333 CSR_WRITE_4(sc, reg, \ 334 CSR_READ_4(sc, reg) | (x)) 335 336 #define VR_CLRBIT32(sc, reg, x) \ 337 CSR_WRITE_4(sc, reg, \ 338 CSR_READ_4(sc, reg) & ~(x)) 339 340 /* 341 * MII bit-bang glue. 342 */ 343 static uint32_t vr_mii_bitbang_read(device_t); 344 static void vr_mii_bitbang_write(device_t, uint32_t); 345 346 static const struct mii_bitbang_ops vr_mii_bitbang_ops = { 347 vr_mii_bitbang_read, 348 vr_mii_bitbang_write, 349 { 350 VR_MIICMD_DATAOUT, /* MII_BIT_MDO */ 351 VR_MIICMD_DATAIN, /* MII_BIT_MDI */ 352 VR_MIICMD_CLK, /* MII_BIT_MDC */ 353 VR_MIICMD_DIR, /* MII_BIT_DIR_HOST_PHY */ 354 0, /* MII_BIT_DIR_PHY_HOST */ 355 } 356 }; 357 358 static uint32_t 359 vr_mii_bitbang_read(device_t self) 360 { 361 struct vr_softc *sc = device_private(self); 362 363 return (CSR_READ_1(sc, VR_MIICMD)); 364 } 365 366 static void 367 vr_mii_bitbang_write(device_t self, uint32_t val) 368 { 369 struct vr_softc *sc = device_private(self); 370 371 CSR_WRITE_1(sc, VR_MIICMD, (val & 0xff) | VR_MIICMD_DIRECTPGM); 372 } 373 374 /* 375 * Read an PHY register through the MII. 376 */ 377 static int 378 vr_mii_readreg(device_t self, int phy, int reg) 379 { 380 struct vr_softc *sc = device_private(self); 381 382 CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 383 return (mii_bitbang_readreg(self, &vr_mii_bitbang_ops, phy, reg)); 384 } 385 386 /* 387 * Write to a PHY register through the MII. 388 */ 389 static void 390 vr_mii_writereg(device_t self, int phy, int reg, int val) 391 { 392 struct vr_softc *sc = device_private(self); 393 394 CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 395 mii_bitbang_writereg(self, &vr_mii_bitbang_ops, phy, reg, val); 396 } 397 398 static void 399 vr_mii_statchg(device_t self) 400 { 401 struct vr_softc *sc = device_private(self); 402 403 /* 404 * In order to fiddle with the 'full-duplex' bit in the netconfig 405 * register, we first have to put the transmit and/or receive logic 406 * in the idle state. 407 */ 408 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 409 410 if (sc->vr_mii.mii_media_active & IFM_FDX) 411 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 412 else 413 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 414 415 if (sc->vr_ec.ec_if.if_flags & IFF_RUNNING) 416 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 417 } 418 419 #define vr_calchash(addr) \ 420 (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26) 421 422 /* 423 * Program the 64-bit multicast hash filter. 424 */ 425 static void 426 vr_setmulti(struct vr_softc *sc) 427 { 428 struct ifnet *ifp; 429 int h = 0; 430 uint32_t hashes[2] = { 0, 0 }; 431 struct ether_multistep step; 432 struct ether_multi *enm; 433 int mcnt = 0; 434 uint8_t rxfilt; 435 436 ifp = &sc->vr_ec.ec_if; 437 438 rxfilt = CSR_READ_1(sc, VR_RXCFG); 439 440 if (ifp->if_flags & IFF_PROMISC) { 441 allmulti: 442 ifp->if_flags |= IFF_ALLMULTI; 443 rxfilt |= VR_RXCFG_RX_MULTI; 444 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 445 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 446 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 447 return; 448 } 449 450 /* first, zot all the existing hash bits */ 451 CSR_WRITE_4(sc, VR_MAR0, 0); 452 CSR_WRITE_4(sc, VR_MAR1, 0); 453 454 /* now program new ones */ 455 ETHER_FIRST_MULTI(step, &sc->vr_ec, enm); 456 while (enm != NULL) { 457 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 458 ETHER_ADDR_LEN) != 0) 459 goto allmulti; 460 461 h = vr_calchash(enm->enm_addrlo); 462 463 if (h < 32) 464 hashes[0] |= (1 << h); 465 else 466 hashes[1] |= (1 << (h - 32)); 467 ETHER_NEXT_MULTI(step, enm); 468 mcnt++; 469 } 470 471 ifp->if_flags &= ~IFF_ALLMULTI; 472 473 if (mcnt) 474 rxfilt |= VR_RXCFG_RX_MULTI; 475 else 476 rxfilt &= ~VR_RXCFG_RX_MULTI; 477 478 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 479 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 480 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 481 } 482 483 static void 484 vr_reset(struct vr_softc *sc) 485 { 486 int i; 487 488 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 489 490 for (i = 0; i < VR_TIMEOUT; i++) { 491 DELAY(10); 492 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 493 break; 494 } 495 if (i == VR_TIMEOUT) { 496 if (sc->vr_revid < REV_ID_VT3065_A) { 497 printf("%s: reset never completed!\n", 498 device_xname(sc->vr_dev)); 499 } else { 500 /* Use newer force reset command */ 501 printf("%s: using force reset command.\n", 502 device_xname(sc->vr_dev)); 503 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 504 } 505 } 506 507 /* Wait a little while for the chip to get its brains in order. */ 508 DELAY(1000); 509 } 510 511 /* 512 * Initialize an RX descriptor and attach an MBUF cluster. 513 * Note: the length fields are only 11 bits wide, which means the 514 * largest size we can specify is 2047. This is important because 515 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 516 * overflow the field and make a mess. 517 */ 518 static int 519 vr_add_rxbuf(struct vr_softc *sc, int i) 520 { 521 struct vr_descsoft *ds = VR_DSRX(sc, i); 522 struct mbuf *m_new; 523 int error; 524 525 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 526 if (m_new == NULL) 527 return (ENOBUFS); 528 529 MCLGET(m_new, M_DONTWAIT); 530 if ((m_new->m_flags & M_EXT) == 0) { 531 m_freem(m_new); 532 return (ENOBUFS); 533 } 534 535 if (ds->ds_mbuf != NULL) 536 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 537 538 ds->ds_mbuf = m_new; 539 540 error = bus_dmamap_load(sc->vr_dmat, ds->ds_dmamap, 541 m_new->m_ext.ext_buf, m_new->m_ext.ext_size, NULL, 542 BUS_DMA_READ|BUS_DMA_NOWAIT); 543 if (error) { 544 aprint_error_dev(sc->vr_dev, "unable to load rx DMA map %d, error = %d\n", 545 i, error); 546 panic("vr_add_rxbuf"); /* XXX */ 547 } 548 549 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 550 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 551 552 VR_INIT_RXDESC(sc, i); 553 554 return (0); 555 } 556 557 /* 558 * A frame has been uploaded: pass the resulting mbuf chain up to 559 * the higher level protocols. 560 */ 561 static void 562 vr_rxeof(struct vr_softc *sc) 563 { 564 struct mbuf *m; 565 struct ifnet *ifp; 566 struct vr_desc *d; 567 struct vr_descsoft *ds; 568 int i, total_len; 569 uint32_t rxstat; 570 571 ifp = &sc->vr_ec.ec_if; 572 573 for (i = sc->vr_rxptr;; i = VR_NEXTRX(i)) { 574 d = VR_CDRX(sc, i); 575 ds = VR_DSRX(sc, i); 576 577 VR_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 578 579 rxstat = le32toh(d->vr_status); 580 581 if (rxstat & VR_RXSTAT_OWN) { 582 /* 583 * We have processed all of the receive buffers. 584 */ 585 break; 586 } 587 588 /* 589 * If an error occurs, update stats, clear the 590 * status word and leave the mbuf cluster in place: 591 * it should simply get re-used next time this descriptor 592 * comes up in the ring. 593 */ 594 if (rxstat & VR_RXSTAT_RXERR) { 595 const char *errstr; 596 597 ifp->if_ierrors++; 598 switch (rxstat & 0x000000FF) { 599 case VR_RXSTAT_CRCERR: 600 errstr = "crc error"; 601 break; 602 case VR_RXSTAT_FRAMEALIGNERR: 603 errstr = "frame alignment error"; 604 break; 605 case VR_RXSTAT_FIFOOFLOW: 606 errstr = "FIFO overflow"; 607 break; 608 case VR_RXSTAT_GIANT: 609 errstr = "received giant packet"; 610 break; 611 case VR_RXSTAT_RUNT: 612 errstr = "received runt packet"; 613 break; 614 case VR_RXSTAT_BUSERR: 615 errstr = "system bus error"; 616 break; 617 case VR_RXSTAT_BUFFERR: 618 errstr = "rx buffer error"; 619 break; 620 default: 621 errstr = "unknown rx error"; 622 break; 623 } 624 printf("%s: receive error: %s\n", device_xname(sc->vr_dev), 625 errstr); 626 627 VR_INIT_RXDESC(sc, i); 628 629 continue; 630 } else if (!(rxstat & VR_RXSTAT_FIRSTFRAG) || 631 !(rxstat & VR_RXSTAT_LASTFRAG)) { 632 /* 633 * This driver expects to receive whole packets every 634 * time. In case we receive a fragment that is not 635 * a complete packet, we discard it. 636 */ 637 ifp->if_ierrors++; 638 639 printf("%s: receive error: incomplete frame; " 640 "size = %d, status = 0x%x\n", 641 device_xname(sc->vr_dev), 642 VR_RXBYTES(le32toh(d->vr_status)), rxstat); 643 644 VR_INIT_RXDESC(sc, i); 645 646 continue; 647 } 648 649 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 650 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 651 652 /* No errors; receive the packet. */ 653 total_len = VR_RXBYTES(le32toh(d->vr_status)); 654 #ifdef DIAGNOSTIC 655 if (total_len == 0) { 656 /* 657 * If we receive a zero-length packet, we probably 658 * missed to handle an error condition above. 659 * Discard it to avoid a later crash. 660 */ 661 ifp->if_ierrors++; 662 663 printf("%s: receive error: zero-length packet; " 664 "status = 0x%x\n", 665 device_xname(sc->vr_dev), rxstat); 666 667 VR_INIT_RXDESC(sc, i); 668 669 continue; 670 } 671 #endif 672 673 /* 674 * The Rhine chip includes the CRC with every packet. 675 * Trim it off here. 676 */ 677 total_len -= ETHER_CRC_LEN; 678 679 #ifdef __NO_STRICT_ALIGNMENT 680 /* 681 * If the packet is small enough to fit in a 682 * single header mbuf, allocate one and copy 683 * the data into it. This greatly reduces 684 * memory consumption when we receive lots 685 * of small packets. 686 * 687 * Otherwise, we add a new buffer to the receive 688 * chain. If this fails, we drop the packet and 689 * recycle the old buffer. 690 */ 691 if (vr_copy_small != 0 && total_len <= MHLEN) { 692 MGETHDR(m, M_DONTWAIT, MT_DATA); 693 if (m == NULL) 694 goto dropit; 695 memcpy(mtod(m, void *), 696 mtod(ds->ds_mbuf, void *), total_len); 697 VR_INIT_RXDESC(sc, i); 698 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 699 ds->ds_dmamap->dm_mapsize, 700 BUS_DMASYNC_PREREAD); 701 } else { 702 m = ds->ds_mbuf; 703 if (vr_add_rxbuf(sc, i) == ENOBUFS) { 704 dropit: 705 ifp->if_ierrors++; 706 VR_INIT_RXDESC(sc, i); 707 bus_dmamap_sync(sc->vr_dmat, 708 ds->ds_dmamap, 0, 709 ds->ds_dmamap->dm_mapsize, 710 BUS_DMASYNC_PREREAD); 711 continue; 712 } 713 } 714 #else 715 /* 716 * The Rhine's packet buffers must be 4-byte aligned. 717 * But this means that the data after the Ethernet header 718 * is misaligned. We must allocate a new buffer and 719 * copy the data, shifted forward 2 bytes. 720 */ 721 MGETHDR(m, M_DONTWAIT, MT_DATA); 722 if (m == NULL) { 723 dropit: 724 ifp->if_ierrors++; 725 VR_INIT_RXDESC(sc, i); 726 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 727 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 728 continue; 729 } 730 if (total_len > (MHLEN - 2)) { 731 MCLGET(m, M_DONTWAIT); 732 if ((m->m_flags & M_EXT) == 0) { 733 m_freem(m); 734 goto dropit; 735 } 736 } 737 m->m_data += 2; 738 739 /* 740 * Note that we use clusters for incoming frames, so the 741 * buffer is virtually contiguous. 742 */ 743 memcpy(mtod(m, void *), mtod(ds->ds_mbuf, void *), 744 total_len); 745 746 /* Allow the receive descriptor to continue using its mbuf. */ 747 VR_INIT_RXDESC(sc, i); 748 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 749 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 750 #endif /* __NO_STRICT_ALIGNMENT */ 751 752 ifp->if_ipackets++; 753 m->m_pkthdr.rcvif = ifp; 754 m->m_pkthdr.len = m->m_len = total_len; 755 /* 756 * Handle BPF listeners. Let the BPF user see the packet, but 757 * don't pass it up to the ether_input() layer unless it's 758 * a broadcast packet, multicast packet, matches our ethernet 759 * address or the interface is in promiscuous mode. 760 */ 761 bpf_mtap(ifp, m); 762 /* Pass it on. */ 763 (*ifp->if_input)(ifp, m); 764 } 765 766 /* Update the receive pointer. */ 767 sc->vr_rxptr = i; 768 } 769 770 void 771 vr_rxeoc(struct vr_softc *sc) 772 { 773 struct ifnet *ifp; 774 int i; 775 776 ifp = &sc->vr_ec.ec_if; 777 778 ifp->if_ierrors++; 779 780 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 781 for (i = 0; i < VR_TIMEOUT; i++) { 782 DELAY(10); 783 if ((CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON) == 0) 784 break; 785 } 786 if (i == VR_TIMEOUT) { 787 /* XXX need reset? */ 788 printf("%s: RX shutdown never complete\n", 789 device_xname(sc->vr_dev)); 790 } 791 792 vr_rxeof(sc); 793 794 CSR_WRITE_4(sc, VR_RXADDR, VR_CDRXADDR(sc, sc->vr_rxptr)); 795 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 796 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 797 } 798 799 /* 800 * A frame was downloaded to the chip. It's safe for us to clean up 801 * the list buffers. 802 */ 803 static void 804 vr_txeof(struct vr_softc *sc) 805 { 806 struct ifnet *ifp = &sc->vr_ec.ec_if; 807 struct vr_desc *d; 808 struct vr_descsoft *ds; 809 uint32_t txstat; 810 int i, j; 811 812 ifp->if_flags &= ~IFF_OACTIVE; 813 814 /* 815 * Go through our tx list and free mbufs for those 816 * frames that have been transmitted. 817 */ 818 for (i = sc->vr_txdirty; sc->vr_txpending != 0; 819 i = VR_NEXTTX(i), sc->vr_txpending--) { 820 d = VR_CDTX(sc, i); 821 ds = VR_DSTX(sc, i); 822 823 VR_CDTXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 824 825 txstat = le32toh(d->vr_status); 826 827 if (txstat & (VR_TXSTAT_ABRT | VR_TXSTAT_UDF)) { 828 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 829 for (j = 0; j < VR_TIMEOUT; j++) { 830 DELAY(10); 831 if ((CSR_READ_2(sc, VR_COMMAND) & 832 VR_CMD_TX_ON) == 0) 833 break; 834 } 835 if (j == VR_TIMEOUT) { 836 /* XXX need reset? */ 837 printf("%s: TX shutdown never complete\n", 838 device_xname(sc->vr_dev)); 839 } 840 d->vr_status = htole32(VR_TXSTAT_OWN); 841 CSR_WRITE_4(sc, VR_TXADDR, VR_CDTXADDR(sc, i)); 842 break; 843 } 844 845 if (txstat & VR_TXSTAT_OWN) 846 break; 847 848 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 849 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 850 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 851 m_freem(ds->ds_mbuf); 852 ds->ds_mbuf = NULL; 853 854 if (txstat & VR_TXSTAT_ERRSUM) { 855 ifp->if_oerrors++; 856 if (txstat & VR_TXSTAT_DEFER) 857 ifp->if_collisions++; 858 if (txstat & VR_TXSTAT_LATECOLL) 859 ifp->if_collisions++; 860 } 861 862 ifp->if_collisions += (txstat & VR_TXSTAT_COLLCNT) >> 3; 863 ifp->if_opackets++; 864 } 865 866 /* Update the dirty transmit buffer pointer. */ 867 sc->vr_txdirty = i; 868 869 /* 870 * Cancel the watchdog timer if there are no pending 871 * transmissions. 872 */ 873 if (sc->vr_txpending == 0) 874 ifp->if_timer = 0; 875 } 876 877 static int 878 vr_intr(void *arg) 879 { 880 struct vr_softc *sc; 881 struct ifnet *ifp; 882 uint16_t status; 883 int handled = 0, dotx = 0; 884 885 sc = arg; 886 ifp = &sc->vr_ec.ec_if; 887 888 /* Suppress unwanted interrupts. */ 889 if ((ifp->if_flags & IFF_UP) == 0) { 890 vr_stop(ifp, 1); 891 return (0); 892 } 893 894 /* Disable interrupts. */ 895 CSR_WRITE_2(sc, VR_IMR, 0x0000); 896 897 for (;;) { 898 status = CSR_READ_2(sc, VR_ISR); 899 if (status) 900 CSR_WRITE_2(sc, VR_ISR, status); 901 902 if ((status & VR_INTRS) == 0) 903 break; 904 905 handled = 1; 906 907 rnd_add_uint32(&sc->rnd_source, status); 908 909 if (status & VR_ISR_RX_OK) 910 vr_rxeof(sc); 911 912 if (status & VR_ISR_RX_DROPPED) { 913 printf("%s: rx packet lost\n", device_xname(sc->vr_dev)); 914 ifp->if_ierrors++; 915 } 916 917 if (status & 918 (VR_ISR_RX_ERR | VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW)) 919 vr_rxeoc(sc); 920 921 922 if (status & (VR_ISR_BUSERR | VR_ISR_TX_UNDERRUN)) { 923 if (status & VR_ISR_BUSERR) 924 printf("%s: PCI bus error\n", 925 device_xname(sc->vr_dev)); 926 if (status & VR_ISR_TX_UNDERRUN) 927 printf("%s: transmit underrun\n", 928 device_xname(sc->vr_dev)); 929 /* vr_init() calls vr_start() */ 930 dotx = 0; 931 (void)vr_init(ifp); 932 933 } 934 935 if (status & VR_ISR_TX_OK) { 936 dotx = 1; 937 vr_txeof(sc); 938 } 939 940 if (status & 941 (VR_ISR_TX_ABRT | VR_ISR_TX_ABRT2 | VR_ISR_TX_UDFI)) { 942 if (status & (VR_ISR_TX_ABRT | VR_ISR_TX_ABRT2)) 943 printf("%s: transmit aborted\n", 944 device_xname(sc->vr_dev)); 945 if (status & VR_ISR_TX_UDFI) 946 printf("%s: transmit underflow\n", 947 device_xname(sc->vr_dev)); 948 ifp->if_oerrors++; 949 dotx = 1; 950 vr_txeof(sc); 951 if (sc->vr_txpending) { 952 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 953 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 954 } 955 } 956 } 957 958 /* Re-enable interrupts. */ 959 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 960 961 if (dotx) 962 vr_start(ifp); 963 964 return (handled); 965 } 966 967 /* 968 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 969 * to the mbuf data regions directly in the transmit lists. We also save a 970 * copy of the pointers since the transmit list fragment pointers are 971 * physical addresses. 972 */ 973 static void 974 vr_start(struct ifnet *ifp) 975 { 976 struct vr_softc *sc = ifp->if_softc; 977 struct mbuf *m0, *m; 978 struct vr_desc *d; 979 struct vr_descsoft *ds; 980 int error, firsttx, nexttx, opending; 981 982 /* 983 * Remember the previous txpending and the first transmit 984 * descriptor we use. 985 */ 986 opending = sc->vr_txpending; 987 firsttx = VR_NEXTTX(sc->vr_txlast); 988 989 /* 990 * Loop through the send queue, setting up transmit descriptors 991 * until we drain the queue, or use up all available transmit 992 * descriptors. 993 */ 994 while (sc->vr_txpending < VR_NTXDESC) { 995 /* 996 * Grab a packet off the queue. 997 */ 998 IFQ_POLL(&ifp->if_snd, m0); 999 if (m0 == NULL) 1000 break; 1001 m = NULL; 1002 1003 /* 1004 * Get the next available transmit descriptor. 1005 */ 1006 nexttx = VR_NEXTTX(sc->vr_txlast); 1007 d = VR_CDTX(sc, nexttx); 1008 ds = VR_DSTX(sc, nexttx); 1009 1010 /* 1011 * Load the DMA map. If this fails, the packet didn't 1012 * fit in one DMA segment, and we need to copy. Note, 1013 * the packet must also be aligned. 1014 * if the packet is too small, copy it too, so we're sure 1015 * we have enough room for the pad buffer. 1016 */ 1017 if ((mtod(m0, uintptr_t) & 3) != 0 || 1018 m0->m_pkthdr.len < VR_MIN_FRAMELEN || 1019 bus_dmamap_load_mbuf(sc->vr_dmat, ds->ds_dmamap, m0, 1020 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1021 MGETHDR(m, M_DONTWAIT, MT_DATA); 1022 if (m == NULL) { 1023 printf("%s: unable to allocate Tx mbuf\n", 1024 device_xname(sc->vr_dev)); 1025 break; 1026 } 1027 if (m0->m_pkthdr.len > MHLEN) { 1028 MCLGET(m, M_DONTWAIT); 1029 if ((m->m_flags & M_EXT) == 0) { 1030 printf("%s: unable to allocate Tx " 1031 "cluster\n", device_xname(sc->vr_dev)); 1032 m_freem(m); 1033 break; 1034 } 1035 } 1036 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1037 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1038 /* 1039 * The Rhine doesn't auto-pad, so we have to do this 1040 * ourselves. 1041 */ 1042 if (m0->m_pkthdr.len < VR_MIN_FRAMELEN) { 1043 memset(mtod(m, char *) + m0->m_pkthdr.len, 1044 0, VR_MIN_FRAMELEN - m0->m_pkthdr.len); 1045 m->m_pkthdr.len = m->m_len = VR_MIN_FRAMELEN; 1046 } 1047 error = bus_dmamap_load_mbuf(sc->vr_dmat, 1048 ds->ds_dmamap, m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1049 if (error) { 1050 m_freem(m); 1051 printf("%s: unable to load Tx buffer, " 1052 "error = %d\n", device_xname(sc->vr_dev), error); 1053 break; 1054 } 1055 } 1056 1057 IFQ_DEQUEUE(&ifp->if_snd, m0); 1058 if (m != NULL) { 1059 m_freem(m0); 1060 m0 = m; 1061 } 1062 1063 /* Sync the DMA map. */ 1064 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 1065 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1066 1067 /* 1068 * Store a pointer to the packet so we can free it later. 1069 */ 1070 ds->ds_mbuf = m0; 1071 1072 /* 1073 * If there's a BPF listener, bounce a copy of this frame 1074 * to him. 1075 */ 1076 bpf_mtap(ifp, m0); 1077 1078 /* 1079 * Fill in the transmit descriptor. 1080 */ 1081 d->vr_data = htole32(ds->ds_dmamap->dm_segs[0].ds_addr); 1082 d->vr_ctl = htole32(m0->m_pkthdr.len); 1083 d->vr_ctl |= htole32(VR_TXCTL_FIRSTFRAG | VR_TXCTL_LASTFRAG); 1084 1085 /* 1086 * If this is the first descriptor we're enqueuing, 1087 * don't give it to the Rhine yet. That could cause 1088 * a race condition. We'll do it below. 1089 */ 1090 if (nexttx == firsttx) 1091 d->vr_status = 0; 1092 else 1093 d->vr_status = htole32(VR_TXSTAT_OWN); 1094 1095 VR_CDTXSYNC(sc, nexttx, 1096 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1097 1098 /* Advance the tx pointer. */ 1099 sc->vr_txpending++; 1100 sc->vr_txlast = nexttx; 1101 } 1102 1103 if (sc->vr_txpending == VR_NTXDESC) { 1104 /* No more slots left; notify upper layer. */ 1105 ifp->if_flags |= IFF_OACTIVE; 1106 } 1107 1108 if (sc->vr_txpending != opending) { 1109 /* 1110 * We enqueued packets. If the transmitter was idle, 1111 * reset the txdirty pointer. 1112 */ 1113 if (opending == 0) 1114 sc->vr_txdirty = firsttx; 1115 1116 /* 1117 * Cause a transmit interrupt to happen on the 1118 * last packet we enqueued. 1119 */ 1120 VR_CDTX(sc, sc->vr_txlast)->vr_ctl |= htole32(VR_TXCTL_FINT); 1121 VR_CDTXSYNC(sc, sc->vr_txlast, 1122 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1123 1124 /* 1125 * The entire packet chain is set up. Give the 1126 * first descriptor to the Rhine now. 1127 */ 1128 VR_CDTX(sc, firsttx)->vr_status = htole32(VR_TXSTAT_OWN); 1129 VR_CDTXSYNC(sc, firsttx, 1130 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1131 1132 /* Start the transmitter. */ 1133 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1134 1135 /* Set the watchdog timer in case the chip flakes out. */ 1136 ifp->if_timer = 5; 1137 } 1138 } 1139 1140 /* 1141 * Initialize the interface. Must be called at splnet. 1142 */ 1143 static int 1144 vr_init(struct ifnet *ifp) 1145 { 1146 struct vr_softc *sc = ifp->if_softc; 1147 struct vr_desc *d; 1148 struct vr_descsoft *ds; 1149 int i, error = 0; 1150 1151 /* Cancel pending I/O. */ 1152 vr_stop(ifp, 0); 1153 1154 /* Reset the Rhine to a known state. */ 1155 vr_reset(sc); 1156 1157 /* set DMA length in BCR0 and BCR1 */ 1158 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1159 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1160 1161 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1162 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTH_128BYTES); 1163 1164 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1165 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTH_STORENFWD); 1166 1167 /* set DMA threshold length in RXCFG and TXCFG */ 1168 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1169 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1170 1171 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1172 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1173 1174 /* 1175 * Initialize the transmit descriptor ring. txlast is initialized 1176 * to the end of the list so that it will wrap around to the first 1177 * descriptor when the first packet is transmitted. 1178 */ 1179 for (i = 0; i < VR_NTXDESC; i++) { 1180 d = VR_CDTX(sc, i); 1181 memset(d, 0, sizeof(struct vr_desc)); 1182 d->vr_next = htole32(VR_CDTXADDR(sc, VR_NEXTTX(i))); 1183 VR_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1184 } 1185 sc->vr_txpending = 0; 1186 sc->vr_txdirty = 0; 1187 sc->vr_txlast = VR_NTXDESC - 1; 1188 1189 /* 1190 * Initialize the receive descriptor ring. 1191 */ 1192 for (i = 0; i < VR_NRXDESC; i++) { 1193 ds = VR_DSRX(sc, i); 1194 if (ds->ds_mbuf == NULL) { 1195 if ((error = vr_add_rxbuf(sc, i)) != 0) { 1196 printf("%s: unable to allocate or map rx " 1197 "buffer %d, error = %d\n", 1198 device_xname(sc->vr_dev), i, error); 1199 /* 1200 * XXX Should attempt to run with fewer receive 1201 * XXX buffers instead of just failing. 1202 */ 1203 vr_rxdrain(sc); 1204 goto out; 1205 } 1206 } else 1207 VR_INIT_RXDESC(sc, i); 1208 } 1209 sc->vr_rxptr = 0; 1210 1211 /* If we want promiscuous mode, set the allframes bit. */ 1212 if (ifp->if_flags & IFF_PROMISC) 1213 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1214 else 1215 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1216 1217 /* Set capture broadcast bit to capture broadcast frames. */ 1218 if (ifp->if_flags & IFF_BROADCAST) 1219 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1220 else 1221 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1222 1223 /* Program the multicast filter, if necessary. */ 1224 vr_setmulti(sc); 1225 1226 /* Give the transmit and receive rings to the Rhine. */ 1227 CSR_WRITE_4(sc, VR_RXADDR, VR_CDRXADDR(sc, sc->vr_rxptr)); 1228 CSR_WRITE_4(sc, VR_TXADDR, VR_CDTXADDR(sc, VR_NEXTTX(sc->vr_txlast))); 1229 1230 /* Set current media. */ 1231 if ((error = ether_mediachange(ifp)) != 0) 1232 goto out; 1233 1234 /* Enable receiver and transmitter. */ 1235 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1236 VR_CMD_TX_ON|VR_CMD_RX_ON| 1237 VR_CMD_RX_GO); 1238 1239 /* Enable interrupts. */ 1240 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1241 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1242 1243 ifp->if_flags |= IFF_RUNNING; 1244 ifp->if_flags &= ~IFF_OACTIVE; 1245 1246 /* Start one second timer. */ 1247 callout_reset(&sc->vr_tick_ch, hz, vr_tick, sc); 1248 1249 /* Attempt to start output on the interface. */ 1250 vr_start(ifp); 1251 1252 out: 1253 if (error) 1254 printf("%s: interface not running\n", device_xname(sc->vr_dev)); 1255 return (error); 1256 } 1257 1258 static int 1259 vr_ioctl(struct ifnet *ifp, u_long command, void *data) 1260 { 1261 struct vr_softc *sc = ifp->if_softc; 1262 int s, error = 0; 1263 1264 s = splnet(); 1265 1266 error = ether_ioctl(ifp, command, data); 1267 if (error == ENETRESET) { 1268 /* 1269 * Multicast list has changed; set the hardware filter 1270 * accordingly. 1271 */ 1272 if (ifp->if_flags & IFF_RUNNING) 1273 vr_setmulti(sc); 1274 error = 0; 1275 } 1276 1277 splx(s); 1278 return (error); 1279 } 1280 1281 static void 1282 vr_watchdog(struct ifnet *ifp) 1283 { 1284 struct vr_softc *sc = ifp->if_softc; 1285 1286 printf("%s: device timeout\n", device_xname(sc->vr_dev)); 1287 ifp->if_oerrors++; 1288 1289 (void) vr_init(ifp); 1290 } 1291 1292 /* 1293 * One second timer, used to tick MII. 1294 */ 1295 static void 1296 vr_tick(void *arg) 1297 { 1298 struct vr_softc *sc = arg; 1299 int s; 1300 1301 s = splnet(); 1302 mii_tick(&sc->vr_mii); 1303 splx(s); 1304 1305 callout_reset(&sc->vr_tick_ch, hz, vr_tick, sc); 1306 } 1307 1308 /* 1309 * Drain the receive queue. 1310 */ 1311 static void 1312 vr_rxdrain(struct vr_softc *sc) 1313 { 1314 struct vr_descsoft *ds; 1315 int i; 1316 1317 for (i = 0; i < VR_NRXDESC; i++) { 1318 ds = VR_DSRX(sc, i); 1319 if (ds->ds_mbuf != NULL) { 1320 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 1321 m_freem(ds->ds_mbuf); 1322 ds->ds_mbuf = NULL; 1323 } 1324 } 1325 } 1326 1327 /* 1328 * Stop the adapter and free any mbufs allocated to the 1329 * transmit lists. 1330 */ 1331 static void 1332 vr_stop(struct ifnet *ifp, int disable) 1333 { 1334 struct vr_softc *sc = ifp->if_softc; 1335 struct vr_descsoft *ds; 1336 int i; 1337 1338 /* Cancel one second timer. */ 1339 callout_stop(&sc->vr_tick_ch); 1340 1341 /* Down the MII. */ 1342 mii_down(&sc->vr_mii); 1343 1344 ifp = &sc->vr_ec.ec_if; 1345 ifp->if_timer = 0; 1346 1347 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1348 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1349 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1350 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1351 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1352 1353 /* 1354 * Release any queued transmit buffers. 1355 */ 1356 for (i = 0; i < VR_NTXDESC; i++) { 1357 ds = VR_DSTX(sc, i); 1358 if (ds->ds_mbuf != NULL) { 1359 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 1360 m_freem(ds->ds_mbuf); 1361 ds->ds_mbuf = NULL; 1362 } 1363 } 1364 1365 /* 1366 * Mark the interface down and cancel the watchdog timer. 1367 */ 1368 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1369 ifp->if_timer = 0; 1370 1371 if (disable) 1372 vr_rxdrain(sc); 1373 } 1374 1375 static int vr_probe(device_t, cfdata_t, void *); 1376 static void vr_attach(device_t, device_t, void *); 1377 static bool vr_shutdown(device_t, int); 1378 1379 CFATTACH_DECL_NEW(vr, sizeof (struct vr_softc), 1380 vr_probe, vr_attach, NULL, NULL); 1381 1382 static const struct vr_type * 1383 vr_lookup(struct pci_attach_args *pa) 1384 { 1385 const struct vr_type *vrt; 1386 int i; 1387 1388 for (i = 0; i < __arraycount(vr_devs); i++) { 1389 vrt = &vr_devs[i]; 1390 if (PCI_VENDOR(pa->pa_id) == vrt->vr_vid && 1391 PCI_PRODUCT(pa->pa_id) == vrt->vr_did) 1392 return (vrt); 1393 } 1394 return (NULL); 1395 } 1396 1397 static int 1398 vr_probe(device_t parent, cfdata_t match, void *aux) 1399 { 1400 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1401 1402 if (vr_lookup(pa) != NULL) 1403 return (1); 1404 1405 return (0); 1406 } 1407 1408 /* 1409 * Stop all chip I/O so that the kernel's probe routines don't 1410 * get confused by errant DMAs when rebooting. 1411 */ 1412 static bool 1413 vr_shutdown(device_t self, int howto) 1414 { 1415 struct vr_softc *sc = device_private(self); 1416 1417 vr_stop(&sc->vr_ec.ec_if, 1); 1418 1419 return true; 1420 } 1421 1422 /* 1423 * Attach the interface. Allocate softc structures, do ifmedia 1424 * setup and ethernet/BPF attach. 1425 */ 1426 static void 1427 vr_attach(device_t parent, device_t self, void *aux) 1428 { 1429 struct vr_softc *sc = device_private(self); 1430 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 1431 bus_dma_segment_t seg; 1432 uint32_t reg; 1433 struct ifnet *ifp; 1434 uint8_t eaddr[ETHER_ADDR_LEN], mac; 1435 int i, rseg, error; 1436 1437 #define PCI_CONF_WRITE(r, v) pci_conf_write(sc->vr_pc, sc->vr_tag, (r), (v)) 1438 #define PCI_CONF_READ(r) pci_conf_read(sc->vr_pc, sc->vr_tag, (r)) 1439 1440 sc->vr_dev = self; 1441 sc->vr_pc = pa->pa_pc; 1442 sc->vr_tag = pa->pa_tag; 1443 sc->vr_id = pa->pa_id; 1444 callout_init(&sc->vr_tick_ch, 0); 1445 1446 pci_aprint_devinfo(pa, NULL); 1447 1448 /* 1449 * Handle power management nonsense. 1450 */ 1451 1452 sc->vr_save_iobase = PCI_CONF_READ(VR_PCI_LOIO); 1453 sc->vr_save_membase = PCI_CONF_READ(VR_PCI_LOMEM); 1454 sc->vr_save_irq = PCI_CONF_READ(PCI_INTERRUPT_REG); 1455 1456 /* power up chip */ 1457 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 1458 vr_restore_state)) && error != EOPNOTSUPP) { 1459 aprint_error_dev(self, "cannot activate %d\n", 1460 error); 1461 return; 1462 } 1463 1464 /* Make sure bus mastering is enabled. */ 1465 reg = PCI_CONF_READ(PCI_COMMAND_STATUS_REG); 1466 reg |= PCI_COMMAND_MASTER_ENABLE; 1467 PCI_CONF_WRITE(PCI_COMMAND_STATUS_REG, reg); 1468 1469 /* Get revision */ 1470 sc->vr_revid = PCI_REVISION(pa->pa_class); 1471 1472 /* 1473 * Map control/status registers. 1474 */ 1475 { 1476 bus_space_tag_t iot, memt; 1477 bus_space_handle_t ioh, memh; 1478 int ioh_valid, memh_valid; 1479 pci_intr_handle_t intrhandle; 1480 const char *intrstr; 1481 1482 ioh_valid = (pci_mapreg_map(pa, VR_PCI_LOIO, 1483 PCI_MAPREG_TYPE_IO, 0, 1484 &iot, &ioh, NULL, NULL) == 0); 1485 memh_valid = (pci_mapreg_map(pa, VR_PCI_LOMEM, 1486 PCI_MAPREG_TYPE_MEM | 1487 PCI_MAPREG_MEM_TYPE_32BIT, 1488 0, &memt, &memh, NULL, NULL) == 0); 1489 #if defined(VR_USEIOSPACE) 1490 if (ioh_valid) { 1491 sc->vr_bst = iot; 1492 sc->vr_bsh = ioh; 1493 } else if (memh_valid) { 1494 sc->vr_bst = memt; 1495 sc->vr_bsh = memh; 1496 } 1497 #else 1498 if (memh_valid) { 1499 sc->vr_bst = memt; 1500 sc->vr_bsh = memh; 1501 } else if (ioh_valid) { 1502 sc->vr_bst = iot; 1503 sc->vr_bsh = ioh; 1504 } 1505 #endif 1506 else { 1507 printf(": unable to map device registers\n"); 1508 return; 1509 } 1510 1511 /* Allocate interrupt */ 1512 if (pci_intr_map(pa, &intrhandle)) { 1513 aprint_error_dev(self, "couldn't map interrupt\n"); 1514 return; 1515 } 1516 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 1517 sc->vr_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 1518 vr_intr, sc); 1519 if (sc->vr_ih == NULL) { 1520 aprint_error_dev(self, "couldn't establish interrupt"); 1521 if (intrstr != NULL) 1522 aprint_error(" at %s", intrstr); 1523 aprint_error("\n"); 1524 } 1525 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 1526 } 1527 1528 /* 1529 * Windows may put the chip in suspend mode when it 1530 * shuts down. Be sure to kick it in the head to wake it 1531 * up again. 1532 * 1533 * Don't touch this register on VT3043 since it causes 1534 * kernel MCHK trap on macppc. 1535 * (Note some VT86C100A chip returns a product ID of VT3043) 1536 */ 1537 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT3043) 1538 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 1539 1540 /* Reset the adapter. */ 1541 vr_reset(sc); 1542 1543 /* 1544 * Get station address. The way the Rhine chips work, 1545 * you're not allowed to directly access the EEPROM once 1546 * they've been programmed a special way. Consequently, 1547 * we need to read the node address from the PAR0 and PAR1 1548 * registers. 1549 * 1550 * XXXSCW: On the Rhine III, setting VR_EECSR_LOAD forces a reload 1551 * of the *whole* EEPROM, not just the MAC address. This is 1552 * pretty pointless since the chip does this automatically 1553 * at powerup/reset. 1554 * I suspect the same thing applies to the other Rhine 1555 * variants, but in the absence of a data sheet for those 1556 * (and the lack of anyone else noticing the problems this 1557 * causes) I'm going to retain the old behaviour for the 1558 * other parts. 1559 * In some cases, the chip really does startup without having 1560 * read the EEPROM (kern/34812). To handle this case, we force 1561 * a reload if we see an all-zeroes MAC address. 1562 */ 1563 for (mac = 0, i = 0; i < ETHER_ADDR_LEN; i++) 1564 mac |= (eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i)); 1565 1566 if (mac == 0 || (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT6105 && 1567 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT6102)) { 1568 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 1569 DELAY(200); 1570 for (i = 0; i < ETHER_ADDR_LEN; i++) 1571 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 1572 } 1573 1574 /* 1575 * A Rhine chip was detected. Inform the world. 1576 */ 1577 aprint_normal("%s: Ethernet address: %s\n", 1578 device_xname(self), ether_sprintf(eaddr)); 1579 1580 memcpy(sc->vr_enaddr, eaddr, ETHER_ADDR_LEN); 1581 1582 sc->vr_dmat = pa->pa_dmat; 1583 1584 /* 1585 * Allocate the control data structures, and create and load 1586 * the DMA map for it. 1587 */ 1588 if ((error = bus_dmamem_alloc(sc->vr_dmat, 1589 sizeof(struct vr_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 1590 0)) != 0) { 1591 aprint_error_dev(self, "unable to allocate control data, error = %d\n", error); 1592 goto fail_0; 1593 } 1594 1595 if ((error = bus_dmamem_map(sc->vr_dmat, &seg, rseg, 1596 sizeof(struct vr_control_data), (void **)&sc->vr_control_data, 1597 BUS_DMA_COHERENT)) != 0) { 1598 aprint_error_dev(self, "unable to map control data, error = %d\n", error); 1599 goto fail_1; 1600 } 1601 1602 if ((error = bus_dmamap_create(sc->vr_dmat, 1603 sizeof(struct vr_control_data), 1, 1604 sizeof(struct vr_control_data), 0, 0, 1605 &sc->vr_cddmamap)) != 0) { 1606 aprint_error_dev(self, "unable to create control data DMA map, " 1607 "error = %d\n", error); 1608 goto fail_2; 1609 } 1610 1611 if ((error = bus_dmamap_load(sc->vr_dmat, sc->vr_cddmamap, 1612 sc->vr_control_data, sizeof(struct vr_control_data), NULL, 1613 0)) != 0) { 1614 aprint_error_dev(self, "unable to load control data DMA map, error = %d\n", 1615 error); 1616 goto fail_3; 1617 } 1618 1619 /* 1620 * Create the transmit buffer DMA maps. 1621 */ 1622 for (i = 0; i < VR_NTXDESC; i++) { 1623 if ((error = bus_dmamap_create(sc->vr_dmat, MCLBYTES, 1624 1, MCLBYTES, 0, 0, 1625 &VR_DSTX(sc, i)->ds_dmamap)) != 0) { 1626 aprint_error_dev(self, "unable to create tx DMA map %d, " 1627 "error = %d\n", i, error); 1628 goto fail_4; 1629 } 1630 } 1631 1632 /* 1633 * Create the receive buffer DMA maps. 1634 */ 1635 for (i = 0; i < VR_NRXDESC; i++) { 1636 if ((error = bus_dmamap_create(sc->vr_dmat, MCLBYTES, 1, 1637 MCLBYTES, 0, 0, 1638 &VR_DSRX(sc, i)->ds_dmamap)) != 0) { 1639 aprint_error_dev(self, "unable to create rx DMA map %d, " 1640 "error = %d\n", i, error); 1641 goto fail_5; 1642 } 1643 VR_DSRX(sc, i)->ds_mbuf = NULL; 1644 } 1645 1646 ifp = &sc->vr_ec.ec_if; 1647 ifp->if_softc = sc; 1648 ifp->if_mtu = ETHERMTU; 1649 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1650 ifp->if_ioctl = vr_ioctl; 1651 ifp->if_start = vr_start; 1652 ifp->if_watchdog = vr_watchdog; 1653 ifp->if_init = vr_init; 1654 ifp->if_stop = vr_stop; 1655 IFQ_SET_READY(&ifp->if_snd); 1656 1657 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 1658 1659 /* 1660 * Initialize MII/media info. 1661 */ 1662 sc->vr_mii.mii_ifp = ifp; 1663 sc->vr_mii.mii_readreg = vr_mii_readreg; 1664 sc->vr_mii.mii_writereg = vr_mii_writereg; 1665 sc->vr_mii.mii_statchg = vr_mii_statchg; 1666 1667 sc->vr_ec.ec_mii = &sc->vr_mii; 1668 ifmedia_init(&sc->vr_mii.mii_media, IFM_IMASK, ether_mediachange, 1669 ether_mediastatus); 1670 mii_attach(self, &sc->vr_mii, 0xffffffff, MII_PHY_ANY, 1671 MII_OFFSET_ANY, MIIF_FORCEANEG); 1672 if (LIST_FIRST(&sc->vr_mii.mii_phys) == NULL) { 1673 ifmedia_add(&sc->vr_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1674 ifmedia_set(&sc->vr_mii.mii_media, IFM_ETHER|IFM_NONE); 1675 } else 1676 ifmedia_set(&sc->vr_mii.mii_media, IFM_ETHER|IFM_AUTO); 1677 1678 sc->vr_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 1679 1680 /* 1681 * Call MI attach routines. 1682 */ 1683 if_attach(ifp); 1684 ether_ifattach(ifp, sc->vr_enaddr); 1685 1686 rnd_attach_source(&sc->rnd_source, device_xname(self), 1687 RND_TYPE_NET, 0); 1688 1689 if (pmf_device_register1(self, NULL, vr_resume, vr_shutdown)) 1690 pmf_class_network_register(self, ifp); 1691 else 1692 aprint_error_dev(self, "couldn't establish power handler\n"); 1693 1694 return; 1695 1696 fail_5: 1697 for (i = 0; i < VR_NRXDESC; i++) { 1698 if (sc->vr_rxsoft[i].ds_dmamap != NULL) 1699 bus_dmamap_destroy(sc->vr_dmat, 1700 sc->vr_rxsoft[i].ds_dmamap); 1701 } 1702 fail_4: 1703 for (i = 0; i < VR_NTXDESC; i++) { 1704 if (sc->vr_txsoft[i].ds_dmamap != NULL) 1705 bus_dmamap_destroy(sc->vr_dmat, 1706 sc->vr_txsoft[i].ds_dmamap); 1707 } 1708 bus_dmamap_unload(sc->vr_dmat, sc->vr_cddmamap); 1709 fail_3: 1710 bus_dmamap_destroy(sc->vr_dmat, sc->vr_cddmamap); 1711 fail_2: 1712 bus_dmamem_unmap(sc->vr_dmat, (void *)sc->vr_control_data, 1713 sizeof(struct vr_control_data)); 1714 fail_1: 1715 bus_dmamem_free(sc->vr_dmat, &seg, rseg); 1716 fail_0: 1717 return; 1718 } 1719 1720 static int 1721 vr_restore_state(pci_chipset_tag_t pc, pcitag_t tag, device_t self, 1722 pcireg_t state) 1723 { 1724 struct vr_softc *sc = device_private(self); 1725 int error; 1726 1727 if (state == PCI_PMCSR_STATE_D0) 1728 return 0; 1729 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 1730 return error; 1731 1732 /* Restore PCI config data. */ 1733 PCI_CONF_WRITE(VR_PCI_LOIO, sc->vr_save_iobase); 1734 PCI_CONF_WRITE(VR_PCI_LOMEM, sc->vr_save_membase); 1735 PCI_CONF_WRITE(PCI_INTERRUPT_REG, sc->vr_save_irq); 1736 return 0; 1737 } 1738 1739 static bool 1740 vr_resume(device_t self, const pmf_qual_t *qual) 1741 { 1742 struct vr_softc *sc = device_private(self); 1743 1744 if (PCI_PRODUCT(sc->vr_id) != PCI_PRODUCT_VIATECH_VT3043) 1745 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 1746 1747 return true; 1748 } 1749