1 /* $NetBSD: if_vr.c,v 1.105 2010/04/28 22:08:58 hubertf Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1997, 1998 35 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Bill Paul. 48 * 4. Neither the name of the author nor the names of any co-contributors 49 * may be used to endorse or promote products derived from this software 50 * without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 56 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 57 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 58 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 59 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 60 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 61 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 62 * THE POSSIBILITY OF SUCH DAMAGE. 63 * 64 * $FreeBSD: if_vr.c,v 1.7 1999/01/10 18:51:49 wpaul Exp $ 65 */ 66 67 /* 68 * VIA Rhine fast ethernet PCI NIC driver 69 * 70 * Supports various network adapters based on the VIA Rhine 71 * and Rhine II PCI controllers, including the D-Link DFE530TX. 72 * Datasheets are available at http://www.via.com.tw. 73 * 74 * Written by Bill Paul <wpaul@ctr.columbia.edu> 75 * Electrical Engineering Department 76 * Columbia University, New York City 77 */ 78 79 /* 80 * The VIA Rhine controllers are similar in some respects to the 81 * the DEC tulip chips, except less complicated. The controller 82 * uses an MII bus and an external physical layer interface. The 83 * receiver has a one entry perfect filter and a 64-bit hash table 84 * multicast filter. Transmit and receive descriptors are similar 85 * to the tulip. 86 * 87 * The Rhine has a serious flaw in its transmit DMA mechanism: 88 * transmit buffers must be longword aligned. Unfortunately, 89 * the kernel doesn't guarantee that mbufs will be filled in starting 90 * at longword boundaries, so we have to do a buffer copy before 91 * transmission. 92 * 93 * Apparently, the receive DMA mechanism also has the same flaw. This 94 * means that on systems with struct alignment requirements, incoming 95 * frames must be copied to a new buffer which shifts the data forward 96 * 2 bytes so that the payload is aligned on a 4-byte boundary. 97 */ 98 99 #include <sys/cdefs.h> 100 __KERNEL_RCSID(0, "$NetBSD: if_vr.c,v 1.105 2010/04/28 22:08:58 hubertf Exp $"); 101 102 #include "rnd.h" 103 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/callout.h> 107 #include <sys/sockio.h> 108 #include <sys/mbuf.h> 109 #include <sys/malloc.h> 110 #include <sys/kernel.h> 111 #include <sys/socket.h> 112 #include <sys/device.h> 113 114 #if NRND > 0 115 #include <sys/rnd.h> 116 #endif 117 118 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 119 120 #include <net/if.h> 121 #include <net/if_arp.h> 122 #include <net/if_dl.h> 123 #include <net/if_media.h> 124 #include <net/if_ether.h> 125 126 #include <net/bpf.h> 127 128 #include <sys/bus.h> 129 #include <sys/intr.h> 130 #include <machine/endian.h> 131 132 #include <dev/mii/mii.h> 133 #include <dev/mii/miivar.h> 134 #include <dev/mii/mii_bitbang.h> 135 136 #include <dev/pci/pcireg.h> 137 #include <dev/pci/pcivar.h> 138 #include <dev/pci/pcidevs.h> 139 140 #include <dev/pci/if_vrreg.h> 141 142 #define VR_USEIOSPACE 143 144 /* 145 * Various supported device vendors/types and their names. 146 */ 147 static const struct vr_type { 148 pci_vendor_id_t vr_vid; 149 pci_product_id_t vr_did; 150 } vr_devs[] = { 151 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT3043 }, 152 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6102 }, 153 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6105 }, 154 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6105M }, 155 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT86C100A } 156 }; 157 158 /* 159 * Transmit descriptor list size. 160 */ 161 #define VR_NTXDESC 64 162 #define VR_NTXDESC_MASK (VR_NTXDESC - 1) 163 #define VR_NEXTTX(x) (((x) + 1) & VR_NTXDESC_MASK) 164 165 /* 166 * Receive descriptor list size. 167 */ 168 #define VR_NRXDESC 64 169 #define VR_NRXDESC_MASK (VR_NRXDESC - 1) 170 #define VR_NEXTRX(x) (((x) + 1) & VR_NRXDESC_MASK) 171 172 /* 173 * Control data structres that are DMA'd to the Rhine chip. We allocate 174 * them in a single clump that maps to a single DMA segment to make several 175 * things easier. 176 * 177 * Note that since we always copy outgoing packets to aligned transmit 178 * buffers, we can reduce the transmit descriptors to one per packet. 179 */ 180 struct vr_control_data { 181 struct vr_desc vr_txdescs[VR_NTXDESC]; 182 struct vr_desc vr_rxdescs[VR_NRXDESC]; 183 }; 184 185 #define VR_CDOFF(x) offsetof(struct vr_control_data, x) 186 #define VR_CDTXOFF(x) VR_CDOFF(vr_txdescs[(x)]) 187 #define VR_CDRXOFF(x) VR_CDOFF(vr_rxdescs[(x)]) 188 189 /* 190 * Software state of transmit and receive descriptors. 191 */ 192 struct vr_descsoft { 193 struct mbuf *ds_mbuf; /* head of mbuf chain */ 194 bus_dmamap_t ds_dmamap; /* our DMA map */ 195 }; 196 197 struct vr_softc { 198 device_t vr_dev; 199 void *vr_ih; /* interrupt cookie */ 200 bus_space_tag_t vr_bst; /* bus space tag */ 201 bus_space_handle_t vr_bsh; /* bus space handle */ 202 bus_dma_tag_t vr_dmat; /* bus DMA tag */ 203 pci_chipset_tag_t vr_pc; /* PCI chipset info */ 204 pcitag_t vr_tag; /* PCI tag */ 205 struct ethercom vr_ec; /* Ethernet common info */ 206 uint8_t vr_enaddr[ETHER_ADDR_LEN]; 207 struct mii_data vr_mii; /* MII/media info */ 208 209 pcireg_t vr_id; /* vendor/product ID */ 210 uint8_t vr_revid; /* Rhine chip revision */ 211 212 callout_t vr_tick_ch; /* tick callout */ 213 214 bus_dmamap_t vr_cddmamap; /* control data DMA map */ 215 #define vr_cddma vr_cddmamap->dm_segs[0].ds_addr 216 217 /* 218 * Software state for transmit and receive descriptors. 219 */ 220 struct vr_descsoft vr_txsoft[VR_NTXDESC]; 221 struct vr_descsoft vr_rxsoft[VR_NRXDESC]; 222 223 /* 224 * Control data structures. 225 */ 226 struct vr_control_data *vr_control_data; 227 228 int vr_txpending; /* number of TX requests pending */ 229 int vr_txdirty; /* first dirty TX descriptor */ 230 int vr_txlast; /* last used TX descriptor */ 231 232 int vr_rxptr; /* next ready RX descriptor */ 233 234 uint32_t vr_save_iobase; 235 uint32_t vr_save_membase; 236 uint32_t vr_save_irq; 237 238 #if NRND > 0 239 rndsource_element_t rnd_source; /* random source */ 240 #endif 241 }; 242 243 #define VR_CDTXADDR(sc, x) ((sc)->vr_cddma + VR_CDTXOFF((x))) 244 #define VR_CDRXADDR(sc, x) ((sc)->vr_cddma + VR_CDRXOFF((x))) 245 246 #define VR_CDTX(sc, x) (&(sc)->vr_control_data->vr_txdescs[(x)]) 247 #define VR_CDRX(sc, x) (&(sc)->vr_control_data->vr_rxdescs[(x)]) 248 249 #define VR_DSTX(sc, x) (&(sc)->vr_txsoft[(x)]) 250 #define VR_DSRX(sc, x) (&(sc)->vr_rxsoft[(x)]) 251 252 #define VR_CDTXSYNC(sc, x, ops) \ 253 bus_dmamap_sync((sc)->vr_dmat, (sc)->vr_cddmamap, \ 254 VR_CDTXOFF((x)), sizeof(struct vr_desc), (ops)) 255 256 #define VR_CDRXSYNC(sc, x, ops) \ 257 bus_dmamap_sync((sc)->vr_dmat, (sc)->vr_cddmamap, \ 258 VR_CDRXOFF((x)), sizeof(struct vr_desc), (ops)) 259 260 /* 261 * Note we rely on MCLBYTES being a power of two below. 262 */ 263 #define VR_INIT_RXDESC(sc, i) \ 264 do { \ 265 struct vr_desc *__d = VR_CDRX((sc), (i)); \ 266 struct vr_descsoft *__ds = VR_DSRX((sc), (i)); \ 267 \ 268 __d->vr_next = htole32(VR_CDRXADDR((sc), VR_NEXTRX((i)))); \ 269 __d->vr_data = htole32(__ds->ds_dmamap->dm_segs[0].ds_addr); \ 270 __d->vr_ctl = htole32(VR_RXCTL_CHAIN | VR_RXCTL_RX_INTR | \ 271 ((MCLBYTES - 1) & VR_RXCTL_BUFLEN)); \ 272 __d->vr_status = htole32(VR_RXSTAT_FIRSTFRAG | \ 273 VR_RXSTAT_LASTFRAG | VR_RXSTAT_OWN); \ 274 VR_CDRXSYNC((sc), (i), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 275 } while (/* CONSTCOND */ 0) 276 277 /* 278 * register space access macros 279 */ 280 #define CSR_WRITE_4(sc, reg, val) \ 281 bus_space_write_4(sc->vr_bst, sc->vr_bsh, reg, val) 282 #define CSR_WRITE_2(sc, reg, val) \ 283 bus_space_write_2(sc->vr_bst, sc->vr_bsh, reg, val) 284 #define CSR_WRITE_1(sc, reg, val) \ 285 bus_space_write_1(sc->vr_bst, sc->vr_bsh, reg, val) 286 287 #define CSR_READ_4(sc, reg) \ 288 bus_space_read_4(sc->vr_bst, sc->vr_bsh, reg) 289 #define CSR_READ_2(sc, reg) \ 290 bus_space_read_2(sc->vr_bst, sc->vr_bsh, reg) 291 #define CSR_READ_1(sc, reg) \ 292 bus_space_read_1(sc->vr_bst, sc->vr_bsh, reg) 293 294 #define VR_TIMEOUT 1000 295 296 static int vr_add_rxbuf(struct vr_softc *, int); 297 298 static void vr_rxeof(struct vr_softc *); 299 static void vr_rxeoc(struct vr_softc *); 300 static void vr_txeof(struct vr_softc *); 301 static int vr_intr(void *); 302 static void vr_start(struct ifnet *); 303 static int vr_ioctl(struct ifnet *, u_long, void *); 304 static int vr_init(struct ifnet *); 305 static void vr_stop(struct ifnet *, int); 306 static void vr_rxdrain(struct vr_softc *); 307 static void vr_watchdog(struct ifnet *); 308 static void vr_tick(void *); 309 310 static int vr_mii_readreg(device_t, int, int); 311 static void vr_mii_writereg(device_t, int, int, int); 312 static void vr_mii_statchg(device_t); 313 314 static void vr_setmulti(struct vr_softc *); 315 static void vr_reset(struct vr_softc *); 316 static int vr_restore_state(pci_chipset_tag_t, pcitag_t, device_t, 317 pcireg_t); 318 static bool vr_resume(device_t, const pmf_qual_t *); 319 320 int vr_copy_small = 0; 321 322 #define VR_SETBIT(sc, reg, x) \ 323 CSR_WRITE_1(sc, reg, \ 324 CSR_READ_1(sc, reg) | (x)) 325 326 #define VR_CLRBIT(sc, reg, x) \ 327 CSR_WRITE_1(sc, reg, \ 328 CSR_READ_1(sc, reg) & ~(x)) 329 330 #define VR_SETBIT16(sc, reg, x) \ 331 CSR_WRITE_2(sc, reg, \ 332 CSR_READ_2(sc, reg) | (x)) 333 334 #define VR_CLRBIT16(sc, reg, x) \ 335 CSR_WRITE_2(sc, reg, \ 336 CSR_READ_2(sc, reg) & ~(x)) 337 338 #define VR_SETBIT32(sc, reg, x) \ 339 CSR_WRITE_4(sc, reg, \ 340 CSR_READ_4(sc, reg) | (x)) 341 342 #define VR_CLRBIT32(sc, reg, x) \ 343 CSR_WRITE_4(sc, reg, \ 344 CSR_READ_4(sc, reg) & ~(x)) 345 346 /* 347 * MII bit-bang glue. 348 */ 349 static uint32_t vr_mii_bitbang_read(device_t); 350 static void vr_mii_bitbang_write(device_t, uint32_t); 351 352 static const struct mii_bitbang_ops vr_mii_bitbang_ops = { 353 vr_mii_bitbang_read, 354 vr_mii_bitbang_write, 355 { 356 VR_MIICMD_DATAOUT, /* MII_BIT_MDO */ 357 VR_MIICMD_DATAIN, /* MII_BIT_MDI */ 358 VR_MIICMD_CLK, /* MII_BIT_MDC */ 359 VR_MIICMD_DIR, /* MII_BIT_DIR_HOST_PHY */ 360 0, /* MII_BIT_DIR_PHY_HOST */ 361 } 362 }; 363 364 static uint32_t 365 vr_mii_bitbang_read(device_t self) 366 { 367 struct vr_softc *sc = device_private(self); 368 369 return (CSR_READ_1(sc, VR_MIICMD)); 370 } 371 372 static void 373 vr_mii_bitbang_write(device_t self, uint32_t val) 374 { 375 struct vr_softc *sc = device_private(self); 376 377 CSR_WRITE_1(sc, VR_MIICMD, (val & 0xff) | VR_MIICMD_DIRECTPGM); 378 } 379 380 /* 381 * Read an PHY register through the MII. 382 */ 383 static int 384 vr_mii_readreg(device_t self, int phy, int reg) 385 { 386 struct vr_softc *sc = device_private(self); 387 388 CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 389 return (mii_bitbang_readreg(self, &vr_mii_bitbang_ops, phy, reg)); 390 } 391 392 /* 393 * Write to a PHY register through the MII. 394 */ 395 static void 396 vr_mii_writereg(device_t self, int phy, int reg, int val) 397 { 398 struct vr_softc *sc = device_private(self); 399 400 CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 401 mii_bitbang_writereg(self, &vr_mii_bitbang_ops, phy, reg, val); 402 } 403 404 static void 405 vr_mii_statchg(device_t self) 406 { 407 struct vr_softc *sc = device_private(self); 408 409 /* 410 * In order to fiddle with the 'full-duplex' bit in the netconfig 411 * register, we first have to put the transmit and/or receive logic 412 * in the idle state. 413 */ 414 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 415 416 if (sc->vr_mii.mii_media_active & IFM_FDX) 417 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 418 else 419 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 420 421 if (sc->vr_ec.ec_if.if_flags & IFF_RUNNING) 422 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 423 } 424 425 #define vr_calchash(addr) \ 426 (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26) 427 428 /* 429 * Program the 64-bit multicast hash filter. 430 */ 431 static void 432 vr_setmulti(struct vr_softc *sc) 433 { 434 struct ifnet *ifp; 435 int h = 0; 436 uint32_t hashes[2] = { 0, 0 }; 437 struct ether_multistep step; 438 struct ether_multi *enm; 439 int mcnt = 0; 440 uint8_t rxfilt; 441 442 ifp = &sc->vr_ec.ec_if; 443 444 rxfilt = CSR_READ_1(sc, VR_RXCFG); 445 446 if (ifp->if_flags & IFF_PROMISC) { 447 allmulti: 448 ifp->if_flags |= IFF_ALLMULTI; 449 rxfilt |= VR_RXCFG_RX_MULTI; 450 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 451 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 452 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 453 return; 454 } 455 456 /* first, zot all the existing hash bits */ 457 CSR_WRITE_4(sc, VR_MAR0, 0); 458 CSR_WRITE_4(sc, VR_MAR1, 0); 459 460 /* now program new ones */ 461 ETHER_FIRST_MULTI(step, &sc->vr_ec, enm); 462 while (enm != NULL) { 463 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 464 ETHER_ADDR_LEN) != 0) 465 goto allmulti; 466 467 h = vr_calchash(enm->enm_addrlo); 468 469 if (h < 32) 470 hashes[0] |= (1 << h); 471 else 472 hashes[1] |= (1 << (h - 32)); 473 ETHER_NEXT_MULTI(step, enm); 474 mcnt++; 475 } 476 477 ifp->if_flags &= ~IFF_ALLMULTI; 478 479 if (mcnt) 480 rxfilt |= VR_RXCFG_RX_MULTI; 481 else 482 rxfilt &= ~VR_RXCFG_RX_MULTI; 483 484 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 485 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 486 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 487 } 488 489 static void 490 vr_reset(struct vr_softc *sc) 491 { 492 int i; 493 494 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 495 496 for (i = 0; i < VR_TIMEOUT; i++) { 497 DELAY(10); 498 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 499 break; 500 } 501 if (i == VR_TIMEOUT) { 502 if (sc->vr_revid < REV_ID_VT3065_A) { 503 printf("%s: reset never completed!\n", 504 device_xname(sc->vr_dev)); 505 } else { 506 /* Use newer force reset command */ 507 printf("%s: using force reset command.\n", 508 device_xname(sc->vr_dev)); 509 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 510 } 511 } 512 513 /* Wait a little while for the chip to get its brains in order. */ 514 DELAY(1000); 515 } 516 517 /* 518 * Initialize an RX descriptor and attach an MBUF cluster. 519 * Note: the length fields are only 11 bits wide, which means the 520 * largest size we can specify is 2047. This is important because 521 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 522 * overflow the field and make a mess. 523 */ 524 static int 525 vr_add_rxbuf(struct vr_softc *sc, int i) 526 { 527 struct vr_descsoft *ds = VR_DSRX(sc, i); 528 struct mbuf *m_new; 529 int error; 530 531 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 532 if (m_new == NULL) 533 return (ENOBUFS); 534 535 MCLGET(m_new, M_DONTWAIT); 536 if ((m_new->m_flags & M_EXT) == 0) { 537 m_freem(m_new); 538 return (ENOBUFS); 539 } 540 541 if (ds->ds_mbuf != NULL) 542 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 543 544 ds->ds_mbuf = m_new; 545 546 error = bus_dmamap_load(sc->vr_dmat, ds->ds_dmamap, 547 m_new->m_ext.ext_buf, m_new->m_ext.ext_size, NULL, 548 BUS_DMA_READ|BUS_DMA_NOWAIT); 549 if (error) { 550 aprint_error_dev(sc->vr_dev, "unable to load rx DMA map %d, error = %d\n", 551 i, error); 552 panic("vr_add_rxbuf"); /* XXX */ 553 } 554 555 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 556 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 557 558 VR_INIT_RXDESC(sc, i); 559 560 return (0); 561 } 562 563 /* 564 * A frame has been uploaded: pass the resulting mbuf chain up to 565 * the higher level protocols. 566 */ 567 static void 568 vr_rxeof(struct vr_softc *sc) 569 { 570 struct mbuf *m; 571 struct ifnet *ifp; 572 struct vr_desc *d; 573 struct vr_descsoft *ds; 574 int i, total_len; 575 uint32_t rxstat; 576 577 ifp = &sc->vr_ec.ec_if; 578 579 for (i = sc->vr_rxptr;; i = VR_NEXTRX(i)) { 580 d = VR_CDRX(sc, i); 581 ds = VR_DSRX(sc, i); 582 583 VR_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 584 585 rxstat = le32toh(d->vr_status); 586 587 if (rxstat & VR_RXSTAT_OWN) { 588 /* 589 * We have processed all of the receive buffers. 590 */ 591 break; 592 } 593 594 /* 595 * If an error occurs, update stats, clear the 596 * status word and leave the mbuf cluster in place: 597 * it should simply get re-used next time this descriptor 598 * comes up in the ring. 599 */ 600 if (rxstat & VR_RXSTAT_RXERR) { 601 const char *errstr; 602 603 ifp->if_ierrors++; 604 switch (rxstat & 0x000000FF) { 605 case VR_RXSTAT_CRCERR: 606 errstr = "crc error"; 607 break; 608 case VR_RXSTAT_FRAMEALIGNERR: 609 errstr = "frame alignment error"; 610 break; 611 case VR_RXSTAT_FIFOOFLOW: 612 errstr = "FIFO overflow"; 613 break; 614 case VR_RXSTAT_GIANT: 615 errstr = "received giant packet"; 616 break; 617 case VR_RXSTAT_RUNT: 618 errstr = "received runt packet"; 619 break; 620 case VR_RXSTAT_BUSERR: 621 errstr = "system bus error"; 622 break; 623 case VR_RXSTAT_BUFFERR: 624 errstr = "rx buffer error"; 625 break; 626 default: 627 errstr = "unknown rx error"; 628 break; 629 } 630 printf("%s: receive error: %s\n", device_xname(sc->vr_dev), 631 errstr); 632 633 VR_INIT_RXDESC(sc, i); 634 635 continue; 636 } else if (!(rxstat & VR_RXSTAT_FIRSTFRAG) || 637 !(rxstat & VR_RXSTAT_LASTFRAG)) { 638 /* 639 * This driver expects to receive whole packets every 640 * time. In case we receive a fragment that is not 641 * a complete packet, we discard it. 642 */ 643 ifp->if_ierrors++; 644 645 printf("%s: receive error: incomplete frame; " 646 "size = %d, status = 0x%x\n", 647 device_xname(sc->vr_dev), 648 VR_RXBYTES(le32toh(d->vr_status)), rxstat); 649 650 VR_INIT_RXDESC(sc, i); 651 652 continue; 653 } 654 655 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 656 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 657 658 /* No errors; receive the packet. */ 659 total_len = VR_RXBYTES(le32toh(d->vr_status)); 660 #ifdef DIAGNOSTIC 661 if (total_len == 0) { 662 /* 663 * If we receive a zero-length packet, we probably 664 * missed to handle an error condition above. 665 * Discard it to avoid a later crash. 666 */ 667 ifp->if_ierrors++; 668 669 printf("%s: receive error: zero-length packet; " 670 "status = 0x%x\n", 671 device_xname(sc->vr_dev), rxstat); 672 673 VR_INIT_RXDESC(sc, i); 674 675 continue; 676 } 677 #endif 678 679 /* 680 * The Rhine chip includes the CRC with every packet. 681 * Trim it off here. 682 */ 683 total_len -= ETHER_CRC_LEN; 684 685 #ifdef __NO_STRICT_ALIGNMENT 686 /* 687 * If the packet is small enough to fit in a 688 * single header mbuf, allocate one and copy 689 * the data into it. This greatly reduces 690 * memory consumption when we receive lots 691 * of small packets. 692 * 693 * Otherwise, we add a new buffer to the receive 694 * chain. If this fails, we drop the packet and 695 * recycle the old buffer. 696 */ 697 if (vr_copy_small != 0 && total_len <= MHLEN) { 698 MGETHDR(m, M_DONTWAIT, MT_DATA); 699 if (m == NULL) 700 goto dropit; 701 memcpy(mtod(m, void *), 702 mtod(ds->ds_mbuf, void *), total_len); 703 VR_INIT_RXDESC(sc, i); 704 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 705 ds->ds_dmamap->dm_mapsize, 706 BUS_DMASYNC_PREREAD); 707 } else { 708 m = ds->ds_mbuf; 709 if (vr_add_rxbuf(sc, i) == ENOBUFS) { 710 dropit: 711 ifp->if_ierrors++; 712 VR_INIT_RXDESC(sc, i); 713 bus_dmamap_sync(sc->vr_dmat, 714 ds->ds_dmamap, 0, 715 ds->ds_dmamap->dm_mapsize, 716 BUS_DMASYNC_PREREAD); 717 continue; 718 } 719 } 720 #else 721 /* 722 * The Rhine's packet buffers must be 4-byte aligned. 723 * But this means that the data after the Ethernet header 724 * is misaligned. We must allocate a new buffer and 725 * copy the data, shifted forward 2 bytes. 726 */ 727 MGETHDR(m, M_DONTWAIT, MT_DATA); 728 if (m == NULL) { 729 dropit: 730 ifp->if_ierrors++; 731 VR_INIT_RXDESC(sc, i); 732 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 733 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 734 continue; 735 } 736 if (total_len > (MHLEN - 2)) { 737 MCLGET(m, M_DONTWAIT); 738 if ((m->m_flags & M_EXT) == 0) { 739 m_freem(m); 740 goto dropit; 741 } 742 } 743 m->m_data += 2; 744 745 /* 746 * Note that we use clusters for incoming frames, so the 747 * buffer is virtually contiguous. 748 */ 749 memcpy(mtod(m, void *), mtod(ds->ds_mbuf, void *), 750 total_len); 751 752 /* Allow the receive descriptor to continue using its mbuf. */ 753 VR_INIT_RXDESC(sc, i); 754 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 755 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 756 #endif /* __NO_STRICT_ALIGNMENT */ 757 758 ifp->if_ipackets++; 759 m->m_pkthdr.rcvif = ifp; 760 m->m_pkthdr.len = m->m_len = total_len; 761 /* 762 * Handle BPF listeners. Let the BPF user see the packet, but 763 * don't pass it up to the ether_input() layer unless it's 764 * a broadcast packet, multicast packet, matches our ethernet 765 * address or the interface is in promiscuous mode. 766 */ 767 bpf_mtap(ifp, m); 768 /* Pass it on. */ 769 (*ifp->if_input)(ifp, m); 770 } 771 772 /* Update the receive pointer. */ 773 sc->vr_rxptr = i; 774 } 775 776 void 777 vr_rxeoc(struct vr_softc *sc) 778 { 779 struct ifnet *ifp; 780 int i; 781 782 ifp = &sc->vr_ec.ec_if; 783 784 ifp->if_ierrors++; 785 786 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 787 for (i = 0; i < VR_TIMEOUT; i++) { 788 DELAY(10); 789 if ((CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON) == 0) 790 break; 791 } 792 if (i == VR_TIMEOUT) { 793 /* XXX need reset? */ 794 printf("%s: RX shutdown never complete\n", 795 device_xname(sc->vr_dev)); 796 } 797 798 vr_rxeof(sc); 799 800 CSR_WRITE_4(sc, VR_RXADDR, VR_CDRXADDR(sc, sc->vr_rxptr)); 801 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 802 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 803 } 804 805 /* 806 * A frame was downloaded to the chip. It's safe for us to clean up 807 * the list buffers. 808 */ 809 static void 810 vr_txeof(struct vr_softc *sc) 811 { 812 struct ifnet *ifp = &sc->vr_ec.ec_if; 813 struct vr_desc *d; 814 struct vr_descsoft *ds; 815 uint32_t txstat; 816 int i, j; 817 818 ifp->if_flags &= ~IFF_OACTIVE; 819 820 /* 821 * Go through our tx list and free mbufs for those 822 * frames that have been transmitted. 823 */ 824 for (i = sc->vr_txdirty; sc->vr_txpending != 0; 825 i = VR_NEXTTX(i), sc->vr_txpending--) { 826 d = VR_CDTX(sc, i); 827 ds = VR_DSTX(sc, i); 828 829 VR_CDTXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 830 831 txstat = le32toh(d->vr_status); 832 833 if (txstat & (VR_TXSTAT_ABRT | VR_TXSTAT_UDF)) { 834 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 835 for (j = 0; j < VR_TIMEOUT; j++) { 836 DELAY(10); 837 if ((CSR_READ_2(sc, VR_COMMAND) & 838 VR_CMD_TX_ON) == 0) 839 break; 840 } 841 if (j == VR_TIMEOUT) { 842 /* XXX need reset? */ 843 printf("%s: TX shutdown never complete\n", 844 device_xname(sc->vr_dev)); 845 } 846 d->vr_status = htole32(VR_TXSTAT_OWN); 847 CSR_WRITE_4(sc, VR_TXADDR, VR_CDTXADDR(sc, i)); 848 break; 849 } 850 851 if (txstat & VR_TXSTAT_OWN) 852 break; 853 854 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 855 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 856 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 857 m_freem(ds->ds_mbuf); 858 ds->ds_mbuf = NULL; 859 860 if (txstat & VR_TXSTAT_ERRSUM) { 861 ifp->if_oerrors++; 862 if (txstat & VR_TXSTAT_DEFER) 863 ifp->if_collisions++; 864 if (txstat & VR_TXSTAT_LATECOLL) 865 ifp->if_collisions++; 866 } 867 868 ifp->if_collisions += (txstat & VR_TXSTAT_COLLCNT) >> 3; 869 ifp->if_opackets++; 870 } 871 872 /* Update the dirty transmit buffer pointer. */ 873 sc->vr_txdirty = i; 874 875 /* 876 * Cancel the watchdog timer if there are no pending 877 * transmissions. 878 */ 879 if (sc->vr_txpending == 0) 880 ifp->if_timer = 0; 881 } 882 883 static int 884 vr_intr(void *arg) 885 { 886 struct vr_softc *sc; 887 struct ifnet *ifp; 888 uint16_t status; 889 int handled = 0, dotx = 0; 890 891 sc = arg; 892 ifp = &sc->vr_ec.ec_if; 893 894 /* Suppress unwanted interrupts. */ 895 if ((ifp->if_flags & IFF_UP) == 0) { 896 vr_stop(ifp, 1); 897 return (0); 898 } 899 900 /* Disable interrupts. */ 901 CSR_WRITE_2(sc, VR_IMR, 0x0000); 902 903 for (;;) { 904 status = CSR_READ_2(sc, VR_ISR); 905 if (status) 906 CSR_WRITE_2(sc, VR_ISR, status); 907 908 if ((status & VR_INTRS) == 0) 909 break; 910 911 handled = 1; 912 913 #if NRND > 0 914 if (RND_ENABLED(&sc->rnd_source)) 915 rnd_add_uint32(&sc->rnd_source, status); 916 #endif 917 918 if (status & VR_ISR_RX_OK) 919 vr_rxeof(sc); 920 921 if (status & VR_ISR_RX_DROPPED) { 922 printf("%s: rx packet lost\n", device_xname(sc->vr_dev)); 923 ifp->if_ierrors++; 924 } 925 926 if (status & 927 (VR_ISR_RX_ERR | VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW)) 928 vr_rxeoc(sc); 929 930 931 if (status & (VR_ISR_BUSERR | VR_ISR_TX_UNDERRUN)) { 932 if (status & VR_ISR_BUSERR) 933 printf("%s: PCI bus error\n", 934 device_xname(sc->vr_dev)); 935 if (status & VR_ISR_TX_UNDERRUN) 936 printf("%s: transmit underrun\n", 937 device_xname(sc->vr_dev)); 938 /* vr_init() calls vr_start() */ 939 dotx = 0; 940 (void)vr_init(ifp); 941 942 } 943 944 if (status & VR_ISR_TX_OK) { 945 dotx = 1; 946 vr_txeof(sc); 947 } 948 949 if (status & 950 (VR_ISR_TX_ABRT | VR_ISR_TX_ABRT2 | VR_ISR_TX_UDFI)) { 951 if (status & (VR_ISR_TX_ABRT | VR_ISR_TX_ABRT2)) 952 printf("%s: transmit aborted\n", 953 device_xname(sc->vr_dev)); 954 if (status & VR_ISR_TX_UDFI) 955 printf("%s: transmit underflow\n", 956 device_xname(sc->vr_dev)); 957 ifp->if_oerrors++; 958 dotx = 1; 959 vr_txeof(sc); 960 if (sc->vr_txpending) { 961 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 962 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 963 } 964 } 965 } 966 967 /* Re-enable interrupts. */ 968 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 969 970 if (dotx) 971 vr_start(ifp); 972 973 return (handled); 974 } 975 976 /* 977 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 978 * to the mbuf data regions directly in the transmit lists. We also save a 979 * copy of the pointers since the transmit list fragment pointers are 980 * physical addresses. 981 */ 982 static void 983 vr_start(struct ifnet *ifp) 984 { 985 struct vr_softc *sc = ifp->if_softc; 986 struct mbuf *m0, *m; 987 struct vr_desc *d; 988 struct vr_descsoft *ds; 989 int error, firsttx, nexttx, opending; 990 991 /* 992 * Remember the previous txpending and the first transmit 993 * descriptor we use. 994 */ 995 opending = sc->vr_txpending; 996 firsttx = VR_NEXTTX(sc->vr_txlast); 997 998 /* 999 * Loop through the send queue, setting up transmit descriptors 1000 * until we drain the queue, or use up all available transmit 1001 * descriptors. 1002 */ 1003 while (sc->vr_txpending < VR_NTXDESC) { 1004 /* 1005 * Grab a packet off the queue. 1006 */ 1007 IFQ_POLL(&ifp->if_snd, m0); 1008 if (m0 == NULL) 1009 break; 1010 m = NULL; 1011 1012 /* 1013 * Get the next available transmit descriptor. 1014 */ 1015 nexttx = VR_NEXTTX(sc->vr_txlast); 1016 d = VR_CDTX(sc, nexttx); 1017 ds = VR_DSTX(sc, nexttx); 1018 1019 /* 1020 * Load the DMA map. If this fails, the packet didn't 1021 * fit in one DMA segment, and we need to copy. Note, 1022 * the packet must also be aligned. 1023 * if the packet is too small, copy it too, so we're sure 1024 * we have enough room for the pad buffer. 1025 */ 1026 if ((mtod(m0, uintptr_t) & 3) != 0 || 1027 m0->m_pkthdr.len < VR_MIN_FRAMELEN || 1028 bus_dmamap_load_mbuf(sc->vr_dmat, ds->ds_dmamap, m0, 1029 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1030 MGETHDR(m, M_DONTWAIT, MT_DATA); 1031 if (m == NULL) { 1032 printf("%s: unable to allocate Tx mbuf\n", 1033 device_xname(sc->vr_dev)); 1034 break; 1035 } 1036 if (m0->m_pkthdr.len > MHLEN) { 1037 MCLGET(m, M_DONTWAIT); 1038 if ((m->m_flags & M_EXT) == 0) { 1039 printf("%s: unable to allocate Tx " 1040 "cluster\n", device_xname(sc->vr_dev)); 1041 m_freem(m); 1042 break; 1043 } 1044 } 1045 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1046 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1047 /* 1048 * The Rhine doesn't auto-pad, so we have to do this 1049 * ourselves. 1050 */ 1051 if (m0->m_pkthdr.len < VR_MIN_FRAMELEN) { 1052 memset(mtod(m, char *) + m0->m_pkthdr.len, 1053 0, VR_MIN_FRAMELEN - m0->m_pkthdr.len); 1054 m->m_pkthdr.len = m->m_len = VR_MIN_FRAMELEN; 1055 } 1056 error = bus_dmamap_load_mbuf(sc->vr_dmat, 1057 ds->ds_dmamap, m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1058 if (error) { 1059 m_freem(m); 1060 printf("%s: unable to load Tx buffer, " 1061 "error = %d\n", device_xname(sc->vr_dev), error); 1062 break; 1063 } 1064 } 1065 1066 IFQ_DEQUEUE(&ifp->if_snd, m0); 1067 if (m != NULL) { 1068 m_freem(m0); 1069 m0 = m; 1070 } 1071 1072 /* Sync the DMA map. */ 1073 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 1074 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1075 1076 /* 1077 * Store a pointer to the packet so we can free it later. 1078 */ 1079 ds->ds_mbuf = m0; 1080 1081 /* 1082 * If there's a BPF listener, bounce a copy of this frame 1083 * to him. 1084 */ 1085 bpf_mtap(ifp, m0); 1086 1087 /* 1088 * Fill in the transmit descriptor. 1089 */ 1090 d->vr_data = htole32(ds->ds_dmamap->dm_segs[0].ds_addr); 1091 d->vr_ctl = htole32(m0->m_pkthdr.len); 1092 d->vr_ctl |= htole32(VR_TXCTL_FIRSTFRAG | VR_TXCTL_LASTFRAG); 1093 1094 /* 1095 * If this is the first descriptor we're enqueuing, 1096 * don't give it to the Rhine yet. That could cause 1097 * a race condition. We'll do it below. 1098 */ 1099 if (nexttx == firsttx) 1100 d->vr_status = 0; 1101 else 1102 d->vr_status = htole32(VR_TXSTAT_OWN); 1103 1104 VR_CDTXSYNC(sc, nexttx, 1105 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1106 1107 /* Advance the tx pointer. */ 1108 sc->vr_txpending++; 1109 sc->vr_txlast = nexttx; 1110 } 1111 1112 if (sc->vr_txpending == VR_NTXDESC) { 1113 /* No more slots left; notify upper layer. */ 1114 ifp->if_flags |= IFF_OACTIVE; 1115 } 1116 1117 if (sc->vr_txpending != opending) { 1118 /* 1119 * We enqueued packets. If the transmitter was idle, 1120 * reset the txdirty pointer. 1121 */ 1122 if (opending == 0) 1123 sc->vr_txdirty = firsttx; 1124 1125 /* 1126 * Cause a transmit interrupt to happen on the 1127 * last packet we enqueued. 1128 */ 1129 VR_CDTX(sc, sc->vr_txlast)->vr_ctl |= htole32(VR_TXCTL_FINT); 1130 VR_CDTXSYNC(sc, sc->vr_txlast, 1131 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1132 1133 /* 1134 * The entire packet chain is set up. Give the 1135 * first descriptor to the Rhine now. 1136 */ 1137 VR_CDTX(sc, firsttx)->vr_status = htole32(VR_TXSTAT_OWN); 1138 VR_CDTXSYNC(sc, firsttx, 1139 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1140 1141 /* Start the transmitter. */ 1142 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1143 1144 /* Set the watchdog timer in case the chip flakes out. */ 1145 ifp->if_timer = 5; 1146 } 1147 } 1148 1149 /* 1150 * Initialize the interface. Must be called at splnet. 1151 */ 1152 static int 1153 vr_init(struct ifnet *ifp) 1154 { 1155 struct vr_softc *sc = ifp->if_softc; 1156 struct vr_desc *d; 1157 struct vr_descsoft *ds; 1158 int i, error = 0; 1159 1160 /* Cancel pending I/O. */ 1161 vr_stop(ifp, 0); 1162 1163 /* Reset the Rhine to a known state. */ 1164 vr_reset(sc); 1165 1166 /* set DMA length in BCR0 and BCR1 */ 1167 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1168 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1169 1170 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1171 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTH_128BYTES); 1172 1173 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1174 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTH_STORENFWD); 1175 1176 /* set DMA threshold length in RXCFG and TXCFG */ 1177 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1178 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1179 1180 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1181 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1182 1183 /* 1184 * Initialize the transmit descriptor ring. txlast is initialized 1185 * to the end of the list so that it will wrap around to the first 1186 * descriptor when the first packet is transmitted. 1187 */ 1188 for (i = 0; i < VR_NTXDESC; i++) { 1189 d = VR_CDTX(sc, i); 1190 memset(d, 0, sizeof(struct vr_desc)); 1191 d->vr_next = htole32(VR_CDTXADDR(sc, VR_NEXTTX(i))); 1192 VR_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1193 } 1194 sc->vr_txpending = 0; 1195 sc->vr_txdirty = 0; 1196 sc->vr_txlast = VR_NTXDESC - 1; 1197 1198 /* 1199 * Initialize the receive descriptor ring. 1200 */ 1201 for (i = 0; i < VR_NRXDESC; i++) { 1202 ds = VR_DSRX(sc, i); 1203 if (ds->ds_mbuf == NULL) { 1204 if ((error = vr_add_rxbuf(sc, i)) != 0) { 1205 printf("%s: unable to allocate or map rx " 1206 "buffer %d, error = %d\n", 1207 device_xname(sc->vr_dev), i, error); 1208 /* 1209 * XXX Should attempt to run with fewer receive 1210 * XXX buffers instead of just failing. 1211 */ 1212 vr_rxdrain(sc); 1213 goto out; 1214 } 1215 } else 1216 VR_INIT_RXDESC(sc, i); 1217 } 1218 sc->vr_rxptr = 0; 1219 1220 /* If we want promiscuous mode, set the allframes bit. */ 1221 if (ifp->if_flags & IFF_PROMISC) 1222 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1223 else 1224 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1225 1226 /* Set capture broadcast bit to capture broadcast frames. */ 1227 if (ifp->if_flags & IFF_BROADCAST) 1228 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1229 else 1230 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1231 1232 /* Program the multicast filter, if necessary. */ 1233 vr_setmulti(sc); 1234 1235 /* Give the transmit and receive rings to the Rhine. */ 1236 CSR_WRITE_4(sc, VR_RXADDR, VR_CDRXADDR(sc, sc->vr_rxptr)); 1237 CSR_WRITE_4(sc, VR_TXADDR, VR_CDTXADDR(sc, VR_NEXTTX(sc->vr_txlast))); 1238 1239 /* Set current media. */ 1240 if ((error = ether_mediachange(ifp)) != 0) 1241 goto out; 1242 1243 /* Enable receiver and transmitter. */ 1244 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1245 VR_CMD_TX_ON|VR_CMD_RX_ON| 1246 VR_CMD_RX_GO); 1247 1248 /* Enable interrupts. */ 1249 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1250 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1251 1252 ifp->if_flags |= IFF_RUNNING; 1253 ifp->if_flags &= ~IFF_OACTIVE; 1254 1255 /* Start one second timer. */ 1256 callout_reset(&sc->vr_tick_ch, hz, vr_tick, sc); 1257 1258 /* Attempt to start output on the interface. */ 1259 vr_start(ifp); 1260 1261 out: 1262 if (error) 1263 printf("%s: interface not running\n", device_xname(sc->vr_dev)); 1264 return (error); 1265 } 1266 1267 static int 1268 vr_ioctl(struct ifnet *ifp, u_long command, void *data) 1269 { 1270 struct vr_softc *sc = ifp->if_softc; 1271 int s, error = 0; 1272 1273 s = splnet(); 1274 1275 error = ether_ioctl(ifp, command, data); 1276 if (error == ENETRESET) { 1277 /* 1278 * Multicast list has changed; set the hardware filter 1279 * accordingly. 1280 */ 1281 if (ifp->if_flags & IFF_RUNNING) 1282 vr_setmulti(sc); 1283 error = 0; 1284 } 1285 1286 splx(s); 1287 return (error); 1288 } 1289 1290 static void 1291 vr_watchdog(struct ifnet *ifp) 1292 { 1293 struct vr_softc *sc = ifp->if_softc; 1294 1295 printf("%s: device timeout\n", device_xname(sc->vr_dev)); 1296 ifp->if_oerrors++; 1297 1298 (void) vr_init(ifp); 1299 } 1300 1301 /* 1302 * One second timer, used to tick MII. 1303 */ 1304 static void 1305 vr_tick(void *arg) 1306 { 1307 struct vr_softc *sc = arg; 1308 int s; 1309 1310 s = splnet(); 1311 mii_tick(&sc->vr_mii); 1312 splx(s); 1313 1314 callout_reset(&sc->vr_tick_ch, hz, vr_tick, sc); 1315 } 1316 1317 /* 1318 * Drain the receive queue. 1319 */ 1320 static void 1321 vr_rxdrain(struct vr_softc *sc) 1322 { 1323 struct vr_descsoft *ds; 1324 int i; 1325 1326 for (i = 0; i < VR_NRXDESC; i++) { 1327 ds = VR_DSRX(sc, i); 1328 if (ds->ds_mbuf != NULL) { 1329 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 1330 m_freem(ds->ds_mbuf); 1331 ds->ds_mbuf = NULL; 1332 } 1333 } 1334 } 1335 1336 /* 1337 * Stop the adapter and free any mbufs allocated to the 1338 * transmit lists. 1339 */ 1340 static void 1341 vr_stop(struct ifnet *ifp, int disable) 1342 { 1343 struct vr_softc *sc = ifp->if_softc; 1344 struct vr_descsoft *ds; 1345 int i; 1346 1347 /* Cancel one second timer. */ 1348 callout_stop(&sc->vr_tick_ch); 1349 1350 /* Down the MII. */ 1351 mii_down(&sc->vr_mii); 1352 1353 ifp = &sc->vr_ec.ec_if; 1354 ifp->if_timer = 0; 1355 1356 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1357 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1358 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1359 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1360 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1361 1362 /* 1363 * Release any queued transmit buffers. 1364 */ 1365 for (i = 0; i < VR_NTXDESC; i++) { 1366 ds = VR_DSTX(sc, i); 1367 if (ds->ds_mbuf != NULL) { 1368 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 1369 m_freem(ds->ds_mbuf); 1370 ds->ds_mbuf = NULL; 1371 } 1372 } 1373 1374 /* 1375 * Mark the interface down and cancel the watchdog timer. 1376 */ 1377 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1378 ifp->if_timer = 0; 1379 1380 if (disable) 1381 vr_rxdrain(sc); 1382 } 1383 1384 static int vr_probe(device_t, cfdata_t, void *); 1385 static void vr_attach(device_t, device_t, void *); 1386 static bool vr_shutdown(device_t, int); 1387 1388 CFATTACH_DECL_NEW(vr, sizeof (struct vr_softc), 1389 vr_probe, vr_attach, NULL, NULL); 1390 1391 static const struct vr_type * 1392 vr_lookup(struct pci_attach_args *pa) 1393 { 1394 const struct vr_type *vrt; 1395 int i; 1396 1397 for (i = 0; i < __arraycount(vr_devs); i++) { 1398 vrt = &vr_devs[i]; 1399 if (PCI_VENDOR(pa->pa_id) == vrt->vr_vid && 1400 PCI_PRODUCT(pa->pa_id) == vrt->vr_did) 1401 return (vrt); 1402 } 1403 return (NULL); 1404 } 1405 1406 static int 1407 vr_probe(device_t parent, cfdata_t match, void *aux) 1408 { 1409 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1410 1411 if (vr_lookup(pa) != NULL) 1412 return (1); 1413 1414 return (0); 1415 } 1416 1417 /* 1418 * Stop all chip I/O so that the kernel's probe routines don't 1419 * get confused by errant DMAs when rebooting. 1420 */ 1421 static bool 1422 vr_shutdown(device_t self, int howto) 1423 { 1424 struct vr_softc *sc = device_private(self); 1425 1426 vr_stop(&sc->vr_ec.ec_if, 1); 1427 1428 return true; 1429 } 1430 1431 /* 1432 * Attach the interface. Allocate softc structures, do ifmedia 1433 * setup and ethernet/BPF attach. 1434 */ 1435 static void 1436 vr_attach(device_t parent, device_t self, void *aux) 1437 { 1438 struct vr_softc *sc = device_private(self); 1439 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 1440 bus_dma_segment_t seg; 1441 uint32_t reg; 1442 struct ifnet *ifp; 1443 uint8_t eaddr[ETHER_ADDR_LEN], mac; 1444 int i, rseg, error; 1445 char devinfo[256]; 1446 1447 #define PCI_CONF_WRITE(r, v) pci_conf_write(sc->vr_pc, sc->vr_tag, (r), (v)) 1448 #define PCI_CONF_READ(r) pci_conf_read(sc->vr_pc, sc->vr_tag, (r)) 1449 1450 sc->vr_dev = self; 1451 sc->vr_pc = pa->pa_pc; 1452 sc->vr_tag = pa->pa_tag; 1453 sc->vr_id = pa->pa_id; 1454 callout_init(&sc->vr_tick_ch, 0); 1455 1456 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 1457 aprint_naive("\n"); 1458 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 1459 PCI_REVISION(pa->pa_class)); 1460 1461 /* 1462 * Handle power management nonsense. 1463 */ 1464 1465 sc->vr_save_iobase = PCI_CONF_READ(VR_PCI_LOIO); 1466 sc->vr_save_membase = PCI_CONF_READ(VR_PCI_LOMEM); 1467 sc->vr_save_irq = PCI_CONF_READ(PCI_INTERRUPT_REG); 1468 1469 /* power up chip */ 1470 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 1471 vr_restore_state)) && error != EOPNOTSUPP) { 1472 aprint_error_dev(self, "cannot activate %d\n", 1473 error); 1474 return; 1475 } 1476 1477 /* Make sure bus mastering is enabled. */ 1478 reg = PCI_CONF_READ(PCI_COMMAND_STATUS_REG); 1479 reg |= PCI_COMMAND_MASTER_ENABLE; 1480 PCI_CONF_WRITE(PCI_COMMAND_STATUS_REG, reg); 1481 1482 /* Get revision */ 1483 sc->vr_revid = PCI_REVISION(pa->pa_class); 1484 1485 /* 1486 * Map control/status registers. 1487 */ 1488 { 1489 bus_space_tag_t iot, memt; 1490 bus_space_handle_t ioh, memh; 1491 int ioh_valid, memh_valid; 1492 pci_intr_handle_t intrhandle; 1493 const char *intrstr; 1494 1495 ioh_valid = (pci_mapreg_map(pa, VR_PCI_LOIO, 1496 PCI_MAPREG_TYPE_IO, 0, 1497 &iot, &ioh, NULL, NULL) == 0); 1498 memh_valid = (pci_mapreg_map(pa, VR_PCI_LOMEM, 1499 PCI_MAPREG_TYPE_MEM | 1500 PCI_MAPREG_MEM_TYPE_32BIT, 1501 0, &memt, &memh, NULL, NULL) == 0); 1502 #if defined(VR_USEIOSPACE) 1503 if (ioh_valid) { 1504 sc->vr_bst = iot; 1505 sc->vr_bsh = ioh; 1506 } else if (memh_valid) { 1507 sc->vr_bst = memt; 1508 sc->vr_bsh = memh; 1509 } 1510 #else 1511 if (memh_valid) { 1512 sc->vr_bst = memt; 1513 sc->vr_bsh = memh; 1514 } else if (ioh_valid) { 1515 sc->vr_bst = iot; 1516 sc->vr_bsh = ioh; 1517 } 1518 #endif 1519 else { 1520 printf(": unable to map device registers\n"); 1521 return; 1522 } 1523 1524 /* Allocate interrupt */ 1525 if (pci_intr_map(pa, &intrhandle)) { 1526 aprint_error_dev(self, "couldn't map interrupt\n"); 1527 return; 1528 } 1529 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 1530 sc->vr_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 1531 vr_intr, sc); 1532 if (sc->vr_ih == NULL) { 1533 aprint_error_dev(self, "couldn't establish interrupt"); 1534 if (intrstr != NULL) 1535 aprint_error(" at %s", intrstr); 1536 aprint_error("\n"); 1537 } 1538 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 1539 } 1540 1541 /* 1542 * Windows may put the chip in suspend mode when it 1543 * shuts down. Be sure to kick it in the head to wake it 1544 * up again. 1545 * 1546 * Don't touch this register on VT3043 since it causes 1547 * kernel MCHK trap on macppc. 1548 * (Note some VT86C100A chip returns a product ID of VT3043) 1549 */ 1550 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT3043) 1551 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 1552 1553 /* Reset the adapter. */ 1554 vr_reset(sc); 1555 1556 /* 1557 * Get station address. The way the Rhine chips work, 1558 * you're not allowed to directly access the EEPROM once 1559 * they've been programmed a special way. Consequently, 1560 * we need to read the node address from the PAR0 and PAR1 1561 * registers. 1562 * 1563 * XXXSCW: On the Rhine III, setting VR_EECSR_LOAD forces a reload 1564 * of the *whole* EEPROM, not just the MAC address. This is 1565 * pretty pointless since the chip does this automatically 1566 * at powerup/reset. 1567 * I suspect the same thing applies to the other Rhine 1568 * variants, but in the absence of a data sheet for those 1569 * (and the lack of anyone else noticing the problems this 1570 * causes) I'm going to retain the old behaviour for the 1571 * other parts. 1572 * In some cases, the chip really does startup without having 1573 * read the EEPROM (kern/34812). To handle this case, we force 1574 * a reload if we see an all-zeroes MAC address. 1575 */ 1576 for (mac = 0, i = 0; i < ETHER_ADDR_LEN; i++) 1577 mac |= (eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i)); 1578 1579 if (mac == 0 || (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT6105 && 1580 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT6102)) { 1581 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 1582 DELAY(200); 1583 for (i = 0; i < ETHER_ADDR_LEN; i++) 1584 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 1585 } 1586 1587 /* 1588 * A Rhine chip was detected. Inform the world. 1589 */ 1590 aprint_normal("%s: Ethernet address: %s\n", 1591 device_xname(self), ether_sprintf(eaddr)); 1592 1593 memcpy(sc->vr_enaddr, eaddr, ETHER_ADDR_LEN); 1594 1595 sc->vr_dmat = pa->pa_dmat; 1596 1597 /* 1598 * Allocate the control data structures, and create and load 1599 * the DMA map for it. 1600 */ 1601 if ((error = bus_dmamem_alloc(sc->vr_dmat, 1602 sizeof(struct vr_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 1603 0)) != 0) { 1604 aprint_error_dev(self, "unable to allocate control data, error = %d\n", error); 1605 goto fail_0; 1606 } 1607 1608 if ((error = bus_dmamem_map(sc->vr_dmat, &seg, rseg, 1609 sizeof(struct vr_control_data), (void **)&sc->vr_control_data, 1610 BUS_DMA_COHERENT)) != 0) { 1611 aprint_error_dev(self, "unable to map control data, error = %d\n", error); 1612 goto fail_1; 1613 } 1614 1615 if ((error = bus_dmamap_create(sc->vr_dmat, 1616 sizeof(struct vr_control_data), 1, 1617 sizeof(struct vr_control_data), 0, 0, 1618 &sc->vr_cddmamap)) != 0) { 1619 aprint_error_dev(self, "unable to create control data DMA map, " 1620 "error = %d\n", error); 1621 goto fail_2; 1622 } 1623 1624 if ((error = bus_dmamap_load(sc->vr_dmat, sc->vr_cddmamap, 1625 sc->vr_control_data, sizeof(struct vr_control_data), NULL, 1626 0)) != 0) { 1627 aprint_error_dev(self, "unable to load control data DMA map, error = %d\n", 1628 error); 1629 goto fail_3; 1630 } 1631 1632 /* 1633 * Create the transmit buffer DMA maps. 1634 */ 1635 for (i = 0; i < VR_NTXDESC; i++) { 1636 if ((error = bus_dmamap_create(sc->vr_dmat, MCLBYTES, 1637 1, MCLBYTES, 0, 0, 1638 &VR_DSTX(sc, i)->ds_dmamap)) != 0) { 1639 aprint_error_dev(self, "unable to create tx DMA map %d, " 1640 "error = %d\n", i, error); 1641 goto fail_4; 1642 } 1643 } 1644 1645 /* 1646 * Create the receive buffer DMA maps. 1647 */ 1648 for (i = 0; i < VR_NRXDESC; i++) { 1649 if ((error = bus_dmamap_create(sc->vr_dmat, MCLBYTES, 1, 1650 MCLBYTES, 0, 0, 1651 &VR_DSRX(sc, i)->ds_dmamap)) != 0) { 1652 aprint_error_dev(self, "unable to create rx DMA map %d, " 1653 "error = %d\n", i, error); 1654 goto fail_5; 1655 } 1656 VR_DSRX(sc, i)->ds_mbuf = NULL; 1657 } 1658 1659 ifp = &sc->vr_ec.ec_if; 1660 ifp->if_softc = sc; 1661 ifp->if_mtu = ETHERMTU; 1662 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1663 ifp->if_ioctl = vr_ioctl; 1664 ifp->if_start = vr_start; 1665 ifp->if_watchdog = vr_watchdog; 1666 ifp->if_init = vr_init; 1667 ifp->if_stop = vr_stop; 1668 IFQ_SET_READY(&ifp->if_snd); 1669 1670 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 1671 1672 /* 1673 * Initialize MII/media info. 1674 */ 1675 sc->vr_mii.mii_ifp = ifp; 1676 sc->vr_mii.mii_readreg = vr_mii_readreg; 1677 sc->vr_mii.mii_writereg = vr_mii_writereg; 1678 sc->vr_mii.mii_statchg = vr_mii_statchg; 1679 1680 sc->vr_ec.ec_mii = &sc->vr_mii; 1681 ifmedia_init(&sc->vr_mii.mii_media, IFM_IMASK, ether_mediachange, 1682 ether_mediastatus); 1683 mii_attach(self, &sc->vr_mii, 0xffffffff, MII_PHY_ANY, 1684 MII_OFFSET_ANY, MIIF_FORCEANEG); 1685 if (LIST_FIRST(&sc->vr_mii.mii_phys) == NULL) { 1686 ifmedia_add(&sc->vr_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1687 ifmedia_set(&sc->vr_mii.mii_media, IFM_ETHER|IFM_NONE); 1688 } else 1689 ifmedia_set(&sc->vr_mii.mii_media, IFM_ETHER|IFM_AUTO); 1690 1691 /* 1692 * Call MI attach routines. 1693 */ 1694 if_attach(ifp); 1695 ether_ifattach(ifp, sc->vr_enaddr); 1696 #if NRND > 0 1697 rnd_attach_source(&sc->rnd_source, device_xname(self), 1698 RND_TYPE_NET, 0); 1699 #endif 1700 1701 if (pmf_device_register1(self, NULL, vr_resume, vr_shutdown)) 1702 pmf_class_network_register(self, ifp); 1703 else 1704 aprint_error_dev(self, "couldn't establish power handler\n"); 1705 1706 return; 1707 1708 fail_5: 1709 for (i = 0; i < VR_NRXDESC; i++) { 1710 if (sc->vr_rxsoft[i].ds_dmamap != NULL) 1711 bus_dmamap_destroy(sc->vr_dmat, 1712 sc->vr_rxsoft[i].ds_dmamap); 1713 } 1714 fail_4: 1715 for (i = 0; i < VR_NTXDESC; i++) { 1716 if (sc->vr_txsoft[i].ds_dmamap != NULL) 1717 bus_dmamap_destroy(sc->vr_dmat, 1718 sc->vr_txsoft[i].ds_dmamap); 1719 } 1720 bus_dmamap_unload(sc->vr_dmat, sc->vr_cddmamap); 1721 fail_3: 1722 bus_dmamap_destroy(sc->vr_dmat, sc->vr_cddmamap); 1723 fail_2: 1724 bus_dmamem_unmap(sc->vr_dmat, (void *)sc->vr_control_data, 1725 sizeof(struct vr_control_data)); 1726 fail_1: 1727 bus_dmamem_free(sc->vr_dmat, &seg, rseg); 1728 fail_0: 1729 return; 1730 } 1731 1732 static int 1733 vr_restore_state(pci_chipset_tag_t pc, pcitag_t tag, device_t self, 1734 pcireg_t state) 1735 { 1736 struct vr_softc *sc = device_private(self); 1737 int error; 1738 1739 if (state == PCI_PMCSR_STATE_D0) 1740 return 0; 1741 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 1742 return error; 1743 1744 /* Restore PCI config data. */ 1745 PCI_CONF_WRITE(VR_PCI_LOIO, sc->vr_save_iobase); 1746 PCI_CONF_WRITE(VR_PCI_LOMEM, sc->vr_save_membase); 1747 PCI_CONF_WRITE(PCI_INTERRUPT_REG, sc->vr_save_irq); 1748 return 0; 1749 } 1750 1751 static bool 1752 vr_resume(device_t self, const pmf_qual_t *qual) 1753 { 1754 struct vr_softc *sc = device_private(self); 1755 1756 if (PCI_PRODUCT(sc->vr_id) != PCI_PRODUCT_VIATECH_VT3043) 1757 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 1758 1759 return true; 1760 } 1761