1 /* $NetBSD: if_vr.c,v 1.135 2021/07/24 22:30:59 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1997, 1998 35 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Bill Paul. 48 * 4. Neither the name of the author nor the names of any co-contributors 49 * may be used to endorse or promote products derived from this software 50 * without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 56 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 57 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 58 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 59 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 60 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 61 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 62 * THE POSSIBILITY OF SUCH DAMAGE. 63 * 64 * $FreeBSD: if_vr.c,v 1.7 1999/01/10 18:51:49 wpaul Exp $ 65 */ 66 67 /* 68 * VIA Rhine fast ethernet PCI NIC driver 69 * 70 * Supports various network adapters based on the VIA Rhine 71 * and Rhine II PCI controllers, including the D-Link DFE530TX. 72 * Datasheets are available at http://www.via.com.tw. 73 * 74 * Written by Bill Paul <wpaul@ctr.columbia.edu> 75 * Electrical Engineering Department 76 * Columbia University, New York City 77 */ 78 79 /* 80 * The VIA Rhine controllers are similar in some respects to the 81 * the DEC tulip chips, except less complicated. The controller 82 * uses an MII bus and an external physical layer interface. The 83 * receiver has a one entry perfect filter and a 64-bit hash table 84 * multicast filter. Transmit and receive descriptors are similar 85 * to the tulip. 86 * 87 * The Rhine has a serious flaw in its transmit DMA mechanism: 88 * transmit buffers must be longword aligned. Unfortunately, 89 * the kernel doesn't guarantee that mbufs will be filled in starting 90 * at longword boundaries, so we have to do a buffer copy before 91 * transmission. 92 * 93 * Apparently, the receive DMA mechanism also has the same flaw. This 94 * means that on systems with struct alignment requirements, incoming 95 * frames must be copied to a new buffer which shifts the data forward 96 * 2 bytes so that the payload is aligned on a 4-byte boundary. 97 */ 98 99 #include <sys/cdefs.h> 100 __KERNEL_RCSID(0, "$NetBSD: if_vr.c,v 1.135 2021/07/24 22:30:59 andvar Exp $"); 101 102 103 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/callout.h> 107 #include <sys/sockio.h> 108 #include <sys/mbuf.h> 109 #include <sys/malloc.h> 110 #include <sys/kernel.h> 111 #include <sys/socket.h> 112 #include <sys/device.h> 113 114 #include <sys/rndsource.h> 115 116 #include <net/if.h> 117 #include <net/if_arp.h> 118 #include <net/if_dl.h> 119 #include <net/if_media.h> 120 #include <net/if_ether.h> 121 122 #include <net/bpf.h> 123 124 #include <sys/bus.h> 125 #include <sys/intr.h> 126 #include <machine/endian.h> 127 128 #include <dev/mii/mii.h> 129 #include <dev/mii/miivar.h> 130 #include <dev/mii/mii_bitbang.h> 131 132 #include <dev/pci/pcireg.h> 133 #include <dev/pci/pcivar.h> 134 #include <dev/pci/pcidevs.h> 135 136 #include <dev/pci/if_vrreg.h> 137 138 #define VR_USEIOSPACE 139 140 /* 141 * Various supported device vendors/types and their names. 142 */ 143 static const struct device_compatible_entry compat_data[] = { 144 { .id = PCI_ID_CODE(PCI_VENDOR_VIATECH, 145 PCI_PRODUCT_VIATECH_VT3043) }, 146 147 { .id = PCI_ID_CODE(PCI_VENDOR_VIATECH, 148 PCI_PRODUCT_VIATECH_VT6102) }, 149 150 { .id = PCI_ID_CODE(PCI_VENDOR_VIATECH, 151 PCI_PRODUCT_VIATECH_VT6105) }, 152 153 { .id = PCI_ID_CODE(PCI_VENDOR_VIATECH, 154 PCI_PRODUCT_VIATECH_VT6105M) }, 155 156 { .id = PCI_ID_CODE(PCI_VENDOR_VIATECH, 157 PCI_PRODUCT_VIATECH_VT86C100A) }, 158 159 PCI_COMPAT_EOL 160 }; 161 162 /* 163 * Transmit descriptor list size. 164 */ 165 #define VR_NTXDESC 64 166 #define VR_NTXDESC_MASK (VR_NTXDESC - 1) 167 #define VR_NEXTTX(x) (((x) + 1) & VR_NTXDESC_MASK) 168 169 /* 170 * Receive descriptor list size. 171 */ 172 #define VR_NRXDESC 64 173 #define VR_NRXDESC_MASK (VR_NRXDESC - 1) 174 #define VR_NEXTRX(x) (((x) + 1) & VR_NRXDESC_MASK) 175 176 /* 177 * Control data structures that are DMA'd to the Rhine chip. We allocate 178 * them in a single clump that maps to a single DMA segment to make several 179 * things easier. 180 * 181 * Note that since we always copy outgoing packets to aligned transmit 182 * buffers, we can reduce the transmit descriptors to one per packet. 183 */ 184 struct vr_control_data { 185 struct vr_desc vr_txdescs[VR_NTXDESC]; 186 struct vr_desc vr_rxdescs[VR_NRXDESC]; 187 }; 188 189 #define VR_CDOFF(x) offsetof(struct vr_control_data, x) 190 #define VR_CDTXOFF(x) VR_CDOFF(vr_txdescs[(x)]) 191 #define VR_CDRXOFF(x) VR_CDOFF(vr_rxdescs[(x)]) 192 193 /* 194 * Software state of transmit and receive descriptors. 195 */ 196 struct vr_descsoft { 197 struct mbuf *ds_mbuf; /* head of mbuf chain */ 198 bus_dmamap_t ds_dmamap; /* our DMA map */ 199 }; 200 201 struct vr_softc { 202 device_t vr_dev; 203 void *vr_ih; /* interrupt cookie */ 204 bus_space_tag_t vr_bst; /* bus space tag */ 205 bus_space_handle_t vr_bsh; /* bus space handle */ 206 bus_dma_tag_t vr_dmat; /* bus DMA tag */ 207 pci_chipset_tag_t vr_pc; /* PCI chipset info */ 208 pcitag_t vr_tag; /* PCI tag */ 209 struct ethercom vr_ec; /* Ethernet common info */ 210 uint8_t vr_enaddr[ETHER_ADDR_LEN]; 211 struct mii_data vr_mii; /* MII/media info */ 212 213 pcireg_t vr_id; /* vendor/product ID */ 214 uint8_t vr_revid; /* Rhine chip revision */ 215 216 callout_t vr_tick_ch; /* tick callout */ 217 218 bus_dmamap_t vr_cddmamap; /* control data DMA map */ 219 #define vr_cddma vr_cddmamap->dm_segs[0].ds_addr 220 221 /* 222 * Software state for transmit and receive descriptors. 223 */ 224 struct vr_descsoft vr_txsoft[VR_NTXDESC]; 225 struct vr_descsoft vr_rxsoft[VR_NRXDESC]; 226 227 /* 228 * Control data structures. 229 */ 230 struct vr_control_data *vr_control_data; 231 232 int vr_txpending; /* number of TX requests pending */ 233 int vr_txdirty; /* first dirty TX descriptor */ 234 int vr_txlast; /* last used TX descriptor */ 235 236 int vr_rxptr; /* next ready RX descriptor */ 237 238 uint32_t vr_save_iobase; 239 uint32_t vr_save_membase; 240 uint32_t vr_save_irq; 241 242 bool vr_link; 243 int vr_flags; 244 #define VR_F_RESTART 0x1 /* restart on next tick */ 245 u_short vr_if_flags; 246 247 krndsource_t rnd_source; /* random source */ 248 }; 249 250 #define VR_CDTXADDR(sc, x) ((sc)->vr_cddma + VR_CDTXOFF((x))) 251 #define VR_CDRXADDR(sc, x) ((sc)->vr_cddma + VR_CDRXOFF((x))) 252 253 #define VR_CDTX(sc, x) (&(sc)->vr_control_data->vr_txdescs[(x)]) 254 #define VR_CDRX(sc, x) (&(sc)->vr_control_data->vr_rxdescs[(x)]) 255 256 #define VR_DSTX(sc, x) (&(sc)->vr_txsoft[(x)]) 257 #define VR_DSRX(sc, x) (&(sc)->vr_rxsoft[(x)]) 258 259 #define VR_CDTXSYNC(sc, x, ops) \ 260 bus_dmamap_sync((sc)->vr_dmat, (sc)->vr_cddmamap, \ 261 VR_CDTXOFF((x)), sizeof(struct vr_desc), (ops)) 262 263 #define VR_CDRXSYNC(sc, x, ops) \ 264 bus_dmamap_sync((sc)->vr_dmat, (sc)->vr_cddmamap, \ 265 VR_CDRXOFF((x)), sizeof(struct vr_desc), (ops)) 266 267 /* 268 * Note we rely on MCLBYTES being a power of two below. 269 */ 270 #define VR_INIT_RXDESC(sc, i) \ 271 do { \ 272 struct vr_desc *__d = VR_CDRX((sc), (i)); \ 273 struct vr_descsoft *__ds = VR_DSRX((sc), (i)); \ 274 \ 275 __d->vr_next = htole32(VR_CDRXADDR((sc), VR_NEXTRX((i)))); \ 276 __d->vr_data = htole32(__ds->ds_dmamap->dm_segs[0].ds_addr); \ 277 __d->vr_ctl = htole32(VR_RXCTL_CHAIN | VR_RXCTL_RX_INTR | \ 278 ((MCLBYTES - 1) & VR_RXCTL_BUFLEN)); \ 279 __d->vr_status = htole32(VR_RXSTAT_FIRSTFRAG | \ 280 VR_RXSTAT_LASTFRAG | VR_RXSTAT_OWN); \ 281 VR_CDRXSYNC((sc), (i), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); \ 282 } while (/* CONSTCOND */ 0) 283 284 /* 285 * register space access macros 286 */ 287 #define CSR_WRITE_4(sc, reg, val) \ 288 bus_space_write_4(sc->vr_bst, sc->vr_bsh, reg, val) 289 #define CSR_WRITE_2(sc, reg, val) \ 290 bus_space_write_2(sc->vr_bst, sc->vr_bsh, reg, val) 291 #define CSR_WRITE_1(sc, reg, val) \ 292 bus_space_write_1(sc->vr_bst, sc->vr_bsh, reg, val) 293 294 #define CSR_READ_4(sc, reg) \ 295 bus_space_read_4(sc->vr_bst, sc->vr_bsh, reg) 296 #define CSR_READ_2(sc, reg) \ 297 bus_space_read_2(sc->vr_bst, sc->vr_bsh, reg) 298 #define CSR_READ_1(sc, reg) \ 299 bus_space_read_1(sc->vr_bst, sc->vr_bsh, reg) 300 301 #define VR_TIMEOUT 1000 302 303 static int vr_add_rxbuf(struct vr_softc *, int); 304 305 static void vr_rxeof(struct vr_softc *); 306 static void vr_rxeoc(struct vr_softc *); 307 static void vr_txeof(struct vr_softc *); 308 static int vr_intr(void *); 309 static void vr_start(struct ifnet *); 310 static int vr_ioctl(struct ifnet *, u_long, void *); 311 static int vr_init(struct ifnet *); 312 static void vr_stop(struct ifnet *, int); 313 static void vr_rxdrain(struct vr_softc *); 314 static void vr_watchdog(struct ifnet *); 315 static void vr_tick(void *); 316 317 static int vr_mii_readreg(device_t, int, int, uint16_t *); 318 static int vr_mii_writereg(device_t, int, int, uint16_t); 319 static void vr_mii_statchg(struct ifnet *); 320 321 static void vr_setmulti(struct vr_softc *); 322 static void vr_reset(struct vr_softc *); 323 static int vr_restore_state(pci_chipset_tag_t, pcitag_t, device_t, 324 pcireg_t); 325 static bool vr_resume(device_t, const pmf_qual_t *); 326 327 int vr_copy_small = 0; 328 329 #define VR_SETBIT(sc, reg, x) \ 330 CSR_WRITE_1(sc, reg, \ 331 CSR_READ_1(sc, reg) | (x)) 332 333 #define VR_CLRBIT(sc, reg, x) \ 334 CSR_WRITE_1(sc, reg, \ 335 CSR_READ_1(sc, reg) & ~(x)) 336 337 #define VR_SETBIT16(sc, reg, x) \ 338 CSR_WRITE_2(sc, reg, \ 339 CSR_READ_2(sc, reg) | (x)) 340 341 #define VR_CLRBIT16(sc, reg, x) \ 342 CSR_WRITE_2(sc, reg, \ 343 CSR_READ_2(sc, reg) & ~(x)) 344 345 #define VR_SETBIT32(sc, reg, x) \ 346 CSR_WRITE_4(sc, reg, \ 347 CSR_READ_4(sc, reg) | (x)) 348 349 #define VR_CLRBIT32(sc, reg, x) \ 350 CSR_WRITE_4(sc, reg, \ 351 CSR_READ_4(sc, reg) & ~(x)) 352 353 /* 354 * MII bit-bang glue. 355 */ 356 static uint32_t vr_mii_bitbang_read(device_t); 357 static void vr_mii_bitbang_write(device_t, uint32_t); 358 359 static const struct mii_bitbang_ops vr_mii_bitbang_ops = { 360 vr_mii_bitbang_read, 361 vr_mii_bitbang_write, 362 { 363 VR_MIICMD_DATAOUT, /* MII_BIT_MDO */ 364 VR_MIICMD_DATAIN, /* MII_BIT_MDI */ 365 VR_MIICMD_CLK, /* MII_BIT_MDC */ 366 VR_MIICMD_DIR, /* MII_BIT_DIR_HOST_PHY */ 367 0, /* MII_BIT_DIR_PHY_HOST */ 368 } 369 }; 370 371 static uint32_t 372 vr_mii_bitbang_read(device_t self) 373 { 374 struct vr_softc *sc = device_private(self); 375 376 return (CSR_READ_1(sc, VR_MIICMD)); 377 } 378 379 static void 380 vr_mii_bitbang_write(device_t self, uint32_t val) 381 { 382 struct vr_softc *sc = device_private(self); 383 384 CSR_WRITE_1(sc, VR_MIICMD, (val & 0xff) | VR_MIICMD_DIRECTPGM); 385 } 386 387 /* 388 * Read an PHY register through the MII. 389 */ 390 static int 391 vr_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 392 { 393 struct vr_softc *sc = device_private(self); 394 395 CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 396 return (mii_bitbang_readreg(self, &vr_mii_bitbang_ops, phy, reg, val)); 397 } 398 399 /* 400 * Write to a PHY register through the MII. 401 */ 402 static int 403 vr_mii_writereg(device_t self, int phy, int reg, uint16_t val) 404 { 405 struct vr_softc *sc = device_private(self); 406 407 CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 408 return mii_bitbang_writereg(self, &vr_mii_bitbang_ops, phy, reg, val); 409 } 410 411 static void 412 vr_mii_statchg(struct ifnet *ifp) 413 { 414 struct vr_softc *sc = ifp->if_softc; 415 int i; 416 417 /* 418 * In order to fiddle with the 'full-duplex' bit in the netconfig 419 * register, we first have to put the transmit and/or receive logic 420 * in the idle state. 421 */ 422 if ((sc->vr_mii.mii_media_status & IFM_ACTIVE) && 423 IFM_SUBTYPE(sc->vr_mii.mii_media_active) != IFM_NONE) { 424 sc->vr_link = true; 425 426 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON | VR_CMD_RX_ON)) 427 VR_CLRBIT16(sc, VR_COMMAND, 428 (VR_CMD_TX_ON | VR_CMD_RX_ON)); 429 430 if (sc->vr_mii.mii_media_active & IFM_FDX) 431 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 432 else 433 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 434 435 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON | VR_CMD_RX_ON); 436 } else { 437 sc->vr_link = false; 438 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_TX_ON | VR_CMD_RX_ON); 439 for (i = VR_TIMEOUT; i > 0; i--) { 440 delay(10); 441 if (!(CSR_READ_2(sc, VR_COMMAND) & 442 (VR_CMD_TX_ON | VR_CMD_RX_ON))) 443 break; 444 } 445 if (i == 0) { 446 #ifdef VR_DEBUG 447 aprint_error_dev(sc->vr_dev, "rx shutdown error!\n"); 448 #endif 449 sc->vr_flags |= VR_F_RESTART; 450 } 451 } 452 } 453 454 #define vr_calchash(addr) \ 455 (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26) 456 457 /* 458 * Program the 64-bit multicast hash filter. 459 */ 460 static void 461 vr_setmulti(struct vr_softc *sc) 462 { 463 struct ethercom *ec = &sc->vr_ec; 464 struct ifnet *ifp = &ec->ec_if; 465 int h = 0; 466 uint32_t hashes[2] = { 0, 0 }; 467 struct ether_multistep step; 468 struct ether_multi *enm; 469 int mcnt = 0; 470 uint8_t rxfilt; 471 472 rxfilt = CSR_READ_1(sc, VR_RXCFG); 473 474 if (ifp->if_flags & IFF_PROMISC) { 475 allmulti: 476 ifp->if_flags |= IFF_ALLMULTI; 477 rxfilt |= VR_RXCFG_RX_MULTI; 478 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 479 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 480 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 481 return; 482 } 483 484 /* first, zot all the existing hash bits */ 485 CSR_WRITE_4(sc, VR_MAR0, 0); 486 CSR_WRITE_4(sc, VR_MAR1, 0); 487 488 /* now program new ones */ 489 ETHER_LOCK(ec); 490 ETHER_FIRST_MULTI(step, ec, enm); 491 while (enm != NULL) { 492 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 493 ETHER_ADDR_LEN) != 0) { 494 ETHER_UNLOCK(ec); 495 goto allmulti; 496 } 497 498 h = vr_calchash(enm->enm_addrlo); 499 500 if (h < 32) 501 hashes[0] |= (1 << h); 502 else 503 hashes[1] |= (1 << (h - 32)); 504 ETHER_NEXT_MULTI(step, enm); 505 mcnt++; 506 } 507 ETHER_UNLOCK(ec); 508 509 ifp->if_flags &= ~IFF_ALLMULTI; 510 511 if (mcnt) 512 rxfilt |= VR_RXCFG_RX_MULTI; 513 else 514 rxfilt &= ~VR_RXCFG_RX_MULTI; 515 516 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 517 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 518 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 519 } 520 521 static void 522 vr_reset(struct vr_softc *sc) 523 { 524 int i; 525 526 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 527 528 for (i = 0; i < VR_TIMEOUT; i++) { 529 DELAY(10); 530 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 531 break; 532 } 533 if (i == VR_TIMEOUT) { 534 if (sc->vr_revid < REV_ID_VT3065_A) { 535 aprint_error_dev(sc->vr_dev, 536 "reset never completed!\n"); 537 } else { 538 /* Use newer force reset command */ 539 aprint_normal_dev(sc->vr_dev, 540 "using force reset command.\n"); 541 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 542 } 543 } 544 545 /* Wait a little while for the chip to get its brains in order. */ 546 DELAY(1000); 547 } 548 549 /* 550 * Initialize an RX descriptor and attach an MBUF cluster. 551 * Note: the length fields are only 11 bits wide, which means the 552 * largest size we can specify is 2047. This is important because 553 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 554 * overflow the field and make a mess. 555 */ 556 static int 557 vr_add_rxbuf(struct vr_softc *sc, int i) 558 { 559 struct vr_descsoft *ds = VR_DSRX(sc, i); 560 struct mbuf *m_new; 561 int error; 562 563 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 564 if (m_new == NULL) 565 return (ENOBUFS); 566 567 MCLGET(m_new, M_DONTWAIT); 568 if ((m_new->m_flags & M_EXT) == 0) { 569 m_freem(m_new); 570 return (ENOBUFS); 571 } 572 573 if (ds->ds_mbuf != NULL) 574 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 575 576 ds->ds_mbuf = m_new; 577 578 error = bus_dmamap_load(sc->vr_dmat, ds->ds_dmamap, 579 m_new->m_ext.ext_buf, m_new->m_ext.ext_size, NULL, 580 BUS_DMA_READ | BUS_DMA_NOWAIT); 581 if (error) { 582 aprint_error_dev(sc->vr_dev, 583 "unable to load rx DMA map %d, error = %d\n", i, error); 584 panic("vr_add_rxbuf"); /* XXX */ 585 } 586 587 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 588 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 589 590 VR_INIT_RXDESC(sc, i); 591 592 return (0); 593 } 594 595 /* 596 * A frame has been uploaded: pass the resulting mbuf chain up to 597 * the higher level protocols. 598 */ 599 static void 600 vr_rxeof(struct vr_softc *sc) 601 { 602 struct mbuf *m; 603 struct ifnet *ifp; 604 struct vr_desc *d; 605 struct vr_descsoft *ds; 606 int i, total_len; 607 uint32_t rxstat; 608 609 ifp = &sc->vr_ec.ec_if; 610 611 for (i = sc->vr_rxptr;; i = VR_NEXTRX(i)) { 612 d = VR_CDRX(sc, i); 613 ds = VR_DSRX(sc, i); 614 615 VR_CDRXSYNC(sc, i, 616 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 617 618 rxstat = le32toh(d->vr_status); 619 620 if (rxstat & VR_RXSTAT_OWN) { 621 /* 622 * We have processed all of the receive buffers. 623 */ 624 break; 625 } 626 627 /* 628 * If an error occurs, update stats, clear the 629 * status word and leave the mbuf cluster in place: 630 * it should simply get re-used next time this descriptor 631 * comes up in the ring. 632 */ 633 if (rxstat & VR_RXSTAT_RXERR) { 634 const char *errstr; 635 636 if_statinc(ifp, if_ierrors); 637 switch (rxstat & 0x000000FF) { 638 case VR_RXSTAT_CRCERR: 639 errstr = "crc error"; 640 break; 641 case VR_RXSTAT_FRAMEALIGNERR: 642 errstr = "frame alignment error"; 643 break; 644 case VR_RXSTAT_FIFOOFLOW: 645 errstr = "FIFO overflow"; 646 break; 647 case VR_RXSTAT_GIANT: 648 errstr = "received giant packet"; 649 break; 650 case VR_RXSTAT_RUNT: 651 errstr = "received runt packet"; 652 break; 653 case VR_RXSTAT_BUSERR: 654 errstr = "system bus error"; 655 break; 656 case VR_RXSTAT_BUFFERR: 657 errstr = "rx buffer error"; 658 break; 659 default: 660 errstr = "unknown rx error"; 661 break; 662 } 663 aprint_error_dev(sc->vr_dev, "receive error: %s\n", 664 errstr); 665 666 VR_INIT_RXDESC(sc, i); 667 668 continue; 669 } else if (!(rxstat & VR_RXSTAT_FIRSTFRAG) || 670 !(rxstat & VR_RXSTAT_LASTFRAG)) { 671 /* 672 * This driver expects to receive whole packets every 673 * time. In case we receive a fragment that is not 674 * a complete packet, we discard it. 675 */ 676 if_statinc(ifp, if_ierrors); 677 678 aprint_error_dev(sc->vr_dev, 679 "receive error: incomplete frame; " 680 "size = %d, status = 0x%x\n", 681 VR_RXBYTES(le32toh(d->vr_status)), rxstat); 682 683 VR_INIT_RXDESC(sc, i); 684 685 continue; 686 } 687 688 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 689 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 690 691 /* No errors; receive the packet. */ 692 total_len = VR_RXBYTES(le32toh(d->vr_status)); 693 #ifdef DIAGNOSTIC 694 if (total_len == 0) { 695 /* 696 * If we receive a zero-length packet, we probably 697 * missed to handle an error condition above. 698 * Discard it to avoid a later crash. 699 */ 700 if_statinc(ifp, if_ierrors); 701 702 aprint_error_dev(sc->vr_dev, 703 "receive error: zero-length packet; " 704 "status = 0x%x\n", rxstat); 705 706 VR_INIT_RXDESC(sc, i); 707 708 continue; 709 } 710 #endif 711 712 /* 713 * The Rhine chip includes the CRC with every packet. 714 * Trim it off here. 715 */ 716 total_len -= ETHER_CRC_LEN; 717 718 #ifdef __NO_STRICT_ALIGNMENT 719 /* 720 * If the packet is small enough to fit in a 721 * single header mbuf, allocate one and copy 722 * the data into it. This greatly reduces 723 * memory consumption when we receive lots 724 * of small packets. 725 * 726 * Otherwise, we add a new buffer to the receive 727 * chain. If this fails, we drop the packet and 728 * recycle the old buffer. 729 */ 730 if (vr_copy_small != 0 && total_len <= MHLEN) { 731 MGETHDR(m, M_DONTWAIT, MT_DATA); 732 if (m == NULL) 733 goto dropit; 734 memcpy(mtod(m, void *), 735 mtod(ds->ds_mbuf, void *), total_len); 736 VR_INIT_RXDESC(sc, i); 737 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 738 ds->ds_dmamap->dm_mapsize, 739 BUS_DMASYNC_PREREAD); 740 } else { 741 m = ds->ds_mbuf; 742 if (vr_add_rxbuf(sc, i) == ENOBUFS) { 743 dropit: 744 if_statinc(ifp, if_ierrors); 745 VR_INIT_RXDESC(sc, i); 746 bus_dmamap_sync(sc->vr_dmat, 747 ds->ds_dmamap, 0, 748 ds->ds_dmamap->dm_mapsize, 749 BUS_DMASYNC_PREREAD); 750 continue; 751 } 752 } 753 #else 754 /* 755 * The Rhine's packet buffers must be 4-byte aligned. 756 * But this means that the data after the Ethernet header 757 * is misaligned. We must allocate a new buffer and 758 * copy the data, shifted forward 2 bytes. 759 */ 760 MGETHDR(m, M_DONTWAIT, MT_DATA); 761 if (m == NULL) { 762 dropit: 763 if_statinc(ifp, if_ierrors); 764 VR_INIT_RXDESC(sc, i); 765 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 766 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 767 continue; 768 } 769 if (total_len > (MHLEN - 2)) { 770 MCLGET(m, M_DONTWAIT); 771 if ((m->m_flags & M_EXT) == 0) { 772 m_freem(m); 773 goto dropit; 774 } 775 } 776 m->m_data += 2; 777 778 /* 779 * Note that we use clusters for incoming frames, so the 780 * buffer is virtually contiguous. 781 */ 782 memcpy(mtod(m, void *), mtod(ds->ds_mbuf, void *), 783 total_len); 784 785 /* Allow the receive descriptor to continue using its mbuf. */ 786 VR_INIT_RXDESC(sc, i); 787 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 788 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 789 #endif /* __NO_STRICT_ALIGNMENT */ 790 791 m_set_rcvif(m, ifp); 792 m->m_pkthdr.len = m->m_len = total_len; 793 /* Pass it on. */ 794 if_percpuq_enqueue(ifp->if_percpuq, m); 795 } 796 797 /* Update the receive pointer. */ 798 sc->vr_rxptr = i; 799 } 800 801 void 802 vr_rxeoc(struct vr_softc *sc) 803 { 804 struct ifnet *ifp; 805 int i; 806 807 ifp = &sc->vr_ec.ec_if; 808 809 if_statinc(ifp, if_ierrors); 810 811 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 812 for (i = 0; i < VR_TIMEOUT; i++) { 813 DELAY(10); 814 if ((CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON) == 0) 815 break; 816 } 817 if (i == VR_TIMEOUT) { 818 /* XXX need reset? */ 819 aprint_error_dev(sc->vr_dev, "RX shutdown never completed\n"); 820 } 821 822 vr_rxeof(sc); 823 824 CSR_WRITE_4(sc, VR_RXADDR, VR_CDRXADDR(sc, sc->vr_rxptr)); 825 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 826 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 827 } 828 829 /* 830 * A frame was downloaded to the chip. It's safe for us to clean up 831 * the list buffers. 832 */ 833 static void 834 vr_txeof(struct vr_softc *sc) 835 { 836 struct ifnet *ifp = &sc->vr_ec.ec_if; 837 struct vr_desc *d; 838 struct vr_descsoft *ds; 839 uint32_t txstat; 840 int i, j; 841 842 ifp->if_flags &= ~IFF_OACTIVE; 843 844 /* 845 * Go through our tx list and free mbufs for those 846 * frames that have been transmitted. 847 */ 848 for (i = sc->vr_txdirty; sc->vr_txpending != 0; 849 i = VR_NEXTTX(i), sc->vr_txpending--) { 850 d = VR_CDTX(sc, i); 851 ds = VR_DSTX(sc, i); 852 853 VR_CDTXSYNC(sc, i, 854 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 855 856 txstat = le32toh(d->vr_status); 857 858 if (txstat & (VR_TXSTAT_ABRT | VR_TXSTAT_UDF)) { 859 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 860 for (j = 0; j < VR_TIMEOUT; j++) { 861 DELAY(10); 862 if ((CSR_READ_2(sc, VR_COMMAND) & 863 VR_CMD_TX_ON) == 0) 864 break; 865 } 866 if (j == VR_TIMEOUT) { 867 /* XXX need reset? */ 868 aprint_error_dev(sc->vr_dev, 869 "TX shutdown never completed\n"); 870 } 871 d->vr_status = htole32(VR_TXSTAT_OWN); 872 CSR_WRITE_4(sc, VR_TXADDR, VR_CDTXADDR(sc, i)); 873 break; 874 } 875 876 if (txstat & VR_TXSTAT_OWN) 877 break; 878 879 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 880 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 881 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 882 m_freem(ds->ds_mbuf); 883 ds->ds_mbuf = NULL; 884 885 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 886 if (txstat & VR_TXSTAT_ERRSUM) { 887 if_statinc_ref(nsr, if_oerrors); 888 if (txstat & VR_TXSTAT_DEFER) 889 if_statinc_ref(nsr, if_collisions); 890 if (txstat & VR_TXSTAT_LATECOLL) 891 if_statinc_ref(nsr, if_collisions); 892 } 893 894 if_statadd_ref(nsr, if_collisions, 895 (txstat & VR_TXSTAT_COLLCNT) >> 3); 896 if_statinc_ref(nsr, if_opackets); 897 IF_STAT_PUTREF(ifp); 898 } 899 900 /* Update the dirty transmit buffer pointer. */ 901 sc->vr_txdirty = i; 902 903 /* 904 * Cancel the watchdog timer if there are no pending 905 * transmissions. 906 */ 907 if (sc->vr_txpending == 0) 908 ifp->if_timer = 0; 909 } 910 911 static int 912 vr_intr(void *arg) 913 { 914 struct vr_softc *sc; 915 struct ifnet *ifp; 916 uint16_t status; 917 int handled = 0, dotx = 0; 918 919 sc = arg; 920 ifp = &sc->vr_ec.ec_if; 921 922 /* Suppress unwanted interrupts. */ 923 if ((ifp->if_flags & IFF_UP) == 0) { 924 vr_stop(ifp, 1); 925 return (0); 926 } 927 928 /* Disable interrupts. */ 929 CSR_WRITE_2(sc, VR_IMR, 0x0000); 930 931 for (;;) { 932 status = CSR_READ_2(sc, VR_ISR); 933 if (status) 934 CSR_WRITE_2(sc, VR_ISR, status); 935 936 if ((status & VR_INTRS) == 0) 937 break; 938 939 handled = 1; 940 941 rnd_add_uint32(&sc->rnd_source, status); 942 943 if (status & VR_ISR_RX_OK) 944 vr_rxeof(sc); 945 946 if (status & VR_ISR_RX_DROPPED) { 947 aprint_error_dev(sc->vr_dev, "rx packet lost\n"); 948 if_statinc(ifp, if_ierrors); 949 } 950 951 if (status & 952 (VR_ISR_RX_ERR | VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW)) 953 vr_rxeoc(sc); 954 955 956 if (status & (VR_ISR_BUSERR | VR_ISR_TX_UNDERRUN)) { 957 if (status & VR_ISR_BUSERR) 958 aprint_error_dev(sc->vr_dev, "PCI bus error\n"); 959 if (status & VR_ISR_TX_UNDERRUN) 960 aprint_error_dev(sc->vr_dev, 961 "transmit underrun\n"); 962 /* vr_init() calls vr_start() */ 963 dotx = 0; 964 (void)vr_init(ifp); 965 966 } 967 968 if (status & VR_ISR_TX_OK) { 969 dotx = 1; 970 vr_txeof(sc); 971 } 972 973 if (status & 974 (VR_ISR_TX_ABRT | VR_ISR_TX_ABRT2 | VR_ISR_TX_UDFI)) { 975 if (status & (VR_ISR_TX_ABRT | VR_ISR_TX_ABRT2)) 976 aprint_error_dev(sc->vr_dev, 977 "transmit aborted\n"); 978 if (status & VR_ISR_TX_UDFI) 979 aprint_error_dev(sc->vr_dev, 980 "transmit underflow\n"); 981 if_statinc(ifp, if_oerrors); 982 dotx = 1; 983 vr_txeof(sc); 984 if (sc->vr_txpending) { 985 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 986 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 987 } 988 } 989 } 990 991 /* Re-enable interrupts. */ 992 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 993 994 if (dotx) 995 if_schedule_deferred_start(ifp); 996 997 return (handled); 998 } 999 1000 /* 1001 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1002 * to the mbuf data regions directly in the transmit lists. We also save a 1003 * copy of the pointers since the transmit list fragment pointers are 1004 * physical addresses. 1005 */ 1006 static void 1007 vr_start(struct ifnet *ifp) 1008 { 1009 struct vr_softc *sc = ifp->if_softc; 1010 struct mbuf *m0, *m; 1011 struct vr_desc *d; 1012 struct vr_descsoft *ds; 1013 int error, firsttx, nexttx, opending; 1014 1015 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1016 return; 1017 if (sc->vr_link == false) 1018 return; 1019 1020 /* 1021 * Remember the previous txpending and the first transmit 1022 * descriptor we use. 1023 */ 1024 opending = sc->vr_txpending; 1025 firsttx = VR_NEXTTX(sc->vr_txlast); 1026 1027 /* 1028 * Loop through the send queue, setting up transmit descriptors 1029 * until we drain the queue, or use up all available transmit 1030 * descriptors. 1031 */ 1032 while (sc->vr_txpending < VR_NTXDESC) { 1033 /* 1034 * Grab a packet off the queue. 1035 */ 1036 IFQ_POLL(&ifp->if_snd, m0); 1037 if (m0 == NULL) 1038 break; 1039 m = NULL; 1040 1041 /* 1042 * Get the next available transmit descriptor. 1043 */ 1044 nexttx = VR_NEXTTX(sc->vr_txlast); 1045 d = VR_CDTX(sc, nexttx); 1046 ds = VR_DSTX(sc, nexttx); 1047 1048 /* 1049 * Load the DMA map. If this fails, the packet didn't 1050 * fit in one DMA segment, and we need to copy. Note, 1051 * the packet must also be aligned. 1052 * if the packet is too small, copy it too, so we're sure 1053 * we have enough room for the pad buffer. 1054 */ 1055 if ((mtod(m0, uintptr_t) & 3) != 0 || 1056 m0->m_pkthdr.len < VR_MIN_FRAMELEN || 1057 bus_dmamap_load_mbuf(sc->vr_dmat, ds->ds_dmamap, m0, 1058 BUS_DMA_WRITE | BUS_DMA_NOWAIT) != 0) { 1059 MGETHDR(m, M_DONTWAIT, MT_DATA); 1060 if (m == NULL) { 1061 aprint_error_dev(sc->vr_dev, 1062 "unable to allocate Tx mbuf\n"); 1063 break; 1064 } 1065 if (m0->m_pkthdr.len > MHLEN) { 1066 MCLGET(m, M_DONTWAIT); 1067 if ((m->m_flags & M_EXT) == 0) { 1068 aprint_error_dev(sc->vr_dev, 1069 "unable to allocate Tx cluster\n"); 1070 m_freem(m); 1071 break; 1072 } 1073 } 1074 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1075 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1076 /* 1077 * The Rhine doesn't auto-pad, so we have to do this 1078 * ourselves. 1079 */ 1080 if (m0->m_pkthdr.len < VR_MIN_FRAMELEN) { 1081 memset(mtod(m, char *) + m0->m_pkthdr.len, 1082 0, VR_MIN_FRAMELEN - m0->m_pkthdr.len); 1083 m->m_pkthdr.len = m->m_len = VR_MIN_FRAMELEN; 1084 } 1085 error = bus_dmamap_load_mbuf(sc->vr_dmat, 1086 ds->ds_dmamap, m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1087 if (error) { 1088 m_freem(m); 1089 aprint_error_dev(sc->vr_dev, "unable to load " 1090 "Tx buffer, error = %d\n", error); 1091 break; 1092 } 1093 } 1094 1095 IFQ_DEQUEUE(&ifp->if_snd, m0); 1096 if (m != NULL) { 1097 m_freem(m0); 1098 m0 = m; 1099 } 1100 1101 /* Sync the DMA map. */ 1102 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 1103 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1104 1105 /* 1106 * Store a pointer to the packet so we can free it later. 1107 */ 1108 ds->ds_mbuf = m0; 1109 1110 /* 1111 * If there's a BPF listener, bounce a copy of this frame 1112 * to him. 1113 */ 1114 bpf_mtap(ifp, m0, BPF_D_OUT); 1115 1116 /* 1117 * Fill in the transmit descriptor. 1118 */ 1119 d->vr_data = htole32(ds->ds_dmamap->dm_segs[0].ds_addr); 1120 d->vr_ctl = htole32(m0->m_pkthdr.len); 1121 d->vr_ctl |= htole32(VR_TXCTL_FIRSTFRAG | VR_TXCTL_LASTFRAG); 1122 1123 /* 1124 * If this is the first descriptor we're enqueuing, 1125 * don't give it to the Rhine yet. That could cause 1126 * a race condition. We'll do it below. 1127 */ 1128 if (nexttx == firsttx) 1129 d->vr_status = 0; 1130 else 1131 d->vr_status = htole32(VR_TXSTAT_OWN); 1132 1133 VR_CDTXSYNC(sc, nexttx, 1134 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1135 1136 /* Advance the tx pointer. */ 1137 sc->vr_txpending++; 1138 sc->vr_txlast = nexttx; 1139 } 1140 1141 if (sc->vr_txpending == VR_NTXDESC) { 1142 /* No more slots left; notify upper layer. */ 1143 ifp->if_flags |= IFF_OACTIVE; 1144 } 1145 1146 if (sc->vr_txpending != opending) { 1147 /* 1148 * We enqueued packets. If the transmitter was idle, 1149 * reset the txdirty pointer. 1150 */ 1151 if (opending == 0) 1152 sc->vr_txdirty = firsttx; 1153 1154 /* 1155 * Cause a transmit interrupt to happen on the 1156 * last packet we enqueued. 1157 */ 1158 VR_CDTX(sc, sc->vr_txlast)->vr_ctl |= htole32(VR_TXCTL_FINT); 1159 VR_CDTXSYNC(sc, sc->vr_txlast, 1160 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1161 1162 /* 1163 * The entire packet chain is set up. Give the 1164 * first descriptor to the Rhine now. 1165 */ 1166 VR_CDTX(sc, firsttx)->vr_status = htole32(VR_TXSTAT_OWN); 1167 VR_CDTXSYNC(sc, firsttx, 1168 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1169 1170 /* Start the transmitter. */ 1171 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1172 1173 /* Set the watchdog timer in case the chip flakes out. */ 1174 ifp->if_timer = 5; 1175 } 1176 } 1177 1178 /* 1179 * Initialize the interface. Must be called at splnet. 1180 */ 1181 static int 1182 vr_init(struct ifnet *ifp) 1183 { 1184 struct vr_softc *sc = ifp->if_softc; 1185 struct vr_desc *d; 1186 struct vr_descsoft *ds; 1187 int i, error = 0; 1188 1189 /* Cancel pending I/O. */ 1190 vr_stop(ifp, 0); 1191 1192 /* Reset the Rhine to a known state. */ 1193 vr_reset(sc); 1194 1195 /* set DMA length in BCR0 and BCR1 */ 1196 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1197 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1198 1199 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1200 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTH_128BYTES); 1201 1202 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1203 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTH_STORENFWD); 1204 1205 /* set DMA threshold length in RXCFG and TXCFG */ 1206 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1207 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1208 1209 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1210 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1211 1212 /* 1213 * Initialize the transmit descriptor ring. txlast is initialized 1214 * to the end of the list so that it will wrap around to the first 1215 * descriptor when the first packet is transmitted. 1216 */ 1217 for (i = 0; i < VR_NTXDESC; i++) { 1218 d = VR_CDTX(sc, i); 1219 memset(d, 0, sizeof(struct vr_desc)); 1220 d->vr_next = htole32(VR_CDTXADDR(sc, VR_NEXTTX(i))); 1221 VR_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1222 } 1223 sc->vr_txpending = 0; 1224 sc->vr_txdirty = 0; 1225 sc->vr_txlast = VR_NTXDESC - 1; 1226 1227 /* 1228 * Initialize the receive descriptor ring. 1229 */ 1230 for (i = 0; i < VR_NRXDESC; i++) { 1231 ds = VR_DSRX(sc, i); 1232 if (ds->ds_mbuf == NULL) { 1233 if ((error = vr_add_rxbuf(sc, i)) != 0) { 1234 aprint_error_dev(sc->vr_dev, 1235 "unable to allocate or map rx buffer %d, " 1236 "error = %d\n", i, error); 1237 /* 1238 * XXX Should attempt to run with fewer receive 1239 * XXX buffers instead of just failing. 1240 */ 1241 vr_rxdrain(sc); 1242 goto out; 1243 } 1244 } else 1245 VR_INIT_RXDESC(sc, i); 1246 } 1247 sc->vr_rxptr = 0; 1248 1249 /* If we want promiscuous mode, set the allframes bit. */ 1250 if (ifp->if_flags & IFF_PROMISC) 1251 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1252 else 1253 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1254 1255 /* Set capture broadcast bit to capture broadcast frames. */ 1256 if (ifp->if_flags & IFF_BROADCAST) 1257 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1258 else 1259 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1260 1261 /* Program the multicast filter, if necessary. */ 1262 vr_setmulti(sc); 1263 1264 /* Give the transmit and receive rings to the Rhine. */ 1265 CSR_WRITE_4(sc, VR_RXADDR, VR_CDRXADDR(sc, sc->vr_rxptr)); 1266 CSR_WRITE_4(sc, VR_TXADDR, VR_CDTXADDR(sc, VR_NEXTTX(sc->vr_txlast))); 1267 1268 /* Set current media. */ 1269 sc->vr_link = true; 1270 if ((error = ether_mediachange(ifp)) != 0) 1271 goto out; 1272 1273 /* Enable receiver and transmitter. */ 1274 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL | VR_CMD_START | 1275 VR_CMD_TX_ON | VR_CMD_RX_ON | 1276 VR_CMD_RX_GO); 1277 1278 /* Enable interrupts. */ 1279 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1280 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1281 1282 ifp->if_flags |= IFF_RUNNING; 1283 ifp->if_flags &= ~IFF_OACTIVE; 1284 1285 /* Start one second timer. */ 1286 callout_schedule(&sc->vr_tick_ch, hz); 1287 1288 /* Attempt to start output on the interface. */ 1289 vr_start(ifp); 1290 1291 out: 1292 if (error) 1293 aprint_error_dev(sc->vr_dev, "interface not running\n"); 1294 return (error); 1295 } 1296 1297 static int 1298 vr_ioctl(struct ifnet *ifp, u_long command, void *data) 1299 { 1300 struct vr_softc *sc = ifp->if_softc; 1301 int s, error = 0; 1302 1303 s = splnet(); 1304 1305 switch (command) { 1306 case SIOCSIFFLAGS: 1307 if ((error = ifioctl_common(ifp, command, data)) != 0) 1308 break; 1309 1310 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 1311 case IFF_RUNNING: 1312 vr_stop(ifp, 1); 1313 break; 1314 case IFF_UP: 1315 vr_init(ifp); 1316 break; 1317 case IFF_UP | IFF_RUNNING: 1318 if ((ifp->if_flags ^ sc->vr_if_flags) == IFF_PROMISC) 1319 vr_setmulti(sc); 1320 else 1321 vr_init(ifp); 1322 break; 1323 } 1324 sc->vr_if_flags = ifp->if_flags; 1325 break; 1326 default: 1327 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1328 break; 1329 error = 0; 1330 if (command == SIOCADDMULTI || command == SIOCDELMULTI) 1331 vr_setmulti(sc); 1332 } 1333 splx(s); 1334 1335 return error; 1336 } 1337 1338 static void 1339 vr_watchdog(struct ifnet *ifp) 1340 { 1341 struct vr_softc *sc = ifp->if_softc; 1342 1343 aprint_error_dev(sc->vr_dev, "device timeout\n"); 1344 if_statinc(ifp, if_oerrors); 1345 1346 (void) vr_init(ifp); 1347 } 1348 1349 /* 1350 * One second timer, used to tick MII. 1351 */ 1352 static void 1353 vr_tick(void *arg) 1354 { 1355 struct vr_softc *sc = arg; 1356 int s; 1357 1358 s = splnet(); 1359 if (sc->vr_flags & VR_F_RESTART) { 1360 aprint_normal_dev(sc->vr_dev, "restarting\n"); 1361 vr_init(&sc->vr_ec.ec_if); 1362 sc->vr_flags &= ~VR_F_RESTART; 1363 } 1364 mii_tick(&sc->vr_mii); 1365 splx(s); 1366 1367 callout_schedule(&sc->vr_tick_ch, hz); 1368 } 1369 1370 /* 1371 * Drain the receive queue. 1372 */ 1373 static void 1374 vr_rxdrain(struct vr_softc *sc) 1375 { 1376 struct vr_descsoft *ds; 1377 int i; 1378 1379 for (i = 0; i < VR_NRXDESC; i++) { 1380 ds = VR_DSRX(sc, i); 1381 if (ds->ds_mbuf != NULL) { 1382 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 1383 m_freem(ds->ds_mbuf); 1384 ds->ds_mbuf = NULL; 1385 } 1386 } 1387 } 1388 1389 /* 1390 * Stop the adapter and free any mbufs allocated to the 1391 * transmit lists. 1392 */ 1393 static void 1394 vr_stop(struct ifnet *ifp, int disable) 1395 { 1396 struct vr_softc *sc = ifp->if_softc; 1397 struct vr_descsoft *ds; 1398 int i; 1399 1400 /* Cancel one second timer. */ 1401 callout_stop(&sc->vr_tick_ch); 1402 1403 /* Down the MII. */ 1404 mii_down(&sc->vr_mii); 1405 1406 ifp = &sc->vr_ec.ec_if; 1407 ifp->if_timer = 0; 1408 1409 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1410 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON | VR_CMD_TX_ON)); 1411 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1412 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1413 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1414 1415 /* 1416 * Release any queued transmit buffers. 1417 */ 1418 for (i = 0; i < VR_NTXDESC; i++) { 1419 ds = VR_DSTX(sc, i); 1420 if (ds->ds_mbuf != NULL) { 1421 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 1422 m_freem(ds->ds_mbuf); 1423 ds->ds_mbuf = NULL; 1424 } 1425 } 1426 1427 /* 1428 * Mark the interface down and cancel the watchdog timer. 1429 */ 1430 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1431 ifp->if_timer = 0; 1432 1433 if (disable) 1434 vr_rxdrain(sc); 1435 } 1436 1437 static int vr_probe(device_t, cfdata_t, void *); 1438 static void vr_attach(device_t, device_t, void *); 1439 static bool vr_shutdown(device_t, int); 1440 1441 CFATTACH_DECL_NEW(vr, sizeof (struct vr_softc), 1442 vr_probe, vr_attach, NULL, NULL); 1443 1444 static int 1445 vr_probe(device_t parent, cfdata_t match, void *aux) 1446 { 1447 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1448 1449 return pci_compatible_match(pa, compat_data); 1450 } 1451 1452 /* 1453 * Stop all chip I/O so that the kernel's probe routines don't 1454 * get confused by errant DMAs when rebooting. 1455 */ 1456 static bool 1457 vr_shutdown(device_t self, int howto) 1458 { 1459 struct vr_softc *sc = device_private(self); 1460 1461 vr_stop(&sc->vr_ec.ec_if, 1); 1462 1463 return true; 1464 } 1465 1466 /* 1467 * Attach the interface. Allocate softc structures, do ifmedia 1468 * setup and ethernet/BPF attach. 1469 */ 1470 static void 1471 vr_attach(device_t parent, device_t self, void *aux) 1472 { 1473 struct vr_softc *sc = device_private(self); 1474 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 1475 bus_dma_segment_t seg; 1476 uint32_t reg; 1477 struct ifnet *ifp; 1478 struct mii_data * const mii = &sc->vr_mii; 1479 uint8_t eaddr[ETHER_ADDR_LEN], mac; 1480 int i, rseg, error; 1481 char intrbuf[PCI_INTRSTR_LEN]; 1482 1483 #define PCI_CONF_WRITE(r, v) pci_conf_write(sc->vr_pc, sc->vr_tag, (r), (v)) 1484 #define PCI_CONF_READ(r) pci_conf_read(sc->vr_pc, sc->vr_tag, (r)) 1485 1486 sc->vr_dev = self; 1487 sc->vr_pc = pa->pa_pc; 1488 sc->vr_tag = pa->pa_tag; 1489 sc->vr_id = pa->pa_id; 1490 callout_init(&sc->vr_tick_ch, 0); 1491 callout_setfunc(&sc->vr_tick_ch, vr_tick, sc); 1492 1493 pci_aprint_devinfo(pa, NULL); 1494 1495 /* 1496 * Handle power management nonsense. 1497 */ 1498 1499 sc->vr_save_iobase = PCI_CONF_READ(VR_PCI_LOIO); 1500 sc->vr_save_membase = PCI_CONF_READ(VR_PCI_LOMEM); 1501 sc->vr_save_irq = PCI_CONF_READ(PCI_INTERRUPT_REG); 1502 1503 /* power up chip */ 1504 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 1505 vr_restore_state)) && error != EOPNOTSUPP) { 1506 aprint_error_dev(self, "cannot activate %d\n", error); 1507 return; 1508 } 1509 1510 /* Make sure bus mastering is enabled. */ 1511 reg = PCI_CONF_READ(PCI_COMMAND_STATUS_REG); 1512 reg |= PCI_COMMAND_MASTER_ENABLE; 1513 PCI_CONF_WRITE(PCI_COMMAND_STATUS_REG, reg); 1514 1515 /* Get revision */ 1516 sc->vr_revid = PCI_REVISION(pa->pa_class); 1517 1518 /* 1519 * Map control/status registers. 1520 */ 1521 { 1522 bus_space_tag_t iot, memt; 1523 bus_space_handle_t ioh, memh; 1524 int ioh_valid, memh_valid; 1525 pci_intr_handle_t intrhandle; 1526 const char *intrstr; 1527 1528 ioh_valid = (pci_mapreg_map(pa, VR_PCI_LOIO, 1529 PCI_MAPREG_TYPE_IO, 0, 1530 &iot, &ioh, NULL, NULL) == 0); 1531 memh_valid = (pci_mapreg_map(pa, VR_PCI_LOMEM, 1532 PCI_MAPREG_TYPE_MEM | 1533 PCI_MAPREG_MEM_TYPE_32BIT, 1534 0, &memt, &memh, NULL, NULL) == 0); 1535 #if defined(VR_USEIOSPACE) 1536 if (ioh_valid) { 1537 sc->vr_bst = iot; 1538 sc->vr_bsh = ioh; 1539 } else if (memh_valid) { 1540 sc->vr_bst = memt; 1541 sc->vr_bsh = memh; 1542 } 1543 #else 1544 if (memh_valid) { 1545 sc->vr_bst = memt; 1546 sc->vr_bsh = memh; 1547 } else if (ioh_valid) { 1548 sc->vr_bst = iot; 1549 sc->vr_bsh = ioh; 1550 } 1551 #endif 1552 else { 1553 aprint_error_dev(self, 1554 "unable to map device registers\n"); 1555 return; 1556 } 1557 1558 /* Allocate interrupt */ 1559 if (pci_intr_map(pa, &intrhandle)) { 1560 aprint_error_dev(self, "couldn't map interrupt\n"); 1561 return; 1562 } 1563 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, 1564 sizeof(intrbuf)); 1565 sc->vr_ih = pci_intr_establish_xname(pa->pa_pc, intrhandle, 1566 IPL_NET, vr_intr, sc, device_xname(self)); 1567 if (sc->vr_ih == NULL) { 1568 aprint_error_dev(self, "couldn't establish interrupt"); 1569 if (intrstr != NULL) 1570 aprint_error(" at %s", intrstr); 1571 aprint_error("\n"); 1572 return; 1573 } 1574 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 1575 } 1576 1577 /* 1578 * Windows may put the chip in suspend mode when it 1579 * shuts down. Be sure to kick it in the head to wake it 1580 * up again. 1581 * 1582 * Don't touch this register on VT3043 since it causes 1583 * kernel MCHK trap on macppc. 1584 * (Note some VT86C100A chip returns a product ID of VT3043) 1585 */ 1586 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT3043) 1587 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0 | VR_STICKHW_DS1)); 1588 1589 /* Reset the adapter. */ 1590 vr_reset(sc); 1591 1592 /* 1593 * Get station address. The way the Rhine chips work, 1594 * you're not allowed to directly access the EEPROM once 1595 * they've been programmed a special way. Consequently, 1596 * we need to read the node address from the PAR registers. 1597 * 1598 * XXXSCW: On the Rhine III, setting VR_EECSR_LOAD forces a reload 1599 * of the *whole* EEPROM, not just the MAC address. This is 1600 * pretty pointless since the chip does this automatically 1601 * at powerup/reset. 1602 * I suspect the same thing applies to the other Rhine 1603 * variants, but in the absence of a data sheet for those 1604 * (and the lack of anyone else noticing the problems this 1605 * causes) I'm going to retain the old behaviour for the 1606 * other parts. 1607 * In some cases, the chip really does startup without having 1608 * read the EEPROM (kern/34812). To handle this case, we force 1609 * a reload if we see an all-zeroes MAC address. 1610 */ 1611 for (mac = 0, i = 0; i < ETHER_ADDR_LEN; i++) 1612 mac |= (eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i)); 1613 1614 if (mac == 0 || (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT6105 && 1615 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT6102)) { 1616 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 1617 DELAY(200); 1618 for (i = 0; i < ETHER_ADDR_LEN; i++) 1619 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 1620 } 1621 1622 /* 1623 * A Rhine chip was detected. Inform the world. 1624 */ 1625 aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(eaddr)); 1626 1627 memcpy(sc->vr_enaddr, eaddr, ETHER_ADDR_LEN); 1628 1629 sc->vr_dmat = pa->pa_dmat; 1630 1631 /* 1632 * Allocate the control data structures, and create and load 1633 * the DMA map for it. 1634 */ 1635 if ((error = bus_dmamem_alloc(sc->vr_dmat, 1636 sizeof(struct vr_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 1637 0)) != 0) { 1638 aprint_error_dev(self, 1639 "unable to allocate control data, error = %d\n", error); 1640 goto fail_0; 1641 } 1642 1643 if ((error = bus_dmamem_map(sc->vr_dmat, &seg, rseg, 1644 sizeof(struct vr_control_data), (void **)&sc->vr_control_data, 1645 BUS_DMA_COHERENT)) != 0) { 1646 aprint_error_dev(self, 1647 "unable to map control data, error = %d\n", error); 1648 goto fail_1; 1649 } 1650 1651 if ((error = bus_dmamap_create(sc->vr_dmat, 1652 sizeof(struct vr_control_data), 1, 1653 sizeof(struct vr_control_data), 0, 0, 1654 &sc->vr_cddmamap)) != 0) { 1655 aprint_error_dev(self, 1656 "unable to create control data DMA map, error = %d\n", 1657 error); 1658 goto fail_2; 1659 } 1660 1661 if ((error = bus_dmamap_load(sc->vr_dmat, sc->vr_cddmamap, 1662 sc->vr_control_data, sizeof(struct vr_control_data), NULL, 1663 0)) != 0) { 1664 aprint_error_dev(self, 1665 "unable to load control data DMA map, error = %d\n", 1666 error); 1667 goto fail_3; 1668 } 1669 1670 /* 1671 * Create the transmit buffer DMA maps. 1672 */ 1673 for (i = 0; i < VR_NTXDESC; i++) { 1674 if ((error = bus_dmamap_create(sc->vr_dmat, MCLBYTES, 1675 1, MCLBYTES, 0, 0, 1676 &VR_DSTX(sc, i)->ds_dmamap)) != 0) { 1677 aprint_error_dev(self, 1678 "unable to create tx DMA map %d, error = %d\n", i, 1679 error); 1680 goto fail_4; 1681 } 1682 } 1683 1684 /* 1685 * Create the receive buffer DMA maps. 1686 */ 1687 for (i = 0; i < VR_NRXDESC; i++) { 1688 if ((error = bus_dmamap_create(sc->vr_dmat, MCLBYTES, 1, 1689 MCLBYTES, 0, 0, 1690 &VR_DSRX(sc, i)->ds_dmamap)) != 0) { 1691 aprint_error_dev(self, 1692 "unable to create rx DMA map %d, error = %d\n", i, 1693 error); 1694 goto fail_5; 1695 } 1696 VR_DSRX(sc, i)->ds_mbuf = NULL; 1697 } 1698 1699 ifp = &sc->vr_ec.ec_if; 1700 ifp->if_softc = sc; 1701 ifp->if_mtu = ETHERMTU; 1702 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1703 ifp->if_ioctl = vr_ioctl; 1704 ifp->if_start = vr_start; 1705 ifp->if_watchdog = vr_watchdog; 1706 ifp->if_init = vr_init; 1707 ifp->if_stop = vr_stop; 1708 IFQ_SET_READY(&ifp->if_snd); 1709 1710 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 1711 1712 /* 1713 * Initialize MII/media info. 1714 */ 1715 mii->mii_ifp = ifp; 1716 mii->mii_readreg = vr_mii_readreg; 1717 mii->mii_writereg = vr_mii_writereg; 1718 mii->mii_statchg = vr_mii_statchg; 1719 1720 sc->vr_ec.ec_mii = mii; 1721 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 1722 ether_mediastatus); 1723 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, 1724 MII_OFFSET_ANY, MIIF_FORCEANEG); 1725 if (LIST_FIRST(&sc->vr_mii.mii_phys) == NULL) { 1726 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 1727 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 1728 } else 1729 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1730 1731 sc->vr_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 1732 1733 /* 1734 * Call MI attach routines. 1735 */ 1736 if_attach(ifp); 1737 if_deferred_start_init(ifp, NULL); 1738 ether_ifattach(ifp, sc->vr_enaddr); 1739 1740 rnd_attach_source(&sc->rnd_source, device_xname(self), 1741 RND_TYPE_NET, RND_FLAG_DEFAULT); 1742 1743 if (pmf_device_register1(self, NULL, vr_resume, vr_shutdown)) 1744 pmf_class_network_register(self, ifp); 1745 else 1746 aprint_error_dev(self, "couldn't establish power handler\n"); 1747 1748 return; 1749 1750 fail_5: 1751 for (i = 0; i < VR_NRXDESC; i++) { 1752 if (sc->vr_rxsoft[i].ds_dmamap != NULL) 1753 bus_dmamap_destroy(sc->vr_dmat, 1754 sc->vr_rxsoft[i].ds_dmamap); 1755 } 1756 fail_4: 1757 for (i = 0; i < VR_NTXDESC; i++) { 1758 if (sc->vr_txsoft[i].ds_dmamap != NULL) 1759 bus_dmamap_destroy(sc->vr_dmat, 1760 sc->vr_txsoft[i].ds_dmamap); 1761 } 1762 bus_dmamap_unload(sc->vr_dmat, sc->vr_cddmamap); 1763 fail_3: 1764 bus_dmamap_destroy(sc->vr_dmat, sc->vr_cddmamap); 1765 fail_2: 1766 bus_dmamem_unmap(sc->vr_dmat, (void *)sc->vr_control_data, 1767 sizeof(struct vr_control_data)); 1768 fail_1: 1769 bus_dmamem_free(sc->vr_dmat, &seg, rseg); 1770 fail_0: 1771 return; 1772 } 1773 1774 static int 1775 vr_restore_state(pci_chipset_tag_t pc, pcitag_t tag, device_t self, 1776 pcireg_t state) 1777 { 1778 struct vr_softc *sc = device_private(self); 1779 int error; 1780 1781 if (state == PCI_PMCSR_STATE_D0) 1782 return 0; 1783 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 1784 return error; 1785 1786 /* Restore PCI config data. */ 1787 PCI_CONF_WRITE(VR_PCI_LOIO, sc->vr_save_iobase); 1788 PCI_CONF_WRITE(VR_PCI_LOMEM, sc->vr_save_membase); 1789 PCI_CONF_WRITE(PCI_INTERRUPT_REG, sc->vr_save_irq); 1790 return 0; 1791 } 1792 1793 static bool 1794 vr_resume(device_t self, const pmf_qual_t *qual) 1795 { 1796 struct vr_softc *sc = device_private(self); 1797 1798 if (PCI_PRODUCT(sc->vr_id) != PCI_PRODUCT_VIATECH_VT3043) 1799 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0 | VR_STICKHW_DS1)); 1800 1801 return true; 1802 } 1803