1 /* $NetBSD: if_vr.c,v 1.95 2008/07/09 16:14:57 joerg Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1997, 1998 35 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Bill Paul. 48 * 4. Neither the name of the author nor the names of any co-contributors 49 * may be used to endorse or promote products derived from this software 50 * without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 56 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 57 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 58 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 59 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 60 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 61 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 62 * THE POSSIBILITY OF SUCH DAMAGE. 63 * 64 * $FreeBSD: if_vr.c,v 1.7 1999/01/10 18:51:49 wpaul Exp $ 65 */ 66 67 /* 68 * VIA Rhine fast ethernet PCI NIC driver 69 * 70 * Supports various network adapters based on the VIA Rhine 71 * and Rhine II PCI controllers, including the D-Link DFE530TX. 72 * Datasheets are available at http://www.via.com.tw. 73 * 74 * Written by Bill Paul <wpaul@ctr.columbia.edu> 75 * Electrical Engineering Department 76 * Columbia University, New York City 77 */ 78 79 /* 80 * The VIA Rhine controllers are similar in some respects to the 81 * the DEC tulip chips, except less complicated. The controller 82 * uses an MII bus and an external physical layer interface. The 83 * receiver has a one entry perfect filter and a 64-bit hash table 84 * multicast filter. Transmit and receive descriptors are similar 85 * to the tulip. 86 * 87 * The Rhine has a serious flaw in its transmit DMA mechanism: 88 * transmit buffers must be longword aligned. Unfortunately, 89 * the kernel doesn't guarantee that mbufs will be filled in starting 90 * at longword boundaries, so we have to do a buffer copy before 91 * transmission. 92 * 93 * Apparently, the receive DMA mechanism also has the same flaw. This 94 * means that on systems with struct alignment requirements, incoming 95 * frames must be copied to a new buffer which shifts the data forward 96 * 2 bytes so that the payload is aligned on a 4-byte boundary. 97 */ 98 99 #include <sys/cdefs.h> 100 __KERNEL_RCSID(0, "$NetBSD: if_vr.c,v 1.95 2008/07/09 16:14:57 joerg Exp $"); 101 102 #include "rnd.h" 103 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/callout.h> 107 #include <sys/sockio.h> 108 #include <sys/mbuf.h> 109 #include <sys/malloc.h> 110 #include <sys/kernel.h> 111 #include <sys/socket.h> 112 #include <sys/device.h> 113 114 #if NRND > 0 115 #include <sys/rnd.h> 116 #endif 117 118 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 119 120 #include <net/if.h> 121 #include <net/if_arp.h> 122 #include <net/if_dl.h> 123 #include <net/if_media.h> 124 #include <net/if_ether.h> 125 126 #include "bpfilter.h" 127 #if NBPFILTER > 0 128 #include <net/bpf.h> 129 #endif 130 131 #include <sys/bus.h> 132 #include <sys/intr.h> 133 #include <machine/endian.h> 134 135 #include <dev/mii/mii.h> 136 #include <dev/mii/miivar.h> 137 #include <dev/mii/mii_bitbang.h> 138 139 #include <dev/pci/pcireg.h> 140 #include <dev/pci/pcivar.h> 141 #include <dev/pci/pcidevs.h> 142 143 #include <dev/pci/if_vrreg.h> 144 145 #define VR_USEIOSPACE 146 147 /* 148 * Various supported device vendors/types and their names. 149 */ 150 static const struct vr_type { 151 pci_vendor_id_t vr_vid; 152 pci_product_id_t vr_did; 153 const char *vr_name; 154 } vr_devs[] = { 155 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT3043, 156 "VIA VT3043 (Rhine) 10/100" }, 157 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6102, 158 "VIA VT6102 (Rhine II) 10/100" }, 159 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6105, 160 "VIA VT6105 (Rhine III) 10/100" }, 161 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6105M, 162 "VIA VT6105M (Rhine III) 10/100" }, 163 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT86C100A, 164 "VIA VT86C100A (Rhine-II) 10/100" }, 165 { 0, 0, NULL } 166 }; 167 168 /* 169 * Transmit descriptor list size. 170 */ 171 #define VR_NTXDESC 64 172 #define VR_NTXDESC_MASK (VR_NTXDESC - 1) 173 #define VR_NEXTTX(x) (((x) + 1) & VR_NTXDESC_MASK) 174 175 /* 176 * Receive descriptor list size. 177 */ 178 #define VR_NRXDESC 64 179 #define VR_NRXDESC_MASK (VR_NRXDESC - 1) 180 #define VR_NEXTRX(x) (((x) + 1) & VR_NRXDESC_MASK) 181 182 /* 183 * Control data structres that are DMA'd to the Rhine chip. We allocate 184 * them in a single clump that maps to a single DMA segment to make several 185 * things easier. 186 * 187 * Note that since we always copy outgoing packets to aligned transmit 188 * buffers, we can reduce the transmit descriptors to one per packet. 189 */ 190 struct vr_control_data { 191 struct vr_desc vr_txdescs[VR_NTXDESC]; 192 struct vr_desc vr_rxdescs[VR_NRXDESC]; 193 }; 194 195 #define VR_CDOFF(x) offsetof(struct vr_control_data, x) 196 #define VR_CDTXOFF(x) VR_CDOFF(vr_txdescs[(x)]) 197 #define VR_CDRXOFF(x) VR_CDOFF(vr_rxdescs[(x)]) 198 199 /* 200 * Software state of transmit and receive descriptors. 201 */ 202 struct vr_descsoft { 203 struct mbuf *ds_mbuf; /* head of mbuf chain */ 204 bus_dmamap_t ds_dmamap; /* our DMA map */ 205 }; 206 207 struct vr_softc { 208 device_t vr_dev; 209 void *vr_ih; /* interrupt cookie */ 210 void *vr_ats; /* shutdown hook */ 211 bus_space_tag_t vr_bst; /* bus space tag */ 212 bus_space_handle_t vr_bsh; /* bus space handle */ 213 bus_dma_tag_t vr_dmat; /* bus DMA tag */ 214 pci_chipset_tag_t vr_pc; /* PCI chipset info */ 215 pcitag_t vr_tag; /* PCI tag */ 216 struct ethercom vr_ec; /* Ethernet common info */ 217 uint8_t vr_enaddr[ETHER_ADDR_LEN]; 218 struct mii_data vr_mii; /* MII/media info */ 219 220 uint8_t vr_revid; /* Rhine chip revision */ 221 222 callout_t vr_tick_ch; /* tick callout */ 223 224 bus_dmamap_t vr_cddmamap; /* control data DMA map */ 225 #define vr_cddma vr_cddmamap->dm_segs[0].ds_addr 226 227 /* 228 * Software state for transmit and receive descriptors. 229 */ 230 struct vr_descsoft vr_txsoft[VR_NTXDESC]; 231 struct vr_descsoft vr_rxsoft[VR_NRXDESC]; 232 233 /* 234 * Control data structures. 235 */ 236 struct vr_control_data *vr_control_data; 237 238 int vr_txpending; /* number of TX requests pending */ 239 int vr_txdirty; /* first dirty TX descriptor */ 240 int vr_txlast; /* last used TX descriptor */ 241 242 int vr_rxptr; /* next ready RX descriptor */ 243 244 uint32_t vr_save_iobase; 245 uint32_t vr_save_membase; 246 uint32_t vr_save_irq; 247 248 #if NRND > 0 249 rndsource_element_t rnd_source; /* random source */ 250 #endif 251 }; 252 253 #define VR_CDTXADDR(sc, x) ((sc)->vr_cddma + VR_CDTXOFF((x))) 254 #define VR_CDRXADDR(sc, x) ((sc)->vr_cddma + VR_CDRXOFF((x))) 255 256 #define VR_CDTX(sc, x) (&(sc)->vr_control_data->vr_txdescs[(x)]) 257 #define VR_CDRX(sc, x) (&(sc)->vr_control_data->vr_rxdescs[(x)]) 258 259 #define VR_DSTX(sc, x) (&(sc)->vr_txsoft[(x)]) 260 #define VR_DSRX(sc, x) (&(sc)->vr_rxsoft[(x)]) 261 262 #define VR_CDTXSYNC(sc, x, ops) \ 263 bus_dmamap_sync((sc)->vr_dmat, (sc)->vr_cddmamap, \ 264 VR_CDTXOFF((x)), sizeof(struct vr_desc), (ops)) 265 266 #define VR_CDRXSYNC(sc, x, ops) \ 267 bus_dmamap_sync((sc)->vr_dmat, (sc)->vr_cddmamap, \ 268 VR_CDRXOFF((x)), sizeof(struct vr_desc), (ops)) 269 270 /* 271 * Note we rely on MCLBYTES being a power of two below. 272 */ 273 #define VR_INIT_RXDESC(sc, i) \ 274 do { \ 275 struct vr_desc *__d = VR_CDRX((sc), (i)); \ 276 struct vr_descsoft *__ds = VR_DSRX((sc), (i)); \ 277 \ 278 __d->vr_next = htole32(VR_CDRXADDR((sc), VR_NEXTRX((i)))); \ 279 __d->vr_data = htole32(__ds->ds_dmamap->dm_segs[0].ds_addr); \ 280 __d->vr_ctl = htole32(VR_RXCTL_CHAIN | VR_RXCTL_RX_INTR | \ 281 ((MCLBYTES - 1) & VR_RXCTL_BUFLEN)); \ 282 __d->vr_status = htole32(VR_RXSTAT_FIRSTFRAG | \ 283 VR_RXSTAT_LASTFRAG | VR_RXSTAT_OWN); \ 284 VR_CDRXSYNC((sc), (i), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 285 } while (/* CONSTCOND */ 0) 286 287 /* 288 * register space access macros 289 */ 290 #define CSR_WRITE_4(sc, reg, val) \ 291 bus_space_write_4(sc->vr_bst, sc->vr_bsh, reg, val) 292 #define CSR_WRITE_2(sc, reg, val) \ 293 bus_space_write_2(sc->vr_bst, sc->vr_bsh, reg, val) 294 #define CSR_WRITE_1(sc, reg, val) \ 295 bus_space_write_1(sc->vr_bst, sc->vr_bsh, reg, val) 296 297 #define CSR_READ_4(sc, reg) \ 298 bus_space_read_4(sc->vr_bst, sc->vr_bsh, reg) 299 #define CSR_READ_2(sc, reg) \ 300 bus_space_read_2(sc->vr_bst, sc->vr_bsh, reg) 301 #define CSR_READ_1(sc, reg) \ 302 bus_space_read_1(sc->vr_bst, sc->vr_bsh, reg) 303 304 #define VR_TIMEOUT 1000 305 306 static int vr_add_rxbuf(struct vr_softc *, int); 307 308 static void vr_rxeof(struct vr_softc *); 309 static void vr_rxeoc(struct vr_softc *); 310 static void vr_txeof(struct vr_softc *); 311 static int vr_intr(void *); 312 static void vr_start(struct ifnet *); 313 static int vr_ioctl(struct ifnet *, u_long, void *); 314 static int vr_init(struct ifnet *); 315 static void vr_stop(struct ifnet *, int); 316 static void vr_rxdrain(struct vr_softc *); 317 static void vr_watchdog(struct ifnet *); 318 static void vr_tick(void *); 319 320 static int vr_mii_readreg(device_t, int, int); 321 static void vr_mii_writereg(device_t, int, int, int); 322 static void vr_mii_statchg(device_t); 323 324 static void vr_setmulti(struct vr_softc *); 325 static void vr_reset(struct vr_softc *); 326 static int vr_restore_state(pci_chipset_tag_t, pcitag_t, device_t, 327 pcireg_t); 328 329 int vr_copy_small = 0; 330 331 #define VR_SETBIT(sc, reg, x) \ 332 CSR_WRITE_1(sc, reg, \ 333 CSR_READ_1(sc, reg) | (x)) 334 335 #define VR_CLRBIT(sc, reg, x) \ 336 CSR_WRITE_1(sc, reg, \ 337 CSR_READ_1(sc, reg) & ~(x)) 338 339 #define VR_SETBIT16(sc, reg, x) \ 340 CSR_WRITE_2(sc, reg, \ 341 CSR_READ_2(sc, reg) | (x)) 342 343 #define VR_CLRBIT16(sc, reg, x) \ 344 CSR_WRITE_2(sc, reg, \ 345 CSR_READ_2(sc, reg) & ~(x)) 346 347 #define VR_SETBIT32(sc, reg, x) \ 348 CSR_WRITE_4(sc, reg, \ 349 CSR_READ_4(sc, reg) | (x)) 350 351 #define VR_CLRBIT32(sc, reg, x) \ 352 CSR_WRITE_4(sc, reg, \ 353 CSR_READ_4(sc, reg) & ~(x)) 354 355 /* 356 * MII bit-bang glue. 357 */ 358 static uint32_t vr_mii_bitbang_read(device_t); 359 static void vr_mii_bitbang_write(device_t, uint32_t); 360 361 static const struct mii_bitbang_ops vr_mii_bitbang_ops = { 362 vr_mii_bitbang_read, 363 vr_mii_bitbang_write, 364 { 365 VR_MIICMD_DATAOUT, /* MII_BIT_MDO */ 366 VR_MIICMD_DATAIN, /* MII_BIT_MDI */ 367 VR_MIICMD_CLK, /* MII_BIT_MDC */ 368 VR_MIICMD_DIR, /* MII_BIT_DIR_HOST_PHY */ 369 0, /* MII_BIT_DIR_PHY_HOST */ 370 } 371 }; 372 373 static uint32_t 374 vr_mii_bitbang_read(device_t self) 375 { 376 struct vr_softc *sc = device_private(self); 377 378 return (CSR_READ_1(sc, VR_MIICMD)); 379 } 380 381 static void 382 vr_mii_bitbang_write(device_t self, uint32_t val) 383 { 384 struct vr_softc *sc = device_private(self); 385 386 CSR_WRITE_1(sc, VR_MIICMD, (val & 0xff) | VR_MIICMD_DIRECTPGM); 387 } 388 389 /* 390 * Read an PHY register through the MII. 391 */ 392 static int 393 vr_mii_readreg(device_t self, int phy, int reg) 394 { 395 struct vr_softc *sc = device_private(self); 396 397 CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 398 return (mii_bitbang_readreg(self, &vr_mii_bitbang_ops, phy, reg)); 399 } 400 401 /* 402 * Write to a PHY register through the MII. 403 */ 404 static void 405 vr_mii_writereg(device_t self, int phy, int reg, int val) 406 { 407 struct vr_softc *sc = device_private(self); 408 409 CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 410 mii_bitbang_writereg(self, &vr_mii_bitbang_ops, phy, reg, val); 411 } 412 413 static void 414 vr_mii_statchg(device_t self) 415 { 416 struct vr_softc *sc = device_private(self); 417 418 /* 419 * In order to fiddle with the 'full-duplex' bit in the netconfig 420 * register, we first have to put the transmit and/or receive logic 421 * in the idle state. 422 */ 423 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 424 425 if (sc->vr_mii.mii_media_active & IFM_FDX) 426 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 427 else 428 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 429 430 if (sc->vr_ec.ec_if.if_flags & IFF_RUNNING) 431 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 432 } 433 434 #define vr_calchash(addr) \ 435 (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26) 436 437 /* 438 * Program the 64-bit multicast hash filter. 439 */ 440 static void 441 vr_setmulti(struct vr_softc *sc) 442 { 443 struct ifnet *ifp; 444 int h = 0; 445 uint32_t hashes[2] = { 0, 0 }; 446 struct ether_multistep step; 447 struct ether_multi *enm; 448 int mcnt = 0; 449 uint8_t rxfilt; 450 451 ifp = &sc->vr_ec.ec_if; 452 453 rxfilt = CSR_READ_1(sc, VR_RXCFG); 454 455 if (ifp->if_flags & IFF_PROMISC) { 456 allmulti: 457 ifp->if_flags |= IFF_ALLMULTI; 458 rxfilt |= VR_RXCFG_RX_MULTI; 459 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 460 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 461 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 462 return; 463 } 464 465 /* first, zot all the existing hash bits */ 466 CSR_WRITE_4(sc, VR_MAR0, 0); 467 CSR_WRITE_4(sc, VR_MAR1, 0); 468 469 /* now program new ones */ 470 ETHER_FIRST_MULTI(step, &sc->vr_ec, enm); 471 while (enm != NULL) { 472 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 473 ETHER_ADDR_LEN) != 0) 474 goto allmulti; 475 476 h = vr_calchash(enm->enm_addrlo); 477 478 if (h < 32) 479 hashes[0] |= (1 << h); 480 else 481 hashes[1] |= (1 << (h - 32)); 482 ETHER_NEXT_MULTI(step, enm); 483 mcnt++; 484 } 485 486 ifp->if_flags &= ~IFF_ALLMULTI; 487 488 if (mcnt) 489 rxfilt |= VR_RXCFG_RX_MULTI; 490 else 491 rxfilt &= ~VR_RXCFG_RX_MULTI; 492 493 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 494 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 495 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 496 } 497 498 static void 499 vr_reset(struct vr_softc *sc) 500 { 501 int i; 502 503 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 504 505 for (i = 0; i < VR_TIMEOUT; i++) { 506 DELAY(10); 507 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 508 break; 509 } 510 if (i == VR_TIMEOUT) { 511 if (sc->vr_revid < REV_ID_VT3065_A) { 512 printf("%s: reset never completed!\n", 513 device_xname(sc->vr_dev)); 514 } else { 515 /* Use newer force reset command */ 516 printf("%s: using force reset command.\n", 517 device_xname(sc->vr_dev)); 518 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 519 } 520 } 521 522 /* Wait a little while for the chip to get its brains in order. */ 523 DELAY(1000); 524 } 525 526 /* 527 * Initialize an RX descriptor and attach an MBUF cluster. 528 * Note: the length fields are only 11 bits wide, which means the 529 * largest size we can specify is 2047. This is important because 530 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 531 * overflow the field and make a mess. 532 */ 533 static int 534 vr_add_rxbuf(struct vr_softc *sc, int i) 535 { 536 struct vr_descsoft *ds = VR_DSRX(sc, i); 537 struct mbuf *m_new; 538 int error; 539 540 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 541 if (m_new == NULL) 542 return (ENOBUFS); 543 544 MCLGET(m_new, M_DONTWAIT); 545 if ((m_new->m_flags & M_EXT) == 0) { 546 m_freem(m_new); 547 return (ENOBUFS); 548 } 549 550 if (ds->ds_mbuf != NULL) 551 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 552 553 ds->ds_mbuf = m_new; 554 555 error = bus_dmamap_load(sc->vr_dmat, ds->ds_dmamap, 556 m_new->m_ext.ext_buf, m_new->m_ext.ext_size, NULL, 557 BUS_DMA_READ|BUS_DMA_NOWAIT); 558 if (error) { 559 aprint_error_dev(sc->vr_dev, "unable to load rx DMA map %d, error = %d\n", 560 i, error); 561 panic("vr_add_rxbuf"); /* XXX */ 562 } 563 564 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 565 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 566 567 VR_INIT_RXDESC(sc, i); 568 569 return (0); 570 } 571 572 /* 573 * A frame has been uploaded: pass the resulting mbuf chain up to 574 * the higher level protocols. 575 */ 576 static void 577 vr_rxeof(struct vr_softc *sc) 578 { 579 struct mbuf *m; 580 struct ifnet *ifp; 581 struct vr_desc *d; 582 struct vr_descsoft *ds; 583 int i, total_len; 584 uint32_t rxstat; 585 586 ifp = &sc->vr_ec.ec_if; 587 588 for (i = sc->vr_rxptr;; i = VR_NEXTRX(i)) { 589 d = VR_CDRX(sc, i); 590 ds = VR_DSRX(sc, i); 591 592 VR_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 593 594 rxstat = le32toh(d->vr_status); 595 596 if (rxstat & VR_RXSTAT_OWN) { 597 /* 598 * We have processed all of the receive buffers. 599 */ 600 break; 601 } 602 603 /* 604 * If an error occurs, update stats, clear the 605 * status word and leave the mbuf cluster in place: 606 * it should simply get re-used next time this descriptor 607 * comes up in the ring. 608 */ 609 if (rxstat & VR_RXSTAT_RXERR) { 610 const char *errstr; 611 612 ifp->if_ierrors++; 613 switch (rxstat & 0x000000FF) { 614 case VR_RXSTAT_CRCERR: 615 errstr = "crc error"; 616 break; 617 case VR_RXSTAT_FRAMEALIGNERR: 618 errstr = "frame alignment error"; 619 break; 620 case VR_RXSTAT_FIFOOFLOW: 621 errstr = "FIFO overflow"; 622 break; 623 case VR_RXSTAT_GIANT: 624 errstr = "received giant packet"; 625 break; 626 case VR_RXSTAT_RUNT: 627 errstr = "received runt packet"; 628 break; 629 case VR_RXSTAT_BUSERR: 630 errstr = "system bus error"; 631 break; 632 case VR_RXSTAT_BUFFERR: 633 errstr = "rx buffer error"; 634 break; 635 default: 636 errstr = "unknown rx error"; 637 break; 638 } 639 printf("%s: receive error: %s\n", device_xname(sc->vr_dev), 640 errstr); 641 642 VR_INIT_RXDESC(sc, i); 643 644 continue; 645 } else if (!(rxstat & VR_RXSTAT_FIRSTFRAG) || 646 !(rxstat & VR_RXSTAT_LASTFRAG)) { 647 /* 648 * This driver expects to receive whole packets every 649 * time. In case we receive a fragment that is not 650 * a complete packet, we discard it. 651 */ 652 ifp->if_ierrors++; 653 654 printf("%s: receive error: incomplete frame; " 655 "size = %d, status = 0x%x\n", 656 device_xname(sc->vr_dev), 657 VR_RXBYTES(le32toh(d->vr_status)), rxstat); 658 659 VR_INIT_RXDESC(sc, i); 660 661 continue; 662 } 663 664 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 665 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 666 667 /* No errors; receive the packet. */ 668 total_len = VR_RXBYTES(le32toh(d->vr_status)); 669 #ifdef DIAGNOSTIC 670 if (total_len == 0) { 671 /* 672 * If we receive a zero-length packet, we probably 673 * missed to handle an error condition above. 674 * Discard it to avoid a later crash. 675 */ 676 ifp->if_ierrors++; 677 678 printf("%s: receive error: zero-length packet; " 679 "status = 0x%x\n", 680 device_xname(sc->vr_dev), rxstat); 681 682 VR_INIT_RXDESC(sc, i); 683 684 continue; 685 } 686 #endif 687 688 /* 689 * The Rhine chip includes the CRC with every packet. 690 * Trim it off here. 691 */ 692 total_len -= ETHER_CRC_LEN; 693 694 #ifdef __NO_STRICT_ALIGNMENT 695 /* 696 * If the packet is small enough to fit in a 697 * single header mbuf, allocate one and copy 698 * the data into it. This greatly reduces 699 * memory consumption when we receive lots 700 * of small packets. 701 * 702 * Otherwise, we add a new buffer to the receive 703 * chain. If this fails, we drop the packet and 704 * recycle the old buffer. 705 */ 706 if (vr_copy_small != 0 && total_len <= MHLEN) { 707 MGETHDR(m, M_DONTWAIT, MT_DATA); 708 if (m == NULL) 709 goto dropit; 710 memcpy(mtod(m, void *), 711 mtod(ds->ds_mbuf, void *), total_len); 712 VR_INIT_RXDESC(sc, i); 713 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 714 ds->ds_dmamap->dm_mapsize, 715 BUS_DMASYNC_PREREAD); 716 } else { 717 m = ds->ds_mbuf; 718 if (vr_add_rxbuf(sc, i) == ENOBUFS) { 719 dropit: 720 ifp->if_ierrors++; 721 VR_INIT_RXDESC(sc, i); 722 bus_dmamap_sync(sc->vr_dmat, 723 ds->ds_dmamap, 0, 724 ds->ds_dmamap->dm_mapsize, 725 BUS_DMASYNC_PREREAD); 726 continue; 727 } 728 } 729 #else 730 /* 731 * The Rhine's packet buffers must be 4-byte aligned. 732 * But this means that the data after the Ethernet header 733 * is misaligned. We must allocate a new buffer and 734 * copy the data, shifted forward 2 bytes. 735 */ 736 MGETHDR(m, M_DONTWAIT, MT_DATA); 737 if (m == NULL) { 738 dropit: 739 ifp->if_ierrors++; 740 VR_INIT_RXDESC(sc, i); 741 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 742 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 743 continue; 744 } 745 if (total_len > (MHLEN - 2)) { 746 MCLGET(m, M_DONTWAIT); 747 if ((m->m_flags & M_EXT) == 0) { 748 m_freem(m); 749 goto dropit; 750 } 751 } 752 m->m_data += 2; 753 754 /* 755 * Note that we use clusters for incoming frames, so the 756 * buffer is virtually contiguous. 757 */ 758 memcpy(mtod(m, void *), mtod(ds->ds_mbuf, void *), 759 total_len); 760 761 /* Allow the receive descriptor to continue using its mbuf. */ 762 VR_INIT_RXDESC(sc, i); 763 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 764 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 765 #endif /* __NO_STRICT_ALIGNMENT */ 766 767 ifp->if_ipackets++; 768 m->m_pkthdr.rcvif = ifp; 769 m->m_pkthdr.len = m->m_len = total_len; 770 #if NBPFILTER > 0 771 /* 772 * Handle BPF listeners. Let the BPF user see the packet, but 773 * don't pass it up to the ether_input() layer unless it's 774 * a broadcast packet, multicast packet, matches our ethernet 775 * address or the interface is in promiscuous mode. 776 */ 777 if (ifp->if_bpf) 778 bpf_mtap(ifp->if_bpf, m); 779 #endif 780 /* Pass it on. */ 781 (*ifp->if_input)(ifp, m); 782 } 783 784 /* Update the receive pointer. */ 785 sc->vr_rxptr = i; 786 } 787 788 void 789 vr_rxeoc(struct vr_softc *sc) 790 { 791 struct ifnet *ifp; 792 int i; 793 794 ifp = &sc->vr_ec.ec_if; 795 796 ifp->if_ierrors++; 797 798 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 799 for (i = 0; i < VR_TIMEOUT; i++) { 800 DELAY(10); 801 if ((CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON) == 0) 802 break; 803 } 804 if (i == VR_TIMEOUT) { 805 /* XXX need reset? */ 806 printf("%s: RX shutdown never complete\n", 807 device_xname(sc->vr_dev)); 808 } 809 810 vr_rxeof(sc); 811 812 CSR_WRITE_4(sc, VR_RXADDR, VR_CDRXADDR(sc, sc->vr_rxptr)); 813 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 814 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 815 } 816 817 /* 818 * A frame was downloaded to the chip. It's safe for us to clean up 819 * the list buffers. 820 */ 821 static void 822 vr_txeof(struct vr_softc *sc) 823 { 824 struct ifnet *ifp = &sc->vr_ec.ec_if; 825 struct vr_desc *d; 826 struct vr_descsoft *ds; 827 uint32_t txstat; 828 int i, j; 829 830 ifp->if_flags &= ~IFF_OACTIVE; 831 832 /* 833 * Go through our tx list and free mbufs for those 834 * frames that have been transmitted. 835 */ 836 for (i = sc->vr_txdirty; sc->vr_txpending != 0; 837 i = VR_NEXTTX(i), sc->vr_txpending--) { 838 d = VR_CDTX(sc, i); 839 ds = VR_DSTX(sc, i); 840 841 VR_CDTXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 842 843 txstat = le32toh(d->vr_status); 844 845 if (txstat & (VR_TXSTAT_ABRT | VR_TXSTAT_UDF)) { 846 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 847 for (j = 0; j < VR_TIMEOUT; j++) { 848 DELAY(10); 849 if ((CSR_READ_2(sc, VR_COMMAND) & 850 VR_CMD_TX_ON) == 0) 851 break; 852 } 853 if (j == VR_TIMEOUT) { 854 /* XXX need reset? */ 855 printf("%s: TX shutdown never complete\n", 856 device_xname(sc->vr_dev)); 857 } 858 d->vr_status = htole32(VR_TXSTAT_OWN); 859 CSR_WRITE_4(sc, VR_TXADDR, VR_CDTXADDR(sc, i)); 860 break; 861 } 862 863 if (txstat & VR_TXSTAT_OWN) 864 break; 865 866 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 867 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 868 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 869 m_freem(ds->ds_mbuf); 870 ds->ds_mbuf = NULL; 871 872 if (txstat & VR_TXSTAT_ERRSUM) { 873 ifp->if_oerrors++; 874 if (txstat & VR_TXSTAT_DEFER) 875 ifp->if_collisions++; 876 if (txstat & VR_TXSTAT_LATECOLL) 877 ifp->if_collisions++; 878 } 879 880 ifp->if_collisions += (txstat & VR_TXSTAT_COLLCNT) >> 3; 881 ifp->if_opackets++; 882 } 883 884 /* Update the dirty transmit buffer pointer. */ 885 sc->vr_txdirty = i; 886 887 /* 888 * Cancel the watchdog timer if there are no pending 889 * transmissions. 890 */ 891 if (sc->vr_txpending == 0) 892 ifp->if_timer = 0; 893 } 894 895 static int 896 vr_intr(void *arg) 897 { 898 struct vr_softc *sc; 899 struct ifnet *ifp; 900 uint16_t status; 901 int handled = 0, dotx = 0; 902 903 sc = arg; 904 ifp = &sc->vr_ec.ec_if; 905 906 /* Suppress unwanted interrupts. */ 907 if ((ifp->if_flags & IFF_UP) == 0) { 908 vr_stop(ifp, 1); 909 return (0); 910 } 911 912 /* Disable interrupts. */ 913 CSR_WRITE_2(sc, VR_IMR, 0x0000); 914 915 for (;;) { 916 status = CSR_READ_2(sc, VR_ISR); 917 if (status) 918 CSR_WRITE_2(sc, VR_ISR, status); 919 920 if ((status & VR_INTRS) == 0) 921 break; 922 923 handled = 1; 924 925 #if NRND > 0 926 if (RND_ENABLED(&sc->rnd_source)) 927 rnd_add_uint32(&sc->rnd_source, status); 928 #endif 929 930 if (status & VR_ISR_RX_OK) 931 vr_rxeof(sc); 932 933 if (status & VR_ISR_RX_DROPPED) { 934 printf("%s: rx packet lost\n", device_xname(sc->vr_dev)); 935 ifp->if_ierrors++; 936 } 937 938 if (status & 939 (VR_ISR_RX_ERR | VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW)) 940 vr_rxeoc(sc); 941 942 943 if (status & (VR_ISR_BUSERR | VR_ISR_TX_UNDERRUN)) { 944 if (status & VR_ISR_BUSERR) 945 printf("%s: PCI bus error\n", 946 device_xname(sc->vr_dev)); 947 if (status & VR_ISR_TX_UNDERRUN) 948 printf("%s: transmit underrun\n", 949 device_xname(sc->vr_dev)); 950 /* vr_init() calls vr_start() */ 951 dotx = 0; 952 (void)vr_init(ifp); 953 954 } 955 956 if (status & VR_ISR_TX_OK) { 957 dotx = 1; 958 vr_txeof(sc); 959 } 960 961 if (status & 962 (VR_ISR_TX_ABRT | VR_ISR_TX_ABRT2 | VR_ISR_TX_UDFI)) { 963 if (status & (VR_ISR_TX_ABRT | VR_ISR_TX_ABRT2)) 964 printf("%s: transmit aborted\n", 965 device_xname(sc->vr_dev)); 966 if (status & VR_ISR_TX_UDFI) 967 printf("%s: transmit underflow\n", 968 device_xname(sc->vr_dev)); 969 ifp->if_oerrors++; 970 dotx = 1; 971 vr_txeof(sc); 972 if (sc->vr_txpending) { 973 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 974 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 975 } 976 } 977 } 978 979 /* Re-enable interrupts. */ 980 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 981 982 if (dotx) 983 vr_start(ifp); 984 985 return (handled); 986 } 987 988 /* 989 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 990 * to the mbuf data regions directly in the transmit lists. We also save a 991 * copy of the pointers since the transmit list fragment pointers are 992 * physical addresses. 993 */ 994 static void 995 vr_start(struct ifnet *ifp) 996 { 997 struct vr_softc *sc = ifp->if_softc; 998 struct mbuf *m0, *m; 999 struct vr_desc *d; 1000 struct vr_descsoft *ds; 1001 int error, firsttx, nexttx, opending; 1002 1003 /* 1004 * Remember the previous txpending and the first transmit 1005 * descriptor we use. 1006 */ 1007 opending = sc->vr_txpending; 1008 firsttx = VR_NEXTTX(sc->vr_txlast); 1009 1010 /* 1011 * Loop through the send queue, setting up transmit descriptors 1012 * until we drain the queue, or use up all available transmit 1013 * descriptors. 1014 */ 1015 while (sc->vr_txpending < VR_NTXDESC) { 1016 /* 1017 * Grab a packet off the queue. 1018 */ 1019 IFQ_POLL(&ifp->if_snd, m0); 1020 if (m0 == NULL) 1021 break; 1022 m = NULL; 1023 1024 /* 1025 * Get the next available transmit descriptor. 1026 */ 1027 nexttx = VR_NEXTTX(sc->vr_txlast); 1028 d = VR_CDTX(sc, nexttx); 1029 ds = VR_DSTX(sc, nexttx); 1030 1031 /* 1032 * Load the DMA map. If this fails, the packet didn't 1033 * fit in one DMA segment, and we need to copy. Note, 1034 * the packet must also be aligned. 1035 * if the packet is too small, copy it too, so we're sure 1036 * we have enough room for the pad buffer. 1037 */ 1038 if ((mtod(m0, uintptr_t) & 3) != 0 || 1039 m0->m_pkthdr.len < VR_MIN_FRAMELEN || 1040 bus_dmamap_load_mbuf(sc->vr_dmat, ds->ds_dmamap, m0, 1041 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1042 MGETHDR(m, M_DONTWAIT, MT_DATA); 1043 if (m == NULL) { 1044 printf("%s: unable to allocate Tx mbuf\n", 1045 device_xname(sc->vr_dev)); 1046 break; 1047 } 1048 if (m0->m_pkthdr.len > MHLEN) { 1049 MCLGET(m, M_DONTWAIT); 1050 if ((m->m_flags & M_EXT) == 0) { 1051 printf("%s: unable to allocate Tx " 1052 "cluster\n", device_xname(sc->vr_dev)); 1053 m_freem(m); 1054 break; 1055 } 1056 } 1057 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1058 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1059 /* 1060 * The Rhine doesn't auto-pad, so we have to do this 1061 * ourselves. 1062 */ 1063 if (m0->m_pkthdr.len < VR_MIN_FRAMELEN) { 1064 memset(mtod(m, char *) + m0->m_pkthdr.len, 1065 0, VR_MIN_FRAMELEN - m0->m_pkthdr.len); 1066 m->m_pkthdr.len = m->m_len = VR_MIN_FRAMELEN; 1067 } 1068 error = bus_dmamap_load_mbuf(sc->vr_dmat, 1069 ds->ds_dmamap, m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1070 if (error) { 1071 m_freem(m); 1072 printf("%s: unable to load Tx buffer, " 1073 "error = %d\n", device_xname(sc->vr_dev), error); 1074 break; 1075 } 1076 } 1077 1078 IFQ_DEQUEUE(&ifp->if_snd, m0); 1079 if (m != NULL) { 1080 m_freem(m0); 1081 m0 = m; 1082 } 1083 1084 /* Sync the DMA map. */ 1085 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 1086 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1087 1088 /* 1089 * Store a pointer to the packet so we can free it later. 1090 */ 1091 ds->ds_mbuf = m0; 1092 1093 #if NBPFILTER > 0 1094 /* 1095 * If there's a BPF listener, bounce a copy of this frame 1096 * to him. 1097 */ 1098 if (ifp->if_bpf) 1099 bpf_mtap(ifp->if_bpf, m0); 1100 #endif 1101 1102 /* 1103 * Fill in the transmit descriptor. 1104 */ 1105 d->vr_data = htole32(ds->ds_dmamap->dm_segs[0].ds_addr); 1106 d->vr_ctl = htole32(m0->m_pkthdr.len); 1107 d->vr_ctl |= htole32(VR_TXCTL_FIRSTFRAG | VR_TXCTL_LASTFRAG); 1108 1109 /* 1110 * If this is the first descriptor we're enqueuing, 1111 * don't give it to the Rhine yet. That could cause 1112 * a race condition. We'll do it below. 1113 */ 1114 if (nexttx == firsttx) 1115 d->vr_status = 0; 1116 else 1117 d->vr_status = htole32(VR_TXSTAT_OWN); 1118 1119 VR_CDTXSYNC(sc, nexttx, 1120 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1121 1122 /* Advance the tx pointer. */ 1123 sc->vr_txpending++; 1124 sc->vr_txlast = nexttx; 1125 } 1126 1127 if (sc->vr_txpending == VR_NTXDESC) { 1128 /* No more slots left; notify upper layer. */ 1129 ifp->if_flags |= IFF_OACTIVE; 1130 } 1131 1132 if (sc->vr_txpending != opending) { 1133 /* 1134 * We enqueued packets. If the transmitter was idle, 1135 * reset the txdirty pointer. 1136 */ 1137 if (opending == 0) 1138 sc->vr_txdirty = firsttx; 1139 1140 /* 1141 * Cause a transmit interrupt to happen on the 1142 * last packet we enqueued. 1143 */ 1144 VR_CDTX(sc, sc->vr_txlast)->vr_ctl |= htole32(VR_TXCTL_FINT); 1145 VR_CDTXSYNC(sc, sc->vr_txlast, 1146 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1147 1148 /* 1149 * The entire packet chain is set up. Give the 1150 * first descriptor to the Rhine now. 1151 */ 1152 VR_CDTX(sc, firsttx)->vr_status = htole32(VR_TXSTAT_OWN); 1153 VR_CDTXSYNC(sc, firsttx, 1154 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1155 1156 /* Start the transmitter. */ 1157 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1158 1159 /* Set the watchdog timer in case the chip flakes out. */ 1160 ifp->if_timer = 5; 1161 } 1162 } 1163 1164 /* 1165 * Initialize the interface. Must be called at splnet. 1166 */ 1167 static int 1168 vr_init(struct ifnet *ifp) 1169 { 1170 struct vr_softc *sc = ifp->if_softc; 1171 struct vr_desc *d; 1172 struct vr_descsoft *ds; 1173 int i, error = 0; 1174 1175 /* Cancel pending I/O. */ 1176 vr_stop(ifp, 0); 1177 1178 /* Reset the Rhine to a known state. */ 1179 vr_reset(sc); 1180 1181 /* set DMA length in BCR0 and BCR1 */ 1182 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1183 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1184 1185 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1186 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTH_128BYTES); 1187 1188 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1189 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTH_STORENFWD); 1190 1191 /* set DMA threshold length in RXCFG and TXCFG */ 1192 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1193 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1194 1195 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1196 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1197 1198 /* 1199 * Initialize the transmit descriptor ring. txlast is initialized 1200 * to the end of the list so that it will wrap around to the first 1201 * descriptor when the first packet is transmitted. 1202 */ 1203 for (i = 0; i < VR_NTXDESC; i++) { 1204 d = VR_CDTX(sc, i); 1205 memset(d, 0, sizeof(struct vr_desc)); 1206 d->vr_next = htole32(VR_CDTXADDR(sc, VR_NEXTTX(i))); 1207 VR_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1208 } 1209 sc->vr_txpending = 0; 1210 sc->vr_txdirty = 0; 1211 sc->vr_txlast = VR_NTXDESC - 1; 1212 1213 /* 1214 * Initialize the receive descriptor ring. 1215 */ 1216 for (i = 0; i < VR_NRXDESC; i++) { 1217 ds = VR_DSRX(sc, i); 1218 if (ds->ds_mbuf == NULL) { 1219 if ((error = vr_add_rxbuf(sc, i)) != 0) { 1220 printf("%s: unable to allocate or map rx " 1221 "buffer %d, error = %d\n", 1222 device_xname(sc->vr_dev), i, error); 1223 /* 1224 * XXX Should attempt to run with fewer receive 1225 * XXX buffers instead of just failing. 1226 */ 1227 vr_rxdrain(sc); 1228 goto out; 1229 } 1230 } else 1231 VR_INIT_RXDESC(sc, i); 1232 } 1233 sc->vr_rxptr = 0; 1234 1235 /* If we want promiscuous mode, set the allframes bit. */ 1236 if (ifp->if_flags & IFF_PROMISC) 1237 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1238 else 1239 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1240 1241 /* Set capture broadcast bit to capture broadcast frames. */ 1242 if (ifp->if_flags & IFF_BROADCAST) 1243 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1244 else 1245 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1246 1247 /* Program the multicast filter, if necessary. */ 1248 vr_setmulti(sc); 1249 1250 /* Give the transmit and receive rings to the Rhine. */ 1251 CSR_WRITE_4(sc, VR_RXADDR, VR_CDRXADDR(sc, sc->vr_rxptr)); 1252 CSR_WRITE_4(sc, VR_TXADDR, VR_CDTXADDR(sc, VR_NEXTTX(sc->vr_txlast))); 1253 1254 /* Set current media. */ 1255 if ((error = ether_mediachange(ifp)) != 0) 1256 goto out; 1257 1258 /* Enable receiver and transmitter. */ 1259 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1260 VR_CMD_TX_ON|VR_CMD_RX_ON| 1261 VR_CMD_RX_GO); 1262 1263 /* Enable interrupts. */ 1264 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1265 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1266 1267 ifp->if_flags |= IFF_RUNNING; 1268 ifp->if_flags &= ~IFF_OACTIVE; 1269 1270 /* Start one second timer. */ 1271 callout_reset(&sc->vr_tick_ch, hz, vr_tick, sc); 1272 1273 /* Attempt to start output on the interface. */ 1274 vr_start(ifp); 1275 1276 out: 1277 if (error) 1278 printf("%s: interface not running\n", device_xname(sc->vr_dev)); 1279 return (error); 1280 } 1281 1282 static int 1283 vr_ioctl(struct ifnet *ifp, u_long command, void *data) 1284 { 1285 struct vr_softc *sc = ifp->if_softc; 1286 int s, error = 0; 1287 1288 s = splnet(); 1289 1290 error = ether_ioctl(ifp, command, data); 1291 if (error == ENETRESET) { 1292 /* 1293 * Multicast list has changed; set the hardware filter 1294 * accordingly. 1295 */ 1296 if (ifp->if_flags & IFF_RUNNING) 1297 vr_setmulti(sc); 1298 error = 0; 1299 } 1300 1301 splx(s); 1302 return (error); 1303 } 1304 1305 static void 1306 vr_watchdog(struct ifnet *ifp) 1307 { 1308 struct vr_softc *sc = ifp->if_softc; 1309 1310 printf("%s: device timeout\n", device_xname(sc->vr_dev)); 1311 ifp->if_oerrors++; 1312 1313 (void) vr_init(ifp); 1314 } 1315 1316 /* 1317 * One second timer, used to tick MII. 1318 */ 1319 static void 1320 vr_tick(void *arg) 1321 { 1322 struct vr_softc *sc = arg; 1323 int s; 1324 1325 s = splnet(); 1326 mii_tick(&sc->vr_mii); 1327 splx(s); 1328 1329 callout_reset(&sc->vr_tick_ch, hz, vr_tick, sc); 1330 } 1331 1332 /* 1333 * Drain the receive queue. 1334 */ 1335 static void 1336 vr_rxdrain(struct vr_softc *sc) 1337 { 1338 struct vr_descsoft *ds; 1339 int i; 1340 1341 for (i = 0; i < VR_NRXDESC; i++) { 1342 ds = VR_DSRX(sc, i); 1343 if (ds->ds_mbuf != NULL) { 1344 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 1345 m_freem(ds->ds_mbuf); 1346 ds->ds_mbuf = NULL; 1347 } 1348 } 1349 } 1350 1351 /* 1352 * Stop the adapter and free any mbufs allocated to the 1353 * transmit lists. 1354 */ 1355 static void 1356 vr_stop(struct ifnet *ifp, int disable) 1357 { 1358 struct vr_softc *sc = ifp->if_softc; 1359 struct vr_descsoft *ds; 1360 int i; 1361 1362 /* Cancel one second timer. */ 1363 callout_stop(&sc->vr_tick_ch); 1364 1365 /* Down the MII. */ 1366 mii_down(&sc->vr_mii); 1367 1368 ifp = &sc->vr_ec.ec_if; 1369 ifp->if_timer = 0; 1370 1371 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1372 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1373 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1374 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1375 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1376 1377 /* 1378 * Release any queued transmit buffers. 1379 */ 1380 for (i = 0; i < VR_NTXDESC; i++) { 1381 ds = VR_DSTX(sc, i); 1382 if (ds->ds_mbuf != NULL) { 1383 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 1384 m_freem(ds->ds_mbuf); 1385 ds->ds_mbuf = NULL; 1386 } 1387 } 1388 1389 /* 1390 * Mark the interface down and cancel the watchdog timer. 1391 */ 1392 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1393 ifp->if_timer = 0; 1394 1395 if (disable) 1396 vr_rxdrain(sc); 1397 } 1398 1399 static int vr_probe(device_t, struct cfdata *, void *); 1400 static void vr_attach(device_t, device_t, void *); 1401 static void vr_shutdown(void *); 1402 1403 CFATTACH_DECL_NEW(vr, sizeof (struct vr_softc), 1404 vr_probe, vr_attach, NULL, NULL); 1405 1406 static const struct vr_type * 1407 vr_lookup(struct pci_attach_args *pa) 1408 { 1409 const struct vr_type *vrt; 1410 1411 for (vrt = vr_devs; vrt->vr_name != NULL; vrt++) { 1412 if (PCI_VENDOR(pa->pa_id) == vrt->vr_vid && 1413 PCI_PRODUCT(pa->pa_id) == vrt->vr_did) 1414 return (vrt); 1415 } 1416 return (NULL); 1417 } 1418 1419 static int 1420 vr_probe(device_t parent, struct cfdata *match, void *aux) 1421 { 1422 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1423 1424 if (vr_lookup(pa) != NULL) 1425 return (1); 1426 1427 return (0); 1428 } 1429 1430 /* 1431 * Stop all chip I/O so that the kernel's probe routines don't 1432 * get confused by errant DMAs when rebooting. 1433 */ 1434 static void 1435 vr_shutdown(void *arg) 1436 { 1437 struct vr_softc *sc = (struct vr_softc *)arg; 1438 1439 vr_stop(&sc->vr_ec.ec_if, 1); 1440 } 1441 1442 /* 1443 * Attach the interface. Allocate softc structures, do ifmedia 1444 * setup and ethernet/BPF attach. 1445 */ 1446 static void 1447 vr_attach(device_t parent, device_t self, void *aux) 1448 { 1449 struct vr_softc *sc = device_private(self); 1450 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 1451 bus_dma_segment_t seg; 1452 const struct vr_type *vrt; 1453 uint32_t reg; 1454 struct ifnet *ifp; 1455 uint8_t eaddr[ETHER_ADDR_LEN], mac; 1456 int i, rseg, error; 1457 1458 #define PCI_CONF_WRITE(r, v) pci_conf_write(sc->vr_pc, sc->vr_tag, (r), (v)) 1459 #define PCI_CONF_READ(r) pci_conf_read(sc->vr_pc, sc->vr_tag, (r)) 1460 1461 sc->vr_dev = self; 1462 sc->vr_pc = pa->pa_pc; 1463 sc->vr_tag = pa->pa_tag; 1464 callout_init(&sc->vr_tick_ch, 0); 1465 1466 vrt = vr_lookup(pa); 1467 if (vrt == NULL) { 1468 printf("\n"); 1469 panic("vr_attach: impossible"); 1470 } 1471 1472 printf(": %s Ethernet\n", vrt->vr_name); 1473 1474 /* 1475 * Handle power management nonsense. 1476 */ 1477 1478 sc->vr_save_iobase = PCI_CONF_READ(VR_PCI_LOIO); 1479 sc->vr_save_membase = PCI_CONF_READ(VR_PCI_LOMEM); 1480 sc->vr_save_irq = PCI_CONF_READ(PCI_INTERRUPT_REG); 1481 1482 /* power up chip */ 1483 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 1484 vr_restore_state)) && error != EOPNOTSUPP) { 1485 aprint_error_dev(self, "cannot activate %d\n", 1486 error); 1487 return; 1488 } 1489 1490 /* Make sure bus mastering is enabled. */ 1491 reg = PCI_CONF_READ(PCI_COMMAND_STATUS_REG); 1492 reg |= PCI_COMMAND_MASTER_ENABLE; 1493 PCI_CONF_WRITE(PCI_COMMAND_STATUS_REG, reg); 1494 1495 /* Get revision */ 1496 sc->vr_revid = PCI_REVISION(pa->pa_class); 1497 1498 /* 1499 * Map control/status registers. 1500 */ 1501 { 1502 bus_space_tag_t iot, memt; 1503 bus_space_handle_t ioh, memh; 1504 int ioh_valid, memh_valid; 1505 pci_intr_handle_t intrhandle; 1506 const char *intrstr; 1507 1508 ioh_valid = (pci_mapreg_map(pa, VR_PCI_LOIO, 1509 PCI_MAPREG_TYPE_IO, 0, 1510 &iot, &ioh, NULL, NULL) == 0); 1511 memh_valid = (pci_mapreg_map(pa, VR_PCI_LOMEM, 1512 PCI_MAPREG_TYPE_MEM | 1513 PCI_MAPREG_MEM_TYPE_32BIT, 1514 0, &memt, &memh, NULL, NULL) == 0); 1515 #if defined(VR_USEIOSPACE) 1516 if (ioh_valid) { 1517 sc->vr_bst = iot; 1518 sc->vr_bsh = ioh; 1519 } else if (memh_valid) { 1520 sc->vr_bst = memt; 1521 sc->vr_bsh = memh; 1522 } 1523 #else 1524 if (memh_valid) { 1525 sc->vr_bst = memt; 1526 sc->vr_bsh = memh; 1527 } else if (ioh_valid) { 1528 sc->vr_bst = iot; 1529 sc->vr_bsh = ioh; 1530 } 1531 #endif 1532 else { 1533 printf(": unable to map device registers\n"); 1534 return; 1535 } 1536 1537 /* Allocate interrupt */ 1538 if (pci_intr_map(pa, &intrhandle)) { 1539 aprint_error_dev(self, "couldn't map interrupt\n"); 1540 return; 1541 } 1542 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 1543 sc->vr_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 1544 vr_intr, sc); 1545 if (sc->vr_ih == NULL) { 1546 aprint_error_dev(self, "couldn't establish interrupt"); 1547 if (intrstr != NULL) 1548 printf(" at %s", intrstr); 1549 printf("\n"); 1550 } 1551 printf("%s: interrupting at %s\n", 1552 device_xname(self), intrstr); 1553 } 1554 1555 /* 1556 * Windows may put the chip in suspend mode when it 1557 * shuts down. Be sure to kick it in the head to wake it 1558 * up again. 1559 * 1560 * Don't touch this register on VT3043 since it causes 1561 * kernel MCHK trap on macppc. 1562 * (Note some VT86C100A chip returns a product ID of VT3043) 1563 */ 1564 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT3043) 1565 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 1566 1567 /* Reset the adapter. */ 1568 vr_reset(sc); 1569 1570 /* 1571 * Get station address. The way the Rhine chips work, 1572 * you're not allowed to directly access the EEPROM once 1573 * they've been programmed a special way. Consequently, 1574 * we need to read the node address from the PAR0 and PAR1 1575 * registers. 1576 * 1577 * XXXSCW: On the Rhine III, setting VR_EECSR_LOAD forces a reload 1578 * of the *whole* EEPROM, not just the MAC address. This is 1579 * pretty pointless since the chip does this automatically 1580 * at powerup/reset. 1581 * I suspect the same thing applies to the other Rhine 1582 * variants, but in the absence of a data sheet for those 1583 * (and the lack of anyone else noticing the problems this 1584 * causes) I'm going to retain the old behaviour for the 1585 * other parts. 1586 * In some cases, the chip really does startup without having 1587 * read the EEPROM (kern/34812). To handle this case, we force 1588 * a reload if we see an all-zeroes MAC address. 1589 */ 1590 for (mac = 0, i = 0; i < ETHER_ADDR_LEN; i++) 1591 mac |= (eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i)); 1592 1593 if (mac == 0 || (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT6105 && 1594 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT6102)) { 1595 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 1596 DELAY(200); 1597 for (i = 0; i < ETHER_ADDR_LEN; i++) 1598 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 1599 } 1600 1601 /* 1602 * A Rhine chip was detected. Inform the world. 1603 */ 1604 printf("%s: Ethernet address: %s\n", 1605 device_xname(self), ether_sprintf(eaddr)); 1606 1607 memcpy(sc->vr_enaddr, eaddr, ETHER_ADDR_LEN); 1608 1609 sc->vr_dmat = pa->pa_dmat; 1610 1611 /* 1612 * Allocate the control data structures, and create and load 1613 * the DMA map for it. 1614 */ 1615 if ((error = bus_dmamem_alloc(sc->vr_dmat, 1616 sizeof(struct vr_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 1617 0)) != 0) { 1618 aprint_error_dev(self, "unable to allocate control data, error = %d\n", error); 1619 goto fail_0; 1620 } 1621 1622 if ((error = bus_dmamem_map(sc->vr_dmat, &seg, rseg, 1623 sizeof(struct vr_control_data), (void **)&sc->vr_control_data, 1624 BUS_DMA_COHERENT)) != 0) { 1625 aprint_error_dev(self, "unable to map control data, error = %d\n", error); 1626 goto fail_1; 1627 } 1628 1629 if ((error = bus_dmamap_create(sc->vr_dmat, 1630 sizeof(struct vr_control_data), 1, 1631 sizeof(struct vr_control_data), 0, 0, 1632 &sc->vr_cddmamap)) != 0) { 1633 aprint_error_dev(self, "unable to create control data DMA map, " 1634 "error = %d\n", error); 1635 goto fail_2; 1636 } 1637 1638 if ((error = bus_dmamap_load(sc->vr_dmat, sc->vr_cddmamap, 1639 sc->vr_control_data, sizeof(struct vr_control_data), NULL, 1640 0)) != 0) { 1641 aprint_error_dev(self, "unable to load control data DMA map, error = %d\n", 1642 error); 1643 goto fail_3; 1644 } 1645 1646 /* 1647 * Create the transmit buffer DMA maps. 1648 */ 1649 for (i = 0; i < VR_NTXDESC; i++) { 1650 if ((error = bus_dmamap_create(sc->vr_dmat, MCLBYTES, 1651 1, MCLBYTES, 0, 0, 1652 &VR_DSTX(sc, i)->ds_dmamap)) != 0) { 1653 aprint_error_dev(self, "unable to create tx DMA map %d, " 1654 "error = %d\n", i, error); 1655 goto fail_4; 1656 } 1657 } 1658 1659 /* 1660 * Create the receive buffer DMA maps. 1661 */ 1662 for (i = 0; i < VR_NRXDESC; i++) { 1663 if ((error = bus_dmamap_create(sc->vr_dmat, MCLBYTES, 1, 1664 MCLBYTES, 0, 0, 1665 &VR_DSRX(sc, i)->ds_dmamap)) != 0) { 1666 aprint_error_dev(self, "unable to create rx DMA map %d, " 1667 "error = %d\n", i, error); 1668 goto fail_5; 1669 } 1670 VR_DSRX(sc, i)->ds_mbuf = NULL; 1671 } 1672 1673 ifp = &sc->vr_ec.ec_if; 1674 ifp->if_softc = sc; 1675 ifp->if_mtu = ETHERMTU; 1676 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1677 ifp->if_ioctl = vr_ioctl; 1678 ifp->if_start = vr_start; 1679 ifp->if_watchdog = vr_watchdog; 1680 ifp->if_init = vr_init; 1681 ifp->if_stop = vr_stop; 1682 IFQ_SET_READY(&ifp->if_snd); 1683 1684 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 1685 1686 /* 1687 * Initialize MII/media info. 1688 */ 1689 sc->vr_mii.mii_ifp = ifp; 1690 sc->vr_mii.mii_readreg = vr_mii_readreg; 1691 sc->vr_mii.mii_writereg = vr_mii_writereg; 1692 sc->vr_mii.mii_statchg = vr_mii_statchg; 1693 1694 sc->vr_ec.ec_mii = &sc->vr_mii; 1695 ifmedia_init(&sc->vr_mii.mii_media, IFM_IMASK, ether_mediachange, 1696 ether_mediastatus); 1697 mii_attach(self, &sc->vr_mii, 0xffffffff, MII_PHY_ANY, 1698 MII_OFFSET_ANY, MIIF_FORCEANEG); 1699 if (LIST_FIRST(&sc->vr_mii.mii_phys) == NULL) { 1700 ifmedia_add(&sc->vr_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1701 ifmedia_set(&sc->vr_mii.mii_media, IFM_ETHER|IFM_NONE); 1702 } else 1703 ifmedia_set(&sc->vr_mii.mii_media, IFM_ETHER|IFM_AUTO); 1704 1705 /* 1706 * Call MI attach routines. 1707 */ 1708 if_attach(ifp); 1709 ether_ifattach(ifp, sc->vr_enaddr); 1710 #if NRND > 0 1711 rnd_attach_source(&sc->rnd_source, device_xname(self), 1712 RND_TYPE_NET, 0); 1713 #endif 1714 1715 sc->vr_ats = shutdownhook_establish(vr_shutdown, sc); 1716 if (sc->vr_ats == NULL) 1717 aprint_error_dev(self, "warning: couldn't establish shutdown hook\n"); 1718 return; 1719 1720 fail_5: 1721 for (i = 0; i < VR_NRXDESC; i++) { 1722 if (sc->vr_rxsoft[i].ds_dmamap != NULL) 1723 bus_dmamap_destroy(sc->vr_dmat, 1724 sc->vr_rxsoft[i].ds_dmamap); 1725 } 1726 fail_4: 1727 for (i = 0; i < VR_NTXDESC; i++) { 1728 if (sc->vr_txsoft[i].ds_dmamap != NULL) 1729 bus_dmamap_destroy(sc->vr_dmat, 1730 sc->vr_txsoft[i].ds_dmamap); 1731 } 1732 bus_dmamap_unload(sc->vr_dmat, sc->vr_cddmamap); 1733 fail_3: 1734 bus_dmamap_destroy(sc->vr_dmat, sc->vr_cddmamap); 1735 fail_2: 1736 bus_dmamem_unmap(sc->vr_dmat, (void *)sc->vr_control_data, 1737 sizeof(struct vr_control_data)); 1738 fail_1: 1739 bus_dmamem_free(sc->vr_dmat, &seg, rseg); 1740 fail_0: 1741 return; 1742 } 1743 1744 static int 1745 vr_restore_state(pci_chipset_tag_t pc, pcitag_t tag, device_t self, 1746 pcireg_t state) 1747 { 1748 struct vr_softc *sc = device_private(self); 1749 int error; 1750 1751 if (state == PCI_PMCSR_STATE_D0) 1752 return 0; 1753 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 1754 return error; 1755 1756 /* Restore PCI config data. */ 1757 PCI_CONF_WRITE(VR_PCI_LOIO, sc->vr_save_iobase); 1758 PCI_CONF_WRITE(VR_PCI_LOMEM, sc->vr_save_membase); 1759 PCI_CONF_WRITE(PCI_INTERRUPT_REG, sc->vr_save_irq); 1760 return 0; 1761 } 1762