1 /* $NetBSD: if_vr.c,v 1.89 2008/01/19 22:10:19 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1997, 1998 42 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Bill Paul. 55 * 4. Neither the name of the author nor the names of any co-contributors 56 * may be used to endorse or promote products derived from this software 57 * without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 63 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 64 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 65 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 66 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 67 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 68 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 69 * THE POSSIBILITY OF SUCH DAMAGE. 70 * 71 * $FreeBSD: if_vr.c,v 1.7 1999/01/10 18:51:49 wpaul Exp $ 72 */ 73 74 /* 75 * VIA Rhine fast ethernet PCI NIC driver 76 * 77 * Supports various network adapters based on the VIA Rhine 78 * and Rhine II PCI controllers, including the D-Link DFE530TX. 79 * Datasheets are available at http://www.via.com.tw. 80 * 81 * Written by Bill Paul <wpaul@ctr.columbia.edu> 82 * Electrical Engineering Department 83 * Columbia University, New York City 84 */ 85 86 /* 87 * The VIA Rhine controllers are similar in some respects to the 88 * the DEC tulip chips, except less complicated. The controller 89 * uses an MII bus and an external physical layer interface. The 90 * receiver has a one entry perfect filter and a 64-bit hash table 91 * multicast filter. Transmit and receive descriptors are similar 92 * to the tulip. 93 * 94 * The Rhine has a serious flaw in its transmit DMA mechanism: 95 * transmit buffers must be longword aligned. Unfortunately, 96 * the kernel doesn't guarantee that mbufs will be filled in starting 97 * at longword boundaries, so we have to do a buffer copy before 98 * transmission. 99 * 100 * Apparently, the receive DMA mechanism also has the same flaw. This 101 * means that on systems with struct alignment requirements, incoming 102 * frames must be copied to a new buffer which shifts the data forward 103 * 2 bytes so that the payload is aligned on a 4-byte boundary. 104 */ 105 106 #include <sys/cdefs.h> 107 __KERNEL_RCSID(0, "$NetBSD: if_vr.c,v 1.89 2008/01/19 22:10:19 dyoung Exp $"); 108 109 #include "rnd.h" 110 111 #include <sys/param.h> 112 #include <sys/systm.h> 113 #include <sys/callout.h> 114 #include <sys/sockio.h> 115 #include <sys/mbuf.h> 116 #include <sys/malloc.h> 117 #include <sys/kernel.h> 118 #include <sys/socket.h> 119 #include <sys/device.h> 120 121 #if NRND > 0 122 #include <sys/rnd.h> 123 #endif 124 125 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 126 127 #include <net/if.h> 128 #include <net/if_arp.h> 129 #include <net/if_dl.h> 130 #include <net/if_media.h> 131 #include <net/if_ether.h> 132 133 #include "bpfilter.h" 134 #if NBPFILTER > 0 135 #include <net/bpf.h> 136 #endif 137 138 #include <sys/bus.h> 139 #include <sys/intr.h> 140 #include <machine/endian.h> 141 142 #include <dev/mii/mii.h> 143 #include <dev/mii/miivar.h> 144 #include <dev/mii/mii_bitbang.h> 145 146 #include <dev/pci/pcireg.h> 147 #include <dev/pci/pcivar.h> 148 #include <dev/pci/pcidevs.h> 149 150 #include <dev/pci/if_vrreg.h> 151 152 #define VR_USEIOSPACE 153 154 /* 155 * Various supported device vendors/types and their names. 156 */ 157 static struct vr_type { 158 pci_vendor_id_t vr_vid; 159 pci_product_id_t vr_did; 160 const char *vr_name; 161 } vr_devs[] = { 162 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT3043, 163 "VIA VT3043 (Rhine) 10/100" }, 164 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6102, 165 "VIA VT6102 (Rhine II) 10/100" }, 166 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6105, 167 "VIA VT6105 (Rhine III) 10/100" }, 168 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6105M, 169 "VIA VT6105M (Rhine III) 10/100" }, 170 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT86C100A, 171 "VIA VT86C100A (Rhine-II) 10/100" }, 172 { 0, 0, NULL } 173 }; 174 175 /* 176 * Transmit descriptor list size. 177 */ 178 #define VR_NTXDESC 64 179 #define VR_NTXDESC_MASK (VR_NTXDESC - 1) 180 #define VR_NEXTTX(x) (((x) + 1) & VR_NTXDESC_MASK) 181 182 /* 183 * Receive descriptor list size. 184 */ 185 #define VR_NRXDESC 64 186 #define VR_NRXDESC_MASK (VR_NRXDESC - 1) 187 #define VR_NEXTRX(x) (((x) + 1) & VR_NRXDESC_MASK) 188 189 /* 190 * Control data structres that are DMA'd to the Rhine chip. We allocate 191 * them in a single clump that maps to a single DMA segment to make several 192 * things easier. 193 * 194 * Note that since we always copy outgoing packets to aligned transmit 195 * buffers, we can reduce the transmit descriptors to one per packet. 196 */ 197 struct vr_control_data { 198 struct vr_desc vr_txdescs[VR_NTXDESC]; 199 struct vr_desc vr_rxdescs[VR_NRXDESC]; 200 }; 201 202 #define VR_CDOFF(x) offsetof(struct vr_control_data, x) 203 #define VR_CDTXOFF(x) VR_CDOFF(vr_txdescs[(x)]) 204 #define VR_CDRXOFF(x) VR_CDOFF(vr_rxdescs[(x)]) 205 206 /* 207 * Software state of transmit and receive descriptors. 208 */ 209 struct vr_descsoft { 210 struct mbuf *ds_mbuf; /* head of mbuf chain */ 211 bus_dmamap_t ds_dmamap; /* our DMA map */ 212 }; 213 214 struct vr_softc { 215 struct device vr_dev; /* generic device glue */ 216 void *vr_ih; /* interrupt cookie */ 217 void *vr_ats; /* shutdown hook */ 218 bus_space_tag_t vr_bst; /* bus space tag */ 219 bus_space_handle_t vr_bsh; /* bus space handle */ 220 bus_dma_tag_t vr_dmat; /* bus DMA tag */ 221 pci_chipset_tag_t vr_pc; /* PCI chipset info */ 222 pcitag_t vr_tag; /* PCI tag */ 223 struct ethercom vr_ec; /* Ethernet common info */ 224 uint8_t vr_enaddr[ETHER_ADDR_LEN]; 225 struct mii_data vr_mii; /* MII/media info */ 226 227 uint8_t vr_revid; /* Rhine chip revision */ 228 229 callout_t vr_tick_ch; /* tick callout */ 230 231 bus_dmamap_t vr_cddmamap; /* control data DMA map */ 232 #define vr_cddma vr_cddmamap->dm_segs[0].ds_addr 233 234 /* 235 * Software state for transmit and receive descriptors. 236 */ 237 struct vr_descsoft vr_txsoft[VR_NTXDESC]; 238 struct vr_descsoft vr_rxsoft[VR_NRXDESC]; 239 240 /* 241 * Control data structures. 242 */ 243 struct vr_control_data *vr_control_data; 244 245 int vr_txpending; /* number of TX requests pending */ 246 int vr_txdirty; /* first dirty TX descriptor */ 247 int vr_txlast; /* last used TX descriptor */ 248 249 int vr_rxptr; /* next ready RX descriptor */ 250 251 uint32_t vr_save_iobase; 252 uint32_t vr_save_membase; 253 uint32_t vr_save_irq; 254 255 #if NRND > 0 256 rndsource_element_t rnd_source; /* random source */ 257 #endif 258 }; 259 260 #define VR_CDTXADDR(sc, x) ((sc)->vr_cddma + VR_CDTXOFF((x))) 261 #define VR_CDRXADDR(sc, x) ((sc)->vr_cddma + VR_CDRXOFF((x))) 262 263 #define VR_CDTX(sc, x) (&(sc)->vr_control_data->vr_txdescs[(x)]) 264 #define VR_CDRX(sc, x) (&(sc)->vr_control_data->vr_rxdescs[(x)]) 265 266 #define VR_DSTX(sc, x) (&(sc)->vr_txsoft[(x)]) 267 #define VR_DSRX(sc, x) (&(sc)->vr_rxsoft[(x)]) 268 269 #define VR_CDTXSYNC(sc, x, ops) \ 270 bus_dmamap_sync((sc)->vr_dmat, (sc)->vr_cddmamap, \ 271 VR_CDTXOFF((x)), sizeof(struct vr_desc), (ops)) 272 273 #define VR_CDRXSYNC(sc, x, ops) \ 274 bus_dmamap_sync((sc)->vr_dmat, (sc)->vr_cddmamap, \ 275 VR_CDRXOFF((x)), sizeof(struct vr_desc), (ops)) 276 277 /* 278 * Note we rely on MCLBYTES being a power of two below. 279 */ 280 #define VR_INIT_RXDESC(sc, i) \ 281 do { \ 282 struct vr_desc *__d = VR_CDRX((sc), (i)); \ 283 struct vr_descsoft *__ds = VR_DSRX((sc), (i)); \ 284 \ 285 __d->vr_next = htole32(VR_CDRXADDR((sc), VR_NEXTRX((i)))); \ 286 __d->vr_data = htole32(__ds->ds_dmamap->dm_segs[0].ds_addr); \ 287 __d->vr_ctl = htole32(VR_RXCTL_CHAIN | VR_RXCTL_RX_INTR | \ 288 ((MCLBYTES - 1) & VR_RXCTL_BUFLEN)); \ 289 __d->vr_status = htole32(VR_RXSTAT_FIRSTFRAG | \ 290 VR_RXSTAT_LASTFRAG | VR_RXSTAT_OWN); \ 291 VR_CDRXSYNC((sc), (i), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 292 } while (/* CONSTCOND */ 0) 293 294 /* 295 * register space access macros 296 */ 297 #define CSR_WRITE_4(sc, reg, val) \ 298 bus_space_write_4(sc->vr_bst, sc->vr_bsh, reg, val) 299 #define CSR_WRITE_2(sc, reg, val) \ 300 bus_space_write_2(sc->vr_bst, sc->vr_bsh, reg, val) 301 #define CSR_WRITE_1(sc, reg, val) \ 302 bus_space_write_1(sc->vr_bst, sc->vr_bsh, reg, val) 303 304 #define CSR_READ_4(sc, reg) \ 305 bus_space_read_4(sc->vr_bst, sc->vr_bsh, reg) 306 #define CSR_READ_2(sc, reg) \ 307 bus_space_read_2(sc->vr_bst, sc->vr_bsh, reg) 308 #define CSR_READ_1(sc, reg) \ 309 bus_space_read_1(sc->vr_bst, sc->vr_bsh, reg) 310 311 #define VR_TIMEOUT 1000 312 313 static int vr_add_rxbuf(struct vr_softc *, int); 314 315 static void vr_rxeof(struct vr_softc *); 316 static void vr_rxeoc(struct vr_softc *); 317 static void vr_txeof(struct vr_softc *); 318 static int vr_intr(void *); 319 static void vr_start(struct ifnet *); 320 static int vr_ioctl(struct ifnet *, u_long, void *); 321 static int vr_init(struct ifnet *); 322 static void vr_stop(struct ifnet *, int); 323 static void vr_rxdrain(struct vr_softc *); 324 static void vr_watchdog(struct ifnet *); 325 static void vr_tick(void *); 326 327 static int vr_mii_readreg(struct device *, int, int); 328 static void vr_mii_writereg(struct device *, int, int, int); 329 static void vr_mii_statchg(struct device *); 330 331 static void vr_setmulti(struct vr_softc *); 332 static void vr_reset(struct vr_softc *); 333 static int vr_restore_state(pci_chipset_tag_t, pcitag_t, void *, pcireg_t); 334 335 int vr_copy_small = 0; 336 337 #define VR_SETBIT(sc, reg, x) \ 338 CSR_WRITE_1(sc, reg, \ 339 CSR_READ_1(sc, reg) | (x)) 340 341 #define VR_CLRBIT(sc, reg, x) \ 342 CSR_WRITE_1(sc, reg, \ 343 CSR_READ_1(sc, reg) & ~(x)) 344 345 #define VR_SETBIT16(sc, reg, x) \ 346 CSR_WRITE_2(sc, reg, \ 347 CSR_READ_2(sc, reg) | (x)) 348 349 #define VR_CLRBIT16(sc, reg, x) \ 350 CSR_WRITE_2(sc, reg, \ 351 CSR_READ_2(sc, reg) & ~(x)) 352 353 #define VR_SETBIT32(sc, reg, x) \ 354 CSR_WRITE_4(sc, reg, \ 355 CSR_READ_4(sc, reg) | (x)) 356 357 #define VR_CLRBIT32(sc, reg, x) \ 358 CSR_WRITE_4(sc, reg, \ 359 CSR_READ_4(sc, reg) & ~(x)) 360 361 /* 362 * MII bit-bang glue. 363 */ 364 static uint32_t vr_mii_bitbang_read(struct device *); 365 static void vr_mii_bitbang_write(struct device *, uint32_t); 366 367 static const struct mii_bitbang_ops vr_mii_bitbang_ops = { 368 vr_mii_bitbang_read, 369 vr_mii_bitbang_write, 370 { 371 VR_MIICMD_DATAOUT, /* MII_BIT_MDO */ 372 VR_MIICMD_DATAIN, /* MII_BIT_MDI */ 373 VR_MIICMD_CLK, /* MII_BIT_MDC */ 374 VR_MIICMD_DIR, /* MII_BIT_DIR_HOST_PHY */ 375 0, /* MII_BIT_DIR_PHY_HOST */ 376 } 377 }; 378 379 static uint32_t 380 vr_mii_bitbang_read(struct device *self) 381 { 382 struct vr_softc *sc = (void *) self; 383 384 return (CSR_READ_1(sc, VR_MIICMD)); 385 } 386 387 static void 388 vr_mii_bitbang_write(struct device *self, uint32_t val) 389 { 390 struct vr_softc *sc = (void *) self; 391 392 CSR_WRITE_1(sc, VR_MIICMD, (val & 0xff) | VR_MIICMD_DIRECTPGM); 393 } 394 395 /* 396 * Read an PHY register through the MII. 397 */ 398 static int 399 vr_mii_readreg(struct device *self, int phy, int reg) 400 { 401 struct vr_softc *sc = (void *) self; 402 403 CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 404 return (mii_bitbang_readreg(self, &vr_mii_bitbang_ops, phy, reg)); 405 } 406 407 /* 408 * Write to a PHY register through the MII. 409 */ 410 static void 411 vr_mii_writereg(struct device *self, int phy, int reg, int val) 412 { 413 struct vr_softc *sc = (void *) self; 414 415 CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 416 mii_bitbang_writereg(self, &vr_mii_bitbang_ops, phy, reg, val); 417 } 418 419 static void 420 vr_mii_statchg(struct device *self) 421 { 422 struct vr_softc *sc = (struct vr_softc *)self; 423 424 /* 425 * In order to fiddle with the 'full-duplex' bit in the netconfig 426 * register, we first have to put the transmit and/or receive logic 427 * in the idle state. 428 */ 429 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 430 431 if (sc->vr_mii.mii_media_active & IFM_FDX) 432 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 433 else 434 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 435 436 if (sc->vr_ec.ec_if.if_flags & IFF_RUNNING) 437 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 438 } 439 440 #define vr_calchash(addr) \ 441 (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26) 442 443 /* 444 * Program the 64-bit multicast hash filter. 445 */ 446 static void 447 vr_setmulti(struct vr_softc *sc) 448 { 449 struct ifnet *ifp; 450 int h = 0; 451 uint32_t hashes[2] = { 0, 0 }; 452 struct ether_multistep step; 453 struct ether_multi *enm; 454 int mcnt = 0; 455 uint8_t rxfilt; 456 457 ifp = &sc->vr_ec.ec_if; 458 459 rxfilt = CSR_READ_1(sc, VR_RXCFG); 460 461 if (ifp->if_flags & IFF_PROMISC) { 462 allmulti: 463 ifp->if_flags |= IFF_ALLMULTI; 464 rxfilt |= VR_RXCFG_RX_MULTI; 465 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 466 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 467 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 468 return; 469 } 470 471 /* first, zot all the existing hash bits */ 472 CSR_WRITE_4(sc, VR_MAR0, 0); 473 CSR_WRITE_4(sc, VR_MAR1, 0); 474 475 /* now program new ones */ 476 ETHER_FIRST_MULTI(step, &sc->vr_ec, enm); 477 while (enm != NULL) { 478 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 479 ETHER_ADDR_LEN) != 0) 480 goto allmulti; 481 482 h = vr_calchash(enm->enm_addrlo); 483 484 if (h < 32) 485 hashes[0] |= (1 << h); 486 else 487 hashes[1] |= (1 << (h - 32)); 488 ETHER_NEXT_MULTI(step, enm); 489 mcnt++; 490 } 491 492 ifp->if_flags &= ~IFF_ALLMULTI; 493 494 if (mcnt) 495 rxfilt |= VR_RXCFG_RX_MULTI; 496 else 497 rxfilt &= ~VR_RXCFG_RX_MULTI; 498 499 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 500 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 501 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 502 } 503 504 static void 505 vr_reset(struct vr_softc *sc) 506 { 507 int i; 508 509 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 510 511 for (i = 0; i < VR_TIMEOUT; i++) { 512 DELAY(10); 513 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 514 break; 515 } 516 if (i == VR_TIMEOUT) { 517 if (sc->vr_revid < REV_ID_VT3065_A) { 518 printf("%s: reset never completed!\n", 519 sc->vr_dev.dv_xname); 520 } else { 521 /* Use newer force reset command */ 522 printf("%s: using force reset command.\n", 523 sc->vr_dev.dv_xname); 524 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 525 } 526 } 527 528 /* Wait a little while for the chip to get its brains in order. */ 529 DELAY(1000); 530 } 531 532 /* 533 * Initialize an RX descriptor and attach an MBUF cluster. 534 * Note: the length fields are only 11 bits wide, which means the 535 * largest size we can specify is 2047. This is important because 536 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 537 * overflow the field and make a mess. 538 */ 539 static int 540 vr_add_rxbuf(struct vr_softc *sc, int i) 541 { 542 struct vr_descsoft *ds = VR_DSRX(sc, i); 543 struct mbuf *m_new; 544 int error; 545 546 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 547 if (m_new == NULL) 548 return (ENOBUFS); 549 550 MCLGET(m_new, M_DONTWAIT); 551 if ((m_new->m_flags & M_EXT) == 0) { 552 m_freem(m_new); 553 return (ENOBUFS); 554 } 555 556 if (ds->ds_mbuf != NULL) 557 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 558 559 ds->ds_mbuf = m_new; 560 561 error = bus_dmamap_load(sc->vr_dmat, ds->ds_dmamap, 562 m_new->m_ext.ext_buf, m_new->m_ext.ext_size, NULL, 563 BUS_DMA_READ|BUS_DMA_NOWAIT); 564 if (error) { 565 printf("%s: unable to load rx DMA map %d, error = %d\n", 566 sc->vr_dev.dv_xname, i, error); 567 panic("vr_add_rxbuf"); /* XXX */ 568 } 569 570 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 571 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 572 573 VR_INIT_RXDESC(sc, i); 574 575 return (0); 576 } 577 578 /* 579 * A frame has been uploaded: pass the resulting mbuf chain up to 580 * the higher level protocols. 581 */ 582 static void 583 vr_rxeof(struct vr_softc *sc) 584 { 585 struct mbuf *m; 586 struct ifnet *ifp; 587 struct vr_desc *d; 588 struct vr_descsoft *ds; 589 int i, total_len; 590 uint32_t rxstat; 591 592 ifp = &sc->vr_ec.ec_if; 593 594 for (i = sc->vr_rxptr;; i = VR_NEXTRX(i)) { 595 d = VR_CDRX(sc, i); 596 ds = VR_DSRX(sc, i); 597 598 VR_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 599 600 rxstat = le32toh(d->vr_status); 601 602 if (rxstat & VR_RXSTAT_OWN) { 603 /* 604 * We have processed all of the receive buffers. 605 */ 606 break; 607 } 608 609 /* 610 * If an error occurs, update stats, clear the 611 * status word and leave the mbuf cluster in place: 612 * it should simply get re-used next time this descriptor 613 * comes up in the ring. 614 */ 615 if (rxstat & VR_RXSTAT_RXERR) { 616 const char *errstr; 617 618 ifp->if_ierrors++; 619 switch (rxstat & 0x000000FF) { 620 case VR_RXSTAT_CRCERR: 621 errstr = "crc error"; 622 break; 623 case VR_RXSTAT_FRAMEALIGNERR: 624 errstr = "frame alignment error"; 625 break; 626 case VR_RXSTAT_FIFOOFLOW: 627 errstr = "FIFO overflow"; 628 break; 629 case VR_RXSTAT_GIANT: 630 errstr = "received giant packet"; 631 break; 632 case VR_RXSTAT_RUNT: 633 errstr = "received runt packet"; 634 break; 635 case VR_RXSTAT_BUSERR: 636 errstr = "system bus error"; 637 break; 638 case VR_RXSTAT_BUFFERR: 639 errstr = "rx buffer error"; 640 break; 641 default: 642 errstr = "unknown rx error"; 643 break; 644 } 645 printf("%s: receive error: %s\n", sc->vr_dev.dv_xname, 646 errstr); 647 648 VR_INIT_RXDESC(sc, i); 649 650 continue; 651 } else if (!(rxstat & VR_RXSTAT_FIRSTFRAG) || 652 !(rxstat & VR_RXSTAT_LASTFRAG)) { 653 /* 654 * This driver expects to receive whole packets every 655 * time. In case we receive a fragment that is not 656 * a complete packet, we discard it. 657 */ 658 ifp->if_ierrors++; 659 660 printf("%s: receive error: incomplete frame; " 661 "size = %d, status = 0x%x\n", 662 sc->vr_dev.dv_xname, 663 VR_RXBYTES(le32toh(d->vr_status)), rxstat); 664 665 VR_INIT_RXDESC(sc, i); 666 667 continue; 668 } 669 670 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 671 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 672 673 /* No errors; receive the packet. */ 674 total_len = VR_RXBYTES(le32toh(d->vr_status)); 675 #ifdef DIAGNOSTIC 676 if (total_len == 0) { 677 /* 678 * If we receive a zero-length packet, we probably 679 * missed to handle an error condition above. 680 * Discard it to avoid a later crash. 681 */ 682 ifp->if_ierrors++; 683 684 printf("%s: receive error: zero-length packet; " 685 "status = 0x%x\n", 686 sc->vr_dev.dv_xname, rxstat); 687 688 VR_INIT_RXDESC(sc, i); 689 690 continue; 691 } 692 #endif 693 694 /* 695 * The Rhine chip includes the CRC with every packet. 696 * Trim it off here. 697 */ 698 total_len -= ETHER_CRC_LEN; 699 700 #ifdef __NO_STRICT_ALIGNMENT 701 /* 702 * If the packet is small enough to fit in a 703 * single header mbuf, allocate one and copy 704 * the data into it. This greatly reduces 705 * memory consumption when we receive lots 706 * of small packets. 707 * 708 * Otherwise, we add a new buffer to the receive 709 * chain. If this fails, we drop the packet and 710 * recycle the old buffer. 711 */ 712 if (vr_copy_small != 0 && total_len <= MHLEN) { 713 MGETHDR(m, M_DONTWAIT, MT_DATA); 714 if (m == NULL) 715 goto dropit; 716 memcpy(mtod(m, void *), 717 mtod(ds->ds_mbuf, void *), total_len); 718 VR_INIT_RXDESC(sc, i); 719 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 720 ds->ds_dmamap->dm_mapsize, 721 BUS_DMASYNC_PREREAD); 722 } else { 723 m = ds->ds_mbuf; 724 if (vr_add_rxbuf(sc, i) == ENOBUFS) { 725 dropit: 726 ifp->if_ierrors++; 727 VR_INIT_RXDESC(sc, i); 728 bus_dmamap_sync(sc->vr_dmat, 729 ds->ds_dmamap, 0, 730 ds->ds_dmamap->dm_mapsize, 731 BUS_DMASYNC_PREREAD); 732 continue; 733 } 734 } 735 #else 736 /* 737 * The Rhine's packet buffers must be 4-byte aligned. 738 * But this means that the data after the Ethernet header 739 * is misaligned. We must allocate a new buffer and 740 * copy the data, shifted forward 2 bytes. 741 */ 742 MGETHDR(m, M_DONTWAIT, MT_DATA); 743 if (m == NULL) { 744 dropit: 745 ifp->if_ierrors++; 746 VR_INIT_RXDESC(sc, i); 747 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 748 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 749 continue; 750 } 751 if (total_len > (MHLEN - 2)) { 752 MCLGET(m, M_DONTWAIT); 753 if ((m->m_flags & M_EXT) == 0) { 754 m_freem(m); 755 goto dropit; 756 } 757 } 758 m->m_data += 2; 759 760 /* 761 * Note that we use clusters for incoming frames, so the 762 * buffer is virtually contiguous. 763 */ 764 memcpy(mtod(m, void *), mtod(ds->ds_mbuf, void *), 765 total_len); 766 767 /* Allow the receive descriptor to continue using its mbuf. */ 768 VR_INIT_RXDESC(sc, i); 769 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 770 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 771 #endif /* __NO_STRICT_ALIGNMENT */ 772 773 ifp->if_ipackets++; 774 m->m_pkthdr.rcvif = ifp; 775 m->m_pkthdr.len = m->m_len = total_len; 776 #if NBPFILTER > 0 777 /* 778 * Handle BPF listeners. Let the BPF user see the packet, but 779 * don't pass it up to the ether_input() layer unless it's 780 * a broadcast packet, multicast packet, matches our ethernet 781 * address or the interface is in promiscuous mode. 782 */ 783 if (ifp->if_bpf) 784 bpf_mtap(ifp->if_bpf, m); 785 #endif 786 /* Pass it on. */ 787 (*ifp->if_input)(ifp, m); 788 } 789 790 /* Update the receive pointer. */ 791 sc->vr_rxptr = i; 792 } 793 794 void 795 vr_rxeoc(struct vr_softc *sc) 796 { 797 struct ifnet *ifp; 798 int i; 799 800 ifp = &sc->vr_ec.ec_if; 801 802 ifp->if_ierrors++; 803 804 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 805 for (i = 0; i < VR_TIMEOUT; i++) { 806 DELAY(10); 807 if ((CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON) == 0) 808 break; 809 } 810 if (i == VR_TIMEOUT) { 811 /* XXX need reset? */ 812 printf("%s: RX shutdown never complete\n", 813 sc->vr_dev.dv_xname); 814 } 815 816 vr_rxeof(sc); 817 818 CSR_WRITE_4(sc, VR_RXADDR, VR_CDRXADDR(sc, sc->vr_rxptr)); 819 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 820 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 821 } 822 823 /* 824 * A frame was downloaded to the chip. It's safe for us to clean up 825 * the list buffers. 826 */ 827 static void 828 vr_txeof(struct vr_softc *sc) 829 { 830 struct ifnet *ifp = &sc->vr_ec.ec_if; 831 struct vr_desc *d; 832 struct vr_descsoft *ds; 833 uint32_t txstat; 834 int i, j; 835 836 ifp->if_flags &= ~IFF_OACTIVE; 837 838 /* 839 * Go through our tx list and free mbufs for those 840 * frames that have been transmitted. 841 */ 842 for (i = sc->vr_txdirty; sc->vr_txpending != 0; 843 i = VR_NEXTTX(i), sc->vr_txpending--) { 844 d = VR_CDTX(sc, i); 845 ds = VR_DSTX(sc, i); 846 847 VR_CDTXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 848 849 txstat = le32toh(d->vr_status); 850 851 if (txstat & (VR_TXSTAT_ABRT | VR_TXSTAT_UDF)) { 852 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 853 for (j = 0; j < VR_TIMEOUT; j++) { 854 DELAY(10); 855 if ((CSR_READ_2(sc, VR_COMMAND) & 856 VR_CMD_TX_ON) == 0) 857 break; 858 } 859 if (j == VR_TIMEOUT) { 860 /* XXX need reset? */ 861 printf("%s: TX shutdown never complete\n", 862 sc->vr_dev.dv_xname); 863 } 864 d->vr_status = htole32(VR_TXSTAT_OWN); 865 CSR_WRITE_4(sc, VR_TXADDR, VR_CDTXADDR(sc, i)); 866 break; 867 } 868 869 if (txstat & VR_TXSTAT_OWN) 870 break; 871 872 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 873 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 874 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 875 m_freem(ds->ds_mbuf); 876 ds->ds_mbuf = NULL; 877 878 if (txstat & VR_TXSTAT_ERRSUM) { 879 ifp->if_oerrors++; 880 if (txstat & VR_TXSTAT_DEFER) 881 ifp->if_collisions++; 882 if (txstat & VR_TXSTAT_LATECOLL) 883 ifp->if_collisions++; 884 } 885 886 ifp->if_collisions += (txstat & VR_TXSTAT_COLLCNT) >> 3; 887 ifp->if_opackets++; 888 } 889 890 /* Update the dirty transmit buffer pointer. */ 891 sc->vr_txdirty = i; 892 893 /* 894 * Cancel the watchdog timer if there are no pending 895 * transmissions. 896 */ 897 if (sc->vr_txpending == 0) 898 ifp->if_timer = 0; 899 } 900 901 static int 902 vr_intr(void *arg) 903 { 904 struct vr_softc *sc; 905 struct ifnet *ifp; 906 uint16_t status; 907 int handled = 0, dotx = 0; 908 909 sc = arg; 910 ifp = &sc->vr_ec.ec_if; 911 912 /* Suppress unwanted interrupts. */ 913 if ((ifp->if_flags & IFF_UP) == 0) { 914 vr_stop(ifp, 1); 915 return (0); 916 } 917 918 /* Disable interrupts. */ 919 CSR_WRITE_2(sc, VR_IMR, 0x0000); 920 921 for (;;) { 922 status = CSR_READ_2(sc, VR_ISR); 923 if (status) 924 CSR_WRITE_2(sc, VR_ISR, status); 925 926 if ((status & VR_INTRS) == 0) 927 break; 928 929 handled = 1; 930 931 #if NRND > 0 932 if (RND_ENABLED(&sc->rnd_source)) 933 rnd_add_uint32(&sc->rnd_source, status); 934 #endif 935 936 if (status & VR_ISR_RX_OK) 937 vr_rxeof(sc); 938 939 if (status & VR_ISR_RX_DROPPED) { 940 printf("%s: rx packet lost\n", sc->vr_dev.dv_xname); 941 ifp->if_ierrors++; 942 } 943 944 if (status & 945 (VR_ISR_RX_ERR | VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW)) 946 vr_rxeoc(sc); 947 948 949 if (status & (VR_ISR_BUSERR | VR_ISR_TX_UNDERRUN)) { 950 if (status & VR_ISR_BUSERR) 951 printf("%s: PCI bus error\n", 952 sc->vr_dev.dv_xname); 953 if (status & VR_ISR_TX_UNDERRUN) 954 printf("%s: transmit underrun\n", 955 sc->vr_dev.dv_xname); 956 /* vr_init() calls vr_start() */ 957 dotx = 0; 958 (void)vr_init(ifp); 959 960 } 961 962 if (status & VR_ISR_TX_OK) { 963 dotx = 1; 964 vr_txeof(sc); 965 } 966 967 if (status & 968 (VR_ISR_TX_ABRT | VR_ISR_TX_ABRT2 | VR_ISR_TX_UDFI)) { 969 if (status & (VR_ISR_TX_ABRT | VR_ISR_TX_ABRT2)) 970 printf("%s: transmit aborted\n", 971 sc->vr_dev.dv_xname); 972 if (status & VR_ISR_TX_UDFI) 973 printf("%s: transmit underflow\n", 974 sc->vr_dev.dv_xname); 975 ifp->if_oerrors++; 976 dotx = 1; 977 vr_txeof(sc); 978 if (sc->vr_txpending) { 979 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 980 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 981 } 982 } 983 } 984 985 /* Re-enable interrupts. */ 986 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 987 988 if (dotx) 989 vr_start(ifp); 990 991 return (handled); 992 } 993 994 /* 995 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 996 * to the mbuf data regions directly in the transmit lists. We also save a 997 * copy of the pointers since the transmit list fragment pointers are 998 * physical addresses. 999 */ 1000 static void 1001 vr_start(struct ifnet *ifp) 1002 { 1003 struct vr_softc *sc = ifp->if_softc; 1004 struct mbuf *m0, *m; 1005 struct vr_desc *d; 1006 struct vr_descsoft *ds; 1007 int error, firsttx, nexttx, opending; 1008 1009 /* 1010 * Remember the previous txpending and the first transmit 1011 * descriptor we use. 1012 */ 1013 opending = sc->vr_txpending; 1014 firsttx = VR_NEXTTX(sc->vr_txlast); 1015 1016 /* 1017 * Loop through the send queue, setting up transmit descriptors 1018 * until we drain the queue, or use up all available transmit 1019 * descriptors. 1020 */ 1021 while (sc->vr_txpending < VR_NTXDESC) { 1022 /* 1023 * Grab a packet off the queue. 1024 */ 1025 IFQ_POLL(&ifp->if_snd, m0); 1026 if (m0 == NULL) 1027 break; 1028 m = NULL; 1029 1030 /* 1031 * Get the next available transmit descriptor. 1032 */ 1033 nexttx = VR_NEXTTX(sc->vr_txlast); 1034 d = VR_CDTX(sc, nexttx); 1035 ds = VR_DSTX(sc, nexttx); 1036 1037 /* 1038 * Load the DMA map. If this fails, the packet didn't 1039 * fit in one DMA segment, and we need to copy. Note, 1040 * the packet must also be aligned. 1041 * if the packet is too small, copy it too, so we're sure 1042 * we have enough room for the pad buffer. 1043 */ 1044 if ((mtod(m0, uintptr_t) & 3) != 0 || 1045 m0->m_pkthdr.len < VR_MIN_FRAMELEN || 1046 bus_dmamap_load_mbuf(sc->vr_dmat, ds->ds_dmamap, m0, 1047 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1048 MGETHDR(m, M_DONTWAIT, MT_DATA); 1049 if (m == NULL) { 1050 printf("%s: unable to allocate Tx mbuf\n", 1051 sc->vr_dev.dv_xname); 1052 break; 1053 } 1054 if (m0->m_pkthdr.len > MHLEN) { 1055 MCLGET(m, M_DONTWAIT); 1056 if ((m->m_flags & M_EXT) == 0) { 1057 printf("%s: unable to allocate Tx " 1058 "cluster\n", sc->vr_dev.dv_xname); 1059 m_freem(m); 1060 break; 1061 } 1062 } 1063 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1064 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1065 /* 1066 * The Rhine doesn't auto-pad, so we have to do this 1067 * ourselves. 1068 */ 1069 if (m0->m_pkthdr.len < VR_MIN_FRAMELEN) { 1070 memset(mtod(m, char *) + m0->m_pkthdr.len, 1071 0, VR_MIN_FRAMELEN - m0->m_pkthdr.len); 1072 m->m_pkthdr.len = m->m_len = VR_MIN_FRAMELEN; 1073 } 1074 error = bus_dmamap_load_mbuf(sc->vr_dmat, 1075 ds->ds_dmamap, m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1076 if (error) { 1077 m_freem(m); 1078 printf("%s: unable to load Tx buffer, " 1079 "error = %d\n", sc->vr_dev.dv_xname, error); 1080 break; 1081 } 1082 } 1083 1084 IFQ_DEQUEUE(&ifp->if_snd, m0); 1085 if (m != NULL) { 1086 m_freem(m0); 1087 m0 = m; 1088 } 1089 1090 /* Sync the DMA map. */ 1091 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 1092 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1093 1094 /* 1095 * Store a pointer to the packet so we can free it later. 1096 */ 1097 ds->ds_mbuf = m0; 1098 1099 #if NBPFILTER > 0 1100 /* 1101 * If there's a BPF listener, bounce a copy of this frame 1102 * to him. 1103 */ 1104 if (ifp->if_bpf) 1105 bpf_mtap(ifp->if_bpf, m0); 1106 #endif 1107 1108 /* 1109 * Fill in the transmit descriptor. 1110 */ 1111 d->vr_data = htole32(ds->ds_dmamap->dm_segs[0].ds_addr); 1112 d->vr_ctl = htole32(m0->m_pkthdr.len); 1113 d->vr_ctl |= htole32(VR_TXCTL_FIRSTFRAG | VR_TXCTL_LASTFRAG); 1114 1115 /* 1116 * If this is the first descriptor we're enqueuing, 1117 * don't give it to the Rhine yet. That could cause 1118 * a race condition. We'll do it below. 1119 */ 1120 if (nexttx == firsttx) 1121 d->vr_status = 0; 1122 else 1123 d->vr_status = htole32(VR_TXSTAT_OWN); 1124 1125 VR_CDTXSYNC(sc, nexttx, 1126 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1127 1128 /* Advance the tx pointer. */ 1129 sc->vr_txpending++; 1130 sc->vr_txlast = nexttx; 1131 } 1132 1133 if (sc->vr_txpending == VR_NTXDESC) { 1134 /* No more slots left; notify upper layer. */ 1135 ifp->if_flags |= IFF_OACTIVE; 1136 } 1137 1138 if (sc->vr_txpending != opending) { 1139 /* 1140 * We enqueued packets. If the transmitter was idle, 1141 * reset the txdirty pointer. 1142 */ 1143 if (opending == 0) 1144 sc->vr_txdirty = firsttx; 1145 1146 /* 1147 * Cause a transmit interrupt to happen on the 1148 * last packet we enqueued. 1149 */ 1150 VR_CDTX(sc, sc->vr_txlast)->vr_ctl |= htole32(VR_TXCTL_FINT); 1151 VR_CDTXSYNC(sc, sc->vr_txlast, 1152 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1153 1154 /* 1155 * The entire packet chain is set up. Give the 1156 * first descriptor to the Rhine now. 1157 */ 1158 VR_CDTX(sc, firsttx)->vr_status = htole32(VR_TXSTAT_OWN); 1159 VR_CDTXSYNC(sc, firsttx, 1160 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1161 1162 /* Start the transmitter. */ 1163 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1164 1165 /* Set the watchdog timer in case the chip flakes out. */ 1166 ifp->if_timer = 5; 1167 } 1168 } 1169 1170 /* 1171 * Initialize the interface. Must be called at splnet. 1172 */ 1173 static int 1174 vr_init(struct ifnet *ifp) 1175 { 1176 struct vr_softc *sc = ifp->if_softc; 1177 struct vr_desc *d; 1178 struct vr_descsoft *ds; 1179 int i, error = 0; 1180 1181 /* Cancel pending I/O. */ 1182 vr_stop(ifp, 0); 1183 1184 /* Reset the Rhine to a known state. */ 1185 vr_reset(sc); 1186 1187 /* set DMA length in BCR0 and BCR1 */ 1188 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1189 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1190 1191 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1192 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTH_128BYTES); 1193 1194 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1195 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTH_STORENFWD); 1196 1197 /* set DMA threshold length in RXCFG and TXCFG */ 1198 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1199 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1200 1201 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1202 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1203 1204 /* 1205 * Initialize the transmit descriptor ring. txlast is initialized 1206 * to the end of the list so that it will wrap around to the first 1207 * descriptor when the first packet is transmitted. 1208 */ 1209 for (i = 0; i < VR_NTXDESC; i++) { 1210 d = VR_CDTX(sc, i); 1211 memset(d, 0, sizeof(struct vr_desc)); 1212 d->vr_next = htole32(VR_CDTXADDR(sc, VR_NEXTTX(i))); 1213 VR_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1214 } 1215 sc->vr_txpending = 0; 1216 sc->vr_txdirty = 0; 1217 sc->vr_txlast = VR_NTXDESC - 1; 1218 1219 /* 1220 * Initialize the receive descriptor ring. 1221 */ 1222 for (i = 0; i < VR_NRXDESC; i++) { 1223 ds = VR_DSRX(sc, i); 1224 if (ds->ds_mbuf == NULL) { 1225 if ((error = vr_add_rxbuf(sc, i)) != 0) { 1226 printf("%s: unable to allocate or map rx " 1227 "buffer %d, error = %d\n", 1228 sc->vr_dev.dv_xname, i, error); 1229 /* 1230 * XXX Should attempt to run with fewer receive 1231 * XXX buffers instead of just failing. 1232 */ 1233 vr_rxdrain(sc); 1234 goto out; 1235 } 1236 } else 1237 VR_INIT_RXDESC(sc, i); 1238 } 1239 sc->vr_rxptr = 0; 1240 1241 /* If we want promiscuous mode, set the allframes bit. */ 1242 if (ifp->if_flags & IFF_PROMISC) 1243 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1244 else 1245 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1246 1247 /* Set capture broadcast bit to capture broadcast frames. */ 1248 if (ifp->if_flags & IFF_BROADCAST) 1249 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1250 else 1251 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1252 1253 /* Program the multicast filter, if necessary. */ 1254 vr_setmulti(sc); 1255 1256 /* Give the transmit and receive rings to the Rhine. */ 1257 CSR_WRITE_4(sc, VR_RXADDR, VR_CDRXADDR(sc, sc->vr_rxptr)); 1258 CSR_WRITE_4(sc, VR_TXADDR, VR_CDTXADDR(sc, VR_NEXTTX(sc->vr_txlast))); 1259 1260 /* Set current media. */ 1261 if ((error = ether_mediachange(ifp)) != 0) 1262 goto out; 1263 1264 /* Enable receiver and transmitter. */ 1265 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1266 VR_CMD_TX_ON|VR_CMD_RX_ON| 1267 VR_CMD_RX_GO); 1268 1269 /* Enable interrupts. */ 1270 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1271 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1272 1273 ifp->if_flags |= IFF_RUNNING; 1274 ifp->if_flags &= ~IFF_OACTIVE; 1275 1276 /* Start one second timer. */ 1277 callout_reset(&sc->vr_tick_ch, hz, vr_tick, sc); 1278 1279 /* Attempt to start output on the interface. */ 1280 vr_start(ifp); 1281 1282 out: 1283 if (error) 1284 printf("%s: interface not running\n", sc->vr_dev.dv_xname); 1285 return (error); 1286 } 1287 1288 static int 1289 vr_ioctl(struct ifnet *ifp, u_long command, void *data) 1290 { 1291 struct vr_softc *sc = ifp->if_softc; 1292 int s, error = 0; 1293 1294 s = splnet(); 1295 1296 error = ether_ioctl(ifp, command, data); 1297 if (error == ENETRESET) { 1298 /* 1299 * Multicast list has changed; set the hardware filter 1300 * accordingly. 1301 */ 1302 if (ifp->if_flags & IFF_RUNNING) 1303 vr_setmulti(sc); 1304 error = 0; 1305 } 1306 1307 splx(s); 1308 return (error); 1309 } 1310 1311 static void 1312 vr_watchdog(struct ifnet *ifp) 1313 { 1314 struct vr_softc *sc = ifp->if_softc; 1315 1316 printf("%s: device timeout\n", sc->vr_dev.dv_xname); 1317 ifp->if_oerrors++; 1318 1319 (void) vr_init(ifp); 1320 } 1321 1322 /* 1323 * One second timer, used to tick MII. 1324 */ 1325 static void 1326 vr_tick(void *arg) 1327 { 1328 struct vr_softc *sc = arg; 1329 int s; 1330 1331 s = splnet(); 1332 mii_tick(&sc->vr_mii); 1333 splx(s); 1334 1335 callout_reset(&sc->vr_tick_ch, hz, vr_tick, sc); 1336 } 1337 1338 /* 1339 * Drain the receive queue. 1340 */ 1341 static void 1342 vr_rxdrain(struct vr_softc *sc) 1343 { 1344 struct vr_descsoft *ds; 1345 int i; 1346 1347 for (i = 0; i < VR_NRXDESC; i++) { 1348 ds = VR_DSRX(sc, i); 1349 if (ds->ds_mbuf != NULL) { 1350 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 1351 m_freem(ds->ds_mbuf); 1352 ds->ds_mbuf = NULL; 1353 } 1354 } 1355 } 1356 1357 /* 1358 * Stop the adapter and free any mbufs allocated to the 1359 * transmit lists. 1360 */ 1361 static void 1362 vr_stop(struct ifnet *ifp, int disable) 1363 { 1364 struct vr_softc *sc = ifp->if_softc; 1365 struct vr_descsoft *ds; 1366 int i; 1367 1368 /* Cancel one second timer. */ 1369 callout_stop(&sc->vr_tick_ch); 1370 1371 /* Down the MII. */ 1372 mii_down(&sc->vr_mii); 1373 1374 ifp = &sc->vr_ec.ec_if; 1375 ifp->if_timer = 0; 1376 1377 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1378 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1379 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1380 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1381 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1382 1383 /* 1384 * Release any queued transmit buffers. 1385 */ 1386 for (i = 0; i < VR_NTXDESC; i++) { 1387 ds = VR_DSTX(sc, i); 1388 if (ds->ds_mbuf != NULL) { 1389 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 1390 m_freem(ds->ds_mbuf); 1391 ds->ds_mbuf = NULL; 1392 } 1393 } 1394 1395 if (disable) 1396 vr_rxdrain(sc); 1397 1398 /* 1399 * Mark the interface down and cancel the watchdog timer. 1400 */ 1401 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1402 ifp->if_timer = 0; 1403 } 1404 1405 static int vr_probe(struct device *, struct cfdata *, void *); 1406 static void vr_attach(struct device *, struct device *, void *); 1407 static void vr_shutdown(void *); 1408 1409 CFATTACH_DECL(vr, sizeof (struct vr_softc), 1410 vr_probe, vr_attach, NULL, NULL); 1411 1412 static struct vr_type * 1413 vr_lookup(struct pci_attach_args *pa) 1414 { 1415 struct vr_type *vrt; 1416 1417 for (vrt = vr_devs; vrt->vr_name != NULL; vrt++) { 1418 if (PCI_VENDOR(pa->pa_id) == vrt->vr_vid && 1419 PCI_PRODUCT(pa->pa_id) == vrt->vr_did) 1420 return (vrt); 1421 } 1422 return (NULL); 1423 } 1424 1425 static int 1426 vr_probe(struct device *parent, struct cfdata *match, 1427 void *aux) 1428 { 1429 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1430 1431 if (vr_lookup(pa) != NULL) 1432 return (1); 1433 1434 return (0); 1435 } 1436 1437 /* 1438 * Stop all chip I/O so that the kernel's probe routines don't 1439 * get confused by errant DMAs when rebooting. 1440 */ 1441 static void 1442 vr_shutdown(void *arg) 1443 { 1444 struct vr_softc *sc = (struct vr_softc *)arg; 1445 1446 vr_stop(&sc->vr_ec.ec_if, 1); 1447 } 1448 1449 /* 1450 * Attach the interface. Allocate softc structures, do ifmedia 1451 * setup and ethernet/BPF attach. 1452 */ 1453 static void 1454 vr_attach(struct device *parent, struct device *self, void *aux) 1455 { 1456 struct vr_softc *sc = (struct vr_softc *) self; 1457 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 1458 bus_dma_segment_t seg; 1459 struct vr_type *vrt; 1460 uint32_t reg; 1461 struct ifnet *ifp; 1462 uint8_t eaddr[ETHER_ADDR_LEN], mac; 1463 int i, rseg, error; 1464 1465 #define PCI_CONF_WRITE(r, v) pci_conf_write(sc->vr_pc, sc->vr_tag, (r), (v)) 1466 #define PCI_CONF_READ(r) pci_conf_read(sc->vr_pc, sc->vr_tag, (r)) 1467 1468 sc->vr_pc = pa->pa_pc; 1469 sc->vr_tag = pa->pa_tag; 1470 callout_init(&sc->vr_tick_ch, 0); 1471 1472 vrt = vr_lookup(pa); 1473 if (vrt == NULL) { 1474 printf("\n"); 1475 panic("vr_attach: impossible"); 1476 } 1477 1478 printf(": %s Ethernet\n", vrt->vr_name); 1479 1480 /* 1481 * Handle power management nonsense. 1482 */ 1483 1484 sc->vr_save_iobase = PCI_CONF_READ(VR_PCI_LOIO); 1485 sc->vr_save_membase = PCI_CONF_READ(VR_PCI_LOMEM); 1486 sc->vr_save_irq = PCI_CONF_READ(PCI_INTERRUPT_REG); 1487 1488 /* power up chip */ 1489 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, sc, 1490 vr_restore_state)) && error != EOPNOTSUPP) { 1491 aprint_error("%s: cannot activate %d\n", sc->vr_dev.dv_xname, 1492 error); 1493 return; 1494 } 1495 1496 /* Make sure bus mastering is enabled. */ 1497 reg = PCI_CONF_READ(PCI_COMMAND_STATUS_REG); 1498 reg |= PCI_COMMAND_MASTER_ENABLE; 1499 PCI_CONF_WRITE(PCI_COMMAND_STATUS_REG, reg); 1500 1501 /* Get revision */ 1502 sc->vr_revid = PCI_REVISION(pa->pa_class); 1503 1504 /* 1505 * Map control/status registers. 1506 */ 1507 { 1508 bus_space_tag_t iot, memt; 1509 bus_space_handle_t ioh, memh; 1510 int ioh_valid, memh_valid; 1511 pci_intr_handle_t intrhandle; 1512 const char *intrstr; 1513 1514 ioh_valid = (pci_mapreg_map(pa, VR_PCI_LOIO, 1515 PCI_MAPREG_TYPE_IO, 0, 1516 &iot, &ioh, NULL, NULL) == 0); 1517 memh_valid = (pci_mapreg_map(pa, VR_PCI_LOMEM, 1518 PCI_MAPREG_TYPE_MEM | 1519 PCI_MAPREG_MEM_TYPE_32BIT, 1520 0, &memt, &memh, NULL, NULL) == 0); 1521 #if defined(VR_USEIOSPACE) 1522 if (ioh_valid) { 1523 sc->vr_bst = iot; 1524 sc->vr_bsh = ioh; 1525 } else if (memh_valid) { 1526 sc->vr_bst = memt; 1527 sc->vr_bsh = memh; 1528 } 1529 #else 1530 if (memh_valid) { 1531 sc->vr_bst = memt; 1532 sc->vr_bsh = memh; 1533 } else if (ioh_valid) { 1534 sc->vr_bst = iot; 1535 sc->vr_bsh = ioh; 1536 } 1537 #endif 1538 else { 1539 printf(": unable to map device registers\n"); 1540 return; 1541 } 1542 1543 /* Allocate interrupt */ 1544 if (pci_intr_map(pa, &intrhandle)) { 1545 printf("%s: couldn't map interrupt\n", 1546 sc->vr_dev.dv_xname); 1547 return; 1548 } 1549 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 1550 sc->vr_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 1551 vr_intr, sc); 1552 if (sc->vr_ih == NULL) { 1553 printf("%s: couldn't establish interrupt", 1554 sc->vr_dev.dv_xname); 1555 if (intrstr != NULL) 1556 printf(" at %s", intrstr); 1557 printf("\n"); 1558 } 1559 printf("%s: interrupting at %s\n", 1560 sc->vr_dev.dv_xname, intrstr); 1561 } 1562 1563 /* 1564 * Windows may put the chip in suspend mode when it 1565 * shuts down. Be sure to kick it in the head to wake it 1566 * up again. 1567 * 1568 * Don't touch this register on VT3043 since it causes 1569 * kernel MCHK trap on macppc. 1570 * (Note some VT86C100A chip returns a product ID of VT3043) 1571 */ 1572 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT3043) 1573 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 1574 1575 /* Reset the adapter. */ 1576 vr_reset(sc); 1577 1578 /* 1579 * Get station address. The way the Rhine chips work, 1580 * you're not allowed to directly access the EEPROM once 1581 * they've been programmed a special way. Consequently, 1582 * we need to read the node address from the PAR0 and PAR1 1583 * registers. 1584 * 1585 * XXXSCW: On the Rhine III, setting VR_EECSR_LOAD forces a reload 1586 * of the *whole* EEPROM, not just the MAC address. This is 1587 * pretty pointless since the chip does this automatically 1588 * at powerup/reset. 1589 * I suspect the same thing applies to the other Rhine 1590 * variants, but in the absence of a data sheet for those 1591 * (and the lack of anyone else noticing the problems this 1592 * causes) I'm going to retain the old behaviour for the 1593 * other parts. 1594 * In some cases, the chip really does startup without having 1595 * read the EEPROM (kern/34812). To handle this case, we force 1596 * a reload if we see an all-zeroes MAC address. 1597 */ 1598 for (mac = 0, i = 0; i < ETHER_ADDR_LEN; i++) 1599 mac |= (eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i)); 1600 1601 if (mac == 0 || (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT6105 && 1602 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT6102)) { 1603 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 1604 DELAY(200); 1605 for (i = 0; i < ETHER_ADDR_LEN; i++) 1606 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 1607 } 1608 1609 /* 1610 * A Rhine chip was detected. Inform the world. 1611 */ 1612 printf("%s: Ethernet address: %s\n", 1613 sc->vr_dev.dv_xname, ether_sprintf(eaddr)); 1614 1615 memcpy(sc->vr_enaddr, eaddr, ETHER_ADDR_LEN); 1616 1617 sc->vr_dmat = pa->pa_dmat; 1618 1619 /* 1620 * Allocate the control data structures, and create and load 1621 * the DMA map for it. 1622 */ 1623 if ((error = bus_dmamem_alloc(sc->vr_dmat, 1624 sizeof(struct vr_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 1625 0)) != 0) { 1626 printf("%s: unable to allocate control data, error = %d\n", 1627 sc->vr_dev.dv_xname, error); 1628 goto fail_0; 1629 } 1630 1631 if ((error = bus_dmamem_map(sc->vr_dmat, &seg, rseg, 1632 sizeof(struct vr_control_data), (void **)&sc->vr_control_data, 1633 BUS_DMA_COHERENT)) != 0) { 1634 printf("%s: unable to map control data, error = %d\n", 1635 sc->vr_dev.dv_xname, error); 1636 goto fail_1; 1637 } 1638 1639 if ((error = bus_dmamap_create(sc->vr_dmat, 1640 sizeof(struct vr_control_data), 1, 1641 sizeof(struct vr_control_data), 0, 0, 1642 &sc->vr_cddmamap)) != 0) { 1643 printf("%s: unable to create control data DMA map, " 1644 "error = %d\n", sc->vr_dev.dv_xname, error); 1645 goto fail_2; 1646 } 1647 1648 if ((error = bus_dmamap_load(sc->vr_dmat, sc->vr_cddmamap, 1649 sc->vr_control_data, sizeof(struct vr_control_data), NULL, 1650 0)) != 0) { 1651 printf("%s: unable to load control data DMA map, error = %d\n", 1652 sc->vr_dev.dv_xname, error); 1653 goto fail_3; 1654 } 1655 1656 /* 1657 * Create the transmit buffer DMA maps. 1658 */ 1659 for (i = 0; i < VR_NTXDESC; i++) { 1660 if ((error = bus_dmamap_create(sc->vr_dmat, MCLBYTES, 1661 1, MCLBYTES, 0, 0, 1662 &VR_DSTX(sc, i)->ds_dmamap)) != 0) { 1663 printf("%s: unable to create tx DMA map %d, " 1664 "error = %d\n", sc->vr_dev.dv_xname, i, error); 1665 goto fail_4; 1666 } 1667 } 1668 1669 /* 1670 * Create the receive buffer DMA maps. 1671 */ 1672 for (i = 0; i < VR_NRXDESC; i++) { 1673 if ((error = bus_dmamap_create(sc->vr_dmat, MCLBYTES, 1, 1674 MCLBYTES, 0, 0, 1675 &VR_DSRX(sc, i)->ds_dmamap)) != 0) { 1676 printf("%s: unable to create rx DMA map %d, " 1677 "error = %d\n", sc->vr_dev.dv_xname, i, error); 1678 goto fail_5; 1679 } 1680 VR_DSRX(sc, i)->ds_mbuf = NULL; 1681 } 1682 1683 ifp = &sc->vr_ec.ec_if; 1684 ifp->if_softc = sc; 1685 ifp->if_mtu = ETHERMTU; 1686 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1687 ifp->if_ioctl = vr_ioctl; 1688 ifp->if_start = vr_start; 1689 ifp->if_watchdog = vr_watchdog; 1690 ifp->if_init = vr_init; 1691 ifp->if_stop = vr_stop; 1692 IFQ_SET_READY(&ifp->if_snd); 1693 1694 strcpy(ifp->if_xname, sc->vr_dev.dv_xname); 1695 1696 /* 1697 * Initialize MII/media info. 1698 */ 1699 sc->vr_mii.mii_ifp = ifp; 1700 sc->vr_mii.mii_readreg = vr_mii_readreg; 1701 sc->vr_mii.mii_writereg = vr_mii_writereg; 1702 sc->vr_mii.mii_statchg = vr_mii_statchg; 1703 1704 sc->vr_ec.ec_mii = &sc->vr_mii; 1705 ifmedia_init(&sc->vr_mii.mii_media, IFM_IMASK, ether_mediachange, 1706 ether_mediastatus); 1707 mii_attach(&sc->vr_dev, &sc->vr_mii, 0xffffffff, MII_PHY_ANY, 1708 MII_OFFSET_ANY, MIIF_FORCEANEG); 1709 if (LIST_FIRST(&sc->vr_mii.mii_phys) == NULL) { 1710 ifmedia_add(&sc->vr_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1711 ifmedia_set(&sc->vr_mii.mii_media, IFM_ETHER|IFM_NONE); 1712 } else 1713 ifmedia_set(&sc->vr_mii.mii_media, IFM_ETHER|IFM_AUTO); 1714 1715 /* 1716 * Call MI attach routines. 1717 */ 1718 if_attach(ifp); 1719 ether_ifattach(ifp, sc->vr_enaddr); 1720 #if NRND > 0 1721 rnd_attach_source(&sc->rnd_source, sc->vr_dev.dv_xname, 1722 RND_TYPE_NET, 0); 1723 #endif 1724 1725 sc->vr_ats = shutdownhook_establish(vr_shutdown, sc); 1726 if (sc->vr_ats == NULL) 1727 printf("%s: warning: couldn't establish shutdown hook\n", 1728 sc->vr_dev.dv_xname); 1729 return; 1730 1731 fail_5: 1732 for (i = 0; i < VR_NRXDESC; i++) { 1733 if (sc->vr_rxsoft[i].ds_dmamap != NULL) 1734 bus_dmamap_destroy(sc->vr_dmat, 1735 sc->vr_rxsoft[i].ds_dmamap); 1736 } 1737 fail_4: 1738 for (i = 0; i < VR_NTXDESC; i++) { 1739 if (sc->vr_txsoft[i].ds_dmamap != NULL) 1740 bus_dmamap_destroy(sc->vr_dmat, 1741 sc->vr_txsoft[i].ds_dmamap); 1742 } 1743 bus_dmamap_unload(sc->vr_dmat, sc->vr_cddmamap); 1744 fail_3: 1745 bus_dmamap_destroy(sc->vr_dmat, sc->vr_cddmamap); 1746 fail_2: 1747 bus_dmamem_unmap(sc->vr_dmat, (void *)sc->vr_control_data, 1748 sizeof(struct vr_control_data)); 1749 fail_1: 1750 bus_dmamem_free(sc->vr_dmat, &seg, rseg); 1751 fail_0: 1752 return; 1753 } 1754 1755 static int 1756 vr_restore_state(pci_chipset_tag_t pc, pcitag_t tag, void *ssc, pcireg_t state) 1757 { 1758 struct vr_softc *sc = ssc; 1759 int error; 1760 1761 if (state == PCI_PMCSR_STATE_D0) 1762 return 0; 1763 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 1764 return error; 1765 1766 /* Restore PCI config data. */ 1767 PCI_CONF_WRITE(VR_PCI_LOIO, sc->vr_save_iobase); 1768 PCI_CONF_WRITE(VR_PCI_LOMEM, sc->vr_save_membase); 1769 PCI_CONF_WRITE(PCI_INTERRUPT_REG, sc->vr_save_irq); 1770 return 0; 1771 } 1772