1 /* $NetBSD: if_vr.c,v 1.70 2004/10/30 18:09:22 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1997, 1998 42 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Bill Paul. 55 * 4. Neither the name of the author nor the names of any co-contributors 56 * may be used to endorse or promote products derived from this software 57 * without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 63 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 64 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 65 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 66 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 67 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 68 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 69 * THE POSSIBILITY OF SUCH DAMAGE. 70 * 71 * $FreeBSD: if_vr.c,v 1.7 1999/01/10 18:51:49 wpaul Exp $ 72 */ 73 74 /* 75 * VIA Rhine fast ethernet PCI NIC driver 76 * 77 * Supports various network adapters based on the VIA Rhine 78 * and Rhine II PCI controllers, including the D-Link DFE530TX. 79 * Datasheets are available at http://www.via.com.tw. 80 * 81 * Written by Bill Paul <wpaul@ctr.columbia.edu> 82 * Electrical Engineering Department 83 * Columbia University, New York City 84 */ 85 86 /* 87 * The VIA Rhine controllers are similar in some respects to the 88 * the DEC tulip chips, except less complicated. The controller 89 * uses an MII bus and an external physical layer interface. The 90 * receiver has a one entry perfect filter and a 64-bit hash table 91 * multicast filter. Transmit and receive descriptors are similar 92 * to the tulip. 93 * 94 * The Rhine has a serious flaw in its transmit DMA mechanism: 95 * transmit buffers must be longword aligned. Unfortunately, 96 * the kernel doesn't guarantee that mbufs will be filled in starting 97 * at longword boundaries, so we have to do a buffer copy before 98 * transmission. 99 * 100 * Apparently, the receive DMA mechanism also has the same flaw. This 101 * means that on systems with struct alignment requirements, incoming 102 * frames must be copied to a new buffer which shifts the data forward 103 * 2 bytes so that the payload is aligned on a 4-byte boundary. 104 */ 105 106 #include <sys/cdefs.h> 107 __KERNEL_RCSID(0, "$NetBSD: if_vr.c,v 1.70 2004/10/30 18:09:22 thorpej Exp $"); 108 109 #include "rnd.h" 110 111 #include <sys/param.h> 112 #include <sys/systm.h> 113 #include <sys/callout.h> 114 #include <sys/sockio.h> 115 #include <sys/mbuf.h> 116 #include <sys/malloc.h> 117 #include <sys/kernel.h> 118 #include <sys/socket.h> 119 #include <sys/device.h> 120 121 #if NRND > 0 122 #include <sys/rnd.h> 123 #endif 124 125 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 126 127 #include <net/if.h> 128 #include <net/if_arp.h> 129 #include <net/if_dl.h> 130 #include <net/if_media.h> 131 #include <net/if_ether.h> 132 133 #include "bpfilter.h" 134 #if NBPFILTER > 0 135 #include <net/bpf.h> 136 #endif 137 138 #include <machine/bus.h> 139 #include <machine/intr.h> 140 #include <machine/endian.h> 141 142 #include <dev/mii/mii.h> 143 #include <dev/mii/miivar.h> 144 #include <dev/mii/mii_bitbang.h> 145 146 #include <dev/pci/pcireg.h> 147 #include <dev/pci/pcivar.h> 148 #include <dev/pci/pcidevs.h> 149 150 #include <dev/pci/if_vrreg.h> 151 152 #define VR_USEIOSPACE 153 154 /* 155 * Various supported device vendors/types and their names. 156 */ 157 static struct vr_type { 158 pci_vendor_id_t vr_vid; 159 pci_product_id_t vr_did; 160 const char *vr_name; 161 } vr_devs[] = { 162 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT3043, 163 "VIA VT3043 (Rhine) 10/100" }, 164 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6102, 165 "VIA VT6102 (Rhine II) 10/100" }, 166 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6105, 167 "VIA VT6105 (Rhine III) 10/100" }, 168 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT86C100A, 169 "VIA VT86C100A (Rhine-II) 10/100" }, 170 { 0, 0, NULL } 171 }; 172 173 /* 174 * Transmit descriptor list size. 175 */ 176 #define VR_NTXDESC 64 177 #define VR_NTXDESC_MASK (VR_NTXDESC - 1) 178 #define VR_NEXTTX(x) (((x) + 1) & VR_NTXDESC_MASK) 179 180 /* 181 * Receive descriptor list size. 182 */ 183 #define VR_NRXDESC 64 184 #define VR_NRXDESC_MASK (VR_NRXDESC - 1) 185 #define VR_NEXTRX(x) (((x) + 1) & VR_NRXDESC_MASK) 186 187 /* 188 * Control data structres that are DMA'd to the Rhine chip. We allocate 189 * them in a single clump that maps to a single DMA segment to make several 190 * things easier. 191 * 192 * Note that since we always copy outgoing packets to aligned transmit 193 * buffers, we can reduce the transmit descriptors to one per packet. 194 */ 195 struct vr_control_data { 196 struct vr_desc vr_txdescs[VR_NTXDESC]; 197 struct vr_desc vr_rxdescs[VR_NRXDESC]; 198 }; 199 200 #define VR_CDOFF(x) offsetof(struct vr_control_data, x) 201 #define VR_CDTXOFF(x) VR_CDOFF(vr_txdescs[(x)]) 202 #define VR_CDRXOFF(x) VR_CDOFF(vr_rxdescs[(x)]) 203 204 /* 205 * Software state of transmit and receive descriptors. 206 */ 207 struct vr_descsoft { 208 struct mbuf *ds_mbuf; /* head of mbuf chain */ 209 bus_dmamap_t ds_dmamap; /* our DMA map */ 210 }; 211 212 struct vr_softc { 213 struct device vr_dev; /* generic device glue */ 214 void *vr_ih; /* interrupt cookie */ 215 void *vr_ats; /* shutdown hook */ 216 bus_space_tag_t vr_bst; /* bus space tag */ 217 bus_space_handle_t vr_bsh; /* bus space handle */ 218 bus_dma_tag_t vr_dmat; /* bus DMA tag */ 219 pci_chipset_tag_t vr_pc; /* PCI chipset info */ 220 struct ethercom vr_ec; /* Ethernet common info */ 221 u_int8_t vr_enaddr[ETHER_ADDR_LEN]; 222 struct mii_data vr_mii; /* MII/media info */ 223 224 u_int8_t vr_revid; /* Rhine chip revision */ 225 226 struct callout vr_tick_ch; /* tick callout */ 227 228 bus_dmamap_t vr_cddmamap; /* control data DMA map */ 229 #define vr_cddma vr_cddmamap->dm_segs[0].ds_addr 230 231 /* 232 * Software state for transmit and receive descriptors. 233 */ 234 struct vr_descsoft vr_txsoft[VR_NTXDESC]; 235 struct vr_descsoft vr_rxsoft[VR_NRXDESC]; 236 237 /* 238 * Control data structures. 239 */ 240 struct vr_control_data *vr_control_data; 241 242 int vr_txpending; /* number of TX requests pending */ 243 int vr_txdirty; /* first dirty TX descriptor */ 244 int vr_txlast; /* last used TX descriptor */ 245 246 int vr_rxptr; /* next ready RX descriptor */ 247 248 #if NRND > 0 249 rndsource_element_t rnd_source; /* random source */ 250 #endif 251 }; 252 253 #define VR_CDTXADDR(sc, x) ((sc)->vr_cddma + VR_CDTXOFF((x))) 254 #define VR_CDRXADDR(sc, x) ((sc)->vr_cddma + VR_CDRXOFF((x))) 255 256 #define VR_CDTX(sc, x) (&(sc)->vr_control_data->vr_txdescs[(x)]) 257 #define VR_CDRX(sc, x) (&(sc)->vr_control_data->vr_rxdescs[(x)]) 258 259 #define VR_DSTX(sc, x) (&(sc)->vr_txsoft[(x)]) 260 #define VR_DSRX(sc, x) (&(sc)->vr_rxsoft[(x)]) 261 262 #define VR_CDTXSYNC(sc, x, ops) \ 263 bus_dmamap_sync((sc)->vr_dmat, (sc)->vr_cddmamap, \ 264 VR_CDTXOFF((x)), sizeof(struct vr_desc), (ops)) 265 266 #define VR_CDRXSYNC(sc, x, ops) \ 267 bus_dmamap_sync((sc)->vr_dmat, (sc)->vr_cddmamap, \ 268 VR_CDRXOFF((x)), sizeof(struct vr_desc), (ops)) 269 270 /* 271 * Note we rely on MCLBYTES being a power of two below. 272 */ 273 #define VR_INIT_RXDESC(sc, i) \ 274 do { \ 275 struct vr_desc *__d = VR_CDRX((sc), (i)); \ 276 struct vr_descsoft *__ds = VR_DSRX((sc), (i)); \ 277 \ 278 __d->vr_next = htole32(VR_CDRXADDR((sc), VR_NEXTRX((i)))); \ 279 __d->vr_status = htole32(VR_RXSTAT_FIRSTFRAG | \ 280 VR_RXSTAT_LASTFRAG | VR_RXSTAT_OWN); \ 281 __d->vr_data = htole32(__ds->ds_dmamap->dm_segs[0].ds_addr); \ 282 __d->vr_ctl = htole32(VR_RXCTL_CHAIN | VR_RXCTL_RX_INTR | \ 283 ((MCLBYTES - 1) & VR_RXCTL_BUFLEN)); \ 284 VR_CDRXSYNC((sc), (i), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 285 } while (/* CONSTCOND */ 0) 286 287 /* 288 * register space access macros 289 */ 290 #define CSR_WRITE_4(sc, reg, val) \ 291 bus_space_write_4(sc->vr_bst, sc->vr_bsh, reg, val) 292 #define CSR_WRITE_2(sc, reg, val) \ 293 bus_space_write_2(sc->vr_bst, sc->vr_bsh, reg, val) 294 #define CSR_WRITE_1(sc, reg, val) \ 295 bus_space_write_1(sc->vr_bst, sc->vr_bsh, reg, val) 296 297 #define CSR_READ_4(sc, reg) \ 298 bus_space_read_4(sc->vr_bst, sc->vr_bsh, reg) 299 #define CSR_READ_2(sc, reg) \ 300 bus_space_read_2(sc->vr_bst, sc->vr_bsh, reg) 301 #define CSR_READ_1(sc, reg) \ 302 bus_space_read_1(sc->vr_bst, sc->vr_bsh, reg) 303 304 #define VR_TIMEOUT 1000 305 306 static int vr_add_rxbuf(struct vr_softc *, int); 307 308 static void vr_rxeof(struct vr_softc *); 309 static void vr_rxeoc(struct vr_softc *); 310 static void vr_txeof(struct vr_softc *); 311 static int vr_intr(void *); 312 static void vr_start(struct ifnet *); 313 static int vr_ioctl(struct ifnet *, u_long, caddr_t); 314 static int vr_init(struct ifnet *); 315 static void vr_stop(struct ifnet *, int); 316 static void vr_rxdrain(struct vr_softc *); 317 static void vr_watchdog(struct ifnet *); 318 static void vr_tick(void *); 319 320 static int vr_ifmedia_upd(struct ifnet *); 321 static void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *); 322 323 static int vr_mii_readreg(struct device *, int, int); 324 static void vr_mii_writereg(struct device *, int, int, int); 325 static void vr_mii_statchg(struct device *); 326 327 static void vr_setmulti(struct vr_softc *); 328 static void vr_reset(struct vr_softc *); 329 330 int vr_copy_small = 0; 331 332 #define VR_SETBIT(sc, reg, x) \ 333 CSR_WRITE_1(sc, reg, \ 334 CSR_READ_1(sc, reg) | (x)) 335 336 #define VR_CLRBIT(sc, reg, x) \ 337 CSR_WRITE_1(sc, reg, \ 338 CSR_READ_1(sc, reg) & ~(x)) 339 340 #define VR_SETBIT16(sc, reg, x) \ 341 CSR_WRITE_2(sc, reg, \ 342 CSR_READ_2(sc, reg) | (x)) 343 344 #define VR_CLRBIT16(sc, reg, x) \ 345 CSR_WRITE_2(sc, reg, \ 346 CSR_READ_2(sc, reg) & ~(x)) 347 348 #define VR_SETBIT32(sc, reg, x) \ 349 CSR_WRITE_4(sc, reg, \ 350 CSR_READ_4(sc, reg) | (x)) 351 352 #define VR_CLRBIT32(sc, reg, x) \ 353 CSR_WRITE_4(sc, reg, \ 354 CSR_READ_4(sc, reg) & ~(x)) 355 356 /* 357 * MII bit-bang glue. 358 */ 359 static u_int32_t vr_mii_bitbang_read(struct device *); 360 static void vr_mii_bitbang_write(struct device *, u_int32_t); 361 362 static const struct mii_bitbang_ops vr_mii_bitbang_ops = { 363 vr_mii_bitbang_read, 364 vr_mii_bitbang_write, 365 { 366 VR_MIICMD_DATAOUT, /* MII_BIT_MDO */ 367 VR_MIICMD_DATAIN, /* MII_BIT_MDI */ 368 VR_MIICMD_CLK, /* MII_BIT_MDC */ 369 VR_MIICMD_DIR, /* MII_BIT_DIR_HOST_PHY */ 370 0, /* MII_BIT_DIR_PHY_HOST */ 371 } 372 }; 373 374 static u_int32_t 375 vr_mii_bitbang_read(struct device *self) 376 { 377 struct vr_softc *sc = (void *) self; 378 379 return (CSR_READ_1(sc, VR_MIICMD)); 380 } 381 382 static void 383 vr_mii_bitbang_write(struct device *self, u_int32_t val) 384 { 385 struct vr_softc *sc = (void *) self; 386 387 CSR_WRITE_1(sc, VR_MIICMD, (val & 0xff) | VR_MIICMD_DIRECTPGM); 388 } 389 390 /* 391 * Read an PHY register through the MII. 392 */ 393 static int 394 vr_mii_readreg(struct device *self, int phy, int reg) 395 { 396 struct vr_softc *sc = (void *) self; 397 398 CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 399 return (mii_bitbang_readreg(self, &vr_mii_bitbang_ops, phy, reg)); 400 } 401 402 /* 403 * Write to a PHY register through the MII. 404 */ 405 static void 406 vr_mii_writereg(struct device *self, int phy, int reg, int val) 407 { 408 struct vr_softc *sc = (void *) self; 409 410 CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 411 mii_bitbang_writereg(self, &vr_mii_bitbang_ops, phy, reg, val); 412 } 413 414 static void 415 vr_mii_statchg(struct device *self) 416 { 417 struct vr_softc *sc = (struct vr_softc *)self; 418 419 /* 420 * In order to fiddle with the 'full-duplex' bit in the netconfig 421 * register, we first have to put the transmit and/or receive logic 422 * in the idle state. 423 */ 424 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 425 426 if (sc->vr_mii.mii_media_active & IFM_FDX) 427 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 428 else 429 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 430 431 if (sc->vr_ec.ec_if.if_flags & IFF_RUNNING) 432 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 433 } 434 435 #define vr_calchash(addr) \ 436 (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26) 437 438 /* 439 * Program the 64-bit multicast hash filter. 440 */ 441 static void 442 vr_setmulti(struct vr_softc *sc) 443 { 444 struct ifnet *ifp; 445 int h = 0; 446 u_int32_t hashes[2] = { 0, 0 }; 447 struct ether_multistep step; 448 struct ether_multi *enm; 449 int mcnt = 0; 450 u_int8_t rxfilt; 451 452 ifp = &sc->vr_ec.ec_if; 453 454 rxfilt = CSR_READ_1(sc, VR_RXCFG); 455 456 if (ifp->if_flags & IFF_PROMISC) { 457 allmulti: 458 ifp->if_flags |= IFF_ALLMULTI; 459 rxfilt |= VR_RXCFG_RX_MULTI; 460 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 461 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 462 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 463 return; 464 } 465 466 /* first, zot all the existing hash bits */ 467 CSR_WRITE_4(sc, VR_MAR0, 0); 468 CSR_WRITE_4(sc, VR_MAR1, 0); 469 470 /* now program new ones */ 471 ETHER_FIRST_MULTI(step, &sc->vr_ec, enm); 472 while (enm != NULL) { 473 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 474 ETHER_ADDR_LEN) != 0) 475 goto allmulti; 476 477 h = vr_calchash(enm->enm_addrlo); 478 479 if (h < 32) 480 hashes[0] |= (1 << h); 481 else 482 hashes[1] |= (1 << (h - 32)); 483 ETHER_NEXT_MULTI(step, enm); 484 mcnt++; 485 } 486 487 ifp->if_flags &= ~IFF_ALLMULTI; 488 489 if (mcnt) 490 rxfilt |= VR_RXCFG_RX_MULTI; 491 else 492 rxfilt &= ~VR_RXCFG_RX_MULTI; 493 494 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 495 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 496 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 497 } 498 499 static void 500 vr_reset(struct vr_softc *sc) 501 { 502 int i; 503 504 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 505 506 for (i = 0; i < VR_TIMEOUT; i++) { 507 DELAY(10); 508 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 509 break; 510 } 511 if (i == VR_TIMEOUT) { 512 if (sc->vr_revid < REV_ID_VT3065_A) { 513 printf("%s: reset never completed!\n", 514 sc->vr_dev.dv_xname); 515 } else { 516 /* Use newer force reset command */ 517 printf("%s: using force reset command.\n", 518 sc->vr_dev.dv_xname); 519 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 520 } 521 } 522 523 /* Wait a little while for the chip to get its brains in order. */ 524 DELAY(1000); 525 } 526 527 /* 528 * Initialize an RX descriptor and attach an MBUF cluster. 529 * Note: the length fields are only 11 bits wide, which means the 530 * largest size we can specify is 2047. This is important because 531 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 532 * overflow the field and make a mess. 533 */ 534 static int 535 vr_add_rxbuf(struct vr_softc *sc, int i) 536 { 537 struct vr_descsoft *ds = VR_DSRX(sc, i); 538 struct mbuf *m_new; 539 int error; 540 541 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 542 if (m_new == NULL) 543 return (ENOBUFS); 544 545 MCLGET(m_new, M_DONTWAIT); 546 if ((m_new->m_flags & M_EXT) == 0) { 547 m_freem(m_new); 548 return (ENOBUFS); 549 } 550 551 if (ds->ds_mbuf != NULL) 552 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 553 554 ds->ds_mbuf = m_new; 555 556 error = bus_dmamap_load(sc->vr_dmat, ds->ds_dmamap, 557 m_new->m_ext.ext_buf, m_new->m_ext.ext_size, NULL, 558 BUS_DMA_READ|BUS_DMA_NOWAIT); 559 if (error) { 560 printf("%s: unable to load rx DMA map %d, error = %d\n", 561 sc->vr_dev.dv_xname, i, error); 562 panic("vr_add_rxbuf"); /* XXX */ 563 } 564 565 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 566 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 567 568 VR_INIT_RXDESC(sc, i); 569 570 return (0); 571 } 572 573 /* 574 * A frame has been uploaded: pass the resulting mbuf chain up to 575 * the higher level protocols. 576 */ 577 static void 578 vr_rxeof(struct vr_softc *sc) 579 { 580 struct mbuf *m; 581 struct ifnet *ifp; 582 struct vr_desc *d; 583 struct vr_descsoft *ds; 584 int i, total_len; 585 u_int32_t rxstat; 586 587 ifp = &sc->vr_ec.ec_if; 588 589 for (i = sc->vr_rxptr;; i = VR_NEXTRX(i)) { 590 d = VR_CDRX(sc, i); 591 ds = VR_DSRX(sc, i); 592 593 VR_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 594 595 rxstat = le32toh(d->vr_status); 596 597 if (rxstat & VR_RXSTAT_OWN) { 598 /* 599 * We have processed all of the receive buffers. 600 */ 601 break; 602 } 603 604 /* 605 * If an error occurs, update stats, clear the 606 * status word and leave the mbuf cluster in place: 607 * it should simply get re-used next time this descriptor 608 * comes up in the ring. 609 */ 610 if (rxstat & VR_RXSTAT_RXERR) { 611 const char *errstr; 612 613 ifp->if_ierrors++; 614 switch (rxstat & 0x000000FF) { 615 case VR_RXSTAT_CRCERR: 616 errstr = "crc error"; 617 break; 618 case VR_RXSTAT_FRAMEALIGNERR: 619 errstr = "frame alignment error"; 620 break; 621 case VR_RXSTAT_FIFOOFLOW: 622 errstr = "FIFO overflow"; 623 break; 624 case VR_RXSTAT_GIANT: 625 errstr = "received giant packet"; 626 break; 627 case VR_RXSTAT_RUNT: 628 errstr = "received runt packet"; 629 break; 630 case VR_RXSTAT_BUSERR: 631 errstr = "system bus error"; 632 break; 633 case VR_RXSTAT_BUFFERR: 634 errstr = "rx buffer error"; 635 break; 636 default: 637 errstr = "unknown rx error"; 638 break; 639 } 640 printf("%s: receive error: %s\n", sc->vr_dev.dv_xname, 641 errstr); 642 643 VR_INIT_RXDESC(sc, i); 644 645 continue; 646 } 647 648 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 649 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 650 651 /* No errors; receive the packet. */ 652 total_len = VR_RXBYTES(le32toh(d->vr_status)); 653 654 #ifdef __NO_STRICT_ALIGNMENT 655 /* 656 * If the packet is small enough to fit in a 657 * single header mbuf, allocate one and copy 658 * the data into it. This greatly reduces 659 * memory consumption when we receive lots 660 * of small packets. 661 * 662 * Otherwise, we add a new buffer to the receive 663 * chain. If this fails, we drop the packet and 664 * recycle the old buffer. 665 */ 666 if (vr_copy_small != 0 && total_len <= MHLEN) { 667 MGETHDR(m, M_DONTWAIT, MT_DATA); 668 if (m == NULL) 669 goto dropit; 670 memcpy(mtod(m, caddr_t), 671 mtod(ds->ds_mbuf, caddr_t), total_len); 672 VR_INIT_RXDESC(sc, i); 673 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 674 ds->ds_dmamap->dm_mapsize, 675 BUS_DMASYNC_PREREAD); 676 } else { 677 m = ds->ds_mbuf; 678 if (vr_add_rxbuf(sc, i) == ENOBUFS) { 679 dropit: 680 ifp->if_ierrors++; 681 VR_INIT_RXDESC(sc, i); 682 bus_dmamap_sync(sc->vr_dmat, 683 ds->ds_dmamap, 0, 684 ds->ds_dmamap->dm_mapsize, 685 BUS_DMASYNC_PREREAD); 686 continue; 687 } 688 } 689 #else 690 /* 691 * The Rhine's packet buffers must be 4-byte aligned. 692 * But this means that the data after the Ethernet header 693 * is misaligned. We must allocate a new buffer and 694 * copy the data, shifted forward 2 bytes. 695 */ 696 MGETHDR(m, M_DONTWAIT, MT_DATA); 697 if (m == NULL) { 698 dropit: 699 ifp->if_ierrors++; 700 VR_INIT_RXDESC(sc, i); 701 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 702 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 703 continue; 704 } 705 if (total_len > (MHLEN - 2)) { 706 MCLGET(m, M_DONTWAIT); 707 if ((m->m_flags & M_EXT) == 0) { 708 m_freem(m); 709 goto dropit; 710 } 711 } 712 m->m_data += 2; 713 714 /* 715 * Note that we use clusters for incoming frames, so the 716 * buffer is virtually contiguous. 717 */ 718 memcpy(mtod(m, caddr_t), mtod(ds->ds_mbuf, caddr_t), 719 total_len); 720 721 /* Allow the receive descriptor to continue using its mbuf. */ 722 VR_INIT_RXDESC(sc, i); 723 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 724 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 725 #endif /* __NO_STRICT_ALIGNMENT */ 726 727 /* 728 * The Rhine chip includes the FCS with every 729 * received packet. 730 */ 731 m->m_flags |= M_HASFCS; 732 733 ifp->if_ipackets++; 734 m->m_pkthdr.rcvif = ifp; 735 m->m_pkthdr.len = m->m_len = total_len; 736 #if NBPFILTER > 0 737 /* 738 * Handle BPF listeners. Let the BPF user see the packet, but 739 * don't pass it up to the ether_input() layer unless it's 740 * a broadcast packet, multicast packet, matches our ethernet 741 * address or the interface is in promiscuous mode. 742 */ 743 if (ifp->if_bpf) 744 bpf_mtap(ifp->if_bpf, m); 745 #endif 746 /* Pass it on. */ 747 (*ifp->if_input)(ifp, m); 748 } 749 750 /* Update the receive pointer. */ 751 sc->vr_rxptr = i; 752 } 753 754 void 755 vr_rxeoc(struct vr_softc *sc) 756 { 757 758 vr_rxeof(sc); 759 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 760 CSR_WRITE_4(sc, VR_RXADDR, VR_CDRXADDR(sc, sc->vr_rxptr)); 761 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 762 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 763 } 764 765 /* 766 * A frame was downloaded to the chip. It's safe for us to clean up 767 * the list buffers. 768 */ 769 static void 770 vr_txeof(struct vr_softc *sc) 771 { 772 struct ifnet *ifp = &sc->vr_ec.ec_if; 773 struct vr_desc *d; 774 struct vr_descsoft *ds; 775 u_int32_t txstat; 776 int i; 777 778 ifp->if_flags &= ~IFF_OACTIVE; 779 780 /* 781 * Go through our tx list and free mbufs for those 782 * frames that have been transmitted. 783 */ 784 for (i = sc->vr_txdirty; sc->vr_txpending != 0; 785 i = VR_NEXTTX(i), sc->vr_txpending--) { 786 d = VR_CDTX(sc, i); 787 ds = VR_DSTX(sc, i); 788 789 VR_CDTXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 790 791 txstat = le32toh(d->vr_status); 792 if (txstat & VR_TXSTAT_OWN) 793 break; 794 795 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 796 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 797 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 798 m_freem(ds->ds_mbuf); 799 ds->ds_mbuf = NULL; 800 801 if (txstat & VR_TXSTAT_ERRSUM) { 802 ifp->if_oerrors++; 803 if (txstat & VR_TXSTAT_DEFER) 804 ifp->if_collisions++; 805 if (txstat & VR_TXSTAT_LATECOLL) 806 ifp->if_collisions++; 807 } 808 809 ifp->if_collisions += (txstat & VR_TXSTAT_COLLCNT) >> 3; 810 ifp->if_opackets++; 811 } 812 813 /* Update the dirty transmit buffer pointer. */ 814 sc->vr_txdirty = i; 815 816 /* 817 * Cancel the watchdog timer if there are no pending 818 * transmissions. 819 */ 820 if (sc->vr_txpending == 0) 821 ifp->if_timer = 0; 822 } 823 824 static int 825 vr_intr(void *arg) 826 { 827 struct vr_softc *sc; 828 struct ifnet *ifp; 829 u_int16_t status; 830 int handled = 0, dotx = 0; 831 832 sc = arg; 833 ifp = &sc->vr_ec.ec_if; 834 835 /* Suppress unwanted interrupts. */ 836 if ((ifp->if_flags & IFF_UP) == 0) { 837 vr_stop(ifp, 1); 838 return (0); 839 } 840 841 /* Disable interrupts. */ 842 CSR_WRITE_2(sc, VR_IMR, 0x0000); 843 844 for (;;) { 845 status = CSR_READ_2(sc, VR_ISR); 846 if (status) 847 CSR_WRITE_2(sc, VR_ISR, status); 848 849 if ((status & VR_INTRS) == 0) 850 break; 851 852 handled = 1; 853 854 #if NRND > 0 855 if (RND_ENABLED(&sc->rnd_source)) 856 rnd_add_uint32(&sc->rnd_source, status); 857 #endif 858 859 if (status & VR_ISR_RX_OK) 860 vr_rxeof(sc); 861 862 if (status & 863 (VR_ISR_RX_ERR | VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW | 864 VR_ISR_RX_DROPPED)) 865 vr_rxeoc(sc); 866 867 if (status & VR_ISR_TX_OK) { 868 dotx = 1; 869 vr_txeof(sc); 870 } 871 872 if (status & (VR_ISR_TX_UNDERRUN | VR_ISR_TX_ABRT)) { 873 if (status & VR_ISR_TX_UNDERRUN) 874 printf("%s: transmit underrun\n", 875 sc->vr_dev.dv_xname); 876 if (status & VR_ISR_TX_ABRT) 877 printf("%s: transmit aborted\n", 878 sc->vr_dev.dv_xname); 879 ifp->if_oerrors++; 880 dotx = 1; 881 vr_txeof(sc); 882 if (sc->vr_txpending) { 883 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 884 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 885 } 886 /* 887 * Unfortunately many cards get stuck after 888 * aborted transmits, so we reset them. 889 */ 890 if (status & VR_ISR_TX_ABRT) { 891 printf("%s: restarting\n", sc->vr_dev.dv_xname); 892 dotx = 0; 893 (void) vr_init(ifp); 894 } 895 } 896 897 if (status & VR_ISR_BUSERR) { 898 printf("%s: PCI bus error\n", sc->vr_dev.dv_xname); 899 /* vr_init() calls vr_start() */ 900 dotx = 0; 901 (void) vr_init(ifp); 902 } 903 } 904 905 /* Re-enable interrupts. */ 906 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 907 908 if (dotx) 909 vr_start(ifp); 910 911 return (handled); 912 } 913 914 /* 915 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 916 * to the mbuf data regions directly in the transmit lists. We also save a 917 * copy of the pointers since the transmit list fragment pointers are 918 * physical addresses. 919 */ 920 static void 921 vr_start(struct ifnet *ifp) 922 { 923 struct vr_softc *sc = ifp->if_softc; 924 struct mbuf *m0, *m; 925 struct vr_desc *d; 926 struct vr_descsoft *ds; 927 int error, firsttx, nexttx, opending; 928 929 /* 930 * Remember the previous txpending and the first transmit 931 * descriptor we use. 932 */ 933 opending = sc->vr_txpending; 934 firsttx = VR_NEXTTX(sc->vr_txlast); 935 936 /* 937 * Loop through the send queue, setting up transmit descriptors 938 * until we drain the queue, or use up all available transmit 939 * descriptors. 940 */ 941 while (sc->vr_txpending < VR_NTXDESC) { 942 /* 943 * Grab a packet off the queue. 944 */ 945 IFQ_POLL(&ifp->if_snd, m0); 946 if (m0 == NULL) 947 break; 948 m = NULL; 949 950 /* 951 * Get the next available transmit descriptor. 952 */ 953 nexttx = VR_NEXTTX(sc->vr_txlast); 954 d = VR_CDTX(sc, nexttx); 955 ds = VR_DSTX(sc, nexttx); 956 957 /* 958 * Load the DMA map. If this fails, the packet didn't 959 * fit in one DMA segment, and we need to copy. Note, 960 * the packet must also be aligned. 961 * if the packet is too small, copy it too, so we're sure 962 * so have enouth room for the pad buffer. 963 */ 964 if ((mtod(m0, uintptr_t) & 3) != 0 || 965 m0->m_pkthdr.len < VR_MIN_FRAMELEN || 966 bus_dmamap_load_mbuf(sc->vr_dmat, ds->ds_dmamap, m0, 967 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 968 MGETHDR(m, M_DONTWAIT, MT_DATA); 969 if (m == NULL) { 970 printf("%s: unable to allocate Tx mbuf\n", 971 sc->vr_dev.dv_xname); 972 break; 973 } 974 if (m0->m_pkthdr.len > MHLEN) { 975 MCLGET(m, M_DONTWAIT); 976 if ((m->m_flags & M_EXT) == 0) { 977 printf("%s: unable to allocate Tx " 978 "cluster\n", sc->vr_dev.dv_xname); 979 m_freem(m); 980 break; 981 } 982 } 983 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 984 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 985 /* 986 * The Rhine doesn't auto-pad, so we have to do this 987 * ourselves. 988 */ 989 if (m0->m_pkthdr.len < VR_MIN_FRAMELEN) { 990 memset(mtod(m, caddr_t) + m0->m_pkthdr.len, 991 0, VR_MIN_FRAMELEN - m0->m_pkthdr.len); 992 m->m_pkthdr.len = m->m_len = VR_MIN_FRAMELEN; 993 } 994 error = bus_dmamap_load_mbuf(sc->vr_dmat, 995 ds->ds_dmamap, m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 996 if (error) { 997 printf("%s: unable to load Tx buffer, " 998 "error = %d\n", sc->vr_dev.dv_xname, error); 999 break; 1000 } 1001 } 1002 1003 IFQ_DEQUEUE(&ifp->if_snd, m0); 1004 if (m != NULL) { 1005 m_freem(m0); 1006 m0 = m; 1007 } 1008 1009 /* Sync the DMA map. */ 1010 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 1011 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1012 1013 /* 1014 * Store a pointer to the packet so we can free it later. 1015 */ 1016 ds->ds_mbuf = m0; 1017 1018 #if NBPFILTER > 0 1019 /* 1020 * If there's a BPF listener, bounce a copy of this frame 1021 * to him. 1022 */ 1023 if (ifp->if_bpf) 1024 bpf_mtap(ifp->if_bpf, m0); 1025 #endif 1026 1027 /* 1028 * Fill in the transmit descriptor. 1029 */ 1030 d->vr_data = htole32(ds->ds_dmamap->dm_segs[0].ds_addr); 1031 d->vr_ctl = htole32(m0->m_pkthdr.len); 1032 d->vr_ctl |= htole32(VR_TXCTL_FIRSTFRAG | VR_TXCTL_LASTFRAG); 1033 1034 /* 1035 * If this is the first descriptor we're enqueuing, 1036 * don't give it to the Rhine yet. That could cause 1037 * a race condition. We'll do it below. 1038 */ 1039 if (nexttx == firsttx) 1040 d->vr_status = 0; 1041 else 1042 d->vr_status = htole32(VR_TXSTAT_OWN); 1043 1044 VR_CDTXSYNC(sc, nexttx, 1045 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1046 1047 /* Advance the tx pointer. */ 1048 sc->vr_txpending++; 1049 sc->vr_txlast = nexttx; 1050 } 1051 1052 if (sc->vr_txpending == VR_NTXDESC) { 1053 /* No more slots left; notify upper layer. */ 1054 ifp->if_flags |= IFF_OACTIVE; 1055 } 1056 1057 if (sc->vr_txpending != opending) { 1058 /* 1059 * We enqueued packets. If the transmitter was idle, 1060 * reset the txdirty pointer. 1061 */ 1062 if (opending == 0) 1063 sc->vr_txdirty = firsttx; 1064 1065 /* 1066 * Cause a transmit interrupt to happen on the 1067 * last packet we enqueued. 1068 */ 1069 VR_CDTX(sc, sc->vr_txlast)->vr_ctl |= htole32(VR_TXCTL_FINT); 1070 VR_CDTXSYNC(sc, sc->vr_txlast, 1071 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1072 1073 /* 1074 * The entire packet chain is set up. Give the 1075 * first descriptor to the Rhine now. 1076 */ 1077 VR_CDTX(sc, firsttx)->vr_status = htole32(VR_TXSTAT_OWN); 1078 VR_CDTXSYNC(sc, firsttx, 1079 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1080 1081 /* Start the transmitter. */ 1082 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1083 1084 /* Set the watchdog timer in case the chip flakes out. */ 1085 ifp->if_timer = 5; 1086 } 1087 } 1088 1089 /* 1090 * Initialize the interface. Must be called at splnet. 1091 */ 1092 static int 1093 vr_init(struct ifnet *ifp) 1094 { 1095 struct vr_softc *sc = ifp->if_softc; 1096 struct vr_desc *d; 1097 struct vr_descsoft *ds; 1098 int i, error = 0; 1099 1100 /* Cancel pending I/O. */ 1101 vr_stop(ifp, 0); 1102 1103 /* Reset the Rhine to a known state. */ 1104 vr_reset(sc); 1105 1106 /* set DMA length in BCR0 and BCR1 */ 1107 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1108 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1109 1110 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1111 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTH_128BYTES); 1112 1113 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1114 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTH_STORENFWD); 1115 1116 /* set DMA threshold length in RXCFG and TXCFG */ 1117 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1118 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1119 1120 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1121 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1122 1123 /* 1124 * Initialize the transmit desciptor ring. txlast is initialized 1125 * to the end of the list so that it will wrap around to the first 1126 * descriptor when the first packet is transmitted. 1127 */ 1128 for (i = 0; i < VR_NTXDESC; i++) { 1129 d = VR_CDTX(sc, i); 1130 memset(d, 0, sizeof(struct vr_desc)); 1131 d->vr_next = htole32(VR_CDTXADDR(sc, VR_NEXTTX(i))); 1132 VR_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1133 } 1134 sc->vr_txpending = 0; 1135 sc->vr_txdirty = 0; 1136 sc->vr_txlast = VR_NTXDESC - 1; 1137 1138 /* 1139 * Initialize the receive descriptor ring. 1140 */ 1141 for (i = 0; i < VR_NRXDESC; i++) { 1142 ds = VR_DSRX(sc, i); 1143 if (ds->ds_mbuf == NULL) { 1144 if ((error = vr_add_rxbuf(sc, i)) != 0) { 1145 printf("%s: unable to allocate or map rx " 1146 "buffer %d, error = %d\n", 1147 sc->vr_dev.dv_xname, i, error); 1148 /* 1149 * XXX Should attempt to run with fewer receive 1150 * XXX buffers instead of just failing. 1151 */ 1152 vr_rxdrain(sc); 1153 goto out; 1154 } 1155 } else 1156 VR_INIT_RXDESC(sc, i); 1157 } 1158 sc->vr_rxptr = 0; 1159 1160 /* If we want promiscuous mode, set the allframes bit. */ 1161 if (ifp->if_flags & IFF_PROMISC) 1162 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1163 else 1164 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1165 1166 /* Set capture broadcast bit to capture broadcast frames. */ 1167 if (ifp->if_flags & IFF_BROADCAST) 1168 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1169 else 1170 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1171 1172 /* Program the multicast filter, if necessary. */ 1173 vr_setmulti(sc); 1174 1175 /* Give the transmit and receive rings to the Rhine. */ 1176 CSR_WRITE_4(sc, VR_RXADDR, VR_CDRXADDR(sc, sc->vr_rxptr)); 1177 CSR_WRITE_4(sc, VR_TXADDR, VR_CDTXADDR(sc, VR_NEXTTX(sc->vr_txlast))); 1178 1179 /* Set current media. */ 1180 mii_mediachg(&sc->vr_mii); 1181 1182 /* Enable receiver and transmitter. */ 1183 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1184 VR_CMD_TX_ON|VR_CMD_RX_ON| 1185 VR_CMD_RX_GO); 1186 1187 /* Enable interrupts. */ 1188 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1189 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1190 1191 ifp->if_flags |= IFF_RUNNING; 1192 ifp->if_flags &= ~IFF_OACTIVE; 1193 1194 /* Start one second timer. */ 1195 callout_reset(&sc->vr_tick_ch, hz, vr_tick, sc); 1196 1197 /* Attempt to start output on the interface. */ 1198 vr_start(ifp); 1199 1200 out: 1201 if (error) 1202 printf("%s: interface not running\n", sc->vr_dev.dv_xname); 1203 return (error); 1204 } 1205 1206 /* 1207 * Set media options. 1208 */ 1209 static int 1210 vr_ifmedia_upd(struct ifnet *ifp) 1211 { 1212 struct vr_softc *sc = ifp->if_softc; 1213 1214 if (ifp->if_flags & IFF_UP) 1215 mii_mediachg(&sc->vr_mii); 1216 return (0); 1217 } 1218 1219 /* 1220 * Report current media status. 1221 */ 1222 static void 1223 vr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1224 { 1225 struct vr_softc *sc = ifp->if_softc; 1226 1227 mii_pollstat(&sc->vr_mii); 1228 ifmr->ifm_status = sc->vr_mii.mii_media_status; 1229 ifmr->ifm_active = sc->vr_mii.mii_media_active; 1230 } 1231 1232 static int 1233 vr_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1234 { 1235 struct vr_softc *sc = ifp->if_softc; 1236 struct ifreq *ifr = (struct ifreq *)data; 1237 int s, error = 0; 1238 1239 s = splnet(); 1240 1241 switch (command) { 1242 case SIOCGIFMEDIA: 1243 case SIOCSIFMEDIA: 1244 error = ifmedia_ioctl(ifp, ifr, &sc->vr_mii.mii_media, command); 1245 break; 1246 1247 default: 1248 error = ether_ioctl(ifp, command, data); 1249 if (error == ENETRESET) { 1250 /* 1251 * Multicast list has changed; set the hardware filter 1252 * accordingly. 1253 */ 1254 if (ifp->if_flags & IFF_RUNNING) 1255 vr_setmulti(sc); 1256 error = 0; 1257 } 1258 break; 1259 } 1260 1261 splx(s); 1262 return (error); 1263 } 1264 1265 static void 1266 vr_watchdog(struct ifnet *ifp) 1267 { 1268 struct vr_softc *sc = ifp->if_softc; 1269 1270 printf("%s: device timeout\n", sc->vr_dev.dv_xname); 1271 ifp->if_oerrors++; 1272 1273 (void) vr_init(ifp); 1274 } 1275 1276 /* 1277 * One second timer, used to tick MII. 1278 */ 1279 static void 1280 vr_tick(void *arg) 1281 { 1282 struct vr_softc *sc = arg; 1283 int s; 1284 1285 s = splnet(); 1286 mii_tick(&sc->vr_mii); 1287 splx(s); 1288 1289 callout_reset(&sc->vr_tick_ch, hz, vr_tick, sc); 1290 } 1291 1292 /* 1293 * Drain the receive queue. 1294 */ 1295 static void 1296 vr_rxdrain(struct vr_softc *sc) 1297 { 1298 struct vr_descsoft *ds; 1299 int i; 1300 1301 for (i = 0; i < VR_NRXDESC; i++) { 1302 ds = VR_DSRX(sc, i); 1303 if (ds->ds_mbuf != NULL) { 1304 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 1305 m_freem(ds->ds_mbuf); 1306 ds->ds_mbuf = NULL; 1307 } 1308 } 1309 } 1310 1311 /* 1312 * Stop the adapter and free any mbufs allocated to the 1313 * transmit lists. 1314 */ 1315 static void 1316 vr_stop(struct ifnet *ifp, int disable) 1317 { 1318 struct vr_softc *sc = ifp->if_softc; 1319 struct vr_descsoft *ds; 1320 int i; 1321 1322 /* Cancel one second timer. */ 1323 callout_stop(&sc->vr_tick_ch); 1324 1325 /* Down the MII. */ 1326 mii_down(&sc->vr_mii); 1327 1328 ifp = &sc->vr_ec.ec_if; 1329 ifp->if_timer = 0; 1330 1331 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1332 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1333 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1334 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1335 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1336 1337 /* 1338 * Release any queued transmit buffers. 1339 */ 1340 for (i = 0; i < VR_NTXDESC; i++) { 1341 ds = VR_DSTX(sc, i); 1342 if (ds->ds_mbuf != NULL) { 1343 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 1344 m_freem(ds->ds_mbuf); 1345 ds->ds_mbuf = NULL; 1346 } 1347 } 1348 1349 if (disable) 1350 vr_rxdrain(sc); 1351 1352 /* 1353 * Mark the interface down and cancel the watchdog timer. 1354 */ 1355 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1356 ifp->if_timer = 0; 1357 } 1358 1359 static int vr_probe(struct device *, struct cfdata *, void *); 1360 static void vr_attach(struct device *, struct device *, void *); 1361 static void vr_shutdown(void *); 1362 1363 CFATTACH_DECL(vr, sizeof (struct vr_softc), 1364 vr_probe, vr_attach, NULL, NULL); 1365 1366 static struct vr_type * 1367 vr_lookup(struct pci_attach_args *pa) 1368 { 1369 struct vr_type *vrt; 1370 1371 for (vrt = vr_devs; vrt->vr_name != NULL; vrt++) { 1372 if (PCI_VENDOR(pa->pa_id) == vrt->vr_vid && 1373 PCI_PRODUCT(pa->pa_id) == vrt->vr_did) 1374 return (vrt); 1375 } 1376 return (NULL); 1377 } 1378 1379 static int 1380 vr_probe(struct device *parent, struct cfdata *match, void *aux) 1381 { 1382 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1383 1384 if (vr_lookup(pa) != NULL) 1385 return (1); 1386 1387 return (0); 1388 } 1389 1390 /* 1391 * Stop all chip I/O so that the kernel's probe routines don't 1392 * get confused by errant DMAs when rebooting. 1393 */ 1394 static void 1395 vr_shutdown(void *arg) 1396 { 1397 struct vr_softc *sc = (struct vr_softc *)arg; 1398 1399 vr_stop(&sc->vr_ec.ec_if, 1); 1400 } 1401 1402 /* 1403 * Attach the interface. Allocate softc structures, do ifmedia 1404 * setup and ethernet/BPF attach. 1405 */ 1406 static void 1407 vr_attach(struct device *parent, struct device *self, void *aux) 1408 { 1409 struct vr_softc *sc = (struct vr_softc *) self; 1410 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 1411 bus_dma_segment_t seg; 1412 struct vr_type *vrt; 1413 u_int32_t pmreg, reg; 1414 struct ifnet *ifp; 1415 u_char eaddr[ETHER_ADDR_LEN]; 1416 int i, rseg, error; 1417 1418 #define PCI_CONF_WRITE(r, v) pci_conf_write(pa->pa_pc, pa->pa_tag, (r), (v)) 1419 #define PCI_CONF_READ(r) pci_conf_read(pa->pa_pc, pa->pa_tag, (r)) 1420 1421 callout_init(&sc->vr_tick_ch); 1422 1423 vrt = vr_lookup(pa); 1424 if (vrt == NULL) { 1425 printf("\n"); 1426 panic("vr_attach: impossible"); 1427 } 1428 1429 printf(": %s Ethernet\n", vrt->vr_name); 1430 1431 /* 1432 * Handle power management nonsense. 1433 */ 1434 1435 if (pci_get_capability(pa->pa_pc, pa->pa_tag, 1436 PCI_CAP_PWRMGMT, &pmreg, 0)) { 1437 reg = PCI_CONF_READ(pmreg + PCI_PMCSR); 1438 if ((reg & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_STATE_D0) { 1439 u_int32_t iobase, membase, irq; 1440 1441 /* Save important PCI config data. */ 1442 iobase = PCI_CONF_READ(VR_PCI_LOIO); 1443 membase = PCI_CONF_READ(VR_PCI_LOMEM); 1444 irq = PCI_CONF_READ(PCI_INTERRUPT_REG); 1445 1446 /* Reset the power state. */ 1447 printf("%s: chip is in D%d power mode " 1448 "-- setting to D0\n", 1449 sc->vr_dev.dv_xname, reg & PCI_PMCSR_STATE_MASK); 1450 reg = (reg & ~PCI_PMCSR_STATE_MASK) | 1451 PCI_PMCSR_STATE_D0; 1452 PCI_CONF_WRITE(pmreg + PCI_PMCSR, reg); 1453 1454 /* Restore PCI config data. */ 1455 PCI_CONF_WRITE(VR_PCI_LOIO, iobase); 1456 PCI_CONF_WRITE(VR_PCI_LOMEM, membase); 1457 PCI_CONF_WRITE(PCI_INTERRUPT_REG, irq); 1458 } 1459 } 1460 1461 /* Make sure bus mastering is enabled. */ 1462 reg = PCI_CONF_READ(PCI_COMMAND_STATUS_REG); 1463 reg |= PCI_COMMAND_MASTER_ENABLE; 1464 PCI_CONF_WRITE(PCI_COMMAND_STATUS_REG, reg); 1465 1466 /* Get revision */ 1467 sc->vr_revid = PCI_REVISION(pa->pa_class); 1468 1469 /* 1470 * Map control/status registers. 1471 */ 1472 { 1473 bus_space_tag_t iot, memt; 1474 bus_space_handle_t ioh, memh; 1475 int ioh_valid, memh_valid; 1476 pci_intr_handle_t intrhandle; 1477 const char *intrstr; 1478 1479 ioh_valid = (pci_mapreg_map(pa, VR_PCI_LOIO, 1480 PCI_MAPREG_TYPE_IO, 0, 1481 &iot, &ioh, NULL, NULL) == 0); 1482 memh_valid = (pci_mapreg_map(pa, VR_PCI_LOMEM, 1483 PCI_MAPREG_TYPE_MEM | 1484 PCI_MAPREG_MEM_TYPE_32BIT, 1485 0, &memt, &memh, NULL, NULL) == 0); 1486 #if defined(VR_USEIOSPACE) 1487 if (ioh_valid) { 1488 sc->vr_bst = iot; 1489 sc->vr_bsh = ioh; 1490 } else if (memh_valid) { 1491 sc->vr_bst = memt; 1492 sc->vr_bsh = memh; 1493 } 1494 #else 1495 if (memh_valid) { 1496 sc->vr_bst = memt; 1497 sc->vr_bsh = memh; 1498 } else if (ioh_valid) { 1499 sc->vr_bst = iot; 1500 sc->vr_bsh = ioh; 1501 } 1502 #endif 1503 else { 1504 printf(": unable to map device registers\n"); 1505 return; 1506 } 1507 1508 /* Allocate interrupt */ 1509 if (pci_intr_map(pa, &intrhandle)) { 1510 printf("%s: couldn't map interrupt\n", 1511 sc->vr_dev.dv_xname); 1512 return; 1513 } 1514 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 1515 sc->vr_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 1516 vr_intr, sc); 1517 if (sc->vr_ih == NULL) { 1518 printf("%s: couldn't establish interrupt", 1519 sc->vr_dev.dv_xname); 1520 if (intrstr != NULL) 1521 printf(" at %s", intrstr); 1522 printf("\n"); 1523 } 1524 printf("%s: interrupting at %s\n", 1525 sc->vr_dev.dv_xname, intrstr); 1526 } 1527 1528 /* 1529 * Windows may put the chip in suspend mode when it 1530 * shuts down. Be sure to kick it in the head to wake it 1531 * up again. 1532 */ 1533 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 1534 1535 /* Reset the adapter. */ 1536 vr_reset(sc); 1537 1538 /* 1539 * Get station address. The way the Rhine chips work, 1540 * you're not allowed to directly access the EEPROM once 1541 * they've been programmed a special way. Consequently, 1542 * we need to read the node address from the PAR0 and PAR1 1543 * registers. 1544 * 1545 * XXXSCW: On the Rhine III, setting VR_EECSR_LOAD forces a reload 1546 * of the *whole* EEPROM, not just the MAC address. This is 1547 * pretty pointless since the chip does this automatically 1548 * at powerup/reset. 1549 * I suspect the same thing applies to the other Rhine 1550 * variants, but in the absence of a data sheet for those 1551 * (and the lack of anyone else noticing the problems this 1552 * causes) I'm going to retain the old behaviour for the 1553 * other parts. 1554 */ 1555 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT6105 && 1556 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT6102) { 1557 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 1558 DELAY(200); 1559 } 1560 for (i = 0; i < ETHER_ADDR_LEN; i++) 1561 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 1562 1563 /* 1564 * A Rhine chip was detected. Inform the world. 1565 */ 1566 printf("%s: Ethernet address: %s\n", 1567 sc->vr_dev.dv_xname, ether_sprintf(eaddr)); 1568 1569 memcpy(sc->vr_enaddr, eaddr, ETHER_ADDR_LEN); 1570 1571 sc->vr_dmat = pa->pa_dmat; 1572 1573 /* 1574 * Allocate the control data structures, and create and load 1575 * the DMA map for it. 1576 */ 1577 if ((error = bus_dmamem_alloc(sc->vr_dmat, 1578 sizeof(struct vr_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 1579 0)) != 0) { 1580 printf("%s: unable to allocate control data, error = %d\n", 1581 sc->vr_dev.dv_xname, error); 1582 goto fail_0; 1583 } 1584 1585 if ((error = bus_dmamem_map(sc->vr_dmat, &seg, rseg, 1586 sizeof(struct vr_control_data), (caddr_t *)&sc->vr_control_data, 1587 BUS_DMA_COHERENT)) != 0) { 1588 printf("%s: unable to map control data, error = %d\n", 1589 sc->vr_dev.dv_xname, error); 1590 goto fail_1; 1591 } 1592 1593 if ((error = bus_dmamap_create(sc->vr_dmat, 1594 sizeof(struct vr_control_data), 1, 1595 sizeof(struct vr_control_data), 0, 0, 1596 &sc->vr_cddmamap)) != 0) { 1597 printf("%s: unable to create control data DMA map, " 1598 "error = %d\n", sc->vr_dev.dv_xname, error); 1599 goto fail_2; 1600 } 1601 1602 if ((error = bus_dmamap_load(sc->vr_dmat, sc->vr_cddmamap, 1603 sc->vr_control_data, sizeof(struct vr_control_data), NULL, 1604 0)) != 0) { 1605 printf("%s: unable to load control data DMA map, error = %d\n", 1606 sc->vr_dev.dv_xname, error); 1607 goto fail_3; 1608 } 1609 1610 /* 1611 * Create the transmit buffer DMA maps. 1612 */ 1613 for (i = 0; i < VR_NTXDESC; i++) { 1614 if ((error = bus_dmamap_create(sc->vr_dmat, MCLBYTES, 1615 1, MCLBYTES, 0, 0, 1616 &VR_DSTX(sc, i)->ds_dmamap)) != 0) { 1617 printf("%s: unable to create tx DMA map %d, " 1618 "error = %d\n", sc->vr_dev.dv_xname, i, error); 1619 goto fail_4; 1620 } 1621 } 1622 1623 /* 1624 * Create the receive buffer DMA maps. 1625 */ 1626 for (i = 0; i < VR_NRXDESC; i++) { 1627 if ((error = bus_dmamap_create(sc->vr_dmat, MCLBYTES, 1, 1628 MCLBYTES, 0, 0, 1629 &VR_DSRX(sc, i)->ds_dmamap)) != 0) { 1630 printf("%s: unable to create rx DMA map %d, " 1631 "error = %d\n", sc->vr_dev.dv_xname, i, error); 1632 goto fail_5; 1633 } 1634 VR_DSRX(sc, i)->ds_mbuf = NULL; 1635 } 1636 1637 ifp = &sc->vr_ec.ec_if; 1638 ifp->if_softc = sc; 1639 ifp->if_mtu = ETHERMTU; 1640 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1641 ifp->if_ioctl = vr_ioctl; 1642 ifp->if_start = vr_start; 1643 ifp->if_watchdog = vr_watchdog; 1644 ifp->if_init = vr_init; 1645 ifp->if_stop = vr_stop; 1646 IFQ_SET_READY(&ifp->if_snd); 1647 1648 strcpy(ifp->if_xname, sc->vr_dev.dv_xname); 1649 1650 /* 1651 * Initialize MII/media info. 1652 */ 1653 sc->vr_mii.mii_ifp = ifp; 1654 sc->vr_mii.mii_readreg = vr_mii_readreg; 1655 sc->vr_mii.mii_writereg = vr_mii_writereg; 1656 sc->vr_mii.mii_statchg = vr_mii_statchg; 1657 ifmedia_init(&sc->vr_mii.mii_media, IFM_IMASK, vr_ifmedia_upd, 1658 vr_ifmedia_sts); 1659 mii_attach(&sc->vr_dev, &sc->vr_mii, 0xffffffff, MII_PHY_ANY, 1660 MII_OFFSET_ANY, MIIF_FORCEANEG); 1661 if (LIST_FIRST(&sc->vr_mii.mii_phys) == NULL) { 1662 ifmedia_add(&sc->vr_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1663 ifmedia_set(&sc->vr_mii.mii_media, IFM_ETHER|IFM_NONE); 1664 } else 1665 ifmedia_set(&sc->vr_mii.mii_media, IFM_ETHER|IFM_AUTO); 1666 1667 /* 1668 * Call MI attach routines. 1669 */ 1670 if_attach(ifp); 1671 ether_ifattach(ifp, sc->vr_enaddr); 1672 #if NRND > 0 1673 rnd_attach_source(&sc->rnd_source, sc->vr_dev.dv_xname, 1674 RND_TYPE_NET, 0); 1675 #endif 1676 1677 sc->vr_ats = shutdownhook_establish(vr_shutdown, sc); 1678 if (sc->vr_ats == NULL) 1679 printf("%s: warning: couldn't establish shutdown hook\n", 1680 sc->vr_dev.dv_xname); 1681 return; 1682 1683 fail_5: 1684 for (i = 0; i < VR_NRXDESC; i++) { 1685 if (sc->vr_rxsoft[i].ds_dmamap != NULL) 1686 bus_dmamap_destroy(sc->vr_dmat, 1687 sc->vr_rxsoft[i].ds_dmamap); 1688 } 1689 fail_4: 1690 for (i = 0; i < VR_NTXDESC; i++) { 1691 if (sc->vr_txsoft[i].ds_dmamap != NULL) 1692 bus_dmamap_destroy(sc->vr_dmat, 1693 sc->vr_txsoft[i].ds_dmamap); 1694 } 1695 bus_dmamap_unload(sc->vr_dmat, sc->vr_cddmamap); 1696 fail_3: 1697 bus_dmamap_destroy(sc->vr_dmat, sc->vr_cddmamap); 1698 fail_2: 1699 bus_dmamem_unmap(sc->vr_dmat, (caddr_t)sc->vr_control_data, 1700 sizeof(struct vr_control_data)); 1701 fail_1: 1702 bus_dmamem_free(sc->vr_dmat, &seg, rseg); 1703 fail_0: 1704 return; 1705 } 1706