1 /* $NetBSD: if_vr.c,v 1.133 2020/02/07 00:04:28 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1997, 1998 35 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Bill Paul. 48 * 4. Neither the name of the author nor the names of any co-contributors 49 * may be used to endorse or promote products derived from this software 50 * without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 56 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 57 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 58 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 59 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 60 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 61 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 62 * THE POSSIBILITY OF SUCH DAMAGE. 63 * 64 * $FreeBSD: if_vr.c,v 1.7 1999/01/10 18:51:49 wpaul Exp $ 65 */ 66 67 /* 68 * VIA Rhine fast ethernet PCI NIC driver 69 * 70 * Supports various network adapters based on the VIA Rhine 71 * and Rhine II PCI controllers, including the D-Link DFE530TX. 72 * Datasheets are available at http://www.via.com.tw. 73 * 74 * Written by Bill Paul <wpaul@ctr.columbia.edu> 75 * Electrical Engineering Department 76 * Columbia University, New York City 77 */ 78 79 /* 80 * The VIA Rhine controllers are similar in some respects to the 81 * the DEC tulip chips, except less complicated. The controller 82 * uses an MII bus and an external physical layer interface. The 83 * receiver has a one entry perfect filter and a 64-bit hash table 84 * multicast filter. Transmit and receive descriptors are similar 85 * to the tulip. 86 * 87 * The Rhine has a serious flaw in its transmit DMA mechanism: 88 * transmit buffers must be longword aligned. Unfortunately, 89 * the kernel doesn't guarantee that mbufs will be filled in starting 90 * at longword boundaries, so we have to do a buffer copy before 91 * transmission. 92 * 93 * Apparently, the receive DMA mechanism also has the same flaw. This 94 * means that on systems with struct alignment requirements, incoming 95 * frames must be copied to a new buffer which shifts the data forward 96 * 2 bytes so that the payload is aligned on a 4-byte boundary. 97 */ 98 99 #include <sys/cdefs.h> 100 __KERNEL_RCSID(0, "$NetBSD: if_vr.c,v 1.133 2020/02/07 00:04:28 thorpej Exp $"); 101 102 103 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/callout.h> 107 #include <sys/sockio.h> 108 #include <sys/mbuf.h> 109 #include <sys/malloc.h> 110 #include <sys/kernel.h> 111 #include <sys/socket.h> 112 #include <sys/device.h> 113 114 #include <sys/rndsource.h> 115 116 #include <net/if.h> 117 #include <net/if_arp.h> 118 #include <net/if_dl.h> 119 #include <net/if_media.h> 120 #include <net/if_ether.h> 121 122 #include <net/bpf.h> 123 124 #include <sys/bus.h> 125 #include <sys/intr.h> 126 #include <machine/endian.h> 127 128 #include <dev/mii/mii.h> 129 #include <dev/mii/miivar.h> 130 #include <dev/mii/mii_bitbang.h> 131 132 #include <dev/pci/pcireg.h> 133 #include <dev/pci/pcivar.h> 134 #include <dev/pci/pcidevs.h> 135 136 #include <dev/pci/if_vrreg.h> 137 138 #define VR_USEIOSPACE 139 140 /* 141 * Various supported device vendors/types and their names. 142 */ 143 static const struct vr_type { 144 pci_vendor_id_t vr_vid; 145 pci_product_id_t vr_did; 146 } vr_devs[] = { 147 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT3043 }, 148 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6102 }, 149 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6105 }, 150 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6105M }, 151 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT86C100A } 152 }; 153 154 /* 155 * Transmit descriptor list size. 156 */ 157 #define VR_NTXDESC 64 158 #define VR_NTXDESC_MASK (VR_NTXDESC - 1) 159 #define VR_NEXTTX(x) (((x) + 1) & VR_NTXDESC_MASK) 160 161 /* 162 * Receive descriptor list size. 163 */ 164 #define VR_NRXDESC 64 165 #define VR_NRXDESC_MASK (VR_NRXDESC - 1) 166 #define VR_NEXTRX(x) (((x) + 1) & VR_NRXDESC_MASK) 167 168 /* 169 * Control data structres that are DMA'd to the Rhine chip. We allocate 170 * them in a single clump that maps to a single DMA segment to make several 171 * things easier. 172 * 173 * Note that since we always copy outgoing packets to aligned transmit 174 * buffers, we can reduce the transmit descriptors to one per packet. 175 */ 176 struct vr_control_data { 177 struct vr_desc vr_txdescs[VR_NTXDESC]; 178 struct vr_desc vr_rxdescs[VR_NRXDESC]; 179 }; 180 181 #define VR_CDOFF(x) offsetof(struct vr_control_data, x) 182 #define VR_CDTXOFF(x) VR_CDOFF(vr_txdescs[(x)]) 183 #define VR_CDRXOFF(x) VR_CDOFF(vr_rxdescs[(x)]) 184 185 /* 186 * Software state of transmit and receive descriptors. 187 */ 188 struct vr_descsoft { 189 struct mbuf *ds_mbuf; /* head of mbuf chain */ 190 bus_dmamap_t ds_dmamap; /* our DMA map */ 191 }; 192 193 struct vr_softc { 194 device_t vr_dev; 195 void *vr_ih; /* interrupt cookie */ 196 bus_space_tag_t vr_bst; /* bus space tag */ 197 bus_space_handle_t vr_bsh; /* bus space handle */ 198 bus_dma_tag_t vr_dmat; /* bus DMA tag */ 199 pci_chipset_tag_t vr_pc; /* PCI chipset info */ 200 pcitag_t vr_tag; /* PCI tag */ 201 struct ethercom vr_ec; /* Ethernet common info */ 202 uint8_t vr_enaddr[ETHER_ADDR_LEN]; 203 struct mii_data vr_mii; /* MII/media info */ 204 205 pcireg_t vr_id; /* vendor/product ID */ 206 uint8_t vr_revid; /* Rhine chip revision */ 207 208 callout_t vr_tick_ch; /* tick callout */ 209 210 bus_dmamap_t vr_cddmamap; /* control data DMA map */ 211 #define vr_cddma vr_cddmamap->dm_segs[0].ds_addr 212 213 /* 214 * Software state for transmit and receive descriptors. 215 */ 216 struct vr_descsoft vr_txsoft[VR_NTXDESC]; 217 struct vr_descsoft vr_rxsoft[VR_NRXDESC]; 218 219 /* 220 * Control data structures. 221 */ 222 struct vr_control_data *vr_control_data; 223 224 int vr_txpending; /* number of TX requests pending */ 225 int vr_txdirty; /* first dirty TX descriptor */ 226 int vr_txlast; /* last used TX descriptor */ 227 228 int vr_rxptr; /* next ready RX descriptor */ 229 230 uint32_t vr_save_iobase; 231 uint32_t vr_save_membase; 232 uint32_t vr_save_irq; 233 234 bool vr_link; 235 int vr_flags; 236 #define VR_F_RESTART 0x1 /* restart on next tick */ 237 u_short vr_if_flags; 238 239 krndsource_t rnd_source; /* random source */ 240 }; 241 242 #define VR_CDTXADDR(sc, x) ((sc)->vr_cddma + VR_CDTXOFF((x))) 243 #define VR_CDRXADDR(sc, x) ((sc)->vr_cddma + VR_CDRXOFF((x))) 244 245 #define VR_CDTX(sc, x) (&(sc)->vr_control_data->vr_txdescs[(x)]) 246 #define VR_CDRX(sc, x) (&(sc)->vr_control_data->vr_rxdescs[(x)]) 247 248 #define VR_DSTX(sc, x) (&(sc)->vr_txsoft[(x)]) 249 #define VR_DSRX(sc, x) (&(sc)->vr_rxsoft[(x)]) 250 251 #define VR_CDTXSYNC(sc, x, ops) \ 252 bus_dmamap_sync((sc)->vr_dmat, (sc)->vr_cddmamap, \ 253 VR_CDTXOFF((x)), sizeof(struct vr_desc), (ops)) 254 255 #define VR_CDRXSYNC(sc, x, ops) \ 256 bus_dmamap_sync((sc)->vr_dmat, (sc)->vr_cddmamap, \ 257 VR_CDRXOFF((x)), sizeof(struct vr_desc), (ops)) 258 259 /* 260 * Note we rely on MCLBYTES being a power of two below. 261 */ 262 #define VR_INIT_RXDESC(sc, i) \ 263 do { \ 264 struct vr_desc *__d = VR_CDRX((sc), (i)); \ 265 struct vr_descsoft *__ds = VR_DSRX((sc), (i)); \ 266 \ 267 __d->vr_next = htole32(VR_CDRXADDR((sc), VR_NEXTRX((i)))); \ 268 __d->vr_data = htole32(__ds->ds_dmamap->dm_segs[0].ds_addr); \ 269 __d->vr_ctl = htole32(VR_RXCTL_CHAIN | VR_RXCTL_RX_INTR | \ 270 ((MCLBYTES - 1) & VR_RXCTL_BUFLEN)); \ 271 __d->vr_status = htole32(VR_RXSTAT_FIRSTFRAG | \ 272 VR_RXSTAT_LASTFRAG | VR_RXSTAT_OWN); \ 273 VR_CDRXSYNC((sc), (i), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); \ 274 } while (/* CONSTCOND */ 0) 275 276 /* 277 * register space access macros 278 */ 279 #define CSR_WRITE_4(sc, reg, val) \ 280 bus_space_write_4(sc->vr_bst, sc->vr_bsh, reg, val) 281 #define CSR_WRITE_2(sc, reg, val) \ 282 bus_space_write_2(sc->vr_bst, sc->vr_bsh, reg, val) 283 #define CSR_WRITE_1(sc, reg, val) \ 284 bus_space_write_1(sc->vr_bst, sc->vr_bsh, reg, val) 285 286 #define CSR_READ_4(sc, reg) \ 287 bus_space_read_4(sc->vr_bst, sc->vr_bsh, reg) 288 #define CSR_READ_2(sc, reg) \ 289 bus_space_read_2(sc->vr_bst, sc->vr_bsh, reg) 290 #define CSR_READ_1(sc, reg) \ 291 bus_space_read_1(sc->vr_bst, sc->vr_bsh, reg) 292 293 #define VR_TIMEOUT 1000 294 295 static int vr_add_rxbuf(struct vr_softc *, int); 296 297 static void vr_rxeof(struct vr_softc *); 298 static void vr_rxeoc(struct vr_softc *); 299 static void vr_txeof(struct vr_softc *); 300 static int vr_intr(void *); 301 static void vr_start(struct ifnet *); 302 static int vr_ioctl(struct ifnet *, u_long, void *); 303 static int vr_init(struct ifnet *); 304 static void vr_stop(struct ifnet *, int); 305 static void vr_rxdrain(struct vr_softc *); 306 static void vr_watchdog(struct ifnet *); 307 static void vr_tick(void *); 308 309 static int vr_mii_readreg(device_t, int, int, uint16_t *); 310 static int vr_mii_writereg(device_t, int, int, uint16_t); 311 static void vr_mii_statchg(struct ifnet *); 312 313 static void vr_setmulti(struct vr_softc *); 314 static void vr_reset(struct vr_softc *); 315 static int vr_restore_state(pci_chipset_tag_t, pcitag_t, device_t, 316 pcireg_t); 317 static bool vr_resume(device_t, const pmf_qual_t *); 318 319 int vr_copy_small = 0; 320 321 #define VR_SETBIT(sc, reg, x) \ 322 CSR_WRITE_1(sc, reg, \ 323 CSR_READ_1(sc, reg) | (x)) 324 325 #define VR_CLRBIT(sc, reg, x) \ 326 CSR_WRITE_1(sc, reg, \ 327 CSR_READ_1(sc, reg) & ~(x)) 328 329 #define VR_SETBIT16(sc, reg, x) \ 330 CSR_WRITE_2(sc, reg, \ 331 CSR_READ_2(sc, reg) | (x)) 332 333 #define VR_CLRBIT16(sc, reg, x) \ 334 CSR_WRITE_2(sc, reg, \ 335 CSR_READ_2(sc, reg) & ~(x)) 336 337 #define VR_SETBIT32(sc, reg, x) \ 338 CSR_WRITE_4(sc, reg, \ 339 CSR_READ_4(sc, reg) | (x)) 340 341 #define VR_CLRBIT32(sc, reg, x) \ 342 CSR_WRITE_4(sc, reg, \ 343 CSR_READ_4(sc, reg) & ~(x)) 344 345 /* 346 * MII bit-bang glue. 347 */ 348 static uint32_t vr_mii_bitbang_read(device_t); 349 static void vr_mii_bitbang_write(device_t, uint32_t); 350 351 static const struct mii_bitbang_ops vr_mii_bitbang_ops = { 352 vr_mii_bitbang_read, 353 vr_mii_bitbang_write, 354 { 355 VR_MIICMD_DATAOUT, /* MII_BIT_MDO */ 356 VR_MIICMD_DATAIN, /* MII_BIT_MDI */ 357 VR_MIICMD_CLK, /* MII_BIT_MDC */ 358 VR_MIICMD_DIR, /* MII_BIT_DIR_HOST_PHY */ 359 0, /* MII_BIT_DIR_PHY_HOST */ 360 } 361 }; 362 363 static uint32_t 364 vr_mii_bitbang_read(device_t self) 365 { 366 struct vr_softc *sc = device_private(self); 367 368 return (CSR_READ_1(sc, VR_MIICMD)); 369 } 370 371 static void 372 vr_mii_bitbang_write(device_t self, uint32_t val) 373 { 374 struct vr_softc *sc = device_private(self); 375 376 CSR_WRITE_1(sc, VR_MIICMD, (val & 0xff) | VR_MIICMD_DIRECTPGM); 377 } 378 379 /* 380 * Read an PHY register through the MII. 381 */ 382 static int 383 vr_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 384 { 385 struct vr_softc *sc = device_private(self); 386 387 CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 388 return (mii_bitbang_readreg(self, &vr_mii_bitbang_ops, phy, reg, val)); 389 } 390 391 /* 392 * Write to a PHY register through the MII. 393 */ 394 static int 395 vr_mii_writereg(device_t self, int phy, int reg, uint16_t val) 396 { 397 struct vr_softc *sc = device_private(self); 398 399 CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 400 return mii_bitbang_writereg(self, &vr_mii_bitbang_ops, phy, reg, val); 401 } 402 403 static void 404 vr_mii_statchg(struct ifnet *ifp) 405 { 406 struct vr_softc *sc = ifp->if_softc; 407 int i; 408 409 /* 410 * In order to fiddle with the 'full-duplex' bit in the netconfig 411 * register, we first have to put the transmit and/or receive logic 412 * in the idle state. 413 */ 414 if ((sc->vr_mii.mii_media_status & IFM_ACTIVE) && 415 IFM_SUBTYPE(sc->vr_mii.mii_media_active) != IFM_NONE) { 416 sc->vr_link = true; 417 418 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON | VR_CMD_RX_ON)) 419 VR_CLRBIT16(sc, VR_COMMAND, 420 (VR_CMD_TX_ON | VR_CMD_RX_ON)); 421 422 if (sc->vr_mii.mii_media_active & IFM_FDX) 423 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 424 else 425 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 426 427 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON | VR_CMD_RX_ON); 428 } else { 429 sc->vr_link = false; 430 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_TX_ON | VR_CMD_RX_ON); 431 for (i = VR_TIMEOUT; i > 0; i--) { 432 delay(10); 433 if (!(CSR_READ_2(sc, VR_COMMAND) & 434 (VR_CMD_TX_ON | VR_CMD_RX_ON))) 435 break; 436 } 437 if (i == 0) { 438 #ifdef VR_DEBUG 439 aprint_error_dev(sc->vr_dev, "rx shutdown error!\n"); 440 #endif 441 sc->vr_flags |= VR_F_RESTART; 442 } 443 } 444 } 445 446 #define vr_calchash(addr) \ 447 (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26) 448 449 /* 450 * Program the 64-bit multicast hash filter. 451 */ 452 static void 453 vr_setmulti(struct vr_softc *sc) 454 { 455 struct ethercom *ec = &sc->vr_ec; 456 struct ifnet *ifp = &ec->ec_if; 457 int h = 0; 458 uint32_t hashes[2] = { 0, 0 }; 459 struct ether_multistep step; 460 struct ether_multi *enm; 461 int mcnt = 0; 462 uint8_t rxfilt; 463 464 rxfilt = CSR_READ_1(sc, VR_RXCFG); 465 466 if (ifp->if_flags & IFF_PROMISC) { 467 allmulti: 468 ifp->if_flags |= IFF_ALLMULTI; 469 rxfilt |= VR_RXCFG_RX_MULTI; 470 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 471 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 472 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 473 return; 474 } 475 476 /* first, zot all the existing hash bits */ 477 CSR_WRITE_4(sc, VR_MAR0, 0); 478 CSR_WRITE_4(sc, VR_MAR1, 0); 479 480 /* now program new ones */ 481 ETHER_LOCK(ec); 482 ETHER_FIRST_MULTI(step, ec, enm); 483 while (enm != NULL) { 484 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 485 ETHER_ADDR_LEN) != 0) { 486 ETHER_UNLOCK(ec); 487 goto allmulti; 488 } 489 490 h = vr_calchash(enm->enm_addrlo); 491 492 if (h < 32) 493 hashes[0] |= (1 << h); 494 else 495 hashes[1] |= (1 << (h - 32)); 496 ETHER_NEXT_MULTI(step, enm); 497 mcnt++; 498 } 499 ETHER_UNLOCK(ec); 500 501 ifp->if_flags &= ~IFF_ALLMULTI; 502 503 if (mcnt) 504 rxfilt |= VR_RXCFG_RX_MULTI; 505 else 506 rxfilt &= ~VR_RXCFG_RX_MULTI; 507 508 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 509 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 510 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 511 } 512 513 static void 514 vr_reset(struct vr_softc *sc) 515 { 516 int i; 517 518 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 519 520 for (i = 0; i < VR_TIMEOUT; i++) { 521 DELAY(10); 522 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 523 break; 524 } 525 if (i == VR_TIMEOUT) { 526 if (sc->vr_revid < REV_ID_VT3065_A) { 527 aprint_error_dev(sc->vr_dev, 528 "reset never completed!\n"); 529 } else { 530 /* Use newer force reset command */ 531 aprint_normal_dev(sc->vr_dev, 532 "using force reset command.\n"); 533 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 534 } 535 } 536 537 /* Wait a little while for the chip to get its brains in order. */ 538 DELAY(1000); 539 } 540 541 /* 542 * Initialize an RX descriptor and attach an MBUF cluster. 543 * Note: the length fields are only 11 bits wide, which means the 544 * largest size we can specify is 2047. This is important because 545 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 546 * overflow the field and make a mess. 547 */ 548 static int 549 vr_add_rxbuf(struct vr_softc *sc, int i) 550 { 551 struct vr_descsoft *ds = VR_DSRX(sc, i); 552 struct mbuf *m_new; 553 int error; 554 555 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 556 if (m_new == NULL) 557 return (ENOBUFS); 558 559 MCLGET(m_new, M_DONTWAIT); 560 if ((m_new->m_flags & M_EXT) == 0) { 561 m_freem(m_new); 562 return (ENOBUFS); 563 } 564 565 if (ds->ds_mbuf != NULL) 566 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 567 568 ds->ds_mbuf = m_new; 569 570 error = bus_dmamap_load(sc->vr_dmat, ds->ds_dmamap, 571 m_new->m_ext.ext_buf, m_new->m_ext.ext_size, NULL, 572 BUS_DMA_READ | BUS_DMA_NOWAIT); 573 if (error) { 574 aprint_error_dev(sc->vr_dev, 575 "unable to load rx DMA map %d, error = %d\n", i, error); 576 panic("vr_add_rxbuf"); /* XXX */ 577 } 578 579 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 580 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 581 582 VR_INIT_RXDESC(sc, i); 583 584 return (0); 585 } 586 587 /* 588 * A frame has been uploaded: pass the resulting mbuf chain up to 589 * the higher level protocols. 590 */ 591 static void 592 vr_rxeof(struct vr_softc *sc) 593 { 594 struct mbuf *m; 595 struct ifnet *ifp; 596 struct vr_desc *d; 597 struct vr_descsoft *ds; 598 int i, total_len; 599 uint32_t rxstat; 600 601 ifp = &sc->vr_ec.ec_if; 602 603 for (i = sc->vr_rxptr;; i = VR_NEXTRX(i)) { 604 d = VR_CDRX(sc, i); 605 ds = VR_DSRX(sc, i); 606 607 VR_CDRXSYNC(sc, i, 608 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 609 610 rxstat = le32toh(d->vr_status); 611 612 if (rxstat & VR_RXSTAT_OWN) { 613 /* 614 * We have processed all of the receive buffers. 615 */ 616 break; 617 } 618 619 /* 620 * If an error occurs, update stats, clear the 621 * status word and leave the mbuf cluster in place: 622 * it should simply get re-used next time this descriptor 623 * comes up in the ring. 624 */ 625 if (rxstat & VR_RXSTAT_RXERR) { 626 const char *errstr; 627 628 if_statinc(ifp, if_ierrors); 629 switch (rxstat & 0x000000FF) { 630 case VR_RXSTAT_CRCERR: 631 errstr = "crc error"; 632 break; 633 case VR_RXSTAT_FRAMEALIGNERR: 634 errstr = "frame alignment error"; 635 break; 636 case VR_RXSTAT_FIFOOFLOW: 637 errstr = "FIFO overflow"; 638 break; 639 case VR_RXSTAT_GIANT: 640 errstr = "received giant packet"; 641 break; 642 case VR_RXSTAT_RUNT: 643 errstr = "received runt packet"; 644 break; 645 case VR_RXSTAT_BUSERR: 646 errstr = "system bus error"; 647 break; 648 case VR_RXSTAT_BUFFERR: 649 errstr = "rx buffer error"; 650 break; 651 default: 652 errstr = "unknown rx error"; 653 break; 654 } 655 aprint_error_dev(sc->vr_dev, "receive error: %s\n", 656 errstr); 657 658 VR_INIT_RXDESC(sc, i); 659 660 continue; 661 } else if (!(rxstat & VR_RXSTAT_FIRSTFRAG) || 662 !(rxstat & VR_RXSTAT_LASTFRAG)) { 663 /* 664 * This driver expects to receive whole packets every 665 * time. In case we receive a fragment that is not 666 * a complete packet, we discard it. 667 */ 668 if_statinc(ifp, if_ierrors); 669 670 aprint_error_dev(sc->vr_dev, 671 "receive error: incomplete frame; " 672 "size = %d, status = 0x%x\n", 673 VR_RXBYTES(le32toh(d->vr_status)), rxstat); 674 675 VR_INIT_RXDESC(sc, i); 676 677 continue; 678 } 679 680 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 681 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 682 683 /* No errors; receive the packet. */ 684 total_len = VR_RXBYTES(le32toh(d->vr_status)); 685 #ifdef DIAGNOSTIC 686 if (total_len == 0) { 687 /* 688 * If we receive a zero-length packet, we probably 689 * missed to handle an error condition above. 690 * Discard it to avoid a later crash. 691 */ 692 if_statinc(ifp, if_ierrors); 693 694 aprint_error_dev(sc->vr_dev, 695 "receive error: zero-length packet; " 696 "status = 0x%x\n", rxstat); 697 698 VR_INIT_RXDESC(sc, i); 699 700 continue; 701 } 702 #endif 703 704 /* 705 * The Rhine chip includes the CRC with every packet. 706 * Trim it off here. 707 */ 708 total_len -= ETHER_CRC_LEN; 709 710 #ifdef __NO_STRICT_ALIGNMENT 711 /* 712 * If the packet is small enough to fit in a 713 * single header mbuf, allocate one and copy 714 * the data into it. This greatly reduces 715 * memory consumption when we receive lots 716 * of small packets. 717 * 718 * Otherwise, we add a new buffer to the receive 719 * chain. If this fails, we drop the packet and 720 * recycle the old buffer. 721 */ 722 if (vr_copy_small != 0 && total_len <= MHLEN) { 723 MGETHDR(m, M_DONTWAIT, MT_DATA); 724 if (m == NULL) 725 goto dropit; 726 memcpy(mtod(m, void *), 727 mtod(ds->ds_mbuf, void *), total_len); 728 VR_INIT_RXDESC(sc, i); 729 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 730 ds->ds_dmamap->dm_mapsize, 731 BUS_DMASYNC_PREREAD); 732 } else { 733 m = ds->ds_mbuf; 734 if (vr_add_rxbuf(sc, i) == ENOBUFS) { 735 dropit: 736 if_statinc(ifp, if_ierrors); 737 VR_INIT_RXDESC(sc, i); 738 bus_dmamap_sync(sc->vr_dmat, 739 ds->ds_dmamap, 0, 740 ds->ds_dmamap->dm_mapsize, 741 BUS_DMASYNC_PREREAD); 742 continue; 743 } 744 } 745 #else 746 /* 747 * The Rhine's packet buffers must be 4-byte aligned. 748 * But this means that the data after the Ethernet header 749 * is misaligned. We must allocate a new buffer and 750 * copy the data, shifted forward 2 bytes. 751 */ 752 MGETHDR(m, M_DONTWAIT, MT_DATA); 753 if (m == NULL) { 754 dropit: 755 if_statinc(ifp, if_ierrors); 756 VR_INIT_RXDESC(sc, i); 757 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 758 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 759 continue; 760 } 761 if (total_len > (MHLEN - 2)) { 762 MCLGET(m, M_DONTWAIT); 763 if ((m->m_flags & M_EXT) == 0) { 764 m_freem(m); 765 goto dropit; 766 } 767 } 768 m->m_data += 2; 769 770 /* 771 * Note that we use clusters for incoming frames, so the 772 * buffer is virtually contiguous. 773 */ 774 memcpy(mtod(m, void *), mtod(ds->ds_mbuf, void *), 775 total_len); 776 777 /* Allow the receive descriptor to continue using its mbuf. */ 778 VR_INIT_RXDESC(sc, i); 779 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 780 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 781 #endif /* __NO_STRICT_ALIGNMENT */ 782 783 m_set_rcvif(m, ifp); 784 m->m_pkthdr.len = m->m_len = total_len; 785 /* Pass it on. */ 786 if_percpuq_enqueue(ifp->if_percpuq, m); 787 } 788 789 /* Update the receive pointer. */ 790 sc->vr_rxptr = i; 791 } 792 793 void 794 vr_rxeoc(struct vr_softc *sc) 795 { 796 struct ifnet *ifp; 797 int i; 798 799 ifp = &sc->vr_ec.ec_if; 800 801 if_statinc(ifp, if_ierrors); 802 803 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 804 for (i = 0; i < VR_TIMEOUT; i++) { 805 DELAY(10); 806 if ((CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON) == 0) 807 break; 808 } 809 if (i == VR_TIMEOUT) { 810 /* XXX need reset? */ 811 aprint_error_dev(sc->vr_dev, "RX shutdown never completed\n"); 812 } 813 814 vr_rxeof(sc); 815 816 CSR_WRITE_4(sc, VR_RXADDR, VR_CDRXADDR(sc, sc->vr_rxptr)); 817 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 818 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 819 } 820 821 /* 822 * A frame was downloaded to the chip. It's safe for us to clean up 823 * the list buffers. 824 */ 825 static void 826 vr_txeof(struct vr_softc *sc) 827 { 828 struct ifnet *ifp = &sc->vr_ec.ec_if; 829 struct vr_desc *d; 830 struct vr_descsoft *ds; 831 uint32_t txstat; 832 int i, j; 833 834 ifp->if_flags &= ~IFF_OACTIVE; 835 836 /* 837 * Go through our tx list and free mbufs for those 838 * frames that have been transmitted. 839 */ 840 for (i = sc->vr_txdirty; sc->vr_txpending != 0; 841 i = VR_NEXTTX(i), sc->vr_txpending--) { 842 d = VR_CDTX(sc, i); 843 ds = VR_DSTX(sc, i); 844 845 VR_CDTXSYNC(sc, i, 846 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 847 848 txstat = le32toh(d->vr_status); 849 850 if (txstat & (VR_TXSTAT_ABRT | VR_TXSTAT_UDF)) { 851 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 852 for (j = 0; j < VR_TIMEOUT; j++) { 853 DELAY(10); 854 if ((CSR_READ_2(sc, VR_COMMAND) & 855 VR_CMD_TX_ON) == 0) 856 break; 857 } 858 if (j == VR_TIMEOUT) { 859 /* XXX need reset? */ 860 aprint_error_dev(sc->vr_dev, 861 "TX shutdown never completed\n"); 862 } 863 d->vr_status = htole32(VR_TXSTAT_OWN); 864 CSR_WRITE_4(sc, VR_TXADDR, VR_CDTXADDR(sc, i)); 865 break; 866 } 867 868 if (txstat & VR_TXSTAT_OWN) 869 break; 870 871 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 872 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 873 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 874 m_freem(ds->ds_mbuf); 875 ds->ds_mbuf = NULL; 876 877 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 878 if (txstat & VR_TXSTAT_ERRSUM) { 879 if_statinc_ref(nsr, if_oerrors); 880 if (txstat & VR_TXSTAT_DEFER) 881 if_statinc_ref(nsr, if_collisions); 882 if (txstat & VR_TXSTAT_LATECOLL) 883 if_statinc_ref(nsr, if_collisions); 884 } 885 886 if_statadd_ref(nsr, if_collisions, 887 (txstat & VR_TXSTAT_COLLCNT) >> 3); 888 if_statinc_ref(nsr, if_opackets); 889 IF_STAT_PUTREF(ifp); 890 } 891 892 /* Update the dirty transmit buffer pointer. */ 893 sc->vr_txdirty = i; 894 895 /* 896 * Cancel the watchdog timer if there are no pending 897 * transmissions. 898 */ 899 if (sc->vr_txpending == 0) 900 ifp->if_timer = 0; 901 } 902 903 static int 904 vr_intr(void *arg) 905 { 906 struct vr_softc *sc; 907 struct ifnet *ifp; 908 uint16_t status; 909 int handled = 0, dotx = 0; 910 911 sc = arg; 912 ifp = &sc->vr_ec.ec_if; 913 914 /* Suppress unwanted interrupts. */ 915 if ((ifp->if_flags & IFF_UP) == 0) { 916 vr_stop(ifp, 1); 917 return (0); 918 } 919 920 /* Disable interrupts. */ 921 CSR_WRITE_2(sc, VR_IMR, 0x0000); 922 923 for (;;) { 924 status = CSR_READ_2(sc, VR_ISR); 925 if (status) 926 CSR_WRITE_2(sc, VR_ISR, status); 927 928 if ((status & VR_INTRS) == 0) 929 break; 930 931 handled = 1; 932 933 rnd_add_uint32(&sc->rnd_source, status); 934 935 if (status & VR_ISR_RX_OK) 936 vr_rxeof(sc); 937 938 if (status & VR_ISR_RX_DROPPED) { 939 aprint_error_dev(sc->vr_dev, "rx packet lost\n"); 940 if_statinc(ifp, if_ierrors); 941 } 942 943 if (status & 944 (VR_ISR_RX_ERR | VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW)) 945 vr_rxeoc(sc); 946 947 948 if (status & (VR_ISR_BUSERR | VR_ISR_TX_UNDERRUN)) { 949 if (status & VR_ISR_BUSERR) 950 aprint_error_dev(sc->vr_dev, "PCI bus error\n"); 951 if (status & VR_ISR_TX_UNDERRUN) 952 aprint_error_dev(sc->vr_dev, 953 "transmit underrun\n"); 954 /* vr_init() calls vr_start() */ 955 dotx = 0; 956 (void)vr_init(ifp); 957 958 } 959 960 if (status & VR_ISR_TX_OK) { 961 dotx = 1; 962 vr_txeof(sc); 963 } 964 965 if (status & 966 (VR_ISR_TX_ABRT | VR_ISR_TX_ABRT2 | VR_ISR_TX_UDFI)) { 967 if (status & (VR_ISR_TX_ABRT | VR_ISR_TX_ABRT2)) 968 aprint_error_dev(sc->vr_dev, 969 "transmit aborted\n"); 970 if (status & VR_ISR_TX_UDFI) 971 aprint_error_dev(sc->vr_dev, 972 "transmit underflow\n"); 973 if_statinc(ifp, if_oerrors); 974 dotx = 1; 975 vr_txeof(sc); 976 if (sc->vr_txpending) { 977 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 978 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 979 } 980 } 981 } 982 983 /* Re-enable interrupts. */ 984 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 985 986 if (dotx) 987 if_schedule_deferred_start(ifp); 988 989 return (handled); 990 } 991 992 /* 993 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 994 * to the mbuf data regions directly in the transmit lists. We also save a 995 * copy of the pointers since the transmit list fragment pointers are 996 * physical addresses. 997 */ 998 static void 999 vr_start(struct ifnet *ifp) 1000 { 1001 struct vr_softc *sc = ifp->if_softc; 1002 struct mbuf *m0, *m; 1003 struct vr_desc *d; 1004 struct vr_descsoft *ds; 1005 int error, firsttx, nexttx, opending; 1006 1007 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1008 return; 1009 if (sc->vr_link == false) 1010 return; 1011 1012 /* 1013 * Remember the previous txpending and the first transmit 1014 * descriptor we use. 1015 */ 1016 opending = sc->vr_txpending; 1017 firsttx = VR_NEXTTX(sc->vr_txlast); 1018 1019 /* 1020 * Loop through the send queue, setting up transmit descriptors 1021 * until we drain the queue, or use up all available transmit 1022 * descriptors. 1023 */ 1024 while (sc->vr_txpending < VR_NTXDESC) { 1025 /* 1026 * Grab a packet off the queue. 1027 */ 1028 IFQ_POLL(&ifp->if_snd, m0); 1029 if (m0 == NULL) 1030 break; 1031 m = NULL; 1032 1033 /* 1034 * Get the next available transmit descriptor. 1035 */ 1036 nexttx = VR_NEXTTX(sc->vr_txlast); 1037 d = VR_CDTX(sc, nexttx); 1038 ds = VR_DSTX(sc, nexttx); 1039 1040 /* 1041 * Load the DMA map. If this fails, the packet didn't 1042 * fit in one DMA segment, and we need to copy. Note, 1043 * the packet must also be aligned. 1044 * if the packet is too small, copy it too, so we're sure 1045 * we have enough room for the pad buffer. 1046 */ 1047 if ((mtod(m0, uintptr_t) & 3) != 0 || 1048 m0->m_pkthdr.len < VR_MIN_FRAMELEN || 1049 bus_dmamap_load_mbuf(sc->vr_dmat, ds->ds_dmamap, m0, 1050 BUS_DMA_WRITE | BUS_DMA_NOWAIT) != 0) { 1051 MGETHDR(m, M_DONTWAIT, MT_DATA); 1052 if (m == NULL) { 1053 aprint_error_dev(sc->vr_dev, 1054 "unable to allocate Tx mbuf\n"); 1055 break; 1056 } 1057 if (m0->m_pkthdr.len > MHLEN) { 1058 MCLGET(m, M_DONTWAIT); 1059 if ((m->m_flags & M_EXT) == 0) { 1060 aprint_error_dev(sc->vr_dev, 1061 "unable to allocate Tx cluster\n"); 1062 m_freem(m); 1063 break; 1064 } 1065 } 1066 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1067 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1068 /* 1069 * The Rhine doesn't auto-pad, so we have to do this 1070 * ourselves. 1071 */ 1072 if (m0->m_pkthdr.len < VR_MIN_FRAMELEN) { 1073 memset(mtod(m, char *) + m0->m_pkthdr.len, 1074 0, VR_MIN_FRAMELEN - m0->m_pkthdr.len); 1075 m->m_pkthdr.len = m->m_len = VR_MIN_FRAMELEN; 1076 } 1077 error = bus_dmamap_load_mbuf(sc->vr_dmat, 1078 ds->ds_dmamap, m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1079 if (error) { 1080 m_freem(m); 1081 aprint_error_dev(sc->vr_dev, "unable to load " 1082 "Tx buffer, error = %d\n", error); 1083 break; 1084 } 1085 } 1086 1087 IFQ_DEQUEUE(&ifp->if_snd, m0); 1088 if (m != NULL) { 1089 m_freem(m0); 1090 m0 = m; 1091 } 1092 1093 /* Sync the DMA map. */ 1094 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0, 1095 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); 1096 1097 /* 1098 * Store a pointer to the packet so we can free it later. 1099 */ 1100 ds->ds_mbuf = m0; 1101 1102 /* 1103 * If there's a BPF listener, bounce a copy of this frame 1104 * to him. 1105 */ 1106 bpf_mtap(ifp, m0, BPF_D_OUT); 1107 1108 /* 1109 * Fill in the transmit descriptor. 1110 */ 1111 d->vr_data = htole32(ds->ds_dmamap->dm_segs[0].ds_addr); 1112 d->vr_ctl = htole32(m0->m_pkthdr.len); 1113 d->vr_ctl |= htole32(VR_TXCTL_FIRSTFRAG | VR_TXCTL_LASTFRAG); 1114 1115 /* 1116 * If this is the first descriptor we're enqueuing, 1117 * don't give it to the Rhine yet. That could cause 1118 * a race condition. We'll do it below. 1119 */ 1120 if (nexttx == firsttx) 1121 d->vr_status = 0; 1122 else 1123 d->vr_status = htole32(VR_TXSTAT_OWN); 1124 1125 VR_CDTXSYNC(sc, nexttx, 1126 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1127 1128 /* Advance the tx pointer. */ 1129 sc->vr_txpending++; 1130 sc->vr_txlast = nexttx; 1131 } 1132 1133 if (sc->vr_txpending == VR_NTXDESC) { 1134 /* No more slots left; notify upper layer. */ 1135 ifp->if_flags |= IFF_OACTIVE; 1136 } 1137 1138 if (sc->vr_txpending != opending) { 1139 /* 1140 * We enqueued packets. If the transmitter was idle, 1141 * reset the txdirty pointer. 1142 */ 1143 if (opending == 0) 1144 sc->vr_txdirty = firsttx; 1145 1146 /* 1147 * Cause a transmit interrupt to happen on the 1148 * last packet we enqueued. 1149 */ 1150 VR_CDTX(sc, sc->vr_txlast)->vr_ctl |= htole32(VR_TXCTL_FINT); 1151 VR_CDTXSYNC(sc, sc->vr_txlast, 1152 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1153 1154 /* 1155 * The entire packet chain is set up. Give the 1156 * first descriptor to the Rhine now. 1157 */ 1158 VR_CDTX(sc, firsttx)->vr_status = htole32(VR_TXSTAT_OWN); 1159 VR_CDTXSYNC(sc, firsttx, 1160 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1161 1162 /* Start the transmitter. */ 1163 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1164 1165 /* Set the watchdog timer in case the chip flakes out. */ 1166 ifp->if_timer = 5; 1167 } 1168 } 1169 1170 /* 1171 * Initialize the interface. Must be called at splnet. 1172 */ 1173 static int 1174 vr_init(struct ifnet *ifp) 1175 { 1176 struct vr_softc *sc = ifp->if_softc; 1177 struct vr_desc *d; 1178 struct vr_descsoft *ds; 1179 int i, error = 0; 1180 1181 /* Cancel pending I/O. */ 1182 vr_stop(ifp, 0); 1183 1184 /* Reset the Rhine to a known state. */ 1185 vr_reset(sc); 1186 1187 /* set DMA length in BCR0 and BCR1 */ 1188 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1189 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1190 1191 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1192 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTH_128BYTES); 1193 1194 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1195 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTH_STORENFWD); 1196 1197 /* set DMA threshold length in RXCFG and TXCFG */ 1198 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1199 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1200 1201 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1202 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1203 1204 /* 1205 * Initialize the transmit descriptor ring. txlast is initialized 1206 * to the end of the list so that it will wrap around to the first 1207 * descriptor when the first packet is transmitted. 1208 */ 1209 for (i = 0; i < VR_NTXDESC; i++) { 1210 d = VR_CDTX(sc, i); 1211 memset(d, 0, sizeof(struct vr_desc)); 1212 d->vr_next = htole32(VR_CDTXADDR(sc, VR_NEXTTX(i))); 1213 VR_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1214 } 1215 sc->vr_txpending = 0; 1216 sc->vr_txdirty = 0; 1217 sc->vr_txlast = VR_NTXDESC - 1; 1218 1219 /* 1220 * Initialize the receive descriptor ring. 1221 */ 1222 for (i = 0; i < VR_NRXDESC; i++) { 1223 ds = VR_DSRX(sc, i); 1224 if (ds->ds_mbuf == NULL) { 1225 if ((error = vr_add_rxbuf(sc, i)) != 0) { 1226 aprint_error_dev(sc->vr_dev, 1227 "unable to allocate or map rx buffer %d, " 1228 "error = %d\n", i, error); 1229 /* 1230 * XXX Should attempt to run with fewer receive 1231 * XXX buffers instead of just failing. 1232 */ 1233 vr_rxdrain(sc); 1234 goto out; 1235 } 1236 } else 1237 VR_INIT_RXDESC(sc, i); 1238 } 1239 sc->vr_rxptr = 0; 1240 1241 /* If we want promiscuous mode, set the allframes bit. */ 1242 if (ifp->if_flags & IFF_PROMISC) 1243 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1244 else 1245 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1246 1247 /* Set capture broadcast bit to capture broadcast frames. */ 1248 if (ifp->if_flags & IFF_BROADCAST) 1249 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1250 else 1251 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1252 1253 /* Program the multicast filter, if necessary. */ 1254 vr_setmulti(sc); 1255 1256 /* Give the transmit and receive rings to the Rhine. */ 1257 CSR_WRITE_4(sc, VR_RXADDR, VR_CDRXADDR(sc, sc->vr_rxptr)); 1258 CSR_WRITE_4(sc, VR_TXADDR, VR_CDTXADDR(sc, VR_NEXTTX(sc->vr_txlast))); 1259 1260 /* Set current media. */ 1261 sc->vr_link = true; 1262 if ((error = ether_mediachange(ifp)) != 0) 1263 goto out; 1264 1265 /* Enable receiver and transmitter. */ 1266 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL | VR_CMD_START | 1267 VR_CMD_TX_ON | VR_CMD_RX_ON | 1268 VR_CMD_RX_GO); 1269 1270 /* Enable interrupts. */ 1271 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1272 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1273 1274 ifp->if_flags |= IFF_RUNNING; 1275 ifp->if_flags &= ~IFF_OACTIVE; 1276 1277 /* Start one second timer. */ 1278 callout_schedule(&sc->vr_tick_ch, hz); 1279 1280 /* Attempt to start output on the interface. */ 1281 vr_start(ifp); 1282 1283 out: 1284 if (error) 1285 aprint_error_dev(sc->vr_dev, "interface not running\n"); 1286 return (error); 1287 } 1288 1289 static int 1290 vr_ioctl(struct ifnet *ifp, u_long command, void *data) 1291 { 1292 struct vr_softc *sc = ifp->if_softc; 1293 int s, error = 0; 1294 1295 s = splnet(); 1296 1297 switch (command) { 1298 case SIOCSIFFLAGS: 1299 if ((error = ifioctl_common(ifp, command, data)) != 0) 1300 break; 1301 1302 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 1303 case IFF_RUNNING: 1304 vr_stop(ifp, 1); 1305 break; 1306 case IFF_UP: 1307 vr_init(ifp); 1308 break; 1309 case IFF_UP | IFF_RUNNING: 1310 if ((ifp->if_flags ^ sc->vr_if_flags) == IFF_PROMISC) 1311 vr_setmulti(sc); 1312 else 1313 vr_init(ifp); 1314 break; 1315 } 1316 sc->vr_if_flags = ifp->if_flags; 1317 break; 1318 default: 1319 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1320 break; 1321 error = 0; 1322 if (command == SIOCADDMULTI || command == SIOCDELMULTI) 1323 vr_setmulti(sc); 1324 } 1325 splx(s); 1326 1327 return error; 1328 } 1329 1330 static void 1331 vr_watchdog(struct ifnet *ifp) 1332 { 1333 struct vr_softc *sc = ifp->if_softc; 1334 1335 aprint_error_dev(sc->vr_dev, "device timeout\n"); 1336 if_statinc(ifp, if_oerrors); 1337 1338 (void) vr_init(ifp); 1339 } 1340 1341 /* 1342 * One second timer, used to tick MII. 1343 */ 1344 static void 1345 vr_tick(void *arg) 1346 { 1347 struct vr_softc *sc = arg; 1348 int s; 1349 1350 s = splnet(); 1351 if (sc->vr_flags & VR_F_RESTART) { 1352 aprint_normal_dev(sc->vr_dev, "restarting\n"); 1353 vr_init(&sc->vr_ec.ec_if); 1354 sc->vr_flags &= ~VR_F_RESTART; 1355 } 1356 mii_tick(&sc->vr_mii); 1357 splx(s); 1358 1359 callout_schedule(&sc->vr_tick_ch, hz); 1360 } 1361 1362 /* 1363 * Drain the receive queue. 1364 */ 1365 static void 1366 vr_rxdrain(struct vr_softc *sc) 1367 { 1368 struct vr_descsoft *ds; 1369 int i; 1370 1371 for (i = 0; i < VR_NRXDESC; i++) { 1372 ds = VR_DSRX(sc, i); 1373 if (ds->ds_mbuf != NULL) { 1374 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 1375 m_freem(ds->ds_mbuf); 1376 ds->ds_mbuf = NULL; 1377 } 1378 } 1379 } 1380 1381 /* 1382 * Stop the adapter and free any mbufs allocated to the 1383 * transmit lists. 1384 */ 1385 static void 1386 vr_stop(struct ifnet *ifp, int disable) 1387 { 1388 struct vr_softc *sc = ifp->if_softc; 1389 struct vr_descsoft *ds; 1390 int i; 1391 1392 /* Cancel one second timer. */ 1393 callout_stop(&sc->vr_tick_ch); 1394 1395 /* Down the MII. */ 1396 mii_down(&sc->vr_mii); 1397 1398 ifp = &sc->vr_ec.ec_if; 1399 ifp->if_timer = 0; 1400 1401 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1402 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON | VR_CMD_TX_ON)); 1403 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1404 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1405 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1406 1407 /* 1408 * Release any queued transmit buffers. 1409 */ 1410 for (i = 0; i < VR_NTXDESC; i++) { 1411 ds = VR_DSTX(sc, i); 1412 if (ds->ds_mbuf != NULL) { 1413 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap); 1414 m_freem(ds->ds_mbuf); 1415 ds->ds_mbuf = NULL; 1416 } 1417 } 1418 1419 /* 1420 * Mark the interface down and cancel the watchdog timer. 1421 */ 1422 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1423 ifp->if_timer = 0; 1424 1425 if (disable) 1426 vr_rxdrain(sc); 1427 } 1428 1429 static int vr_probe(device_t, cfdata_t, void *); 1430 static void vr_attach(device_t, device_t, void *); 1431 static bool vr_shutdown(device_t, int); 1432 1433 CFATTACH_DECL_NEW(vr, sizeof (struct vr_softc), 1434 vr_probe, vr_attach, NULL, NULL); 1435 1436 static const struct vr_type * 1437 vr_lookup(struct pci_attach_args *pa) 1438 { 1439 const struct vr_type *vrt; 1440 int i; 1441 1442 for (i = 0; i < __arraycount(vr_devs); i++) { 1443 vrt = &vr_devs[i]; 1444 if (PCI_VENDOR(pa->pa_id) == vrt->vr_vid && 1445 PCI_PRODUCT(pa->pa_id) == vrt->vr_did) 1446 return (vrt); 1447 } 1448 return (NULL); 1449 } 1450 1451 static int 1452 vr_probe(device_t parent, cfdata_t match, void *aux) 1453 { 1454 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1455 1456 if (vr_lookup(pa) != NULL) 1457 return (1); 1458 1459 return (0); 1460 } 1461 1462 /* 1463 * Stop all chip I/O so that the kernel's probe routines don't 1464 * get confused by errant DMAs when rebooting. 1465 */ 1466 static bool 1467 vr_shutdown(device_t self, int howto) 1468 { 1469 struct vr_softc *sc = device_private(self); 1470 1471 vr_stop(&sc->vr_ec.ec_if, 1); 1472 1473 return true; 1474 } 1475 1476 /* 1477 * Attach the interface. Allocate softc structures, do ifmedia 1478 * setup and ethernet/BPF attach. 1479 */ 1480 static void 1481 vr_attach(device_t parent, device_t self, void *aux) 1482 { 1483 struct vr_softc *sc = device_private(self); 1484 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 1485 bus_dma_segment_t seg; 1486 uint32_t reg; 1487 struct ifnet *ifp; 1488 struct mii_data * const mii = &sc->vr_mii; 1489 uint8_t eaddr[ETHER_ADDR_LEN], mac; 1490 int i, rseg, error; 1491 char intrbuf[PCI_INTRSTR_LEN]; 1492 1493 #define PCI_CONF_WRITE(r, v) pci_conf_write(sc->vr_pc, sc->vr_tag, (r), (v)) 1494 #define PCI_CONF_READ(r) pci_conf_read(sc->vr_pc, sc->vr_tag, (r)) 1495 1496 sc->vr_dev = self; 1497 sc->vr_pc = pa->pa_pc; 1498 sc->vr_tag = pa->pa_tag; 1499 sc->vr_id = pa->pa_id; 1500 callout_init(&sc->vr_tick_ch, 0); 1501 callout_setfunc(&sc->vr_tick_ch, vr_tick, sc); 1502 1503 pci_aprint_devinfo(pa, NULL); 1504 1505 /* 1506 * Handle power management nonsense. 1507 */ 1508 1509 sc->vr_save_iobase = PCI_CONF_READ(VR_PCI_LOIO); 1510 sc->vr_save_membase = PCI_CONF_READ(VR_PCI_LOMEM); 1511 sc->vr_save_irq = PCI_CONF_READ(PCI_INTERRUPT_REG); 1512 1513 /* power up chip */ 1514 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, 1515 vr_restore_state)) && error != EOPNOTSUPP) { 1516 aprint_error_dev(self, "cannot activate %d\n", error); 1517 return; 1518 } 1519 1520 /* Make sure bus mastering is enabled. */ 1521 reg = PCI_CONF_READ(PCI_COMMAND_STATUS_REG); 1522 reg |= PCI_COMMAND_MASTER_ENABLE; 1523 PCI_CONF_WRITE(PCI_COMMAND_STATUS_REG, reg); 1524 1525 /* Get revision */ 1526 sc->vr_revid = PCI_REVISION(pa->pa_class); 1527 1528 /* 1529 * Map control/status registers. 1530 */ 1531 { 1532 bus_space_tag_t iot, memt; 1533 bus_space_handle_t ioh, memh; 1534 int ioh_valid, memh_valid; 1535 pci_intr_handle_t intrhandle; 1536 const char *intrstr; 1537 1538 ioh_valid = (pci_mapreg_map(pa, VR_PCI_LOIO, 1539 PCI_MAPREG_TYPE_IO, 0, 1540 &iot, &ioh, NULL, NULL) == 0); 1541 memh_valid = (pci_mapreg_map(pa, VR_PCI_LOMEM, 1542 PCI_MAPREG_TYPE_MEM | 1543 PCI_MAPREG_MEM_TYPE_32BIT, 1544 0, &memt, &memh, NULL, NULL) == 0); 1545 #if defined(VR_USEIOSPACE) 1546 if (ioh_valid) { 1547 sc->vr_bst = iot; 1548 sc->vr_bsh = ioh; 1549 } else if (memh_valid) { 1550 sc->vr_bst = memt; 1551 sc->vr_bsh = memh; 1552 } 1553 #else 1554 if (memh_valid) { 1555 sc->vr_bst = memt; 1556 sc->vr_bsh = memh; 1557 } else if (ioh_valid) { 1558 sc->vr_bst = iot; 1559 sc->vr_bsh = ioh; 1560 } 1561 #endif 1562 else { 1563 aprint_error_dev(self, 1564 "unable to map device registers\n"); 1565 return; 1566 } 1567 1568 /* Allocate interrupt */ 1569 if (pci_intr_map(pa, &intrhandle)) { 1570 aprint_error_dev(self, "couldn't map interrupt\n"); 1571 return; 1572 } 1573 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, 1574 sizeof(intrbuf)); 1575 sc->vr_ih = pci_intr_establish_xname(pa->pa_pc, intrhandle, 1576 IPL_NET, vr_intr, sc, device_xname(self)); 1577 if (sc->vr_ih == NULL) { 1578 aprint_error_dev(self, "couldn't establish interrupt"); 1579 if (intrstr != NULL) 1580 aprint_error(" at %s", intrstr); 1581 aprint_error("\n"); 1582 return; 1583 } 1584 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 1585 } 1586 1587 /* 1588 * Windows may put the chip in suspend mode when it 1589 * shuts down. Be sure to kick it in the head to wake it 1590 * up again. 1591 * 1592 * Don't touch this register on VT3043 since it causes 1593 * kernel MCHK trap on macppc. 1594 * (Note some VT86C100A chip returns a product ID of VT3043) 1595 */ 1596 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT3043) 1597 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0 | VR_STICKHW_DS1)); 1598 1599 /* Reset the adapter. */ 1600 vr_reset(sc); 1601 1602 /* 1603 * Get station address. The way the Rhine chips work, 1604 * you're not allowed to directly access the EEPROM once 1605 * they've been programmed a special way. Consequently, 1606 * we need to read the node address from the PAR registers. 1607 * 1608 * XXXSCW: On the Rhine III, setting VR_EECSR_LOAD forces a reload 1609 * of the *whole* EEPROM, not just the MAC address. This is 1610 * pretty pointless since the chip does this automatically 1611 * at powerup/reset. 1612 * I suspect the same thing applies to the other Rhine 1613 * variants, but in the absence of a data sheet for those 1614 * (and the lack of anyone else noticing the problems this 1615 * causes) I'm going to retain the old behaviour for the 1616 * other parts. 1617 * In some cases, the chip really does startup without having 1618 * read the EEPROM (kern/34812). To handle this case, we force 1619 * a reload if we see an all-zeroes MAC address. 1620 */ 1621 for (mac = 0, i = 0; i < ETHER_ADDR_LEN; i++) 1622 mac |= (eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i)); 1623 1624 if (mac == 0 || (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT6105 && 1625 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT6102)) { 1626 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 1627 DELAY(200); 1628 for (i = 0; i < ETHER_ADDR_LEN; i++) 1629 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 1630 } 1631 1632 /* 1633 * A Rhine chip was detected. Inform the world. 1634 */ 1635 aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(eaddr)); 1636 1637 memcpy(sc->vr_enaddr, eaddr, ETHER_ADDR_LEN); 1638 1639 sc->vr_dmat = pa->pa_dmat; 1640 1641 /* 1642 * Allocate the control data structures, and create and load 1643 * the DMA map for it. 1644 */ 1645 if ((error = bus_dmamem_alloc(sc->vr_dmat, 1646 sizeof(struct vr_control_data), PAGE_SIZE, 0, &seg, 1, &rseg, 1647 0)) != 0) { 1648 aprint_error_dev(self, 1649 "unable to allocate control data, error = %d\n", error); 1650 goto fail_0; 1651 } 1652 1653 if ((error = bus_dmamem_map(sc->vr_dmat, &seg, rseg, 1654 sizeof(struct vr_control_data), (void **)&sc->vr_control_data, 1655 BUS_DMA_COHERENT)) != 0) { 1656 aprint_error_dev(self, 1657 "unable to map control data, error = %d\n", error); 1658 goto fail_1; 1659 } 1660 1661 if ((error = bus_dmamap_create(sc->vr_dmat, 1662 sizeof(struct vr_control_data), 1, 1663 sizeof(struct vr_control_data), 0, 0, 1664 &sc->vr_cddmamap)) != 0) { 1665 aprint_error_dev(self, 1666 "unable to create control data DMA map, error = %d\n", 1667 error); 1668 goto fail_2; 1669 } 1670 1671 if ((error = bus_dmamap_load(sc->vr_dmat, sc->vr_cddmamap, 1672 sc->vr_control_data, sizeof(struct vr_control_data), NULL, 1673 0)) != 0) { 1674 aprint_error_dev(self, 1675 "unable to load control data DMA map, error = %d\n", 1676 error); 1677 goto fail_3; 1678 } 1679 1680 /* 1681 * Create the transmit buffer DMA maps. 1682 */ 1683 for (i = 0; i < VR_NTXDESC; i++) { 1684 if ((error = bus_dmamap_create(sc->vr_dmat, MCLBYTES, 1685 1, MCLBYTES, 0, 0, 1686 &VR_DSTX(sc, i)->ds_dmamap)) != 0) { 1687 aprint_error_dev(self, 1688 "unable to create tx DMA map %d, error = %d\n", i, 1689 error); 1690 goto fail_4; 1691 } 1692 } 1693 1694 /* 1695 * Create the receive buffer DMA maps. 1696 */ 1697 for (i = 0; i < VR_NRXDESC; i++) { 1698 if ((error = bus_dmamap_create(sc->vr_dmat, MCLBYTES, 1, 1699 MCLBYTES, 0, 0, 1700 &VR_DSRX(sc, i)->ds_dmamap)) != 0) { 1701 aprint_error_dev(self, 1702 "unable to create rx DMA map %d, error = %d\n", i, 1703 error); 1704 goto fail_5; 1705 } 1706 VR_DSRX(sc, i)->ds_mbuf = NULL; 1707 } 1708 1709 ifp = &sc->vr_ec.ec_if; 1710 ifp->if_softc = sc; 1711 ifp->if_mtu = ETHERMTU; 1712 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1713 ifp->if_ioctl = vr_ioctl; 1714 ifp->if_start = vr_start; 1715 ifp->if_watchdog = vr_watchdog; 1716 ifp->if_init = vr_init; 1717 ifp->if_stop = vr_stop; 1718 IFQ_SET_READY(&ifp->if_snd); 1719 1720 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 1721 1722 /* 1723 * Initialize MII/media info. 1724 */ 1725 mii->mii_ifp = ifp; 1726 mii->mii_readreg = vr_mii_readreg; 1727 mii->mii_writereg = vr_mii_writereg; 1728 mii->mii_statchg = vr_mii_statchg; 1729 1730 sc->vr_ec.ec_mii = mii; 1731 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 1732 ether_mediastatus); 1733 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, 1734 MII_OFFSET_ANY, MIIF_FORCEANEG); 1735 if (LIST_FIRST(&sc->vr_mii.mii_phys) == NULL) { 1736 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 1737 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 1738 } else 1739 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1740 1741 sc->vr_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 1742 1743 /* 1744 * Call MI attach routines. 1745 */ 1746 if_attach(ifp); 1747 if_deferred_start_init(ifp, NULL); 1748 ether_ifattach(ifp, sc->vr_enaddr); 1749 1750 rnd_attach_source(&sc->rnd_source, device_xname(self), 1751 RND_TYPE_NET, RND_FLAG_DEFAULT); 1752 1753 if (pmf_device_register1(self, NULL, vr_resume, vr_shutdown)) 1754 pmf_class_network_register(self, ifp); 1755 else 1756 aprint_error_dev(self, "couldn't establish power handler\n"); 1757 1758 return; 1759 1760 fail_5: 1761 for (i = 0; i < VR_NRXDESC; i++) { 1762 if (sc->vr_rxsoft[i].ds_dmamap != NULL) 1763 bus_dmamap_destroy(sc->vr_dmat, 1764 sc->vr_rxsoft[i].ds_dmamap); 1765 } 1766 fail_4: 1767 for (i = 0; i < VR_NTXDESC; i++) { 1768 if (sc->vr_txsoft[i].ds_dmamap != NULL) 1769 bus_dmamap_destroy(sc->vr_dmat, 1770 sc->vr_txsoft[i].ds_dmamap); 1771 } 1772 bus_dmamap_unload(sc->vr_dmat, sc->vr_cddmamap); 1773 fail_3: 1774 bus_dmamap_destroy(sc->vr_dmat, sc->vr_cddmamap); 1775 fail_2: 1776 bus_dmamem_unmap(sc->vr_dmat, (void *)sc->vr_control_data, 1777 sizeof(struct vr_control_data)); 1778 fail_1: 1779 bus_dmamem_free(sc->vr_dmat, &seg, rseg); 1780 fail_0: 1781 return; 1782 } 1783 1784 static int 1785 vr_restore_state(pci_chipset_tag_t pc, pcitag_t tag, device_t self, 1786 pcireg_t state) 1787 { 1788 struct vr_softc *sc = device_private(self); 1789 int error; 1790 1791 if (state == PCI_PMCSR_STATE_D0) 1792 return 0; 1793 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0))) 1794 return error; 1795 1796 /* Restore PCI config data. */ 1797 PCI_CONF_WRITE(VR_PCI_LOIO, sc->vr_save_iobase); 1798 PCI_CONF_WRITE(VR_PCI_LOMEM, sc->vr_save_membase); 1799 PCI_CONF_WRITE(PCI_INTERRUPT_REG, sc->vr_save_irq); 1800 return 0; 1801 } 1802 1803 static bool 1804 vr_resume(device_t self, const pmf_qual_t *qual) 1805 { 1806 struct vr_softc *sc = device_private(self); 1807 1808 if (PCI_PRODUCT(sc->vr_id) != PCI_PRODUCT_VIATECH_VT3043) 1809 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0 | VR_STICKHW_DS1)); 1810 1811 return true; 1812 } 1813