1 /* $NetBSD: if_vge.c,v 1.9 2006/03/08 23:46:27 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD: src/sys/dev/vge/if_vge.c,v 1.5 2005/02/07 19:39:29 glebius Exp 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_vge.c,v 1.9 2006/03/08 23:46:27 lukem Exp $"); 39 40 /* 41 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 42 * 43 * Written by Bill Paul <wpaul@windriver.com> 44 * Senior Networking Software Engineer 45 * Wind River Systems 46 */ 47 48 /* 49 * The VIA Networking VT6122 is a 32bit, 33/66 MHz PCI device that 50 * combines a tri-speed ethernet MAC and PHY, with the following 51 * features: 52 * 53 * o Jumbo frame support up to 16K 54 * o Transmit and receive flow control 55 * o IPv4 checksum offload 56 * o VLAN tag insertion and stripping 57 * o TCP large send 58 * o 64-bit multicast hash table filter 59 * o 64 entry CAM filter 60 * o 16K RX FIFO and 48K TX FIFO memory 61 * o Interrupt moderation 62 * 63 * The VT6122 supports up to four transmit DMA queues. The descriptors 64 * in the transmit ring can address up to 7 data fragments; frames which 65 * span more than 7 data buffers must be coalesced, but in general the 66 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 67 * long. The receive descriptors address only a single buffer. 68 * 69 * There are two peculiar design issues with the VT6122. One is that 70 * receive data buffers must be aligned on a 32-bit boundary. This is 71 * not a problem where the VT6122 is used as a LOM device in x86-based 72 * systems, but on architectures that generate unaligned access traps, we 73 * have to do some copying. 74 * 75 * The other issue has to do with the way 64-bit addresses are handled. 76 * The DMA descriptors only allow you to specify 48 bits of addressing 77 * information. The remaining 16 bits are specified using one of the 78 * I/O registers. If you only have a 32-bit system, then this isn't 79 * an issue, but if you have a 64-bit system and more than 4GB of 80 * memory, you must have to make sure your network data buffers reside 81 * in the same 48-bit 'segment.' 82 * 83 * Special thanks to Ryan Fu at VIA Networking for providing documentation 84 * and sample NICs for testing. 85 */ 86 87 #include "bpfilter.h" 88 89 #include <sys/param.h> 90 #include <sys/endian.h> 91 #include <sys/systm.h> 92 #include <sys/sockio.h> 93 #include <sys/mbuf.h> 94 #include <sys/malloc.h> 95 #include <sys/kernel.h> 96 #include <sys/socket.h> 97 98 #include <net/if.h> 99 #include <net/if_arp.h> 100 #include <net/if_ether.h> 101 #include <net/if_dl.h> 102 #include <net/if_media.h> 103 104 #include <net/bpf.h> 105 106 #include <machine/bus.h> 107 108 #include <dev/mii/mii.h> 109 #include <dev/mii/miivar.h> 110 111 #include <dev/pci/pcireg.h> 112 #include <dev/pci/pcivar.h> 113 #include <dev/pci/pcidevs.h> 114 115 #include <dev/pci/if_vgereg.h> 116 #include <dev/pci/if_vgevar.h> 117 118 static int vge_probe (struct device *, struct cfdata *, void *); 119 static void vge_attach (struct device *, struct device *, void *); 120 121 static int vge_encap (struct vge_softc *, struct mbuf *, int); 122 123 static int vge_dma_map_rx_desc (struct vge_softc *, int); 124 static void vge_dma_map_tx_desc (struct vge_softc *, struct mbuf *, int, int); 125 static int vge_allocmem (struct vge_softc *); 126 static int vge_newbuf (struct vge_softc *, int, struct mbuf *); 127 static int vge_rx_list_init (struct vge_softc *); 128 static int vge_tx_list_init (struct vge_softc *); 129 #ifdef VGE_FIXUP_RX 130 static inline void vge_fixup_rx 131 (struct mbuf *); 132 #endif 133 static void vge_rxeof (struct vge_softc *); 134 static void vge_txeof (struct vge_softc *); 135 static int vge_intr (void *); 136 static void vge_tick (void *); 137 static void vge_start (struct ifnet *); 138 static int vge_ioctl (struct ifnet *, u_long, caddr_t); 139 static int vge_init (struct ifnet *); 140 static void vge_stop (struct vge_softc *); 141 static void vge_watchdog (struct ifnet *); 142 #if VGE_POWER_MANAGEMENT 143 static int vge_suspend (struct device *); 144 static int vge_resume (struct device *); 145 #endif 146 static void vge_shutdown (void *); 147 static int vge_ifmedia_upd (struct ifnet *); 148 static void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 149 150 static void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 151 static void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 152 153 static void vge_miipoll_start (struct vge_softc *); 154 static void vge_miipoll_stop (struct vge_softc *); 155 static int vge_miibus_readreg (struct device *, int, int); 156 static void vge_miibus_writereg (struct device *, int, int, int); 157 static void vge_miibus_statchg (struct device *); 158 159 static void vge_cam_clear (struct vge_softc *); 160 static int vge_cam_set (struct vge_softc *, uint8_t *); 161 static void vge_setmulti (struct vge_softc *); 162 static void vge_reset (struct vge_softc *); 163 164 #define VGE_PCI_LOIO 0x10 165 #define VGE_PCI_LOMEM 0x14 166 167 CFATTACH_DECL(vge, sizeof(struct vge_softc), 168 vge_probe, vge_attach, NULL, NULL); 169 170 /* 171 * Defragment mbuf chain contents to be as linear as possible. 172 * Returns new mbuf chain on success, NULL on failure. Old mbuf 173 * chain is always freed. 174 * XXX temporary until there would be generic function doing this. 175 */ 176 #define m_defrag vge_m_defrag 177 struct mbuf * vge_m_defrag(struct mbuf *, int); 178 179 struct mbuf * 180 vge_m_defrag(struct mbuf *mold, int flags) 181 { 182 struct mbuf *m0, *mn, *n; 183 size_t sz = mold->m_pkthdr.len; 184 185 #ifdef DIAGNOSTIC 186 if ((mold->m_flags & M_PKTHDR) == 0) 187 panic("m_defrag: not a mbuf chain header"); 188 #endif 189 190 MGETHDR(m0, flags, MT_DATA); 191 if (m0 == NULL) 192 return NULL; 193 m0->m_pkthdr.len = mold->m_pkthdr.len; 194 mn = m0; 195 196 do { 197 if (sz > MHLEN) { 198 MCLGET(mn, M_DONTWAIT); 199 if ((mn->m_flags & M_EXT) == 0) { 200 m_freem(m0); 201 return NULL; 202 } 203 } 204 205 mn->m_len = MIN(sz, MCLBYTES); 206 207 m_copydata(mold, mold->m_pkthdr.len - sz, mn->m_len, 208 mtod(mn, caddr_t)); 209 210 sz -= mn->m_len; 211 212 if (sz > 0) { 213 /* need more mbufs */ 214 MGET(n, M_NOWAIT, MT_DATA); 215 if (n == NULL) { 216 m_freem(m0); 217 return NULL; 218 } 219 220 mn->m_next = n; 221 mn = n; 222 } 223 } while (sz > 0); 224 225 return m0; 226 } 227 228 /* 229 * Read a word of data stored in the EEPROM at address 'addr.' 230 */ 231 static void 232 vge_eeprom_getword(sc, addr, dest) 233 struct vge_softc *sc; 234 int addr; 235 u_int16_t *dest; 236 { 237 register int i; 238 u_int16_t word = 0; 239 240 /* 241 * Enter EEPROM embedded programming mode. In order to 242 * access the EEPROM at all, we first have to set the 243 * EELOAD bit in the CHIPCFG2 register. 244 */ 245 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 246 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 247 248 /* Select the address of the word we want to read */ 249 CSR_WRITE_1(sc, VGE_EEADDR, addr); 250 251 /* Issue read command */ 252 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 253 254 /* Wait for the done bit to be set. */ 255 for (i = 0; i < VGE_TIMEOUT; i++) { 256 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 257 break; 258 } 259 260 if (i == VGE_TIMEOUT) { 261 printf("%s: EEPROM read timed out\n", sc->sc_dev.dv_xname); 262 *dest = 0; 263 return; 264 } 265 266 /* Read the result */ 267 word = CSR_READ_2(sc, VGE_EERDDAT); 268 269 /* Turn off EEPROM access mode. */ 270 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 271 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 272 273 *dest = word; 274 275 return; 276 } 277 278 /* 279 * Read a sequence of words from the EEPROM. 280 */ 281 static void 282 vge_read_eeprom(sc, dest, off, cnt, swap) 283 struct vge_softc *sc; 284 caddr_t dest; 285 int off; 286 int cnt; 287 int swap; 288 { 289 int i; 290 u_int16_t word = 0, *ptr; 291 292 for (i = 0; i < cnt; i++) { 293 vge_eeprom_getword(sc, off + i, &word); 294 ptr = (u_int16_t *)(dest + (i * 2)); 295 if (swap) 296 *ptr = ntohs(word); 297 else 298 *ptr = word; 299 } 300 } 301 302 static void 303 vge_miipoll_stop(sc) 304 struct vge_softc *sc; 305 { 306 int i; 307 308 CSR_WRITE_1(sc, VGE_MIICMD, 0); 309 310 for (i = 0; i < VGE_TIMEOUT; i++) { 311 DELAY(1); 312 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 313 break; 314 } 315 316 if (i == VGE_TIMEOUT) { 317 printf("%s: failed to idle MII autopoll\n", 318 sc->sc_dev.dv_xname); 319 } 320 321 return; 322 } 323 324 static void 325 vge_miipoll_start(sc) 326 struct vge_softc *sc; 327 { 328 int i; 329 330 /* First, make sure we're idle. */ 331 332 CSR_WRITE_1(sc, VGE_MIICMD, 0); 333 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 334 335 for (i = 0; i < VGE_TIMEOUT; i++) { 336 DELAY(1); 337 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 338 break; 339 } 340 341 if (i == VGE_TIMEOUT) { 342 printf("%s: failed to idle MII autopoll\n", 343 sc->sc_dev.dv_xname); 344 return; 345 } 346 347 /* Now enable auto poll mode. */ 348 349 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 350 351 /* And make sure it started. */ 352 353 for (i = 0; i < VGE_TIMEOUT; i++) { 354 DELAY(1); 355 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 356 break; 357 } 358 359 if (i == VGE_TIMEOUT) { 360 printf("%s: failed to start MII autopoll\n", 361 sc->sc_dev.dv_xname); 362 } 363 } 364 365 static int 366 vge_miibus_readreg(dev, phy, reg) 367 struct device *dev; 368 int phy, reg; 369 { 370 struct vge_softc *sc = (struct vge_softc *)dev; 371 int i; 372 u_int16_t rval = 0; 373 374 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 375 return(0); 376 377 VGE_LOCK(sc); 378 vge_miipoll_stop(sc); 379 380 /* Specify the register we want to read. */ 381 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 382 383 /* Issue read command. */ 384 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 385 386 /* Wait for the read command bit to self-clear. */ 387 for (i = 0; i < VGE_TIMEOUT; i++) { 388 DELAY(1); 389 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 390 break; 391 } 392 393 if (i == VGE_TIMEOUT) 394 printf("%s: MII read timed out\n", sc->sc_dev.dv_xname); 395 else 396 rval = CSR_READ_2(sc, VGE_MIIDATA); 397 398 vge_miipoll_start(sc); 399 VGE_UNLOCK(sc); 400 401 return (rval); 402 } 403 404 static void 405 vge_miibus_writereg(dev, phy, reg, data) 406 struct device *dev; 407 int phy, reg, data; 408 { 409 struct vge_softc *sc = (struct vge_softc *)dev; 410 int i; 411 412 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 413 return; 414 415 VGE_LOCK(sc); 416 vge_miipoll_stop(sc); 417 418 /* Specify the register we want to write. */ 419 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 420 421 /* Specify the data we want to write. */ 422 CSR_WRITE_2(sc, VGE_MIIDATA, data); 423 424 /* Issue write command. */ 425 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 426 427 /* Wait for the write command bit to self-clear. */ 428 for (i = 0; i < VGE_TIMEOUT; i++) { 429 DELAY(1); 430 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 431 break; 432 } 433 434 if (i == VGE_TIMEOUT) { 435 printf("%s: MII write timed out\n", sc->sc_dev.dv_xname); 436 } 437 438 vge_miipoll_start(sc); 439 VGE_UNLOCK(sc); 440 } 441 442 static void 443 vge_cam_clear(sc) 444 struct vge_softc *sc; 445 { 446 int i; 447 448 /* 449 * Turn off all the mask bits. This tells the chip 450 * that none of the entries in the CAM filter are valid. 451 * desired entries will be enabled as we fill the filter in. 452 */ 453 454 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 455 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 456 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 457 for (i = 0; i < 8; i++) 458 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 459 460 /* Clear the VLAN filter too. */ 461 462 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 463 for (i = 0; i < 8; i++) 464 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 465 466 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 467 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 468 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 469 470 sc->vge_camidx = 0; 471 472 return; 473 } 474 475 static int 476 vge_cam_set(sc, addr) 477 struct vge_softc *sc; 478 uint8_t *addr; 479 { 480 int i, error = 0; 481 482 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 483 return(ENOSPC); 484 485 /* Select the CAM data page. */ 486 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 487 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 488 489 /* Set the filter entry we want to update and enable writing. */ 490 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 491 492 /* Write the address to the CAM registers */ 493 for (i = 0; i < ETHER_ADDR_LEN; i++) 494 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 495 496 /* Issue a write command. */ 497 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 498 499 /* Wake for it to clear. */ 500 for (i = 0; i < VGE_TIMEOUT; i++) { 501 DELAY(1); 502 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 503 break; 504 } 505 506 if (i == VGE_TIMEOUT) { 507 printf("%s: setting CAM filter failed\n", sc->sc_dev.dv_xname); 508 error = EIO; 509 goto fail; 510 } 511 512 /* Select the CAM mask page. */ 513 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 514 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 515 516 /* Set the mask bit that enables this filter. */ 517 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 518 1<<(sc->vge_camidx & 7)); 519 520 sc->vge_camidx++; 521 522 fail: 523 /* Turn off access to CAM. */ 524 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 525 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 526 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 527 528 return (error); 529 } 530 531 /* 532 * Program the multicast filter. We use the 64-entry CAM filter 533 * for perfect filtering. If there's more than 64 multicast addresses, 534 * we use the hash filter insted. 535 */ 536 static void 537 vge_setmulti(sc) 538 struct vge_softc *sc; 539 { 540 struct ifnet *ifp; 541 int error = 0; 542 u_int32_t h, hashes[2] = { 0, 0 }; 543 struct ether_multi *enm; 544 struct ether_multistep step; 545 546 ifp = &sc->sc_ethercom.ec_if; 547 548 /* First, zot all the multicast entries. */ 549 vge_cam_clear(sc); 550 CSR_WRITE_4(sc, VGE_MAR0, 0); 551 CSR_WRITE_4(sc, VGE_MAR1, 0); 552 ifp->if_flags &= ~IFF_ALLMULTI; 553 554 /* 555 * If the user wants allmulti or promisc mode, enable reception 556 * of all multicast frames. 557 */ 558 if (ifp->if_flags & IFF_PROMISC) { 559 allmulti: 560 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 561 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 562 ifp->if_flags |= IFF_ALLMULTI; 563 return; 564 } 565 566 /* Now program new ones */ 567 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 568 while(enm != NULL) { 569 /* 570 * If multicast range, fall back to ALLMULTI. 571 */ 572 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 573 ETHER_ADDR_LEN) != 0) 574 goto allmulti; 575 576 error = vge_cam_set(sc, enm->enm_addrlo); 577 if (error) 578 break; 579 580 ETHER_NEXT_MULTI(step, enm); 581 } 582 583 /* If there were too many addresses, use the hash filter. */ 584 if (error) { 585 vge_cam_clear(sc); 586 587 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 588 while(enm != NULL) { 589 /* 590 * If multicast range, fall back to ALLMULTI. 591 */ 592 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 593 ETHER_ADDR_LEN) != 0) 594 goto allmulti; 595 596 h = ether_crc32_be(enm->enm_addrlo, 597 ETHER_ADDR_LEN) >> 26; 598 hashes[h >> 5] |= 1 << (h & 0x1f); 599 600 ETHER_NEXT_MULTI(step, enm); 601 } 602 603 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 604 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 605 } 606 607 return; 608 } 609 610 static void 611 vge_reset(sc) 612 struct vge_softc *sc; 613 { 614 register int i; 615 616 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 617 618 for (i = 0; i < VGE_TIMEOUT; i++) { 619 DELAY(5); 620 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 621 break; 622 } 623 624 if (i == VGE_TIMEOUT) { 625 printf("%s: soft reset timed out", sc->sc_dev.dv_xname); 626 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 627 DELAY(2000); 628 } 629 630 DELAY(5000); 631 632 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 633 634 for (i = 0; i < VGE_TIMEOUT; i++) { 635 DELAY(5); 636 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 637 break; 638 } 639 640 if (i == VGE_TIMEOUT) { 641 printf("%s: EEPROM reload timed out\n", sc->sc_dev.dv_xname); 642 return; 643 } 644 645 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 646 647 return; 648 } 649 650 /* 651 * Probe for a VIA gigabit chip. Check the PCI vendor and device 652 * IDs against our list and return a device name if we find a match. 653 */ 654 static int 655 vge_probe(struct device *parent, struct cfdata *match, void *aux) 656 { 657 struct pci_attach_args *pa = aux; 658 659 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH 660 && PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_VIATECH_VT612X) 661 return 1; 662 663 return (0); 664 } 665 666 static int 667 vge_dma_map_rx_desc(sc, idx) 668 struct vge_softc *sc; 669 int idx; 670 { 671 struct vge_rx_desc *d = NULL; 672 bus_dma_segment_t *segs; 673 674 /* 675 * Map the segment array into descriptors. 676 */ 677 678 d = &sc->vge_ldata.vge_rx_list[idx]; 679 680 /* If this descriptor is still owned by the chip, bail. */ 681 682 if (le32toh(d->vge_sts) & VGE_RDSTS_OWN) { 683 printf("%s: tried to map busy descriptor\n", 684 sc->sc_dev.dv_xname); 685 return (EBUSY); 686 } 687 688 segs = sc->vge_ldata.vge_rx_dmamap[idx]->dm_segs; 689 690 d->vge_buflen = htole16(VGE_BUFLEN(segs[0].ds_len) | VGE_RXDESC_I); 691 d->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 692 d->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 693 d->vge_sts = 0; 694 d->vge_ctl = 0; 695 696 return (0); 697 } 698 699 static void 700 vge_dma_map_tx_desc(sc, m0, idx, flags) 701 struct vge_softc *sc; 702 struct mbuf *m0; 703 int idx, flags; 704 { 705 struct vge_tx_desc *d = &sc->vge_ldata.vge_tx_list[idx]; 706 struct vge_tx_frag *f; 707 int i = 0; 708 bus_dma_segment_t *segs; 709 size_t sz; 710 bus_dmamap_t map = sc->vge_ldata.vge_tx_dmamap[idx]; 711 712 /* Map the segment array into descriptors. */ 713 714 segs = map->dm_segs; 715 for (i = 0; i < map->dm_nsegs; i++) { 716 f = &d->vge_frag[i]; 717 f->vge_buflen = htole16(VGE_BUFLEN(segs[i].ds_len)); 718 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[i].ds_addr)); 719 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[i].ds_addr) & 0xFFFF); 720 } 721 722 /* Argh. This chip does not autopad short frames */ 723 724 sz = m0->m_pkthdr.len; 725 if (m0->m_pkthdr.len < VGE_MIN_FRAMELEN) { 726 f = &d->vge_frag[i]; 727 f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - sz)); 728 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 729 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 730 sz = VGE_MIN_FRAMELEN; 731 i++; 732 } 733 734 /* 735 * When telling the chip how many segments there are, we 736 * must use nsegs + 1 instead of just nsegs. Darned if I 737 * know why. 738 */ 739 i++; 740 741 d->vge_sts = sz << 16; 742 d->vge_ctl = flags|(i << 28)|VGE_TD_LS_NORM; 743 744 if (sz > ETHERMTU + ETHER_HDR_LEN) 745 d->vge_ctl |= VGE_TDCTL_JUMBO; 746 } 747 748 static int 749 vge_allocmem(sc) 750 struct vge_softc *sc; 751 { 752 int error; 753 int nseg; 754 int i; 755 bus_dma_segment_t seg; 756 757 /* 758 * Allocate map for TX descriptor list. 759 */ 760 error = bus_dmamap_create(sc->vge_dmat, 761 round_page(VGE_TX_LIST_SZ), 1, round_page(VGE_TX_LIST_SZ), 762 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, 763 &sc->vge_ldata.vge_tx_list_map); 764 if (error) { 765 printf("%s: could not allocate TX dma list map\n", 766 sc->sc_dev.dv_xname); 767 return (ENOMEM); 768 } 769 770 /* 771 * Allocate memory for TX descriptor list. 772 */ 773 774 error = bus_dmamem_alloc(sc->vge_dmat, VGE_TX_LIST_SZ, VGE_RING_ALIGN, 775 0, &seg, 1, &nseg, BUS_DMA_NOWAIT); 776 if (error) { 777 printf("%s: could not allocate TX ring dma memory\n", 778 sc->sc_dev.dv_xname); 779 return (ENOMEM); 780 } 781 782 /* Map the memory to kernel VA space */ 783 784 error = bus_dmamem_map(sc->vge_dmat, &seg, nseg, seg.ds_len, 785 (caddr_t *) &sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT); 786 if (error) { 787 printf("%s: could not map TX ring dma memory\n", 788 sc->sc_dev.dv_xname); 789 return (ENOMEM); 790 } 791 792 /* Load the map for the TX ring. */ 793 error = bus_dmamap_load(sc->vge_dmat, sc->vge_ldata.vge_tx_list_map, 794 sc->vge_ldata.vge_tx_list, seg.ds_len, NULL, BUS_DMA_NOWAIT); 795 if (error) { 796 printf("%s: could not load TX ring dma memory\n", 797 sc->sc_dev.dv_xname); 798 return (ENOMEM); 799 } 800 801 sc->vge_ldata.vge_tx_list_addr = 802 sc->vge_ldata.vge_tx_list_map->dm_segs[0].ds_addr; 803 804 /* Create DMA maps for TX buffers */ 805 806 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 807 error = bus_dmamap_create(sc->vge_dmat, VGE_TX_MAXLEN, 808 VGE_TX_FRAGS, VGE_TX_MAXLEN, 0, 809 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW, 810 &sc->vge_ldata.vge_tx_dmamap[i]); 811 if (error) { 812 printf("%s: can't create DMA map for TX\n", 813 sc->sc_dev.dv_xname); 814 return (ENOMEM); 815 } 816 } 817 818 /* 819 * Allocate map for RX descriptor list. 820 */ 821 error = bus_dmamap_create(sc->vge_dmat, 822 round_page(VGE_RX_LIST_SZ), 1, round_page(VGE_RX_LIST_SZ), 823 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, 824 &sc->vge_ldata.vge_rx_list_map); 825 if (error) { 826 printf("%s: could not allocate RX dma list map\n", 827 sc->sc_dev.dv_xname); 828 return (ENOMEM); 829 } 830 831 /* Allocate DMA'able memory for the RX ring */ 832 833 error = bus_dmamem_alloc(sc->vge_dmat, VGE_RX_LIST_SZ, VGE_RING_ALIGN, 834 0, &seg, 1, &nseg, BUS_DMA_NOWAIT); 835 if (error) 836 return (ENOMEM); 837 838 /* Map the memory to kernel VA space */ 839 840 error = bus_dmamem_map(sc->vge_dmat, &seg, nseg, seg.ds_len, 841 (caddr_t *) &sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT); 842 if (error) 843 return (ENOMEM); 844 845 /* Load the map for the RX ring. */ 846 error = bus_dmamap_load(sc->vge_dmat, sc->vge_ldata.vge_rx_list_map, 847 sc->vge_ldata.vge_rx_list, seg.ds_len, NULL, BUS_DMA_NOWAIT); 848 if (error) { 849 printf("%s: could not load RX ring dma memory\n", 850 sc->sc_dev.dv_xname); 851 return (ENOMEM); 852 } 853 854 sc->vge_ldata.vge_rx_list_addr = 855 sc->vge_ldata.vge_rx_list_map->dm_segs[0].ds_addr; 856 857 /* Create DMA maps for RX buffers */ 858 859 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 860 error = bus_dmamap_create(sc->vge_dmat, MCLBYTES, 861 1, MCLBYTES, 0, BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW, 862 &sc->vge_ldata.vge_rx_dmamap[i]); 863 if (error) { 864 printf("%s: can't create DMA map for RX\n", 865 sc->sc_dev.dv_xname); 866 return (ENOMEM); 867 } 868 } 869 870 return (0); 871 } 872 873 /* 874 * Attach the interface. Allocate softc structures, do ifmedia 875 * setup and ethernet/BPF attach. 876 */ 877 static void 878 vge_attach(struct device *parent, struct device *self, void *aux) 879 { 880 u_char eaddr[ETHER_ADDR_LEN]; 881 struct vge_softc *sc = (struct vge_softc *)self; 882 struct ifnet *ifp; 883 struct pci_attach_args *pa = aux; 884 pci_chipset_tag_t pc = pa->pa_pc; 885 const char *intrstr; 886 pci_intr_handle_t ih; 887 888 aprint_normal(": VIA VT612X Gigabit Ethernet (rev. %#x)\n", 889 PCI_REVISION(pa->pa_class)); 890 891 /* Make sure bus-mastering is enabled */ 892 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 893 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 894 PCI_COMMAND_MASTER_ENABLE); 895 896 /* 897 * Map control/status registers. 898 */ 899 if (0 != pci_mapreg_map(pa, VGE_PCI_LOMEM, 900 PCI_MAPREG_TYPE_MEM, 0, 901 &sc->vge_btag, &sc->vge_bhandle, NULL, NULL)) { 902 aprint_error("%s: couldn't map memory\n", 903 sc->sc_dev.dv_xname); 904 return; 905 } 906 907 /* 908 * Map and establish our interrupt. 909 */ 910 if (pci_intr_map(pa, &ih)) { 911 aprint_error("%s: unable to map interrupt\n", 912 sc->sc_dev.dv_xname); 913 return; 914 } 915 intrstr = pci_intr_string(pc, ih); 916 sc->vge_intrhand = pci_intr_establish(pc, ih, IPL_NET, vge_intr, sc); 917 if (sc->vge_intrhand == NULL) { 918 printf("%s: unable to establish interrupt", 919 sc->sc_dev.dv_xname); 920 if (intrstr != NULL) 921 printf(" at %s", intrstr); 922 printf("\n"); 923 return; 924 } 925 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 926 927 /* Reset the adapter. */ 928 vge_reset(sc); 929 930 /* 931 * Get station address from the EEPROM. 932 */ 933 vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0); 934 bcopy(eaddr, (char *)&sc->vge_eaddr, ETHER_ADDR_LEN); 935 936 printf("%s: Ethernet address: %s\n", sc->sc_dev.dv_xname, 937 ether_sprintf(eaddr)); 938 939 /* 940 * Use the 32bit tag. Hardware supports 48bit physical addresses, 941 * but we don't use that for now. 942 */ 943 sc->vge_dmat = pa->pa_dmat; 944 945 if (vge_allocmem(sc)) 946 return; 947 948 ifp = &sc->sc_ethercom.ec_if; 949 ifp->if_softc = sc; 950 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 951 ifp->if_mtu = ETHERMTU; 952 ifp->if_baudrate = IF_Gbps(1); 953 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 954 ifp->if_ioctl = vge_ioctl; 955 ifp->if_start = vge_start; 956 957 /* 958 * We can support 802.1Q VLAN-sized frames and jumbo 959 * Ethernet frames. 960 */ 961 sc->sc_ethercom.ec_capabilities |= 962 ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU | 963 ETHERCAP_VLAN_HWTAGGING; 964 965 /* 966 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 967 */ 968 ifp->if_capabilities |= 969 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 970 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 971 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 972 973 #ifdef DEVICE_POLLING 974 #ifdef IFCAP_POLLING 975 ifp->if_capabilities |= IFCAP_POLLING; 976 #endif 977 #endif 978 ifp->if_watchdog = vge_watchdog; 979 ifp->if_init = vge_init; 980 IFQ_SET_MAXLEN(&ifp->if_snd, max(VGE_IFQ_MAXLEN, IFQ_MAXLEN)); 981 982 /* 983 * Initialize our media structures and probe the MII. 984 */ 985 sc->sc_mii.mii_ifp = ifp; 986 sc->sc_mii.mii_readreg = vge_miibus_readreg; 987 sc->sc_mii.mii_writereg = vge_miibus_writereg; 988 sc->sc_mii.mii_statchg = vge_miibus_statchg; 989 ifmedia_init(&sc->sc_mii.mii_media, 0, vge_ifmedia_upd, 990 vge_ifmedia_sts); 991 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 992 MII_OFFSET_ANY, MIIF_DOPAUSE); 993 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 994 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 995 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 996 } else 997 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 998 999 /* 1000 * Attach the interface. 1001 */ 1002 if_attach(ifp); 1003 ether_ifattach(ifp, eaddr); 1004 1005 callout_init(&sc->vge_timeout); 1006 callout_setfunc(&sc->vge_timeout, vge_tick, sc); 1007 1008 /* 1009 * Make sure the interface is shutdown during reboot. 1010 */ 1011 if (shutdownhook_establish(vge_shutdown, sc) == NULL) { 1012 printf("%s: WARNING: unable to establish shutdown hook\n", 1013 sc->sc_dev.dv_xname); 1014 } 1015 } 1016 1017 static int 1018 vge_newbuf(sc, idx, m) 1019 struct vge_softc *sc; 1020 int idx; 1021 struct mbuf *m; 1022 { 1023 struct mbuf *n = NULL; 1024 int i, error; 1025 1026 if (m == NULL) { 1027 n = m_gethdr(M_DONTWAIT, MT_DATA); 1028 if (n == NULL) 1029 return (ENOBUFS); 1030 1031 m_clget(n, M_DONTWAIT); 1032 if ((n->m_flags & M_EXT) == 0) { 1033 m_freem(n); 1034 return (ENOBUFS); 1035 } 1036 1037 m = n; 1038 } else 1039 m->m_data = m->m_ext.ext_buf; 1040 1041 1042 #ifdef VGE_FIXUP_RX 1043 /* 1044 * This is part of an evil trick to deal with non-x86 platforms. 1045 * The VIA chip requires RX buffers to be aligned on 32-bit 1046 * boundaries, but that will hose non-x86 machines. To get around 1047 * this, we leave some empty space at the start of each buffer 1048 * and for non-x86 hosts, we copy the buffer back two bytes 1049 * to achieve word alignment. This is slightly more efficient 1050 * than allocating a new buffer, copying the contents, and 1051 * discarding the old buffer. 1052 */ 1053 m->m_len = m->m_pkthdr.len = MCLBYTES - VGE_ETHER_ALIGN; 1054 m_adj(m, VGE_ETHER_ALIGN); 1055 #else 1056 m->m_len = m->m_pkthdr.len = MCLBYTES; 1057 #endif 1058 1059 error = bus_dmamap_load_mbuf(sc->vge_dmat, 1060 sc->vge_ldata.vge_rx_dmamap[idx], m, BUS_DMA_NOWAIT); 1061 if (error || vge_dma_map_rx_desc(sc, idx)) { 1062 if (n != NULL) 1063 m_freem(n); 1064 return (ENOMEM); 1065 } 1066 1067 /* 1068 * Note: the manual fails to document the fact that for 1069 * proper opration, the driver needs to replentish the RX 1070 * DMA ring 4 descriptors at a time (rather than one at a 1071 * time, like most chips). We can allocate the new buffers 1072 * but we should not set the OWN bits until we're ready 1073 * to hand back 4 of them in one shot. 1074 */ 1075 1076 #define VGE_RXCHUNK 4 1077 sc->vge_rx_consumed++; 1078 if (sc->vge_rx_consumed == VGE_RXCHUNK) { 1079 for (i = idx; i != idx - sc->vge_rx_consumed; i--) 1080 sc->vge_ldata.vge_rx_list[i].vge_sts |= 1081 htole32(VGE_RDSTS_OWN); 1082 sc->vge_rx_consumed = 0; 1083 } 1084 1085 sc->vge_ldata.vge_rx_mbuf[idx] = m; 1086 1087 bus_dmamap_sync(sc->vge_dmat, 1088 sc->vge_ldata.vge_rx_dmamap[idx], 1089 0, sc->vge_ldata.vge_rx_dmamap[idx]->dm_mapsize, 1090 BUS_DMASYNC_PREREAD); 1091 1092 return (0); 1093 } 1094 1095 static int 1096 vge_tx_list_init(sc) 1097 struct vge_softc *sc; 1098 { 1099 bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); 1100 bzero ((char *)&sc->vge_ldata.vge_tx_mbuf, 1101 (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); 1102 1103 bus_dmamap_sync(sc->vge_dmat, 1104 sc->vge_ldata.vge_tx_list_map, 1105 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1106 BUS_DMASYNC_PREWRITE); 1107 1108 sc->vge_ldata.vge_tx_prodidx = 0; 1109 sc->vge_ldata.vge_tx_considx = 0; 1110 sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; 1111 1112 return (0); 1113 } 1114 1115 static int 1116 vge_rx_list_init(sc) 1117 struct vge_softc *sc; 1118 { 1119 int i; 1120 1121 bzero ((char *)sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); 1122 bzero ((char *)&sc->vge_ldata.vge_rx_mbuf, 1123 (VGE_RX_DESC_CNT * sizeof(struct mbuf *))); 1124 1125 sc->vge_rx_consumed = 0; 1126 1127 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1128 if (vge_newbuf(sc, i, NULL) == ENOBUFS) 1129 return (ENOBUFS); 1130 } 1131 1132 /* Flush the RX descriptors */ 1133 1134 bus_dmamap_sync(sc->vge_dmat, 1135 sc->vge_ldata.vge_rx_list_map, 1136 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 1137 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1138 1139 sc->vge_ldata.vge_rx_prodidx = 0; 1140 sc->vge_rx_consumed = 0; 1141 sc->vge_head = sc->vge_tail = NULL; 1142 1143 return (0); 1144 } 1145 1146 #ifdef VGE_FIXUP_RX 1147 static inline void 1148 vge_fixup_rx(m) 1149 struct mbuf *m; 1150 { 1151 int i; 1152 uint16_t *src, *dst; 1153 1154 src = mtod(m, uint16_t *); 1155 dst = src - 1; 1156 1157 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1158 *dst++ = *src++; 1159 1160 m->m_data -= ETHER_ALIGN; 1161 1162 return; 1163 } 1164 #endif 1165 1166 /* 1167 * RX handler. We support the reception of jumbo frames that have 1168 * been fragmented across multiple 2K mbuf cluster buffers. 1169 */ 1170 static void 1171 vge_rxeof(sc) 1172 struct vge_softc *sc; 1173 { 1174 struct mbuf *m; 1175 struct ifnet *ifp; 1176 int i, total_len; 1177 int lim = 0; 1178 struct vge_rx_desc *cur_rx; 1179 u_int32_t rxstat, rxctl; 1180 1181 VGE_LOCK_ASSERT(sc); 1182 ifp = &sc->sc_ethercom.ec_if; 1183 i = sc->vge_ldata.vge_rx_prodidx; 1184 1185 /* Invalidate the descriptor memory */ 1186 1187 bus_dmamap_sync(sc->vge_dmat, 1188 sc->vge_ldata.vge_rx_list_map, 1189 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 1190 BUS_DMASYNC_POSTREAD); 1191 1192 while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { 1193 1194 #ifdef DEVICE_POLLING 1195 if (ifp->if_flags & IFF_POLLING) { 1196 if (sc->rxcycles <= 0) 1197 break; 1198 sc->rxcycles--; 1199 } 1200 #endif /* DEVICE_POLLING */ 1201 1202 cur_rx = &sc->vge_ldata.vge_rx_list[i]; 1203 m = sc->vge_ldata.vge_rx_mbuf[i]; 1204 total_len = VGE_RXBYTES(cur_rx); 1205 rxstat = le32toh(cur_rx->vge_sts); 1206 rxctl = le32toh(cur_rx->vge_ctl); 1207 1208 /* Invalidate the RX mbuf and unload its map */ 1209 1210 bus_dmamap_sync(sc->vge_dmat, 1211 sc->vge_ldata.vge_rx_dmamap[i], 1212 0, sc->vge_ldata.vge_rx_dmamap[i]->dm_mapsize, 1213 BUS_DMASYNC_POSTWRITE); 1214 bus_dmamap_unload(sc->vge_dmat, 1215 sc->vge_ldata.vge_rx_dmamap[i]); 1216 1217 /* 1218 * If the 'start of frame' bit is set, this indicates 1219 * either the first fragment in a multi-fragment receive, 1220 * or an intermediate fragment. Either way, we want to 1221 * accumulate the buffers. 1222 */ 1223 if (rxstat & VGE_RXPKT_SOF) { 1224 m->m_len = MCLBYTES - VGE_ETHER_ALIGN; 1225 if (sc->vge_head == NULL) 1226 sc->vge_head = sc->vge_tail = m; 1227 else { 1228 m->m_flags &= ~M_PKTHDR; 1229 sc->vge_tail->m_next = m; 1230 sc->vge_tail = m; 1231 } 1232 vge_newbuf(sc, i, NULL); 1233 VGE_RX_DESC_INC(i); 1234 continue; 1235 } 1236 1237 /* 1238 * Bad/error frames will have the RXOK bit cleared. 1239 * However, there's one error case we want to allow: 1240 * if a VLAN tagged frame arrives and the chip can't 1241 * match it against the CAM filter, it considers this 1242 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1243 * We don't want to drop the frame though: our VLAN 1244 * filtering is done in software. 1245 */ 1246 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1247 && !(rxstat & VGE_RDSTS_CSUMERR)) { 1248 ifp->if_ierrors++; 1249 /* 1250 * If this is part of a multi-fragment packet, 1251 * discard all the pieces. 1252 */ 1253 if (sc->vge_head != NULL) { 1254 m_freem(sc->vge_head); 1255 sc->vge_head = sc->vge_tail = NULL; 1256 } 1257 vge_newbuf(sc, i, m); 1258 VGE_RX_DESC_INC(i); 1259 continue; 1260 } 1261 1262 /* 1263 * If allocating a replacement mbuf fails, 1264 * reload the current one. 1265 */ 1266 1267 if (vge_newbuf(sc, i, NULL)) { 1268 ifp->if_ierrors++; 1269 if (sc->vge_head != NULL) { 1270 m_freem(sc->vge_head); 1271 sc->vge_head = sc->vge_tail = NULL; 1272 } 1273 vge_newbuf(sc, i, m); 1274 VGE_RX_DESC_INC(i); 1275 continue; 1276 } 1277 1278 VGE_RX_DESC_INC(i); 1279 1280 if (sc->vge_head != NULL) { 1281 m->m_len = total_len % (MCLBYTES - VGE_ETHER_ALIGN); 1282 /* 1283 * Special case: if there's 4 bytes or less 1284 * in this buffer, the mbuf can be discarded: 1285 * the last 4 bytes is the CRC, which we don't 1286 * care about anyway. 1287 */ 1288 if (m->m_len <= ETHER_CRC_LEN) { 1289 sc->vge_tail->m_len -= 1290 (ETHER_CRC_LEN - m->m_len); 1291 m_freem(m); 1292 } else { 1293 m->m_len -= ETHER_CRC_LEN; 1294 m->m_flags &= ~M_PKTHDR; 1295 sc->vge_tail->m_next = m; 1296 } 1297 m = sc->vge_head; 1298 sc->vge_head = sc->vge_tail = NULL; 1299 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1300 } else 1301 m->m_pkthdr.len = m->m_len = 1302 (total_len - ETHER_CRC_LEN); 1303 1304 #ifdef VGE_FIXUP_RX 1305 vge_fixup_rx(m); 1306 #endif 1307 ifp->if_ipackets++; 1308 m->m_pkthdr.rcvif = ifp; 1309 1310 /* Do RX checksumming if enabled */ 1311 if (ifp->if_csum_flags_rx & M_CSUM_IPv4) { 1312 1313 /* Check IP header checksum */ 1314 if (rxctl & VGE_RDCTL_IPPKT) 1315 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1316 if ((rxctl & VGE_RDCTL_IPCSUMOK) == 0) 1317 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1318 } 1319 1320 if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) { 1321 /* Check UDP checksum */ 1322 if (rxctl & VGE_RDCTL_TCPPKT) 1323 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1324 1325 if ((rxctl & VGE_RDCTL_PROTOCSUMOK) == 0) 1326 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1327 } 1328 1329 if (ifp->if_csum_flags_rx & M_CSUM_UDPv4) { 1330 /* Check UDP checksum */ 1331 if (rxctl & VGE_RDCTL_UDPPKT) 1332 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1333 1334 if ((rxctl & VGE_RDCTL_PROTOCSUMOK) == 0) 1335 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1336 } 1337 1338 if (rxstat & VGE_RDSTS_VTAG) 1339 VLAN_INPUT_TAG(ifp, m, 1340 ntohs((rxctl & VGE_RDCTL_VLANID)), continue); 1341 1342 #if NBPFILTER > 0 1343 /* 1344 * Handle BPF listeners. 1345 */ 1346 if (ifp->if_bpf) 1347 bpf_mtap(ifp->if_bpf, m); 1348 #endif 1349 1350 VGE_UNLOCK(sc); 1351 (*ifp->if_input)(ifp, m); 1352 VGE_LOCK(sc); 1353 1354 lim++; 1355 if (lim == VGE_RX_DESC_CNT) 1356 break; 1357 1358 } 1359 1360 /* Flush the RX DMA ring */ 1361 1362 bus_dmamap_sync(sc->vge_dmat, 1363 sc->vge_ldata.vge_rx_list_map, 1364 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 1365 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1366 1367 sc->vge_ldata.vge_rx_prodidx = i; 1368 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1369 1370 1371 return; 1372 } 1373 1374 static void 1375 vge_txeof(sc) 1376 struct vge_softc *sc; 1377 { 1378 struct ifnet *ifp; 1379 u_int32_t txstat; 1380 int idx; 1381 1382 ifp = &sc->sc_ethercom.ec_if; 1383 idx = sc->vge_ldata.vge_tx_considx; 1384 1385 /* Invalidate the TX descriptor list */ 1386 1387 bus_dmamap_sync(sc->vge_dmat, 1388 sc->vge_ldata.vge_tx_list_map, 1389 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1390 BUS_DMASYNC_POSTREAD); 1391 1392 while (idx != sc->vge_ldata.vge_tx_prodidx) { 1393 1394 txstat = le32toh(sc->vge_ldata.vge_tx_list[idx].vge_sts); 1395 if (txstat & VGE_TDSTS_OWN) 1396 break; 1397 1398 m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); 1399 sc->vge_ldata.vge_tx_mbuf[idx] = NULL; 1400 bus_dmamap_unload(sc->vge_dmat, 1401 sc->vge_ldata.vge_tx_dmamap[idx]); 1402 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1403 ifp->if_collisions++; 1404 if (txstat & VGE_TDSTS_TXERR) 1405 ifp->if_oerrors++; 1406 else 1407 ifp->if_opackets++; 1408 1409 sc->vge_ldata.vge_tx_free++; 1410 VGE_TX_DESC_INC(idx); 1411 } 1412 1413 /* No changes made to the TX ring, so no flush needed */ 1414 1415 if (idx != sc->vge_ldata.vge_tx_considx) { 1416 sc->vge_ldata.vge_tx_considx = idx; 1417 ifp->if_flags &= ~IFF_OACTIVE; 1418 ifp->if_timer = 0; 1419 } 1420 1421 /* 1422 * If not all descriptors have been released reaped yet, 1423 * reload the timer so that we will eventually get another 1424 * interrupt that will cause us to re-enter this routine. 1425 * This is done in case the transmitter has gone idle. 1426 */ 1427 if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) { 1428 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1429 } 1430 1431 return; 1432 } 1433 1434 static void 1435 vge_tick(xsc) 1436 void *xsc; 1437 { 1438 struct vge_softc *sc = xsc; 1439 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1440 struct mii_data *mii = &sc->sc_mii; 1441 int s; 1442 1443 s = splnet(); 1444 1445 VGE_LOCK(sc); 1446 1447 callout_schedule(&sc->vge_timeout, hz); 1448 1449 mii_tick(mii); 1450 if (sc->vge_link) { 1451 if (!(mii->mii_media_status & IFM_ACTIVE)) 1452 sc->vge_link = 0; 1453 } else { 1454 if (mii->mii_media_status & IFM_ACTIVE && 1455 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1456 sc->vge_link = 1; 1457 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1458 vge_start(ifp); 1459 } 1460 } 1461 1462 VGE_UNLOCK(sc); 1463 1464 splx(s); 1465 } 1466 1467 #ifdef DEVICE_POLLING 1468 static void 1469 vge_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1470 { 1471 struct vge_softc *sc = ifp->if_softc; 1472 1473 VGE_LOCK(sc); 1474 #ifdef IFCAP_POLLING 1475 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1476 ether_poll_deregister(ifp); 1477 cmd = POLL_DEREGISTER; 1478 } 1479 #endif 1480 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1481 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1482 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 1483 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1484 goto done; 1485 } 1486 1487 sc->rxcycles = count; 1488 vge_rxeof(sc); 1489 vge_txeof(sc); 1490 1491 #if __FreeBSD_version < 502114 1492 if (ifp->if_snd.ifq_head != NULL) 1493 #else 1494 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1495 #endif 1496 taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); 1497 1498 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1499 u_int32_t status; 1500 status = CSR_READ_4(sc, VGE_ISR); 1501 if (status == 0xFFFFFFFF) 1502 goto done; 1503 if (status) 1504 CSR_WRITE_4(sc, VGE_ISR, status); 1505 1506 /* 1507 * XXX check behaviour on receiver stalls. 1508 */ 1509 1510 if (status & VGE_ISR_TXDMA_STALL || 1511 status & VGE_ISR_RXDMA_STALL) 1512 vge_init(sc); 1513 1514 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1515 vge_rxeof(sc); 1516 ifp->if_ierrors++; 1517 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1518 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1519 } 1520 } 1521 done: 1522 VGE_UNLOCK(sc); 1523 } 1524 #endif /* DEVICE_POLLING */ 1525 1526 static int 1527 vge_intr(arg) 1528 void *arg; 1529 { 1530 struct vge_softc *sc = arg; 1531 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1532 u_int32_t status; 1533 int claim = 0; 1534 1535 if (sc->suspended) { 1536 return claim; 1537 } 1538 1539 VGE_LOCK(sc); 1540 1541 if (!(ifp->if_flags & IFF_UP)) { 1542 VGE_UNLOCK(sc); 1543 return claim; 1544 } 1545 1546 #ifdef DEVICE_POLLING 1547 if (ifp->if_flags & IFF_POLLING) 1548 goto done; 1549 if ( 1550 #ifdef IFCAP_POLLING 1551 (ifp->if_capenable & IFCAP_POLLING) && 1552 #endif 1553 ether_poll_register(vge_poll, ifp)) { /* ok, disable interrupts */ 1554 CSR_WRITE_4(sc, VGE_IMR, 0); 1555 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1556 vge_poll(ifp, 0, 1); 1557 goto done; 1558 } 1559 1560 #endif /* DEVICE_POLLING */ 1561 1562 /* Disable interrupts */ 1563 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1564 1565 for (;;) { 1566 1567 status = CSR_READ_4(sc, VGE_ISR); 1568 /* If the card has gone away the read returns 0xffff. */ 1569 if (status == 0xFFFFFFFF) 1570 break; 1571 1572 if (status) { 1573 claim = 1; 1574 CSR_WRITE_4(sc, VGE_ISR, status); 1575 } 1576 1577 if ((status & VGE_INTRS) == 0) 1578 break; 1579 1580 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1581 vge_rxeof(sc); 1582 1583 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1584 vge_rxeof(sc); 1585 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1586 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1587 } 1588 1589 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1590 vge_txeof(sc); 1591 1592 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) 1593 vge_init(ifp); 1594 1595 if (status & VGE_ISR_LINKSTS) 1596 vge_tick(sc); 1597 } 1598 1599 /* Re-enable interrupts */ 1600 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1601 1602 #ifdef DEVICE_POLLING 1603 done: 1604 #endif 1605 VGE_UNLOCK(sc); 1606 1607 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1608 vge_start(ifp); 1609 1610 return claim; 1611 } 1612 1613 static int 1614 vge_encap(sc, m_head, idx) 1615 struct vge_softc *sc; 1616 struct mbuf *m_head; 1617 int idx; 1618 { 1619 struct mbuf *m_new = NULL; 1620 bus_dmamap_t map; 1621 int error, flags; 1622 struct m_tag *mtag; 1623 1624 /* If this descriptor is still owned by the chip, bail. */ 1625 if (sc->vge_ldata.vge_tx_free <= 2 1626 || le32toh(sc->vge_ldata.vge_tx_list[idx].vge_sts) & VGE_TDSTS_OWN) 1627 return (ENOBUFS); 1628 1629 flags = 0; 1630 1631 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 1632 flags |= VGE_TDCTL_IPCSUM; 1633 if (m_head->m_pkthdr.csum_flags & M_CSUM_TCPv4) 1634 flags |= VGE_TDCTL_TCPCSUM; 1635 if (m_head->m_pkthdr.csum_flags & M_CSUM_UDPv4) 1636 flags |= VGE_TDCTL_UDPCSUM; 1637 1638 map = sc->vge_ldata.vge_tx_dmamap[idx]; 1639 error = bus_dmamap_load_mbuf(sc->vge_dmat, map, 1640 m_head, BUS_DMA_NOWAIT); 1641 1642 /* If too many segments to map, coalesce */ 1643 if (error == EFBIG) { 1644 m_new = m_defrag(m_head, M_DONTWAIT); 1645 if (m_new == NULL) 1646 return (error); 1647 1648 error = bus_dmamap_load_mbuf(sc->vge_dmat, map, 1649 m_new, BUS_DMA_NOWAIT); 1650 if (error) { 1651 m_freem(m_new); 1652 return (error); 1653 } 1654 1655 m_head = m_new; 1656 } else if (error) 1657 return (error); 1658 1659 vge_dma_map_tx_desc(sc, m_head, idx, flags); 1660 1661 sc->vge_ldata.vge_tx_mbuf[idx] = m_head; 1662 sc->vge_ldata.vge_tx_free--; 1663 1664 /* 1665 * Set up hardware VLAN tagging. 1666 */ 1667 1668 mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m_head); 1669 if (mtag != NULL) 1670 sc->vge_ldata.vge_tx_list[idx].vge_ctl |= 1671 htole32(htons(VLAN_TAG_VALUE(mtag)) | VGE_TDCTL_VTAG); 1672 1673 sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); 1674 1675 return (0); 1676 } 1677 1678 /* 1679 * Main transmit routine. 1680 */ 1681 1682 static void 1683 vge_start(ifp) 1684 struct ifnet *ifp; 1685 { 1686 struct vge_softc *sc; 1687 struct mbuf *m_head = NULL; 1688 int idx, pidx = 0, error; 1689 1690 sc = ifp->if_softc; 1691 VGE_LOCK(sc); 1692 1693 if (!sc->vge_link 1694 || (ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) { 1695 VGE_UNLOCK(sc); 1696 return; 1697 } 1698 1699 idx = sc->vge_ldata.vge_tx_prodidx; 1700 1701 pidx = idx - 1; 1702 if (pidx < 0) 1703 pidx = VGE_TX_DESC_CNT - 1; 1704 1705 /* 1706 * Loop through the send queue, setting up transmit descriptors 1707 * until we drain the queue, or use up all available transmit 1708 * descriptors. 1709 */ 1710 for(;;) { 1711 /* Grab a packet off the queue. */ 1712 IFQ_POLL(&ifp->if_snd, m_head); 1713 if (m_head == NULL) 1714 break; 1715 1716 if (sc->vge_ldata.vge_tx_mbuf[idx] != NULL) { 1717 /* 1718 * Slot already used, stop for now. 1719 */ 1720 ifp->if_flags |= IFF_OACTIVE; 1721 break; 1722 } 1723 1724 if ((error = vge_encap(sc, m_head, idx))) { 1725 if (error == EFBIG) { 1726 printf("%s: Tx packet consumes too many " 1727 "DMA segments, dropping...\n", 1728 sc->sc_dev.dv_xname); 1729 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1730 m_freem(m_head); 1731 continue; 1732 } 1733 1734 /* 1735 * Short on resources, just stop for now. 1736 */ 1737 if (error == ENOBUFS) 1738 ifp->if_flags |= IFF_OACTIVE; 1739 break; 1740 } 1741 1742 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1743 1744 /* 1745 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1746 */ 1747 1748 sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= 1749 htole16(VGE_TXDESC_Q); 1750 1751 if (sc->vge_ldata.vge_tx_mbuf[idx] != m_head) { 1752 m_freem(m_head); 1753 m_head = sc->vge_ldata.vge_tx_mbuf[idx]; 1754 } 1755 1756 pidx = idx; 1757 VGE_TX_DESC_INC(idx); 1758 1759 /* 1760 * If there's a BPF listener, bounce a copy of this frame 1761 * to him. 1762 */ 1763 #if NBPFILTER > 0 1764 if (ifp->if_bpf) 1765 bpf_mtap(ifp->if_bpf, m_head); 1766 #endif 1767 } 1768 1769 if (idx == sc->vge_ldata.vge_tx_prodidx) { 1770 VGE_UNLOCK(sc); 1771 return; 1772 } 1773 1774 /* Flush the TX descriptors */ 1775 1776 bus_dmamap_sync(sc->vge_dmat, 1777 sc->vge_ldata.vge_tx_list_map, 1778 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1779 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1780 1781 /* Issue a transmit command. */ 1782 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1783 1784 sc->vge_ldata.vge_tx_prodidx = idx; 1785 1786 /* 1787 * Use the countdown timer for interrupt moderation. 1788 * 'TX done' interrupts are disabled. Instead, we reset the 1789 * countdown timer, which will begin counting until it hits 1790 * the value in the SSTIMER register, and then trigger an 1791 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1792 * the timer count is reloaded. Only when the transmitter 1793 * is idle will the timer hit 0 and an interrupt fire. 1794 */ 1795 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1796 1797 VGE_UNLOCK(sc); 1798 1799 /* 1800 * Set a timeout in case the chip goes out to lunch. 1801 */ 1802 ifp->if_timer = 5; 1803 1804 return; 1805 } 1806 1807 static int 1808 vge_init(ifp) 1809 struct ifnet *ifp; 1810 { 1811 struct vge_softc *sc = ifp->if_softc; 1812 struct mii_data *mii = &sc->sc_mii; 1813 int i; 1814 1815 VGE_LOCK(sc); 1816 1817 /* 1818 * Cancel pending I/O and free all RX/TX buffers. 1819 */ 1820 vge_stop(sc); 1821 vge_reset(sc); 1822 1823 /* 1824 * Initialize the RX and TX descriptors and mbufs. 1825 */ 1826 1827 vge_rx_list_init(sc); 1828 vge_tx_list_init(sc); 1829 1830 /* Set our station address */ 1831 for (i = 0; i < ETHER_ADDR_LEN; i++) 1832 CSR_WRITE_1(sc, VGE_PAR0 + i, sc->vge_eaddr[i]); 1833 1834 /* 1835 * Set receive FIFO threshold. Also allow transmission and 1836 * reception of VLAN tagged frames. 1837 */ 1838 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 1839 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 1840 1841 /* Set DMA burst length */ 1842 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1843 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1844 1845 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1846 1847 /* Set collision backoff algorithm */ 1848 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1849 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1850 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1851 1852 /* Disable LPSEL field in priority resolution */ 1853 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1854 1855 /* 1856 * Load the addresses of the DMA queues into the chip. 1857 * Note that we only use one transmit queue. 1858 */ 1859 1860 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 1861 VGE_ADDR_LO(sc->vge_ldata.vge_tx_list_addr)); 1862 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 1863 1864 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 1865 VGE_ADDR_LO(sc->vge_ldata.vge_rx_list_addr)); 1866 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 1867 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 1868 1869 /* Enable and wake up the RX descriptor queue */ 1870 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1871 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1872 1873 /* Enable the TX descriptor queue */ 1874 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 1875 1876 /* Set up the receive filter -- allow large frames for VLANs. */ 1877 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 1878 1879 /* If we want promiscuous mode, set the allframes bit. */ 1880 if (ifp->if_flags & IFF_PROMISC) { 1881 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 1882 } 1883 1884 /* Set capture broadcast bit to capture broadcast frames. */ 1885 if (ifp->if_flags & IFF_BROADCAST) { 1886 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 1887 } 1888 1889 /* Set multicast bit to capture multicast frames. */ 1890 if (ifp->if_flags & IFF_MULTICAST) { 1891 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 1892 } 1893 1894 /* Init the cam filter. */ 1895 vge_cam_clear(sc); 1896 1897 /* Init the multicast filter. */ 1898 vge_setmulti(sc); 1899 1900 /* Enable flow control */ 1901 1902 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 1903 1904 /* Enable jumbo frame reception (if desired) */ 1905 1906 /* Start the MAC. */ 1907 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 1908 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 1909 CSR_WRITE_1(sc, VGE_CRS0, 1910 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 1911 1912 /* 1913 * Configure one-shot timer for microsecond 1914 * resulution and load it for 500 usecs. 1915 */ 1916 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 1917 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 1918 1919 /* 1920 * Configure interrupt moderation for receive. Enable 1921 * the holdoff counter and load it, and set the RX 1922 * suppression count to the number of descriptors we 1923 * want to allow before triggering an interrupt. 1924 * The holdoff timer is in units of 20 usecs. 1925 */ 1926 1927 #ifdef notyet 1928 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 1929 /* Select the interrupt holdoff timer page. */ 1930 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1931 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 1932 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 1933 1934 /* Enable use of the holdoff timer. */ 1935 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 1936 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 1937 1938 /* Select the RX suppression threshold page. */ 1939 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1940 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 1941 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 1942 1943 /* Restore the page select bits. */ 1944 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1945 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 1946 #endif 1947 1948 #ifdef DEVICE_POLLING 1949 /* 1950 * Disable interrupts if we are polling. 1951 */ 1952 if (ifp->if_flags & IFF_POLLING) { 1953 CSR_WRITE_4(sc, VGE_IMR, 0); 1954 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1955 } else /* otherwise ... */ 1956 #endif /* DEVICE_POLLING */ 1957 { 1958 /* 1959 * Enable interrupts. 1960 */ 1961 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1962 CSR_WRITE_4(sc, VGE_ISR, 0); 1963 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1964 } 1965 1966 mii_mediachg(mii); 1967 1968 ifp->if_flags |= IFF_RUNNING; 1969 ifp->if_flags &= ~IFF_OACTIVE; 1970 1971 sc->vge_if_flags = 0; 1972 sc->vge_link = 0; 1973 1974 VGE_UNLOCK(sc); 1975 1976 callout_schedule(&sc->vge_timeout, hz); 1977 1978 return (0); 1979 } 1980 1981 /* 1982 * Set media options. 1983 */ 1984 static int 1985 vge_ifmedia_upd(ifp) 1986 struct ifnet *ifp; 1987 { 1988 struct vge_softc *sc = ifp->if_softc; 1989 struct mii_data *mii = &sc->sc_mii; 1990 1991 mii_mediachg(mii); 1992 1993 return (0); 1994 } 1995 1996 /* 1997 * Report current media status. 1998 */ 1999 static void 2000 vge_ifmedia_sts(ifp, ifmr) 2001 struct ifnet *ifp; 2002 struct ifmediareq *ifmr; 2003 { 2004 struct vge_softc *sc = ifp->if_softc; 2005 struct mii_data *mii = &sc->sc_mii; 2006 2007 mii_pollstat(mii); 2008 ifmr->ifm_active = mii->mii_media_active; 2009 ifmr->ifm_status = mii->mii_media_status; 2010 2011 return; 2012 } 2013 2014 static void 2015 vge_miibus_statchg(self) 2016 struct device *self; 2017 { 2018 struct vge_softc *sc = (struct vge_softc *) self; 2019 struct mii_data *mii = &sc->sc_mii; 2020 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 2021 2022 /* 2023 * If the user manually selects a media mode, we need to turn 2024 * on the forced MAC mode bit in the DIAGCTL register. If the 2025 * user happens to choose a full duplex mode, we also need to 2026 * set the 'force full duplex' bit. This applies only to 2027 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 2028 * mode is disabled, and in 1000baseT mode, full duplex is 2029 * always implied, so we turn on the forced mode bit but leave 2030 * the FDX bit cleared. 2031 */ 2032 2033 switch (IFM_SUBTYPE(ife->ifm_media)) { 2034 case IFM_AUTO: 2035 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2036 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2037 break; 2038 case IFM_1000_T: 2039 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2040 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2041 break; 2042 case IFM_100_TX: 2043 case IFM_10_T: 2044 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2045 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 2046 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2047 } else { 2048 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2049 } 2050 break; 2051 default: 2052 printf("%s: unknown media type: %x\n", 2053 sc->sc_dev.dv_xname, 2054 IFM_SUBTYPE(ife->ifm_media)); 2055 break; 2056 } 2057 2058 return; 2059 } 2060 2061 static int 2062 vge_ioctl(ifp, command, data) 2063 struct ifnet *ifp; 2064 u_long command; 2065 caddr_t data; 2066 { 2067 struct vge_softc *sc = ifp->if_softc; 2068 struct ifreq *ifr = (struct ifreq *) data; 2069 struct mii_data *mii; 2070 int s, error = 0; 2071 2072 s = splnet(); 2073 2074 switch (command) { 2075 case SIOCSIFMTU: 2076 if (ifr->ifr_mtu > VGE_JUMBO_MTU) 2077 error = EINVAL; 2078 ifp->if_mtu = ifr->ifr_mtu; 2079 break; 2080 case SIOCSIFFLAGS: 2081 if (ifp->if_flags & IFF_UP) { 2082 if (ifp->if_flags & IFF_RUNNING && 2083 ifp->if_flags & IFF_PROMISC && 2084 !(sc->vge_if_flags & IFF_PROMISC)) { 2085 CSR_SETBIT_1(sc, VGE_RXCTL, 2086 VGE_RXCTL_RX_PROMISC); 2087 vge_setmulti(sc); 2088 } else if (ifp->if_flags & IFF_RUNNING && 2089 !(ifp->if_flags & IFF_PROMISC) && 2090 sc->vge_if_flags & IFF_PROMISC) { 2091 CSR_CLRBIT_1(sc, VGE_RXCTL, 2092 VGE_RXCTL_RX_PROMISC); 2093 vge_setmulti(sc); 2094 } else 2095 vge_init(ifp); 2096 } else { 2097 if (ifp->if_flags & IFF_RUNNING) 2098 vge_stop(sc); 2099 } 2100 sc->vge_if_flags = ifp->if_flags; 2101 break; 2102 case SIOCADDMULTI: 2103 case SIOCDELMULTI: 2104 error = (command == SIOCADDMULTI) ? 2105 ether_addmulti(ifr, &sc->sc_ethercom) : 2106 ether_delmulti(ifr, &sc->sc_ethercom); 2107 2108 if (error == ENETRESET) { 2109 /* 2110 * Multicast list has changed; set the hardware filter 2111 * accordingly. 2112 */ 2113 if (ifp->if_flags & IFF_RUNNING) 2114 vge_setmulti(sc); 2115 error = 0; 2116 } 2117 break; 2118 case SIOCGIFMEDIA: 2119 case SIOCSIFMEDIA: 2120 mii = &sc->sc_mii; 2121 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2122 break; 2123 default: 2124 error = ether_ioctl(ifp, command, data); 2125 break; 2126 } 2127 2128 splx(s); 2129 return (error); 2130 } 2131 2132 static void 2133 vge_watchdog(ifp) 2134 struct ifnet *ifp; 2135 { 2136 struct vge_softc *sc; 2137 2138 sc = ifp->if_softc; 2139 VGE_LOCK(sc); 2140 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 2141 ifp->if_oerrors++; 2142 2143 vge_txeof(sc); 2144 vge_rxeof(sc); 2145 2146 vge_init(ifp); 2147 2148 VGE_UNLOCK(sc); 2149 2150 return; 2151 } 2152 2153 /* 2154 * Stop the adapter and free any mbufs allocated to the 2155 * RX and TX lists. 2156 */ 2157 static void 2158 vge_stop(sc) 2159 struct vge_softc *sc; 2160 { 2161 register int i; 2162 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2163 2164 VGE_LOCK(sc); 2165 ifp->if_timer = 0; 2166 2167 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2168 #ifdef DEVICE_POLLING 2169 ether_poll_deregister(ifp); 2170 #endif /* DEVICE_POLLING */ 2171 2172 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2173 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2174 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2175 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2176 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2177 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2178 2179 if (sc->vge_head != NULL) { 2180 m_freem(sc->vge_head); 2181 sc->vge_head = sc->vge_tail = NULL; 2182 } 2183 2184 /* Free the TX list buffers. */ 2185 2186 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 2187 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { 2188 bus_dmamap_unload(sc->vge_dmat, 2189 sc->vge_ldata.vge_tx_dmamap[i]); 2190 m_freem(sc->vge_ldata.vge_tx_mbuf[i]); 2191 sc->vge_ldata.vge_tx_mbuf[i] = NULL; 2192 } 2193 } 2194 2195 /* Free the RX list buffers. */ 2196 2197 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 2198 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { 2199 bus_dmamap_unload(sc->vge_dmat, 2200 sc->vge_ldata.vge_rx_dmamap[i]); 2201 m_freem(sc->vge_ldata.vge_rx_mbuf[i]); 2202 sc->vge_ldata.vge_rx_mbuf[i] = NULL; 2203 } 2204 } 2205 2206 VGE_UNLOCK(sc); 2207 2208 return; 2209 } 2210 2211 #if VGE_POWER_MANAGEMENT 2212 /* 2213 * Device suspend routine. Stop the interface and save some PCI 2214 * settings in case the BIOS doesn't restore them properly on 2215 * resume. 2216 */ 2217 static int 2218 vge_suspend(dev) 2219 struct device * dev; 2220 { 2221 struct vge_softc *sc; 2222 int i; 2223 2224 sc = device_get_softc(dev); 2225 2226 vge_stop(sc); 2227 2228 for (i = 0; i < 5; i++) 2229 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2230 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2231 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2232 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2233 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2234 2235 sc->suspended = 1; 2236 2237 return (0); 2238 } 2239 2240 /* 2241 * Device resume routine. Restore some PCI settings in case the BIOS 2242 * doesn't, re-enable busmastering, and restart the interface if 2243 * appropriate. 2244 */ 2245 static int 2246 vge_resume(dev) 2247 struct device * dev; 2248 { 2249 struct vge_softc *sc = (struct vge_softc *)dev; 2250 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2251 int i; 2252 2253 /* better way to do this? */ 2254 for (i = 0; i < 5; i++) 2255 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 2256 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 2257 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 2258 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 2259 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 2260 2261 /* reenable busmastering */ 2262 pci_enable_busmaster(dev); 2263 pci_enable_io(dev, SYS_RES_MEMORY); 2264 2265 /* reinitialize interface if necessary */ 2266 if (ifp->if_flags & IFF_UP) 2267 vge_init(sc); 2268 2269 sc->suspended = 0; 2270 2271 return (0); 2272 } 2273 #endif 2274 2275 /* 2276 * Stop all chip I/O so that the kernel's probe routines don't 2277 * get confused by errant DMAs when rebooting. 2278 */ 2279 static void 2280 vge_shutdown(arg) 2281 void *arg; 2282 { 2283 struct vge_softc *sc = (struct vge_softc *)arg; 2284 2285 vge_stop(sc); 2286 } 2287