1 /* $NetBSD: if_vge.c,v 1.41 2008/04/10 19:13:37 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD: src/sys/dev/vge/if_vge.c,v 1.5 2005/02/07 19:39:29 glebius Exp 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_vge.c,v 1.41 2008/04/10 19:13:37 cegger Exp $"); 39 40 /* 41 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 42 * 43 * Written by Bill Paul <wpaul@windriver.com> 44 * Senior Networking Software Engineer 45 * Wind River Systems 46 */ 47 48 /* 49 * The VIA Networking VT6122 is a 32bit, 33/66 MHz PCI device that 50 * combines a tri-speed ethernet MAC and PHY, with the following 51 * features: 52 * 53 * o Jumbo frame support up to 16K 54 * o Transmit and receive flow control 55 * o IPv4 checksum offload 56 * o VLAN tag insertion and stripping 57 * o TCP large send 58 * o 64-bit multicast hash table filter 59 * o 64 entry CAM filter 60 * o 16K RX FIFO and 48K TX FIFO memory 61 * o Interrupt moderation 62 * 63 * The VT6122 supports up to four transmit DMA queues. The descriptors 64 * in the transmit ring can address up to 7 data fragments; frames which 65 * span more than 7 data buffers must be coalesced, but in general the 66 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 67 * long. The receive descriptors address only a single buffer. 68 * 69 * There are two peculiar design issues with the VT6122. One is that 70 * receive data buffers must be aligned on a 32-bit boundary. This is 71 * not a problem where the VT6122 is used as a LOM device in x86-based 72 * systems, but on architectures that generate unaligned access traps, we 73 * have to do some copying. 74 * 75 * The other issue has to do with the way 64-bit addresses are handled. 76 * The DMA descriptors only allow you to specify 48 bits of addressing 77 * information. The remaining 16 bits are specified using one of the 78 * I/O registers. If you only have a 32-bit system, then this isn't 79 * an issue, but if you have a 64-bit system and more than 4GB of 80 * memory, you must have to make sure your network data buffers reside 81 * in the same 48-bit 'segment.' 82 * 83 * Special thanks to Ryan Fu at VIA Networking for providing documentation 84 * and sample NICs for testing. 85 */ 86 87 #include "bpfilter.h" 88 89 #include <sys/param.h> 90 #include <sys/endian.h> 91 #include <sys/systm.h> 92 #include <sys/device.h> 93 #include <sys/sockio.h> 94 #include <sys/mbuf.h> 95 #include <sys/malloc.h> 96 #include <sys/kernel.h> 97 #include <sys/socket.h> 98 99 #include <net/if.h> 100 #include <net/if_arp.h> 101 #include <net/if_ether.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 105 #include <net/bpf.h> 106 107 #include <sys/bus.h> 108 109 #include <dev/mii/mii.h> 110 #include <dev/mii/miivar.h> 111 112 #include <dev/pci/pcireg.h> 113 #include <dev/pci/pcivar.h> 114 #include <dev/pci/pcidevs.h> 115 116 #include <dev/pci/if_vgereg.h> 117 118 #define VGE_JUMBO_MTU 9000 119 120 #define VGE_IFQ_MAXLEN 64 121 122 #define VGE_RING_ALIGN 256 123 124 #define VGE_NTXDESC 256 125 #define VGE_NTXDESC_MASK (VGE_NTXDESC - 1) 126 #define VGE_NEXT_TXDESC(x) ((x + 1) & VGE_NTXDESC_MASK) 127 #define VGE_PREV_TXDESC(x) ((x - 1) & VGE_NTXDESC_MASK) 128 129 #define VGE_NRXDESC 256 /* Must be a multiple of 4!! */ 130 #define VGE_NRXDESC_MASK (VGE_NRXDESC - 1) 131 #define VGE_NEXT_RXDESC(x) ((x + 1) & VGE_NRXDESC_MASK) 132 #define VGE_PREV_RXDESC(x) ((x - 1) & VGE_NRXDESC_MASK) 133 134 #define VGE_ADDR_LO(y) ((uint64_t)(y) & 0xFFFFFFFF) 135 #define VGE_ADDR_HI(y) ((uint64_t)(y) >> 32) 136 #define VGE_BUFLEN(y) ((y) & 0x7FFF) 137 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 138 139 #define VGE_POWER_MANAGEMENT 0 /* disabled for now */ 140 141 /* 142 * Mbuf adjust factor to force 32-bit alignment of IP header. 143 * Drivers should pad ETHER_ALIGN bytes when setting up a 144 * RX mbuf so the upper layers get the IP header properly aligned 145 * past the 14-byte Ethernet header. 146 * 147 * See also comment in vge_encap(). 148 */ 149 #define ETHER_ALIGN 2 150 151 #ifdef __NO_STRICT_ALIGNMENT 152 #define VGE_RX_BUFSIZE MCLBYTES 153 #else 154 #define VGE_RX_PAD sizeof(uint32_t) 155 #define VGE_RX_BUFSIZE (MCLBYTES - VGE_RX_PAD) 156 #endif 157 158 /* 159 * Control structures are DMA'd to the vge chip. We allocate them in 160 * a single clump that maps to a single DMA segment to make several things 161 * easier. 162 */ 163 struct vge_control_data { 164 /* TX descriptors */ 165 struct vge_txdesc vcd_txdescs[VGE_NTXDESC]; 166 /* RX descriptors */ 167 struct vge_rxdesc vcd_rxdescs[VGE_NRXDESC]; 168 /* dummy data for TX padding */ 169 uint8_t vcd_pad[ETHER_PAD_LEN]; 170 }; 171 172 #define VGE_CDOFF(x) offsetof(struct vge_control_data, x) 173 #define VGE_CDTXOFF(x) VGE_CDOFF(vcd_txdescs[(x)]) 174 #define VGE_CDRXOFF(x) VGE_CDOFF(vcd_rxdescs[(x)]) 175 #define VGE_CDPADOFF() VGE_CDOFF(vcd_pad[0]) 176 177 /* 178 * Software state for TX jobs. 179 */ 180 struct vge_txsoft { 181 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 182 bus_dmamap_t txs_dmamap; /* our DMA map */ 183 }; 184 185 /* 186 * Software state for RX jobs. 187 */ 188 struct vge_rxsoft { 189 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 190 bus_dmamap_t rxs_dmamap; /* our DMA map */ 191 }; 192 193 194 struct vge_softc { 195 struct device sc_dev; 196 197 bus_space_tag_t sc_bst; /* bus space tag */ 198 bus_space_handle_t sc_bsh; /* bus space handle */ 199 bus_dma_tag_t sc_dmat; 200 201 struct ethercom sc_ethercom; /* interface info */ 202 uint8_t sc_eaddr[ETHER_ADDR_LEN]; 203 204 void *sc_intrhand; 205 struct mii_data sc_mii; 206 uint8_t sc_type; 207 int sc_if_flags; 208 int sc_link; 209 int sc_camidx; 210 callout_t sc_timeout; 211 212 bus_dmamap_t sc_cddmamap; 213 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 214 215 struct vge_txsoft sc_txsoft[VGE_NTXDESC]; 216 struct vge_rxsoft sc_rxsoft[VGE_NRXDESC]; 217 struct vge_control_data *sc_control_data; 218 #define sc_txdescs sc_control_data->vcd_txdescs 219 #define sc_rxdescs sc_control_data->vcd_rxdescs 220 221 int sc_tx_prodidx; 222 int sc_tx_considx; 223 int sc_tx_free; 224 225 struct mbuf *sc_rx_mhead; 226 struct mbuf *sc_rx_mtail; 227 int sc_rx_prodidx; 228 int sc_rx_consumed; 229 230 int sc_suspended; /* 0 = normal 1 = suspended */ 231 uint32_t sc_saved_maps[5]; /* pci data */ 232 uint32_t sc_saved_biosaddr; 233 uint8_t sc_saved_intline; 234 uint8_t sc_saved_cachelnsz; 235 uint8_t sc_saved_lattimer; 236 }; 237 238 #define VGE_CDTXADDR(sc, x) ((sc)->sc_cddma + VGE_CDTXOFF(x)) 239 #define VGE_CDRXADDR(sc, x) ((sc)->sc_cddma + VGE_CDRXOFF(x)) 240 #define VGE_CDPADADDR(sc) ((sc)->sc_cddma + VGE_CDPADOFF()) 241 242 #define VGE_TXDESCSYNC(sc, idx, ops) \ 243 bus_dmamap_sync((sc)->sc_dmat,(sc)->sc_cddmamap, \ 244 VGE_CDTXOFF(idx), \ 245 offsetof(struct vge_txdesc, td_frag[0]), \ 246 (ops)) 247 #define VGE_TXFRAGSYNC(sc, idx, nsegs, ops) \ 248 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 249 VGE_CDTXOFF(idx) + \ 250 offsetof(struct vge_txdesc, td_frag[0]), \ 251 sizeof(struct vge_txfrag) * (nsegs), \ 252 (ops)) 253 #define VGE_RXDESCSYNC(sc, idx, ops) \ 254 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 255 VGE_CDRXOFF(idx), \ 256 sizeof(struct vge_rxdesc), \ 257 (ops)) 258 259 /* 260 * register space access macros 261 */ 262 #define CSR_WRITE_4(sc, reg, val) \ 263 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 264 #define CSR_WRITE_2(sc, reg, val) \ 265 bus_space_write_2((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 266 #define CSR_WRITE_1(sc, reg, val) \ 267 bus_space_write_1((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 268 269 #define CSR_READ_4(sc, reg) \ 270 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 271 #define CSR_READ_2(sc, reg) \ 272 bus_space_read_2((sc)->sc_bst, (sc)->sc_bsh, (reg)) 273 #define CSR_READ_1(sc, reg) \ 274 bus_space_read_1((sc)->sc_bst, (sc)->sc_bsh, (reg)) 275 276 #define CSR_SETBIT_1(sc, reg, x) \ 277 CSR_WRITE_1((sc), (reg), CSR_READ_1((sc), (reg)) | (x)) 278 #define CSR_SETBIT_2(sc, reg, x) \ 279 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (x)) 280 #define CSR_SETBIT_4(sc, reg, x) \ 281 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (x)) 282 283 #define CSR_CLRBIT_1(sc, reg, x) \ 284 CSR_WRITE_1((sc), (reg), CSR_READ_1((sc), (reg)) & ~(x)) 285 #define CSR_CLRBIT_2(sc, reg, x) \ 286 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(x)) 287 #define CSR_CLRBIT_4(sc, reg, x) \ 288 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(x)) 289 290 #define VGE_TIMEOUT 10000 291 292 #define VGE_PCI_LOIO 0x10 293 #define VGE_PCI_LOMEM 0x14 294 295 static inline void vge_set_txaddr(struct vge_txfrag *, bus_addr_t); 296 static inline void vge_set_rxaddr(struct vge_rxdesc *, bus_addr_t); 297 298 static int vge_match(struct device *, struct cfdata *, void *); 299 static void vge_attach(struct device *, struct device *, void *); 300 301 static int vge_encap(struct vge_softc *, struct mbuf *, int); 302 303 static int vge_allocmem(struct vge_softc *); 304 static int vge_newbuf(struct vge_softc *, int, struct mbuf *); 305 #ifndef __NO_STRICT_ALIGNMENT 306 static inline void vge_fixup_rx(struct mbuf *); 307 #endif 308 static void vge_rxeof(struct vge_softc *); 309 static void vge_txeof(struct vge_softc *); 310 static int vge_intr(void *); 311 static void vge_tick(void *); 312 static void vge_start(struct ifnet *); 313 static int vge_ioctl(struct ifnet *, u_long, void *); 314 static int vge_init(struct ifnet *); 315 static void vge_stop(struct vge_softc *); 316 static void vge_watchdog(struct ifnet *); 317 #if VGE_POWER_MANAGEMENT 318 static int vge_suspend(struct device *); 319 static int vge_resume(struct device *); 320 #endif 321 static void vge_shutdown(void *); 322 323 static uint16_t vge_read_eeprom(struct vge_softc *, int); 324 325 static void vge_miipoll_start(struct vge_softc *); 326 static void vge_miipoll_stop(struct vge_softc *); 327 static int vge_miibus_readreg(struct device *, int, int); 328 static void vge_miibus_writereg(struct device *, int, int, int); 329 static void vge_miibus_statchg(struct device *); 330 331 static void vge_cam_clear(struct vge_softc *); 332 static int vge_cam_set(struct vge_softc *, uint8_t *); 333 static void vge_setmulti(struct vge_softc *); 334 static void vge_reset(struct vge_softc *); 335 336 CFATTACH_DECL(vge, sizeof(struct vge_softc), 337 vge_match, vge_attach, NULL, NULL); 338 339 static inline void 340 vge_set_txaddr(struct vge_txfrag *f, bus_addr_t daddr) 341 { 342 343 f->tf_addrlo = htole32((uint32_t)daddr); 344 if (sizeof(bus_addr_t) == sizeof(uint64_t)) 345 f->tf_addrhi = htole16(((uint64_t)daddr >> 32) & 0xFFFF); 346 else 347 f->tf_addrhi = 0; 348 } 349 350 static inline void 351 vge_set_rxaddr(struct vge_rxdesc *rxd, bus_addr_t daddr) 352 { 353 354 rxd->rd_addrlo = htole32((uint32_t)daddr); 355 if (sizeof(bus_addr_t) == sizeof(uint64_t)) 356 rxd->rd_addrhi = htole16(((uint64_t)daddr >> 32) & 0xFFFF); 357 else 358 rxd->rd_addrhi = 0; 359 } 360 361 /* 362 * Defragment mbuf chain contents to be as linear as possible. 363 * Returns new mbuf chain on success, NULL on failure. Old mbuf 364 * chain is always freed. 365 * XXX temporary until there would be generic function doing this. 366 */ 367 #define m_defrag vge_m_defrag 368 struct mbuf * vge_m_defrag(struct mbuf *, int); 369 370 struct mbuf * 371 vge_m_defrag(struct mbuf *mold, int flags) 372 { 373 struct mbuf *m0, *mn, *n; 374 size_t sz = mold->m_pkthdr.len; 375 376 #ifdef DIAGNOSTIC 377 if ((mold->m_flags & M_PKTHDR) == 0) 378 panic("m_defrag: not a mbuf chain header"); 379 #endif 380 381 MGETHDR(m0, flags, MT_DATA); 382 if (m0 == NULL) 383 return NULL; 384 m0->m_pkthdr.len = mold->m_pkthdr.len; 385 mn = m0; 386 387 do { 388 if (sz > MHLEN) { 389 MCLGET(mn, M_DONTWAIT); 390 if ((mn->m_flags & M_EXT) == 0) { 391 m_freem(m0); 392 return NULL; 393 } 394 } 395 396 mn->m_len = MIN(sz, MCLBYTES); 397 398 m_copydata(mold, mold->m_pkthdr.len - sz, mn->m_len, 399 mtod(mn, void *)); 400 401 sz -= mn->m_len; 402 403 if (sz > 0) { 404 /* need more mbufs */ 405 MGET(n, M_NOWAIT, MT_DATA); 406 if (n == NULL) { 407 m_freem(m0); 408 return NULL; 409 } 410 411 mn->m_next = n; 412 mn = n; 413 } 414 } while (sz > 0); 415 416 return m0; 417 } 418 419 /* 420 * Read a word of data stored in the EEPROM at address 'addr.' 421 */ 422 static uint16_t 423 vge_read_eeprom(struct vge_softc *sc, int addr) 424 { 425 int i; 426 uint16_t word = 0; 427 428 /* 429 * Enter EEPROM embedded programming mode. In order to 430 * access the EEPROM at all, we first have to set the 431 * EELOAD bit in the CHIPCFG2 register. 432 */ 433 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 434 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 435 436 /* Select the address of the word we want to read */ 437 CSR_WRITE_1(sc, VGE_EEADDR, addr); 438 439 /* Issue read command */ 440 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 441 442 /* Wait for the done bit to be set. */ 443 for (i = 0; i < VGE_TIMEOUT; i++) { 444 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 445 break; 446 } 447 448 if (i == VGE_TIMEOUT) { 449 aprint_error_dev(&sc->sc_dev, "EEPROM read timed out\n"); 450 return 0; 451 } 452 453 /* Read the result */ 454 word = CSR_READ_2(sc, VGE_EERDDAT); 455 456 /* Turn off EEPROM access mode. */ 457 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 458 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 459 460 return word; 461 } 462 463 static void 464 vge_miipoll_stop(struct vge_softc *sc) 465 { 466 int i; 467 468 CSR_WRITE_1(sc, VGE_MIICMD, 0); 469 470 for (i = 0; i < VGE_TIMEOUT; i++) { 471 DELAY(1); 472 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 473 break; 474 } 475 476 if (i == VGE_TIMEOUT) { 477 aprint_error_dev(&sc->sc_dev, "failed to idle MII autopoll\n"); 478 } 479 } 480 481 static void 482 vge_miipoll_start(struct vge_softc *sc) 483 { 484 int i; 485 486 /* First, make sure we're idle. */ 487 488 CSR_WRITE_1(sc, VGE_MIICMD, 0); 489 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 490 491 for (i = 0; i < VGE_TIMEOUT; i++) { 492 DELAY(1); 493 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 494 break; 495 } 496 497 if (i == VGE_TIMEOUT) { 498 aprint_error_dev(&sc->sc_dev, "failed to idle MII autopoll\n"); 499 return; 500 } 501 502 /* Now enable auto poll mode. */ 503 504 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 505 506 /* And make sure it started. */ 507 508 for (i = 0; i < VGE_TIMEOUT; i++) { 509 DELAY(1); 510 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 511 break; 512 } 513 514 if (i == VGE_TIMEOUT) { 515 aprint_error_dev(&sc->sc_dev, "failed to start MII autopoll\n"); 516 } 517 } 518 519 static int 520 vge_miibus_readreg(struct device *dev, int phy, int reg) 521 { 522 struct vge_softc *sc; 523 int i, s; 524 uint16_t rval; 525 526 sc = (void *)dev; 527 rval = 0; 528 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 529 return 0; 530 531 s = splnet(); 532 vge_miipoll_stop(sc); 533 534 /* Specify the register we want to read. */ 535 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 536 537 /* Issue read command. */ 538 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 539 540 /* Wait for the read command bit to self-clear. */ 541 for (i = 0; i < VGE_TIMEOUT; i++) { 542 DELAY(1); 543 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 544 break; 545 } 546 547 if (i == VGE_TIMEOUT) 548 aprint_error_dev(&sc->sc_dev, "MII read timed out\n"); 549 else 550 rval = CSR_READ_2(sc, VGE_MIIDATA); 551 552 vge_miipoll_start(sc); 553 splx(s); 554 555 return rval; 556 } 557 558 static void 559 vge_miibus_writereg(struct device *dev, int phy, int reg, int data) 560 { 561 struct vge_softc *sc; 562 int i, s; 563 564 sc = (void *)dev; 565 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 566 return; 567 568 s = splnet(); 569 vge_miipoll_stop(sc); 570 571 /* Specify the register we want to write. */ 572 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 573 574 /* Specify the data we want to write. */ 575 CSR_WRITE_2(sc, VGE_MIIDATA, data); 576 577 /* Issue write command. */ 578 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 579 580 /* Wait for the write command bit to self-clear. */ 581 for (i = 0; i < VGE_TIMEOUT; i++) { 582 DELAY(1); 583 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 584 break; 585 } 586 587 if (i == VGE_TIMEOUT) { 588 aprint_error_dev(&sc->sc_dev, "MII write timed out\n"); 589 } 590 591 vge_miipoll_start(sc); 592 splx(s); 593 } 594 595 static void 596 vge_cam_clear(struct vge_softc *sc) 597 { 598 int i; 599 600 /* 601 * Turn off all the mask bits. This tells the chip 602 * that none of the entries in the CAM filter are valid. 603 * desired entries will be enabled as we fill the filter in. 604 */ 605 606 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 607 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 608 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 609 for (i = 0; i < 8; i++) 610 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 611 612 /* Clear the VLAN filter too. */ 613 614 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 615 for (i = 0; i < 8; i++) 616 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 617 618 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 619 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 620 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 621 622 sc->sc_camidx = 0; 623 } 624 625 static int 626 vge_cam_set(struct vge_softc *sc, uint8_t *addr) 627 { 628 int i, error; 629 630 error = 0; 631 632 if (sc->sc_camidx == VGE_CAM_MAXADDRS) 633 return ENOSPC; 634 635 /* Select the CAM data page. */ 636 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 637 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 638 639 /* Set the filter entry we want to update and enable writing. */ 640 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE | sc->sc_camidx); 641 642 /* Write the address to the CAM registers */ 643 for (i = 0; i < ETHER_ADDR_LEN; i++) 644 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 645 646 /* Issue a write command. */ 647 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 648 649 /* Wake for it to clear. */ 650 for (i = 0; i < VGE_TIMEOUT; i++) { 651 DELAY(1); 652 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 653 break; 654 } 655 656 if (i == VGE_TIMEOUT) { 657 aprint_error_dev(&sc->sc_dev, "setting CAM filter failed\n"); 658 error = EIO; 659 goto fail; 660 } 661 662 /* Select the CAM mask page. */ 663 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 664 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 665 666 /* Set the mask bit that enables this filter. */ 667 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->sc_camidx / 8), 668 1 << (sc->sc_camidx & 7)); 669 670 sc->sc_camidx++; 671 672 fail: 673 /* Turn off access to CAM. */ 674 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 675 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 676 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 677 678 return error; 679 } 680 681 /* 682 * Program the multicast filter. We use the 64-entry CAM filter 683 * for perfect filtering. If there's more than 64 multicast addresses, 684 * we use the hash filter instead. 685 */ 686 static void 687 vge_setmulti(struct vge_softc *sc) 688 { 689 struct ifnet *ifp; 690 int error; 691 uint32_t h, hashes[2] = { 0, 0 }; 692 struct ether_multi *enm; 693 struct ether_multistep step; 694 695 error = 0; 696 ifp = &sc->sc_ethercom.ec_if; 697 698 /* First, zot all the multicast entries. */ 699 vge_cam_clear(sc); 700 CSR_WRITE_4(sc, VGE_MAR0, 0); 701 CSR_WRITE_4(sc, VGE_MAR1, 0); 702 ifp->if_flags &= ~IFF_ALLMULTI; 703 704 /* 705 * If the user wants allmulti or promisc mode, enable reception 706 * of all multicast frames. 707 */ 708 if (ifp->if_flags & IFF_PROMISC) { 709 allmulti: 710 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 711 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 712 ifp->if_flags |= IFF_ALLMULTI; 713 return; 714 } 715 716 /* Now program new ones */ 717 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 718 while (enm != NULL) { 719 /* 720 * If multicast range, fall back to ALLMULTI. 721 */ 722 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 723 ETHER_ADDR_LEN) != 0) 724 goto allmulti; 725 726 error = vge_cam_set(sc, enm->enm_addrlo); 727 if (error) 728 break; 729 730 ETHER_NEXT_MULTI(step, enm); 731 } 732 733 /* If there were too many addresses, use the hash filter. */ 734 if (error) { 735 vge_cam_clear(sc); 736 737 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 738 while (enm != NULL) { 739 /* 740 * If multicast range, fall back to ALLMULTI. 741 */ 742 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 743 ETHER_ADDR_LEN) != 0) 744 goto allmulti; 745 746 h = ether_crc32_be(enm->enm_addrlo, 747 ETHER_ADDR_LEN) >> 26; 748 hashes[h >> 5] |= 1 << (h & 0x1f); 749 750 ETHER_NEXT_MULTI(step, enm); 751 } 752 753 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 754 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 755 } 756 } 757 758 static void 759 vge_reset(struct vge_softc *sc) 760 { 761 int i; 762 763 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 764 765 for (i = 0; i < VGE_TIMEOUT; i++) { 766 DELAY(5); 767 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 768 break; 769 } 770 771 if (i == VGE_TIMEOUT) { 772 aprint_error_dev(&sc->sc_dev, "soft reset timed out"); 773 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 774 DELAY(2000); 775 } 776 777 DELAY(5000); 778 779 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 780 781 for (i = 0; i < VGE_TIMEOUT; i++) { 782 DELAY(5); 783 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 784 break; 785 } 786 787 if (i == VGE_TIMEOUT) { 788 aprint_error_dev(&sc->sc_dev, "EEPROM reload timed out\n"); 789 return; 790 } 791 792 /* 793 * On some machine, the first read data from EEPROM could be 794 * messed up, so read one dummy data here to avoid the mess. 795 */ 796 (void)vge_read_eeprom(sc, 0); 797 798 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 799 } 800 801 /* 802 * Probe for a VIA gigabit chip. Check the PCI vendor and device 803 * IDs against our list and return a device name if we find a match. 804 */ 805 static int 806 vge_match(struct device *parent, struct cfdata *match, void *aux) 807 { 808 struct pci_attach_args *pa = aux; 809 810 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH 811 && PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_VIATECH_VT612X) 812 return 1; 813 814 return 0; 815 } 816 817 static int 818 vge_allocmem(struct vge_softc *sc) 819 { 820 int error; 821 int nseg; 822 int i; 823 bus_dma_segment_t seg; 824 825 /* 826 * Allocate memory for control data. 827 */ 828 829 error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct vge_control_data), 830 VGE_RING_ALIGN, 0, &seg, 1, &nseg, BUS_DMA_NOWAIT); 831 if (error) { 832 aprint_error_dev(&sc->sc_dev, "could not allocate control data dma memory\n"); 833 goto fail_1; 834 } 835 836 /* Map the memory to kernel VA space */ 837 838 error = bus_dmamem_map(sc->sc_dmat, &seg, nseg, 839 sizeof(struct vge_control_data), (void **)&sc->sc_control_data, 840 BUS_DMA_NOWAIT); 841 if (error) { 842 aprint_error_dev(&sc->sc_dev, "could not map control data dma memory\n"); 843 goto fail_2; 844 } 845 memset(sc->sc_control_data, 0, sizeof(struct vge_control_data)); 846 847 /* 848 * Create map for control data. 849 */ 850 error = bus_dmamap_create(sc->sc_dmat, 851 sizeof(struct vge_control_data), 1, 852 sizeof(struct vge_control_data), 0, BUS_DMA_NOWAIT, 853 &sc->sc_cddmamap); 854 if (error) { 855 aprint_error_dev(&sc->sc_dev, "could not create control data dmamap\n"); 856 goto fail_3; 857 } 858 859 /* Load the map for the control data. */ 860 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 861 sc->sc_control_data, sizeof(struct vge_control_data), NULL, 862 BUS_DMA_NOWAIT); 863 if (error) { 864 aprint_error_dev(&sc->sc_dev, "could not load control data dma memory\n"); 865 goto fail_4; 866 } 867 868 /* Create DMA maps for TX buffers */ 869 870 for (i = 0; i < VGE_NTXDESC; i++) { 871 error = bus_dmamap_create(sc->sc_dmat, VGE_TX_MAXLEN, 872 VGE_TX_FRAGS, VGE_TX_MAXLEN, 0, BUS_DMA_NOWAIT, 873 &sc->sc_txsoft[i].txs_dmamap); 874 if (error) { 875 aprint_error_dev(&sc->sc_dev, "can't create DMA map for TX descs\n"); 876 goto fail_5; 877 } 878 } 879 880 /* Create DMA maps for RX buffers */ 881 882 for (i = 0; i < VGE_NRXDESC; i++) { 883 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 884 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 885 &sc->sc_rxsoft[i].rxs_dmamap); 886 if (error) { 887 aprint_error_dev(&sc->sc_dev, "can't create DMA map for RX descs\n"); 888 goto fail_6; 889 } 890 sc->sc_rxsoft[i].rxs_mbuf = NULL; 891 } 892 893 return 0; 894 895 fail_6: 896 for (i = 0; i < VGE_NRXDESC; i++) { 897 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 898 bus_dmamap_destroy(sc->sc_dmat, 899 sc->sc_rxsoft[i].rxs_dmamap); 900 } 901 fail_5: 902 for (i = 0; i < VGE_NTXDESC; i++) { 903 if (sc->sc_txsoft[i].txs_dmamap != NULL) 904 bus_dmamap_destroy(sc->sc_dmat, 905 sc->sc_txsoft[i].txs_dmamap); 906 } 907 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 908 fail_4: 909 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 910 fail_3: 911 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 912 sizeof(struct vge_control_data)); 913 fail_2: 914 bus_dmamem_free(sc->sc_dmat, &seg, nseg); 915 fail_1: 916 return ENOMEM; 917 } 918 919 /* 920 * Attach the interface. Allocate softc structures, do ifmedia 921 * setup and ethernet/BPF attach. 922 */ 923 static void 924 vge_attach(struct device *parent, struct device *self, void *aux) 925 { 926 uint8_t *eaddr; 927 struct vge_softc *sc = (void *)self; 928 struct ifnet *ifp; 929 struct pci_attach_args *pa = aux; 930 pci_chipset_tag_t pc = pa->pa_pc; 931 const char *intrstr; 932 pci_intr_handle_t ih; 933 uint16_t val; 934 935 aprint_normal(": VIA VT612X Gigabit Ethernet (rev. %#x)\n", 936 PCI_REVISION(pa->pa_class)); 937 938 /* Make sure bus-mastering is enabled */ 939 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 940 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 941 PCI_COMMAND_MASTER_ENABLE); 942 943 /* 944 * Map control/status registers. 945 */ 946 if (pci_mapreg_map(pa, VGE_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 947 &sc->sc_bst, &sc->sc_bsh, NULL, NULL) != 0) { 948 aprint_error_dev(&sc->sc_dev, "couldn't map memory\n"); 949 return; 950 } 951 952 /* 953 * Map and establish our interrupt. 954 */ 955 if (pci_intr_map(pa, &ih)) { 956 aprint_error_dev(&sc->sc_dev, "unable to map interrupt\n"); 957 return; 958 } 959 intrstr = pci_intr_string(pc, ih); 960 sc->sc_intrhand = pci_intr_establish(pc, ih, IPL_NET, vge_intr, sc); 961 if (sc->sc_intrhand == NULL) { 962 aprint_error_dev(&sc->sc_dev, "unable to establish interrupt"); 963 if (intrstr != NULL) 964 aprint_error(" at %s", intrstr); 965 aprint_error("\n"); 966 return; 967 } 968 aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", intrstr); 969 970 /* Reset the adapter. */ 971 vge_reset(sc); 972 973 /* 974 * Get station address from the EEPROM. 975 */ 976 eaddr = sc->sc_eaddr; 977 val = vge_read_eeprom(sc, VGE_EE_EADDR + 0); 978 eaddr[0] = val & 0xff; 979 eaddr[1] = val >> 8; 980 val = vge_read_eeprom(sc, VGE_EE_EADDR + 1); 981 eaddr[2] = val & 0xff; 982 eaddr[3] = val >> 8; 983 val = vge_read_eeprom(sc, VGE_EE_EADDR + 2); 984 eaddr[4] = val & 0xff; 985 eaddr[5] = val >> 8; 986 987 aprint_normal_dev(&sc->sc_dev, "Ethernet address: %s\n", 988 ether_sprintf(eaddr)); 989 990 /* 991 * Use the 32bit tag. Hardware supports 48bit physical addresses, 992 * but we don't use that for now. 993 */ 994 sc->sc_dmat = pa->pa_dmat; 995 996 if (vge_allocmem(sc) != 0) 997 return; 998 999 ifp = &sc->sc_ethercom.ec_if; 1000 ifp->if_softc = sc; 1001 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 1002 ifp->if_mtu = ETHERMTU; 1003 ifp->if_baudrate = IF_Gbps(1); 1004 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1005 ifp->if_ioctl = vge_ioctl; 1006 ifp->if_start = vge_start; 1007 1008 /* 1009 * We can support 802.1Q VLAN-sized frames and jumbo 1010 * Ethernet frames. 1011 */ 1012 sc->sc_ethercom.ec_capabilities |= 1013 ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU | 1014 ETHERCAP_VLAN_HWTAGGING; 1015 1016 /* 1017 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 1018 */ 1019 ifp->if_capabilities |= 1020 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1021 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1022 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1023 1024 #ifdef DEVICE_POLLING 1025 #ifdef IFCAP_POLLING 1026 ifp->if_capabilities |= IFCAP_POLLING; 1027 #endif 1028 #endif 1029 ifp->if_watchdog = vge_watchdog; 1030 ifp->if_init = vge_init; 1031 IFQ_SET_MAXLEN(&ifp->if_snd, max(VGE_IFQ_MAXLEN, IFQ_MAXLEN)); 1032 1033 /* 1034 * Initialize our media structures and probe the MII. 1035 */ 1036 sc->sc_mii.mii_ifp = ifp; 1037 sc->sc_mii.mii_readreg = vge_miibus_readreg; 1038 sc->sc_mii.mii_writereg = vge_miibus_writereg; 1039 sc->sc_mii.mii_statchg = vge_miibus_statchg; 1040 1041 sc->sc_ethercom.ec_mii = &sc->sc_mii; 1042 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 1043 ether_mediastatus); 1044 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1045 MII_OFFSET_ANY, MIIF_DOPAUSE); 1046 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1047 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1048 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1049 } else 1050 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1051 1052 /* 1053 * Attach the interface. 1054 */ 1055 if_attach(ifp); 1056 ether_ifattach(ifp, eaddr); 1057 1058 callout_init(&sc->sc_timeout, 0); 1059 callout_setfunc(&sc->sc_timeout, vge_tick, sc); 1060 1061 /* 1062 * Make sure the interface is shutdown during reboot. 1063 */ 1064 if (shutdownhook_establish(vge_shutdown, sc) == NULL) { 1065 aprint_error_dev(&sc->sc_dev, "WARNING: unable to establish shutdown hook\n"); 1066 } 1067 } 1068 1069 static int 1070 vge_newbuf(struct vge_softc *sc, int idx, struct mbuf *m) 1071 { 1072 struct mbuf *m_new; 1073 struct vge_rxdesc *rxd; 1074 struct vge_rxsoft *rxs; 1075 bus_dmamap_t map; 1076 int i; 1077 #ifdef DIAGNOSTIC 1078 uint32_t rd_sts; 1079 #endif 1080 1081 m_new = NULL; 1082 if (m == NULL) { 1083 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1084 if (m_new == NULL) 1085 return ENOBUFS; 1086 1087 MCLGET(m_new, M_DONTWAIT); 1088 if ((m_new->m_flags & M_EXT) == 0) { 1089 m_freem(m_new); 1090 return ENOBUFS; 1091 } 1092 1093 m = m_new; 1094 } else 1095 m->m_data = m->m_ext.ext_buf; 1096 1097 1098 /* 1099 * This is part of an evil trick to deal with non-x86 platforms. 1100 * The VIA chip requires RX buffers to be aligned on 32-bit 1101 * boundaries, but that will hose non-x86 machines. To get around 1102 * this, we leave some empty space at the start of each buffer 1103 * and for non-x86 hosts, we copy the buffer back two bytes 1104 * to achieve word alignment. This is slightly more efficient 1105 * than allocating a new buffer, copying the contents, and 1106 * discarding the old buffer. 1107 */ 1108 m->m_len = m->m_pkthdr.len = VGE_RX_BUFSIZE; 1109 #ifndef __NO_STRICT_ALIGNMENT 1110 m->m_data += VGE_RX_PAD; 1111 #endif 1112 rxs = &sc->sc_rxsoft[idx]; 1113 map = rxs->rxs_dmamap; 1114 1115 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT) != 0) 1116 goto out; 1117 1118 rxd = &sc->sc_rxdescs[idx]; 1119 1120 #ifdef DIAGNOSTIC 1121 /* If this descriptor is still owned by the chip, bail. */ 1122 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1123 rd_sts = le32toh(rxd->rd_sts); 1124 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1125 if (rd_sts & VGE_RDSTS_OWN) { 1126 panic("%s: tried to map busy RX descriptor", 1127 device_xname(&sc->sc_dev)); 1128 } 1129 #endif 1130 1131 rxs->rxs_mbuf = m; 1132 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1133 BUS_DMASYNC_PREREAD); 1134 1135 rxd->rd_buflen = 1136 htole16(VGE_BUFLEN(map->dm_segs[0].ds_len) | VGE_RXDESC_I); 1137 vge_set_rxaddr(rxd, map->dm_segs[0].ds_addr); 1138 rxd->rd_sts = 0; 1139 rxd->rd_ctl = 0; 1140 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1141 1142 /* 1143 * Note: the manual fails to document the fact that for 1144 * proper opration, the driver needs to replentish the RX 1145 * DMA ring 4 descriptors at a time (rather than one at a 1146 * time, like most chips). We can allocate the new buffers 1147 * but we should not set the OWN bits until we're ready 1148 * to hand back 4 of them in one shot. 1149 */ 1150 1151 #define VGE_RXCHUNK 4 1152 sc->sc_rx_consumed++; 1153 if (sc->sc_rx_consumed == VGE_RXCHUNK) { 1154 for (i = idx; i != idx - VGE_RXCHUNK; i--) { 1155 KASSERT(i >= 0); 1156 sc->sc_rxdescs[i].rd_sts |= htole32(VGE_RDSTS_OWN); 1157 VGE_RXDESCSYNC(sc, i, 1158 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1159 } 1160 sc->sc_rx_consumed = 0; 1161 } 1162 1163 return 0; 1164 out: 1165 if (m_new != NULL) 1166 m_freem(m_new); 1167 return ENOMEM; 1168 } 1169 1170 #ifndef __NO_STRICT_ALIGNMENT 1171 static inline void 1172 vge_fixup_rx(struct mbuf *m) 1173 { 1174 int i; 1175 uint16_t *src, *dst; 1176 1177 src = mtod(m, uint16_t *); 1178 dst = src - 1; 1179 1180 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1181 *dst++ = *src++; 1182 1183 m->m_data -= ETHER_ALIGN; 1184 } 1185 #endif 1186 1187 /* 1188 * RX handler. We support the reception of jumbo frames that have 1189 * been fragmented across multiple 2K mbuf cluster buffers. 1190 */ 1191 static void 1192 vge_rxeof(struct vge_softc *sc) 1193 { 1194 struct mbuf *m; 1195 struct ifnet *ifp; 1196 int idx, total_len, lim; 1197 struct vge_rxdesc *cur_rxd; 1198 struct vge_rxsoft *rxs; 1199 uint32_t rxstat, rxctl; 1200 1201 ifp = &sc->sc_ethercom.ec_if; 1202 lim = 0; 1203 1204 /* Invalidate the descriptor memory */ 1205 1206 for (idx = sc->sc_rx_prodidx;; idx = VGE_NEXT_RXDESC(idx)) { 1207 cur_rxd = &sc->sc_rxdescs[idx]; 1208 1209 VGE_RXDESCSYNC(sc, idx, 1210 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1211 rxstat = le32toh(cur_rxd->rd_sts); 1212 if ((rxstat & VGE_RDSTS_OWN) != 0) { 1213 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1214 break; 1215 } 1216 1217 rxctl = le32toh(cur_rxd->rd_ctl); 1218 rxs = &sc->sc_rxsoft[idx]; 1219 m = rxs->rxs_mbuf; 1220 total_len = (rxstat & VGE_RDSTS_BUFSIZ) >> 16; 1221 1222 /* Invalidate the RX mbuf and unload its map */ 1223 1224 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 1225 0, rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1226 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1227 1228 /* 1229 * If the 'start of frame' bit is set, this indicates 1230 * either the first fragment in a multi-fragment receive, 1231 * or an intermediate fragment. Either way, we want to 1232 * accumulate the buffers. 1233 */ 1234 if (rxstat & VGE_RXPKT_SOF) { 1235 m->m_len = VGE_RX_BUFSIZE; 1236 if (sc->sc_rx_mhead == NULL) 1237 sc->sc_rx_mhead = sc->sc_rx_mtail = m; 1238 else { 1239 m->m_flags &= ~M_PKTHDR; 1240 sc->sc_rx_mtail->m_next = m; 1241 sc->sc_rx_mtail = m; 1242 } 1243 vge_newbuf(sc, idx, NULL); 1244 continue; 1245 } 1246 1247 /* 1248 * Bad/error frames will have the RXOK bit cleared. 1249 * However, there's one error case we want to allow: 1250 * if a VLAN tagged frame arrives and the chip can't 1251 * match it against the CAM filter, it considers this 1252 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1253 * We don't want to drop the frame though: our VLAN 1254 * filtering is done in software. 1255 */ 1256 if ((rxstat & VGE_RDSTS_RXOK) == 0 && 1257 (rxstat & VGE_RDSTS_VIDM) == 0 && 1258 (rxstat & VGE_RDSTS_CSUMERR) == 0) { 1259 ifp->if_ierrors++; 1260 /* 1261 * If this is part of a multi-fragment packet, 1262 * discard all the pieces. 1263 */ 1264 if (sc->sc_rx_mhead != NULL) { 1265 m_freem(sc->sc_rx_mhead); 1266 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL; 1267 } 1268 vge_newbuf(sc, idx, m); 1269 continue; 1270 } 1271 1272 /* 1273 * If allocating a replacement mbuf fails, 1274 * reload the current one. 1275 */ 1276 1277 if (vge_newbuf(sc, idx, NULL)) { 1278 ifp->if_ierrors++; 1279 if (sc->sc_rx_mhead != NULL) { 1280 m_freem(sc->sc_rx_mhead); 1281 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL; 1282 } 1283 vge_newbuf(sc, idx, m); 1284 continue; 1285 } 1286 1287 if (sc->sc_rx_mhead != NULL) { 1288 m->m_len = total_len % VGE_RX_BUFSIZE; 1289 /* 1290 * Special case: if there's 4 bytes or less 1291 * in this buffer, the mbuf can be discarded: 1292 * the last 4 bytes is the CRC, which we don't 1293 * care about anyway. 1294 */ 1295 if (m->m_len <= ETHER_CRC_LEN) { 1296 sc->sc_rx_mtail->m_len -= 1297 (ETHER_CRC_LEN - m->m_len); 1298 m_freem(m); 1299 } else { 1300 m->m_len -= ETHER_CRC_LEN; 1301 m->m_flags &= ~M_PKTHDR; 1302 sc->sc_rx_mtail->m_next = m; 1303 } 1304 m = sc->sc_rx_mhead; 1305 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL; 1306 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1307 } else 1308 m->m_pkthdr.len = m->m_len = total_len - ETHER_CRC_LEN; 1309 1310 #ifndef __NO_STRICT_ALIGNMENT 1311 vge_fixup_rx(m); 1312 #endif 1313 ifp->if_ipackets++; 1314 m->m_pkthdr.rcvif = ifp; 1315 1316 /* Do RX checksumming if enabled */ 1317 if (ifp->if_csum_flags_rx & M_CSUM_IPv4) { 1318 1319 /* Check IP header checksum */ 1320 if (rxctl & VGE_RDCTL_IPPKT) 1321 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1322 if ((rxctl & VGE_RDCTL_IPCSUMOK) == 0) 1323 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1324 } 1325 1326 if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) { 1327 /* Check UDP checksum */ 1328 if (rxctl & VGE_RDCTL_TCPPKT) 1329 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1330 1331 if ((rxctl & VGE_RDCTL_PROTOCSUMOK) == 0) 1332 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1333 } 1334 1335 if (ifp->if_csum_flags_rx & M_CSUM_UDPv4) { 1336 /* Check UDP checksum */ 1337 if (rxctl & VGE_RDCTL_UDPPKT) 1338 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1339 1340 if ((rxctl & VGE_RDCTL_PROTOCSUMOK) == 0) 1341 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1342 } 1343 1344 if (rxstat & VGE_RDSTS_VTAG) { 1345 /* 1346 * We use bswap16() here because: 1347 * On LE machines, tag is stored in BE as stream data. 1348 * On BE machines, tag is stored in BE as stream data 1349 * but it was already swapped by le32toh() above. 1350 */ 1351 VLAN_INPUT_TAG(ifp, m, 1352 bswap16(rxctl & VGE_RDCTL_VLANID), continue); 1353 } 1354 1355 #if NBPFILTER > 0 1356 /* 1357 * Handle BPF listeners. 1358 */ 1359 if (ifp->if_bpf) 1360 bpf_mtap(ifp->if_bpf, m); 1361 #endif 1362 1363 (*ifp->if_input)(ifp, m); 1364 1365 lim++; 1366 if (lim == VGE_NRXDESC) 1367 break; 1368 } 1369 1370 sc->sc_rx_prodidx = idx; 1371 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1372 } 1373 1374 static void 1375 vge_txeof(struct vge_softc *sc) 1376 { 1377 struct ifnet *ifp; 1378 struct vge_txsoft *txs; 1379 uint32_t txstat; 1380 int idx; 1381 1382 ifp = &sc->sc_ethercom.ec_if; 1383 1384 for (idx = sc->sc_tx_considx; 1385 sc->sc_tx_free < VGE_NTXDESC; 1386 idx = VGE_NEXT_TXDESC(idx), sc->sc_tx_free++) { 1387 VGE_TXDESCSYNC(sc, idx, 1388 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1389 txstat = le32toh(sc->sc_txdescs[idx].td_sts); 1390 VGE_TXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1391 if (txstat & VGE_TDSTS_OWN) { 1392 break; 1393 } 1394 1395 txs = &sc->sc_txsoft[idx]; 1396 m_freem(txs->txs_mbuf); 1397 txs->txs_mbuf = NULL; 1398 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 0, 1399 txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1400 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1401 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1402 ifp->if_collisions++; 1403 if (txstat & VGE_TDSTS_TXERR) 1404 ifp->if_oerrors++; 1405 else 1406 ifp->if_opackets++; 1407 } 1408 1409 sc->sc_tx_considx = idx; 1410 1411 if (sc->sc_tx_free > 0) { 1412 ifp->if_flags &= ~IFF_OACTIVE; 1413 } 1414 1415 /* 1416 * If not all descriptors have been released reaped yet, 1417 * reload the timer so that we will eventually get another 1418 * interrupt that will cause us to re-enter this routine. 1419 * This is done in case the transmitter has gone idle. 1420 */ 1421 if (sc->sc_tx_free < VGE_NTXDESC) 1422 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1423 else 1424 ifp->if_timer = 0; 1425 } 1426 1427 static void 1428 vge_tick(void *xsc) 1429 { 1430 struct vge_softc *sc; 1431 struct ifnet *ifp; 1432 struct mii_data *mii; 1433 int s; 1434 1435 sc = xsc; 1436 ifp = &sc->sc_ethercom.ec_if; 1437 mii = &sc->sc_mii; 1438 1439 s = splnet(); 1440 1441 callout_schedule(&sc->sc_timeout, hz); 1442 1443 mii_tick(mii); 1444 if (sc->sc_link) { 1445 if ((mii->mii_media_status & IFM_ACTIVE) == 0) 1446 sc->sc_link = 0; 1447 } else { 1448 if (mii->mii_media_status & IFM_ACTIVE && 1449 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1450 sc->sc_link = 1; 1451 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1452 vge_start(ifp); 1453 } 1454 } 1455 1456 splx(s); 1457 } 1458 1459 static int 1460 vge_intr(void *arg) 1461 { 1462 struct vge_softc *sc; 1463 struct ifnet *ifp; 1464 uint32_t status; 1465 int claim; 1466 1467 sc = arg; 1468 claim = 0; 1469 if (sc->sc_suspended) { 1470 return claim; 1471 } 1472 1473 ifp = &sc->sc_ethercom.ec_if; 1474 1475 if ((ifp->if_flags & IFF_UP) == 0) { 1476 return claim; 1477 } 1478 1479 /* Disable interrupts */ 1480 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1481 1482 for (;;) { 1483 1484 status = CSR_READ_4(sc, VGE_ISR); 1485 /* If the card has gone away the read returns 0xffff. */ 1486 if (status == 0xFFFFFFFF) 1487 break; 1488 1489 if (status) { 1490 claim = 1; 1491 CSR_WRITE_4(sc, VGE_ISR, status); 1492 } 1493 1494 if ((status & VGE_INTRS) == 0) 1495 break; 1496 1497 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1498 vge_rxeof(sc); 1499 1500 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1501 vge_rxeof(sc); 1502 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1503 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1504 } 1505 1506 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1507 vge_txeof(sc); 1508 1509 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) 1510 vge_init(ifp); 1511 1512 if (status & VGE_ISR_LINKSTS) 1513 vge_tick(sc); 1514 } 1515 1516 /* Re-enable interrupts */ 1517 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1518 1519 if (claim && !IFQ_IS_EMPTY(&ifp->if_snd)) 1520 vge_start(ifp); 1521 1522 return claim; 1523 } 1524 1525 static int 1526 vge_encap(struct vge_softc *sc, struct mbuf *m_head, int idx) 1527 { 1528 struct vge_txsoft *txs; 1529 struct vge_txdesc *txd; 1530 struct vge_txfrag *f; 1531 struct mbuf *m_new; 1532 bus_dmamap_t map; 1533 int m_csumflags, seg, error, flags; 1534 struct m_tag *mtag; 1535 size_t sz; 1536 uint32_t td_sts, td_ctl; 1537 1538 KASSERT(sc->sc_tx_free > 0); 1539 1540 txd = &sc->sc_txdescs[idx]; 1541 1542 #ifdef DIAGNOSTIC 1543 /* If this descriptor is still owned by the chip, bail. */ 1544 VGE_TXDESCSYNC(sc, idx, 1545 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1546 td_sts = le32toh(txd->td_sts); 1547 VGE_TXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1548 if (td_sts & VGE_TDSTS_OWN) { 1549 return ENOBUFS; 1550 } 1551 #endif 1552 1553 /* 1554 * Preserve m_pkthdr.csum_flags here since m_head might be 1555 * updated by m_defrag() 1556 */ 1557 m_csumflags = m_head->m_pkthdr.csum_flags; 1558 1559 txs = &sc->sc_txsoft[idx]; 1560 map = txs->txs_dmamap; 1561 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m_head, BUS_DMA_NOWAIT); 1562 1563 /* If too many segments to map, coalesce */ 1564 if (error == EFBIG || 1565 (m_head->m_pkthdr.len < ETHER_PAD_LEN && 1566 map->dm_nsegs == VGE_TX_FRAGS)) { 1567 m_new = m_defrag(m_head, M_DONTWAIT); 1568 if (m_new == NULL) 1569 return EFBIG; 1570 1571 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, 1572 m_new, BUS_DMA_NOWAIT); 1573 if (error) { 1574 m_freem(m_new); 1575 return error; 1576 } 1577 1578 m_head = m_new; 1579 } else if (error) 1580 return error; 1581 1582 txs->txs_mbuf = m_head; 1583 1584 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1585 BUS_DMASYNC_PREWRITE); 1586 1587 for (seg = 0, f = &txd->td_frag[0]; seg < map->dm_nsegs; seg++, f++) { 1588 f->tf_buflen = htole16(VGE_BUFLEN(map->dm_segs[seg].ds_len)); 1589 vge_set_txaddr(f, map->dm_segs[seg].ds_addr); 1590 } 1591 1592 /* Argh. This chip does not autopad short frames */ 1593 sz = m_head->m_pkthdr.len; 1594 if (sz < ETHER_PAD_LEN) { 1595 f->tf_buflen = htole16(VGE_BUFLEN(ETHER_PAD_LEN - sz)); 1596 vge_set_txaddr(f, VGE_CDPADADDR(sc)); 1597 sz = ETHER_PAD_LEN; 1598 seg++; 1599 } 1600 VGE_TXFRAGSYNC(sc, idx, seg, BUS_DMASYNC_PREWRITE); 1601 1602 /* 1603 * When telling the chip how many segments there are, we 1604 * must use nsegs + 1 instead of just nsegs. Darned if I 1605 * know why. 1606 */ 1607 seg++; 1608 1609 flags = 0; 1610 if (m_csumflags & M_CSUM_IPv4) 1611 flags |= VGE_TDCTL_IPCSUM; 1612 if (m_csumflags & M_CSUM_TCPv4) 1613 flags |= VGE_TDCTL_TCPCSUM; 1614 if (m_csumflags & M_CSUM_UDPv4) 1615 flags |= VGE_TDCTL_UDPCSUM; 1616 td_sts = sz << 16; 1617 td_ctl = flags | (seg << 28) | VGE_TD_LS_NORM; 1618 1619 if (sz > ETHERMTU + ETHER_HDR_LEN) 1620 td_ctl |= VGE_TDCTL_JUMBO; 1621 1622 /* 1623 * Set up hardware VLAN tagging. 1624 */ 1625 mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m_head); 1626 if (mtag != NULL) { 1627 /* 1628 * No need htons() here since vge(4) chip assumes 1629 * that tags are written in little endian and 1630 * we already use htole32() here. 1631 */ 1632 td_ctl |= VLAN_TAG_VALUE(mtag) | VGE_TDCTL_VTAG; 1633 } 1634 txd->td_ctl = htole32(td_ctl); 1635 txd->td_sts = htole32(td_sts); 1636 VGE_TXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1637 1638 txd->td_sts = htole32(VGE_TDSTS_OWN | td_sts); 1639 VGE_TXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1640 1641 sc->sc_tx_free--; 1642 1643 return 0; 1644 } 1645 1646 /* 1647 * Main transmit routine. 1648 */ 1649 1650 static void 1651 vge_start(struct ifnet *ifp) 1652 { 1653 struct vge_softc *sc; 1654 struct vge_txsoft *txs; 1655 struct mbuf *m_head; 1656 int idx, pidx, ofree, error; 1657 1658 sc = ifp->if_softc; 1659 1660 if (!sc->sc_link || 1661 (ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) { 1662 return; 1663 } 1664 1665 m_head = NULL; 1666 idx = sc->sc_tx_prodidx; 1667 pidx = VGE_PREV_TXDESC(idx); 1668 ofree = sc->sc_tx_free; 1669 1670 /* 1671 * Loop through the send queue, setting up transmit descriptors 1672 * until we drain the queue, or use up all available transmit 1673 * descriptors. 1674 */ 1675 for (;;) { 1676 /* Grab a packet off the queue. */ 1677 IFQ_POLL(&ifp->if_snd, m_head); 1678 if (m_head == NULL) 1679 break; 1680 1681 if (sc->sc_tx_free == 0) { 1682 /* 1683 * All slots used, stop for now. 1684 */ 1685 ifp->if_flags |= IFF_OACTIVE; 1686 break; 1687 } 1688 1689 txs = &sc->sc_txsoft[idx]; 1690 KASSERT(txs->txs_mbuf == NULL); 1691 1692 if ((error = vge_encap(sc, m_head, idx))) { 1693 if (error == EFBIG) { 1694 aprint_error_dev(&sc->sc_dev, "Tx packet consumes too many " 1695 "DMA segments, dropping...\n"); 1696 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1697 m_freem(m_head); 1698 continue; 1699 } 1700 1701 /* 1702 * Short on resources, just stop for now. 1703 */ 1704 if (error == ENOBUFS) 1705 ifp->if_flags |= IFF_OACTIVE; 1706 break; 1707 } 1708 1709 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1710 1711 /* 1712 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1713 */ 1714 1715 sc->sc_txdescs[pidx].td_frag[0].tf_buflen |= 1716 htole16(VGE_TXDESC_Q); 1717 VGE_TXFRAGSYNC(sc, pidx, 1, 1718 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1719 1720 if (txs->txs_mbuf != m_head) { 1721 m_freem(m_head); 1722 m_head = txs->txs_mbuf; 1723 } 1724 1725 pidx = idx; 1726 idx = VGE_NEXT_TXDESC(idx); 1727 1728 /* 1729 * If there's a BPF listener, bounce a copy of this frame 1730 * to him. 1731 */ 1732 #if NBPFILTER > 0 1733 if (ifp->if_bpf) 1734 bpf_mtap(ifp->if_bpf, m_head); 1735 #endif 1736 } 1737 1738 if (sc->sc_tx_free < ofree) { 1739 /* TX packet queued */ 1740 1741 sc->sc_tx_prodidx = idx; 1742 1743 /* Issue a transmit command. */ 1744 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1745 1746 /* 1747 * Use the countdown timer for interrupt moderation. 1748 * 'TX done' interrupts are disabled. Instead, we reset the 1749 * countdown timer, which will begin counting until it hits 1750 * the value in the SSTIMER register, and then trigger an 1751 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1752 * the timer count is reloaded. Only when the transmitter 1753 * is idle will the timer hit 0 and an interrupt fire. 1754 */ 1755 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1756 1757 /* 1758 * Set a timeout in case the chip goes out to lunch. 1759 */ 1760 ifp->if_timer = 5; 1761 } 1762 } 1763 1764 static int 1765 vge_init(struct ifnet *ifp) 1766 { 1767 struct vge_softc *sc; 1768 int i, rc = 0; 1769 1770 sc = ifp->if_softc; 1771 1772 /* 1773 * Cancel pending I/O and free all RX/TX buffers. 1774 */ 1775 vge_stop(sc); 1776 vge_reset(sc); 1777 1778 /* Initialize the RX descriptors and mbufs. */ 1779 memset(sc->sc_rxdescs, 0, sizeof(sc->sc_rxdescs)); 1780 sc->sc_rx_consumed = 0; 1781 for (i = 0; i < VGE_NRXDESC; i++) { 1782 if (vge_newbuf(sc, i, NULL) == ENOBUFS) { 1783 aprint_error_dev(&sc->sc_dev, "unable to allocate or map " 1784 "rx buffer\n"); 1785 return 1; /* XXX */ 1786 } 1787 } 1788 sc->sc_rx_prodidx = 0; 1789 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL; 1790 1791 /* Initialize the TX descriptors and mbufs. */ 1792 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1793 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 1794 VGE_CDTXOFF(0), sizeof(sc->sc_txdescs), 1795 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1796 for (i = 0; i < VGE_NTXDESC; i++) 1797 sc->sc_txsoft[i].txs_mbuf = NULL; 1798 1799 sc->sc_tx_prodidx = 0; 1800 sc->sc_tx_considx = 0; 1801 sc->sc_tx_free = VGE_NTXDESC; 1802 1803 /* Set our station address */ 1804 for (i = 0; i < ETHER_ADDR_LEN; i++) 1805 CSR_WRITE_1(sc, VGE_PAR0 + i, sc->sc_eaddr[i]); 1806 1807 /* 1808 * Set receive FIFO threshold. Also allow transmission and 1809 * reception of VLAN tagged frames. 1810 */ 1811 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 1812 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 1813 1814 /* Set DMA burst length */ 1815 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1816 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1817 1818 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1819 1820 /* Set collision backoff algorithm */ 1821 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1822 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1823 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1824 1825 /* Disable LPSEL field in priority resolution */ 1826 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1827 1828 /* 1829 * Load the addresses of the DMA queues into the chip. 1830 * Note that we only use one transmit queue. 1831 */ 1832 1833 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, VGE_ADDR_LO(VGE_CDTXADDR(sc, 0))); 1834 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_NTXDESC - 1); 1835 1836 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, VGE_ADDR_LO(VGE_CDRXADDR(sc, 0))); 1837 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_NRXDESC - 1); 1838 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_NRXDESC); 1839 1840 /* Enable and wake up the RX descriptor queue */ 1841 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1842 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1843 1844 /* Enable the TX descriptor queue */ 1845 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 1846 1847 /* Set up the receive filter -- allow large frames for VLANs. */ 1848 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 1849 1850 /* If we want promiscuous mode, set the allframes bit. */ 1851 if (ifp->if_flags & IFF_PROMISC) { 1852 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 1853 } 1854 1855 /* Set capture broadcast bit to capture broadcast frames. */ 1856 if (ifp->if_flags & IFF_BROADCAST) { 1857 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 1858 } 1859 1860 /* Set multicast bit to capture multicast frames. */ 1861 if (ifp->if_flags & IFF_MULTICAST) { 1862 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 1863 } 1864 1865 /* Init the cam filter. */ 1866 vge_cam_clear(sc); 1867 1868 /* Init the multicast filter. */ 1869 vge_setmulti(sc); 1870 1871 /* Enable flow control */ 1872 1873 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 1874 1875 /* Enable jumbo frame reception (if desired) */ 1876 1877 /* Start the MAC. */ 1878 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 1879 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 1880 CSR_WRITE_1(sc, VGE_CRS0, 1881 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 1882 1883 /* 1884 * Configure one-shot timer for microsecond 1885 * resulution and load it for 500 usecs. 1886 */ 1887 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 1888 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 1889 1890 /* 1891 * Configure interrupt moderation for receive. Enable 1892 * the holdoff counter and load it, and set the RX 1893 * suppression count to the number of descriptors we 1894 * want to allow before triggering an interrupt. 1895 * The holdoff timer is in units of 20 usecs. 1896 */ 1897 1898 #ifdef notyet 1899 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 1900 /* Select the interrupt holdoff timer page. */ 1901 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1902 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 1903 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 1904 1905 /* Enable use of the holdoff timer. */ 1906 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 1907 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 1908 1909 /* Select the RX suppression threshold page. */ 1910 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1911 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 1912 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 1913 1914 /* Restore the page select bits. */ 1915 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1916 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 1917 #endif 1918 1919 #ifdef DEVICE_POLLING 1920 /* 1921 * Disable interrupts if we are polling. 1922 */ 1923 if (ifp->if_flags & IFF_POLLING) { 1924 CSR_WRITE_4(sc, VGE_IMR, 0); 1925 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1926 } else /* otherwise ... */ 1927 #endif /* DEVICE_POLLING */ 1928 { 1929 /* 1930 * Enable interrupts. 1931 */ 1932 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1933 CSR_WRITE_4(sc, VGE_ISR, 0); 1934 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1935 } 1936 1937 if ((rc = ether_mediachange(ifp)) != 0) 1938 goto out; 1939 1940 ifp->if_flags |= IFF_RUNNING; 1941 ifp->if_flags &= ~IFF_OACTIVE; 1942 1943 sc->sc_if_flags = 0; 1944 sc->sc_link = 0; 1945 1946 callout_schedule(&sc->sc_timeout, hz); 1947 1948 out: 1949 return rc; 1950 } 1951 1952 static void 1953 vge_miibus_statchg(struct device *self) 1954 { 1955 struct vge_softc *sc; 1956 struct mii_data *mii; 1957 struct ifmedia_entry *ife; 1958 1959 sc = (void *)self; 1960 mii = &sc->sc_mii; 1961 ife = mii->mii_media.ifm_cur; 1962 /* 1963 * If the user manually selects a media mode, we need to turn 1964 * on the forced MAC mode bit in the DIAGCTL register. If the 1965 * user happens to choose a full duplex mode, we also need to 1966 * set the 'force full duplex' bit. This applies only to 1967 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 1968 * mode is disabled, and in 1000baseT mode, full duplex is 1969 * always implied, so we turn on the forced mode bit but leave 1970 * the FDX bit cleared. 1971 */ 1972 1973 switch (IFM_SUBTYPE(ife->ifm_media)) { 1974 case IFM_AUTO: 1975 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1976 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1977 break; 1978 case IFM_1000_T: 1979 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1980 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1981 break; 1982 case IFM_100_TX: 1983 case IFM_10_T: 1984 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1985 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 1986 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1987 } else { 1988 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1989 } 1990 break; 1991 default: 1992 aprint_error_dev(&sc->sc_dev, "unknown media type: %x\n", 1993 IFM_SUBTYPE(ife->ifm_media)); 1994 break; 1995 } 1996 } 1997 1998 static int 1999 vge_ioctl(struct ifnet *ifp, u_long command, void *data) 2000 { 2001 struct vge_softc *sc; 2002 struct ifreq *ifr; 2003 int s, error; 2004 2005 sc = ifp->if_softc; 2006 ifr = (struct ifreq *)data; 2007 error = 0; 2008 2009 s = splnet(); 2010 2011 switch (command) { 2012 case SIOCSIFMTU: 2013 if (ifr->ifr_mtu > VGE_JUMBO_MTU) 2014 error = EINVAL; 2015 else if ((error = ifioctl_common(ifp, command, data)) == ENETRESET) 2016 error = 0; 2017 break; 2018 case SIOCSIFFLAGS: 2019 if (ifp->if_flags & IFF_UP) { 2020 if (ifp->if_flags & IFF_RUNNING && 2021 ifp->if_flags & IFF_PROMISC && 2022 (sc->sc_if_flags & IFF_PROMISC) == 0) { 2023 CSR_SETBIT_1(sc, VGE_RXCTL, 2024 VGE_RXCTL_RX_PROMISC); 2025 vge_setmulti(sc); 2026 } else if (ifp->if_flags & IFF_RUNNING && 2027 (ifp->if_flags & IFF_PROMISC) == 0 && 2028 sc->sc_if_flags & IFF_PROMISC) { 2029 CSR_CLRBIT_1(sc, VGE_RXCTL, 2030 VGE_RXCTL_RX_PROMISC); 2031 vge_setmulti(sc); 2032 } else 2033 vge_init(ifp); 2034 } else { 2035 if (ifp->if_flags & IFF_RUNNING) 2036 vge_stop(sc); 2037 } 2038 sc->sc_if_flags = ifp->if_flags; 2039 break; 2040 default: 2041 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 2042 break; 2043 2044 error = 0; 2045 2046 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 2047 ; 2048 else if (ifp->if_flags & IFF_RUNNING) { 2049 /* 2050 * Multicast list has changed; set the hardware filter 2051 * accordingly. 2052 */ 2053 vge_setmulti(sc); 2054 } 2055 break; 2056 } 2057 2058 splx(s); 2059 return error; 2060 } 2061 2062 static void 2063 vge_watchdog(struct ifnet *ifp) 2064 { 2065 struct vge_softc *sc; 2066 int s; 2067 2068 sc = ifp->if_softc; 2069 s = splnet(); 2070 aprint_error_dev(&sc->sc_dev, "watchdog timeout\n"); 2071 ifp->if_oerrors++; 2072 2073 vge_txeof(sc); 2074 vge_rxeof(sc); 2075 2076 vge_init(ifp); 2077 2078 splx(s); 2079 } 2080 2081 /* 2082 * Stop the adapter and free any mbufs allocated to the 2083 * RX and TX lists. 2084 */ 2085 static void 2086 vge_stop(struct vge_softc *sc) 2087 { 2088 struct ifnet *ifp; 2089 struct vge_txsoft *txs; 2090 struct vge_rxsoft *rxs; 2091 int i, s; 2092 2093 ifp = &sc->sc_ethercom.ec_if; 2094 2095 s = splnet(); 2096 ifp->if_timer = 0; 2097 2098 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2099 #ifdef DEVICE_POLLING 2100 ether_poll_deregister(ifp); 2101 #endif /* DEVICE_POLLING */ 2102 2103 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2104 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2105 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2106 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2107 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2108 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2109 2110 if (sc->sc_rx_mhead != NULL) { 2111 m_freem(sc->sc_rx_mhead); 2112 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL; 2113 } 2114 2115 /* Free the TX list buffers. */ 2116 2117 for (i = 0; i < VGE_NTXDESC; i++) { 2118 txs = &sc->sc_txsoft[i]; 2119 if (txs->txs_mbuf != NULL) { 2120 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2121 m_freem(txs->txs_mbuf); 2122 txs->txs_mbuf = NULL; 2123 } 2124 } 2125 2126 /* Free the RX list buffers. */ 2127 2128 for (i = 0; i < VGE_NRXDESC; i++) { 2129 rxs = &sc->sc_rxsoft[i]; 2130 if (rxs->rxs_mbuf != NULL) { 2131 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2132 m_freem(rxs->rxs_mbuf); 2133 rxs->rxs_mbuf = NULL; 2134 } 2135 } 2136 2137 splx(s); 2138 } 2139 2140 #if VGE_POWER_MANAGEMENT 2141 /* 2142 * Device suspend routine. Stop the interface and save some PCI 2143 * settings in case the BIOS doesn't restore them properly on 2144 * resume. 2145 */ 2146 static int 2147 vge_suspend(struct device *dev) 2148 { 2149 struct vge_softc *sc; 2150 int i; 2151 2152 sc = device_get_softc(dev); 2153 2154 vge_stop(sc); 2155 2156 for (i = 0; i < 5; i++) 2157 sc->sc_saved_maps[i] = 2158 pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2159 sc->sc_saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2160 sc->sc_saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2161 sc->sc_saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2162 sc->sc_saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2163 2164 sc->suspended = 1; 2165 2166 return 0; 2167 } 2168 2169 /* 2170 * Device resume routine. Restore some PCI settings in case the BIOS 2171 * doesn't, re-enable busmastering, and restart the interface if 2172 * appropriate. 2173 */ 2174 static int 2175 vge_resume(struct device *dev) 2176 { 2177 struct vge_softc *sc; 2178 struct ifnet *ifp; 2179 int i; 2180 2181 sc = (void *)dev; 2182 ifp = &sc->sc_ethercom.ec_if; 2183 2184 /* better way to do this? */ 2185 for (i = 0; i < 5; i++) 2186 pci_write_config(dev, PCIR_MAPS + i * 4, 2187 sc->sc_saved_maps[i], 4); 2188 pci_write_config(dev, PCIR_BIOS, sc->sc_saved_biosaddr, 4); 2189 pci_write_config(dev, PCIR_INTLINE, sc->sc_saved_intline, 1); 2190 pci_write_config(dev, PCIR_CACHELNSZ, sc->sc_saved_cachelnsz, 1); 2191 pci_write_config(dev, PCIR_LATTIMER, sc->sc_saved_lattimer, 1); 2192 2193 /* reenable busmastering */ 2194 pci_enable_busmaster(dev); 2195 pci_enable_io(dev, SYS_RES_MEMORY); 2196 2197 /* reinitialize interface if necessary */ 2198 if (ifp->if_flags & IFF_UP) 2199 vge_init(sc); 2200 2201 sc->suspended = 0; 2202 2203 return 0; 2204 } 2205 #endif 2206 2207 /* 2208 * Stop all chip I/O so that the kernel's probe routines don't 2209 * get confused by errant DMAs when rebooting. 2210 */ 2211 static void 2212 vge_shutdown(void *arg) 2213 { 2214 struct vge_softc *sc; 2215 2216 sc = arg; 2217 vge_stop(sc); 2218 } 2219