1 /* $NetBSD: if_vge.c,v 1.5 2005/05/02 15:34:32 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD: src/sys/dev/vge/if_vge.c,v 1.5 2005/02/07 19:39:29 glebius Exp 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_vge.c,v 1.5 2005/05/02 15:34:32 yamt Exp $"); 39 40 /* 41 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 42 * 43 * Written by Bill Paul <wpaul@windriver.com> 44 * Senior Networking Software Engineer 45 * Wind River Systems 46 */ 47 48 /* 49 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that 50 * combines a tri-speed ethernet MAC and PHY, with the following 51 * features: 52 * 53 * o Jumbo frame support up to 16K 54 * o Transmit and receive flow control 55 * o IPv4 checksum offload 56 * o VLAN tag insertion and stripping 57 * o TCP large send 58 * o 64-bit multicast hash table filter 59 * o 64 entry CAM filter 60 * o 16K RX FIFO and 48K TX FIFO memory 61 * o Interrupt moderation 62 * 63 * The VT6122 supports up to four transmit DMA queues. The descriptors 64 * in the transmit ring can address up to 7 data fragments; frames which 65 * span more than 7 data buffers must be coalesced, but in general the 66 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 67 * long. The receive descriptors address only a single buffer. 68 * 69 * There are two peculiar design issues with the VT6122. One is that 70 * receive data buffers must be aligned on a 32-bit boundary. This is 71 * not a problem where the VT6122 is used as a LOM device in x86-based 72 * systems, but on architectures that generate unaligned access traps, we 73 * have to do some copying. 74 * 75 * The other issue has to do with the way 64-bit addresses are handled. 76 * The DMA descriptors only allow you to specify 48 bits of addressing 77 * information. The remaining 16 bits are specified using one of the 78 * I/O registers. If you only have a 32-bit system, then this isn't 79 * an issue, but if you have a 64-bit system and more than 4GB of 80 * memory, you must have to make sure your network data buffers reside 81 * in the same 48-bit 'segment.' 82 * 83 * Special thanks to Ryan Fu at VIA Networking for providing documentation 84 * and sample NICs for testing. 85 */ 86 87 #include "bpfilter.h" 88 89 #include <sys/param.h> 90 #include <sys/endian.h> 91 #include <sys/systm.h> 92 #include <sys/sockio.h> 93 #include <sys/mbuf.h> 94 #include <sys/malloc.h> 95 #include <sys/kernel.h> 96 #include <sys/socket.h> 97 98 #include <net/if.h> 99 #include <net/if_arp.h> 100 #include <net/if_ether.h> 101 #include <net/if_dl.h> 102 #include <net/if_media.h> 103 104 #include <net/bpf.h> 105 106 #include <machine/bus.h> 107 108 #include <dev/mii/mii.h> 109 #include <dev/mii/miivar.h> 110 111 #include <dev/pci/pcireg.h> 112 #include <dev/pci/pcivar.h> 113 #include <dev/pci/pcidevs.h> 114 115 #include <dev/pci/if_vgereg.h> 116 #include <dev/pci/if_vgevar.h> 117 118 static int vge_probe (struct device *, struct cfdata *, void *); 119 static void vge_attach (struct device *, struct device *, void *); 120 121 static int vge_encap (struct vge_softc *, struct mbuf *, int); 122 123 static int vge_dma_map_rx_desc (struct vge_softc *, int); 124 static void vge_dma_map_tx_desc (struct vge_softc *, struct mbuf *, int, int); 125 static int vge_allocmem (struct vge_softc *); 126 static int vge_newbuf (struct vge_softc *, int, struct mbuf *); 127 static int vge_rx_list_init (struct vge_softc *); 128 static int vge_tx_list_init (struct vge_softc *); 129 #ifdef VGE_FIXUP_RX 130 static __inline void vge_fixup_rx 131 (struct mbuf *); 132 #endif 133 static void vge_rxeof (struct vge_softc *); 134 static void vge_txeof (struct vge_softc *); 135 static int vge_intr (void *); 136 static void vge_tick (void *); 137 static void vge_start (struct ifnet *); 138 static int vge_ioctl (struct ifnet *, u_long, caddr_t); 139 static int vge_init (struct ifnet *); 140 static void vge_stop (struct vge_softc *); 141 static void vge_watchdog (struct ifnet *); 142 #if VGE_POWER_MANAGEMENT 143 static int vge_suspend (struct device *); 144 static int vge_resume (struct device *); 145 #endif 146 static void vge_shutdown (void *); 147 static int vge_ifmedia_upd (struct ifnet *); 148 static void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 149 150 static void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 151 static void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 152 153 static void vge_miipoll_start (struct vge_softc *); 154 static void vge_miipoll_stop (struct vge_softc *); 155 static int vge_miibus_readreg (struct device *, int, int); 156 static void vge_miibus_writereg (struct device *, int, int, int); 157 static void vge_miibus_statchg (struct device *); 158 159 static void vge_cam_clear (struct vge_softc *); 160 static int vge_cam_set (struct vge_softc *, uint8_t *); 161 static void vge_setmulti (struct vge_softc *); 162 static void vge_reset (struct vge_softc *); 163 164 #define VGE_PCI_LOIO 0x10 165 #define VGE_PCI_LOMEM 0x14 166 167 CFATTACH_DECL(vge, sizeof(struct vge_softc), 168 vge_probe, vge_attach, NULL, NULL); 169 170 /* 171 * Defragment mbuf chain contents to be as linear as possible. 172 * Returns new mbuf chain on success, NULL on failure. Old mbuf 173 * chain is always freed. 174 * XXX temporary until there would be generic function doing this. 175 */ 176 #define m_defrag vge_m_defrag 177 struct mbuf * vge_m_defrag(struct mbuf *, int); 178 179 struct mbuf * 180 vge_m_defrag(struct mbuf *mold, int flags) 181 { 182 struct mbuf *m0, *mn, *n; 183 size_t sz = mold->m_pkthdr.len; 184 185 #ifdef DIAGNOSTIC 186 if ((mold->m_flags & M_PKTHDR) == 0) 187 panic("m_defrag: not a mbuf chain header"); 188 #endif 189 190 MGETHDR(m0, flags, MT_DATA); 191 if (m0 == NULL) 192 return NULL; 193 m0->m_pkthdr.len = mold->m_pkthdr.len; 194 mn = m0; 195 196 do { 197 if (sz > MHLEN) { 198 MCLGET(mn, M_DONTWAIT); 199 if ((mn->m_flags & M_EXT) == 0) { 200 m_freem(m0); 201 return NULL; 202 } 203 } 204 205 mn->m_len = MIN(sz, MCLBYTES); 206 207 m_copydata(mold, mold->m_pkthdr.len - sz, mn->m_len, 208 mtod(mn, caddr_t)); 209 210 sz -= mn->m_len; 211 212 if (sz > 0) { 213 /* need more mbufs */ 214 MGET(n, M_NOWAIT, MT_DATA); 215 if (n == NULL) { 216 m_freem(m0); 217 return NULL; 218 } 219 220 mn->m_next = n; 221 mn = n; 222 } 223 } while (sz > 0); 224 225 return m0; 226 } 227 228 /* 229 * Read a word of data stored in the EEPROM at address 'addr.' 230 */ 231 static void 232 vge_eeprom_getword(sc, addr, dest) 233 struct vge_softc *sc; 234 int addr; 235 u_int16_t *dest; 236 { 237 register int i; 238 u_int16_t word = 0; 239 240 /* 241 * Enter EEPROM embedded programming mode. In order to 242 * access the EEPROM at all, we first have to set the 243 * EELOAD bit in the CHIPCFG2 register. 244 */ 245 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 246 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 247 248 /* Select the address of the word we want to read */ 249 CSR_WRITE_1(sc, VGE_EEADDR, addr); 250 251 /* Issue read command */ 252 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 253 254 /* Wait for the done bit to be set. */ 255 for (i = 0; i < VGE_TIMEOUT; i++) { 256 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 257 break; 258 } 259 260 if (i == VGE_TIMEOUT) { 261 printf("%s: EEPROM read timed out\n", sc->sc_dev.dv_xname); 262 *dest = 0; 263 return; 264 } 265 266 /* Read the result */ 267 word = CSR_READ_2(sc, VGE_EERDDAT); 268 269 /* Turn off EEPROM access mode. */ 270 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 271 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 272 273 *dest = word; 274 275 return; 276 } 277 278 /* 279 * Read a sequence of words from the EEPROM. 280 */ 281 static void 282 vge_read_eeprom(sc, dest, off, cnt, swap) 283 struct vge_softc *sc; 284 caddr_t dest; 285 int off; 286 int cnt; 287 int swap; 288 { 289 int i; 290 u_int16_t word = 0, *ptr; 291 292 for (i = 0; i < cnt; i++) { 293 vge_eeprom_getword(sc, off + i, &word); 294 ptr = (u_int16_t *)(dest + (i * 2)); 295 if (swap) 296 *ptr = ntohs(word); 297 else 298 *ptr = word; 299 } 300 } 301 302 static void 303 vge_miipoll_stop(sc) 304 struct vge_softc *sc; 305 { 306 int i; 307 308 CSR_WRITE_1(sc, VGE_MIICMD, 0); 309 310 for (i = 0; i < VGE_TIMEOUT; i++) { 311 DELAY(1); 312 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 313 break; 314 } 315 316 if (i == VGE_TIMEOUT) { 317 printf("%s: failed to idle MII autopoll\n", 318 sc->sc_dev.dv_xname); 319 } 320 321 return; 322 } 323 324 static void 325 vge_miipoll_start(sc) 326 struct vge_softc *sc; 327 { 328 int i; 329 330 /* First, make sure we're idle. */ 331 332 CSR_WRITE_1(sc, VGE_MIICMD, 0); 333 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 334 335 for (i = 0; i < VGE_TIMEOUT; i++) { 336 DELAY(1); 337 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 338 break; 339 } 340 341 if (i == VGE_TIMEOUT) { 342 printf("%s: failed to idle MII autopoll\n", 343 sc->sc_dev.dv_xname); 344 return; 345 } 346 347 /* Now enable auto poll mode. */ 348 349 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 350 351 /* And make sure it started. */ 352 353 for (i = 0; i < VGE_TIMEOUT; i++) { 354 DELAY(1); 355 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 356 break; 357 } 358 359 if (i == VGE_TIMEOUT) { 360 printf("%s: failed to start MII autopoll\n", 361 sc->sc_dev.dv_xname); 362 } 363 } 364 365 static int 366 vge_miibus_readreg(dev, phy, reg) 367 struct device *dev; 368 int phy, reg; 369 { 370 struct vge_softc *sc = (struct vge_softc *)dev; 371 int i; 372 u_int16_t rval = 0; 373 374 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 375 return(0); 376 377 VGE_LOCK(sc); 378 vge_miipoll_stop(sc); 379 380 /* Specify the register we want to read. */ 381 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 382 383 /* Issue read command. */ 384 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 385 386 /* Wait for the read command bit to self-clear. */ 387 for (i = 0; i < VGE_TIMEOUT; i++) { 388 DELAY(1); 389 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 390 break; 391 } 392 393 if (i == VGE_TIMEOUT) 394 printf("%s: MII read timed out\n", sc->sc_dev.dv_xname); 395 else 396 rval = CSR_READ_2(sc, VGE_MIIDATA); 397 398 vge_miipoll_start(sc); 399 VGE_UNLOCK(sc); 400 401 return (rval); 402 } 403 404 static void 405 vge_miibus_writereg(dev, phy, reg, data) 406 struct device *dev; 407 int phy, reg, data; 408 { 409 struct vge_softc *sc = (struct vge_softc *)dev; 410 int i; 411 412 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 413 return; 414 415 VGE_LOCK(sc); 416 vge_miipoll_stop(sc); 417 418 /* Specify the register we want to write. */ 419 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 420 421 /* Specify the data we want to write. */ 422 CSR_WRITE_2(sc, VGE_MIIDATA, data); 423 424 /* Issue write command. */ 425 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 426 427 /* Wait for the write command bit to self-clear. */ 428 for (i = 0; i < VGE_TIMEOUT; i++) { 429 DELAY(1); 430 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 431 break; 432 } 433 434 if (i == VGE_TIMEOUT) { 435 printf("%s: MII write timed out\n", sc->sc_dev.dv_xname); 436 } 437 438 vge_miipoll_start(sc); 439 VGE_UNLOCK(sc); 440 } 441 442 static void 443 vge_cam_clear(sc) 444 struct vge_softc *sc; 445 { 446 int i; 447 448 /* 449 * Turn off all the mask bits. This tells the chip 450 * that none of the entries in the CAM filter are valid. 451 * desired entries will be enabled as we fill the filter in. 452 */ 453 454 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 455 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 456 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 457 for (i = 0; i < 8; i++) 458 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 459 460 /* Clear the VLAN filter too. */ 461 462 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 463 for (i = 0; i < 8; i++) 464 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 465 466 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 467 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 468 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 469 470 sc->vge_camidx = 0; 471 472 return; 473 } 474 475 static int 476 vge_cam_set(sc, addr) 477 struct vge_softc *sc; 478 uint8_t *addr; 479 { 480 int i, error = 0; 481 482 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 483 return(ENOSPC); 484 485 /* Select the CAM data page. */ 486 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 487 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 488 489 /* Set the filter entry we want to update and enable writing. */ 490 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 491 492 /* Write the address to the CAM registers */ 493 for (i = 0; i < ETHER_ADDR_LEN; i++) 494 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 495 496 /* Issue a write command. */ 497 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 498 499 /* Wake for it to clear. */ 500 for (i = 0; i < VGE_TIMEOUT; i++) { 501 DELAY(1); 502 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 503 break; 504 } 505 506 if (i == VGE_TIMEOUT) { 507 printf("%s: setting CAM filter failed\n", sc->sc_dev.dv_xname); 508 error = EIO; 509 goto fail; 510 } 511 512 /* Select the CAM mask page. */ 513 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 514 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 515 516 /* Set the mask bit that enables this filter. */ 517 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 518 1<<(sc->vge_camidx & 7)); 519 520 sc->vge_camidx++; 521 522 fail: 523 /* Turn off access to CAM. */ 524 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 525 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 526 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 527 528 return (error); 529 } 530 531 /* 532 * Program the multicast filter. We use the 64-entry CAM filter 533 * for perfect filtering. If there's more than 64 multicast addresses, 534 * we use the hash filter insted. 535 */ 536 static void 537 vge_setmulti(sc) 538 struct vge_softc *sc; 539 { 540 struct ifnet *ifp; 541 int error = 0; 542 u_int32_t h, hashes[2] = { 0, 0 }; 543 struct ether_multi *enm; 544 struct ether_multistep step; 545 546 ifp = &sc->sc_ethercom.ec_if; 547 548 /* First, zot all the multicast entries. */ 549 vge_cam_clear(sc); 550 CSR_WRITE_4(sc, VGE_MAR0, 0); 551 CSR_WRITE_4(sc, VGE_MAR1, 0); 552 553 /* 554 * If the user wants allmulti or promisc mode, enable reception 555 * of all multicast frames. 556 */ 557 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 558 allmulti: 559 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 560 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 561 return; 562 } 563 564 /* Now program new ones */ 565 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 566 while(enm != NULL) { 567 /* 568 * If multicast range, fall back to ALLMULTI. 569 */ 570 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 571 ETHER_ADDR_LEN) != 0) 572 goto allmulti; 573 574 error = vge_cam_set(sc, 575 LLADDR((struct sockaddr_dl *)enm->enm_addrlo)); 576 if (error) 577 break; 578 579 ETHER_NEXT_MULTI(step, enm); 580 } 581 582 /* If there were too many addresses, use the hash filter. */ 583 if (error) { 584 vge_cam_clear(sc); 585 586 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 587 while(enm != NULL) { 588 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 589 enm->enm_addrlo), ETHER_ADDR_LEN) >> 26; 590 if (h < 32) 591 hashes[0] |= (1 << h); 592 else 593 hashes[1] |= (1 << (h - 32)); 594 } 595 596 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 597 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 598 } 599 600 return; 601 } 602 603 static void 604 vge_reset(sc) 605 struct vge_softc *sc; 606 { 607 register int i; 608 609 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 610 611 for (i = 0; i < VGE_TIMEOUT; i++) { 612 DELAY(5); 613 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 614 break; 615 } 616 617 if (i == VGE_TIMEOUT) { 618 printf("%s: soft reset timed out", sc->sc_dev.dv_xname); 619 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 620 DELAY(2000); 621 } 622 623 DELAY(5000); 624 625 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 626 627 for (i = 0; i < VGE_TIMEOUT; i++) { 628 DELAY(5); 629 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 630 break; 631 } 632 633 if (i == VGE_TIMEOUT) { 634 printf("%s: EEPROM reload timed out\n", sc->sc_dev.dv_xname); 635 return; 636 } 637 638 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 639 640 return; 641 } 642 643 /* 644 * Probe for a VIA gigabit chip. Check the PCI vendor and device 645 * IDs against our list and return a device name if we find a match. 646 */ 647 static int 648 vge_probe(struct device *parent, struct cfdata *match, void *aux) 649 { 650 struct pci_attach_args *pa = aux; 651 652 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH 653 && PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_VIATECH_VT612X) 654 return 1; 655 656 return (0); 657 } 658 659 static int 660 vge_dma_map_rx_desc(sc, idx) 661 struct vge_softc *sc; 662 int idx; 663 { 664 struct vge_rx_desc *d = NULL; 665 bus_dma_segment_t *segs; 666 667 /* 668 * Map the segment array into descriptors. 669 */ 670 671 d = &sc->vge_ldata.vge_rx_list[idx]; 672 673 /* If this descriptor is still owned by the chip, bail. */ 674 675 if (le32toh(d->vge_sts) & VGE_RDSTS_OWN) { 676 printf("%s: tried to map busy descriptor\n", 677 sc->sc_dev.dv_xname); 678 return (EBUSY); 679 } 680 681 segs = sc->vge_ldata.vge_rx_dmamap[idx]->dm_segs; 682 683 d->vge_buflen = htole16(VGE_BUFLEN(segs[0].ds_len) | VGE_RXDESC_I); 684 d->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 685 d->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 686 d->vge_sts = 0; 687 d->vge_ctl = 0; 688 689 return (0); 690 } 691 692 static void 693 vge_dma_map_tx_desc(sc, m0, idx, flags) 694 struct vge_softc *sc; 695 struct mbuf *m0; 696 int idx, flags; 697 { 698 struct vge_tx_desc *d = &sc->vge_ldata.vge_tx_list[idx]; 699 struct vge_tx_frag *f; 700 int i = 0; 701 bus_dma_segment_t *segs; 702 size_t sz; 703 bus_dmamap_t map = sc->vge_ldata.vge_tx_dmamap[idx]; 704 705 /* Map the segment array into descriptors. */ 706 707 segs = map->dm_segs; 708 for (i = 0; i < map->dm_nsegs; i++) { 709 f = &d->vge_frag[i]; 710 f->vge_buflen = htole16(VGE_BUFLEN(segs[i].ds_len)); 711 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[i].ds_addr)); 712 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[i].ds_addr) & 0xFFFF); 713 } 714 715 /* Argh. This chip does not autopad short frames */ 716 717 sz = m0->m_pkthdr.len; 718 if (m0->m_pkthdr.len < VGE_MIN_FRAMELEN) { 719 f = &d->vge_frag[i]; 720 f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - sz)); 721 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 722 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 723 sz = VGE_MIN_FRAMELEN; 724 i++; 725 } 726 727 /* 728 * When telling the chip how many segments there are, we 729 * must use nsegs + 1 instead of just nsegs. Darned if I 730 * know why. 731 */ 732 i++; 733 734 d->vge_sts = sz << 16; 735 d->vge_ctl = flags|(i << 28)|VGE_TD_LS_NORM; 736 737 if (sz > ETHERMTU + ETHER_HDR_LEN) 738 d->vge_ctl |= VGE_TDCTL_JUMBO; 739 } 740 741 static int 742 vge_allocmem(sc) 743 struct vge_softc *sc; 744 { 745 int error; 746 int nseg; 747 int i; 748 bus_dma_segment_t seg; 749 750 /* 751 * Allocate map for TX descriptor list. 752 */ 753 error = bus_dmamap_create(sc->vge_dmat, 754 round_page(VGE_TX_LIST_SZ), 1, round_page(VGE_TX_LIST_SZ), 755 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, 756 &sc->vge_ldata.vge_tx_list_map); 757 if (error) { 758 printf("%s: could not allocate TX dma list map\n", 759 sc->sc_dev.dv_xname); 760 return (ENOMEM); 761 } 762 763 /* 764 * Allocate memory for TX descriptor list. 765 */ 766 767 error = bus_dmamem_alloc(sc->vge_dmat, VGE_TX_LIST_SZ, VGE_RING_ALIGN, 768 0, &seg, 1, &nseg, BUS_DMA_NOWAIT); 769 if (error) { 770 printf("%s: could not allocate TX ring dma memory\n", 771 sc->sc_dev.dv_xname); 772 return (ENOMEM); 773 } 774 775 /* Map the memory to kernel VA space */ 776 777 error = bus_dmamem_map(sc->vge_dmat, &seg, nseg, seg.ds_len, 778 (caddr_t *) &sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT); 779 if (error) { 780 printf("%s: could not map TX ring dma memory\n", 781 sc->sc_dev.dv_xname); 782 return (ENOMEM); 783 } 784 785 /* Load the map for the TX ring. */ 786 error = bus_dmamap_load(sc->vge_dmat, sc->vge_ldata.vge_tx_list_map, 787 sc->vge_ldata.vge_tx_list, seg.ds_len, NULL, BUS_DMA_NOWAIT); 788 if (error) { 789 printf("%s: could not load TX ring dma memory\n", 790 sc->sc_dev.dv_xname); 791 return (ENOMEM); 792 } 793 794 sc->vge_ldata.vge_tx_list_addr = 795 sc->vge_ldata.vge_tx_list_map->dm_segs[0].ds_addr; 796 797 /* Create DMA maps for TX buffers */ 798 799 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 800 error = bus_dmamap_create(sc->vge_dmat, VGE_TX_MAXLEN, 801 VGE_TX_FRAGS, VGE_TX_MAXLEN, 0, 802 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW, 803 &sc->vge_ldata.vge_tx_dmamap[i]); 804 if (error) { 805 printf("%s: can't create DMA map for TX\n", 806 sc->sc_dev.dv_xname); 807 return (ENOMEM); 808 } 809 } 810 811 /* 812 * Allocate map for RX descriptor list. 813 */ 814 error = bus_dmamap_create(sc->vge_dmat, 815 round_page(VGE_RX_LIST_SZ), 1, round_page(VGE_RX_LIST_SZ), 816 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, 817 &sc->vge_ldata.vge_rx_list_map); 818 if (error) { 819 printf("%s: could not allocate RX dma list map\n", 820 sc->sc_dev.dv_xname); 821 return (ENOMEM); 822 } 823 824 /* Allocate DMA'able memory for the RX ring */ 825 826 error = bus_dmamem_alloc(sc->vge_dmat, VGE_RX_LIST_SZ, VGE_RING_ALIGN, 827 0, &seg, 1, &nseg, BUS_DMA_NOWAIT); 828 if (error) 829 return (ENOMEM); 830 831 /* Map the memory to kernel VA space */ 832 833 error = bus_dmamem_map(sc->vge_dmat, &seg, nseg, seg.ds_len, 834 (caddr_t *) &sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT); 835 if (error) 836 return (ENOMEM); 837 838 /* Load the map for the RX ring. */ 839 error = bus_dmamap_load(sc->vge_dmat, sc->vge_ldata.vge_rx_list_map, 840 sc->vge_ldata.vge_rx_list, seg.ds_len, NULL, BUS_DMA_NOWAIT); 841 if (error) { 842 printf("%s: could not load RX ring dma memory\n", 843 sc->sc_dev.dv_xname); 844 return (ENOMEM); 845 } 846 847 sc->vge_ldata.vge_rx_list_addr = 848 sc->vge_ldata.vge_rx_list_map->dm_segs[0].ds_addr; 849 850 /* Create DMA maps for RX buffers */ 851 852 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 853 error = bus_dmamap_create(sc->vge_dmat, MCLBYTES, 854 1, MCLBYTES, 0, BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW, 855 &sc->vge_ldata.vge_rx_dmamap[i]); 856 if (error) { 857 printf("%s: can't create DMA map for RX\n", 858 sc->sc_dev.dv_xname); 859 return (ENOMEM); 860 } 861 } 862 863 return (0); 864 } 865 866 /* 867 * Attach the interface. Allocate softc structures, do ifmedia 868 * setup and ethernet/BPF attach. 869 */ 870 static void 871 vge_attach(struct device *parent, struct device *self, void *aux) 872 { 873 u_char eaddr[ETHER_ADDR_LEN]; 874 struct vge_softc *sc = (struct vge_softc *)self; 875 struct ifnet *ifp; 876 struct pci_attach_args *pa = aux; 877 pci_chipset_tag_t pc = pa->pa_pc; 878 const char *intrstr; 879 pci_intr_handle_t ih; 880 881 aprint_normal(": VIA VT612X Gigabit Ethernet (rev. %#x)\n", 882 PCI_REVISION(pa->pa_class)); 883 884 /* Make sure bus-mastering is enabled */ 885 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 886 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 887 PCI_COMMAND_MASTER_ENABLE); 888 889 /* 890 * Map control/status registers. 891 */ 892 if (0 != pci_mapreg_map(pa, VGE_PCI_LOMEM, 893 PCI_MAPREG_TYPE_MEM, BUS_SPACE_MAP_LINEAR, 894 &sc->vge_btag, &sc->vge_bhandle, NULL, NULL)) { 895 aprint_error("%s: couldn't map memory\n", 896 sc->sc_dev.dv_xname); 897 return; 898 } 899 900 /* 901 * Map and establish our interrupt. 902 */ 903 if (pci_intr_map(pa, &ih)) { 904 aprint_error("%s: unable to map interrupt\n", 905 sc->sc_dev.dv_xname); 906 return; 907 } 908 intrstr = pci_intr_string(pc, ih); 909 sc->vge_intrhand = pci_intr_establish(pc, ih, IPL_NET, vge_intr, sc); 910 if (sc->vge_intrhand == NULL) { 911 printf("%s: unable to establish interrupt", 912 sc->sc_dev.dv_xname); 913 if (intrstr != NULL) 914 printf(" at %s", intrstr); 915 printf("\n"); 916 return; 917 } 918 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 919 920 /* Reset the adapter. */ 921 vge_reset(sc); 922 923 /* 924 * Get station address from the EEPROM. 925 */ 926 vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0); 927 bcopy(eaddr, (char *)&sc->vge_eaddr, ETHER_ADDR_LEN); 928 929 printf("%s: Ethernet address: %s\n", sc->sc_dev.dv_xname, 930 ether_sprintf(eaddr)); 931 932 /* 933 * Use the 32bit tag. Hardware supports 48bit physical addresses, 934 * but we don't use that for now. 935 */ 936 sc->vge_dmat = pa->pa_dmat; 937 938 if (vge_allocmem(sc)) 939 return; 940 941 ifp = &sc->sc_ethercom.ec_if; 942 ifp->if_softc = sc; 943 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 944 ifp->if_mtu = ETHERMTU; 945 ifp->if_baudrate = IF_Gbps(1); 946 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 947 ifp->if_ioctl = vge_ioctl; 948 ifp->if_start = vge_start; 949 950 /* 951 * We can support 802.1Q VLAN-sized frames and jumbo 952 * Ethernet frames. 953 */ 954 sc->sc_ethercom.ec_capabilities |= 955 ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU | 956 ETHERCAP_VLAN_HWTAGGING; 957 958 /* 959 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 960 */ 961 ifp->if_capabilities |= 962 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 963 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 964 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 965 966 #ifdef DEVICE_POLLING 967 #ifdef IFCAP_POLLING 968 ifp->if_capabilities |= IFCAP_POLLING; 969 #endif 970 #endif 971 ifp->if_watchdog = vge_watchdog; 972 ifp->if_init = vge_init; 973 IFQ_SET_MAXLEN(&ifp->if_snd, max(VGE_IFQ_MAXLEN, IFQ_MAXLEN)); 974 975 /* 976 * Initialize our media structures and probe the MII. 977 */ 978 sc->sc_mii.mii_ifp = ifp; 979 sc->sc_mii.mii_readreg = vge_miibus_readreg; 980 sc->sc_mii.mii_writereg = vge_miibus_writereg; 981 sc->sc_mii.mii_statchg = vge_miibus_statchg; 982 ifmedia_init(&sc->sc_mii.mii_media, 0, vge_ifmedia_upd, 983 vge_ifmedia_sts); 984 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 985 MII_OFFSET_ANY, MIIF_DOPAUSE); 986 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 987 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 988 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 989 } else 990 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 991 992 /* 993 * Attach the interface. 994 */ 995 if_attach(ifp); 996 ether_ifattach(ifp, eaddr); 997 998 callout_init(&sc->vge_timeout); 999 callout_setfunc(&sc->vge_timeout, vge_tick, sc); 1000 1001 /* 1002 * Make sure the interface is shutdown during reboot. 1003 */ 1004 if (shutdownhook_establish(vge_shutdown, sc) == NULL) { 1005 printf("%s: WARNING: unable to establish shutdown hook\n", 1006 sc->sc_dev.dv_xname); 1007 } 1008 } 1009 1010 static int 1011 vge_newbuf(sc, idx, m) 1012 struct vge_softc *sc; 1013 int idx; 1014 struct mbuf *m; 1015 { 1016 struct mbuf *n = NULL; 1017 int i, error; 1018 1019 if (m == NULL) { 1020 n = m_gethdr(M_DONTWAIT, MT_DATA); 1021 if (n == NULL) 1022 return (ENOBUFS); 1023 1024 m_clget(n, M_DONTWAIT); 1025 if ((n->m_flags & M_EXT) == 0) { 1026 m_freem(n); 1027 return (ENOBUFS); 1028 } 1029 1030 m = n; 1031 } else 1032 m->m_data = m->m_ext.ext_buf; 1033 1034 1035 #ifdef VGE_FIXUP_RX 1036 /* 1037 * This is part of an evil trick to deal with non-x86 platforms. 1038 * The VIA chip requires RX buffers to be aligned on 32-bit 1039 * boundaries, but that will hose non-x86 machines. To get around 1040 * this, we leave some empty space at the start of each buffer 1041 * and for non-x86 hosts, we copy the buffer back two bytes 1042 * to achieve word alignment. This is slightly more efficient 1043 * than allocating a new buffer, copying the contents, and 1044 * discarding the old buffer. 1045 */ 1046 m->m_len = m->m_pkthdr.len = MCLBYTES - VGE_ETHER_ALIGN; 1047 m_adj(m, VGE_ETHER_ALIGN); 1048 #else 1049 m->m_len = m->m_pkthdr.len = MCLBYTES; 1050 #endif 1051 1052 error = bus_dmamap_load_mbuf(sc->vge_dmat, 1053 sc->vge_ldata.vge_rx_dmamap[idx], m, BUS_DMA_NOWAIT); 1054 if (error || vge_dma_map_rx_desc(sc, idx)) { 1055 if (n != NULL) 1056 m_freem(n); 1057 return (ENOMEM); 1058 } 1059 1060 /* 1061 * Note: the manual fails to document the fact that for 1062 * proper opration, the driver needs to replentish the RX 1063 * DMA ring 4 descriptors at a time (rather than one at a 1064 * time, like most chips). We can allocate the new buffers 1065 * but we should not set the OWN bits until we're ready 1066 * to hand back 4 of them in one shot. 1067 */ 1068 1069 #define VGE_RXCHUNK 4 1070 sc->vge_rx_consumed++; 1071 if (sc->vge_rx_consumed == VGE_RXCHUNK) { 1072 for (i = idx; i != idx - sc->vge_rx_consumed; i--) 1073 sc->vge_ldata.vge_rx_list[i].vge_sts |= 1074 htole32(VGE_RDSTS_OWN); 1075 sc->vge_rx_consumed = 0; 1076 } 1077 1078 sc->vge_ldata.vge_rx_mbuf[idx] = m; 1079 1080 bus_dmamap_sync(sc->vge_dmat, 1081 sc->vge_ldata.vge_rx_dmamap[idx], 1082 0, sc->vge_ldata.vge_rx_dmamap[idx]->dm_mapsize, 1083 BUS_DMASYNC_PREREAD); 1084 1085 return (0); 1086 } 1087 1088 static int 1089 vge_tx_list_init(sc) 1090 struct vge_softc *sc; 1091 { 1092 bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); 1093 bzero ((char *)&sc->vge_ldata.vge_tx_mbuf, 1094 (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); 1095 1096 bus_dmamap_sync(sc->vge_dmat, 1097 sc->vge_ldata.vge_tx_list_map, 1098 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1099 BUS_DMASYNC_PREWRITE); 1100 1101 sc->vge_ldata.vge_tx_prodidx = 0; 1102 sc->vge_ldata.vge_tx_considx = 0; 1103 sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; 1104 1105 return (0); 1106 } 1107 1108 static int 1109 vge_rx_list_init(sc) 1110 struct vge_softc *sc; 1111 { 1112 int i; 1113 1114 bzero ((char *)sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); 1115 bzero ((char *)&sc->vge_ldata.vge_rx_mbuf, 1116 (VGE_RX_DESC_CNT * sizeof(struct mbuf *))); 1117 1118 sc->vge_rx_consumed = 0; 1119 1120 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1121 if (vge_newbuf(sc, i, NULL) == ENOBUFS) 1122 return (ENOBUFS); 1123 } 1124 1125 /* Flush the RX descriptors */ 1126 1127 bus_dmamap_sync(sc->vge_dmat, 1128 sc->vge_ldata.vge_rx_list_map, 1129 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 1130 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1131 1132 sc->vge_ldata.vge_rx_prodidx = 0; 1133 sc->vge_rx_consumed = 0; 1134 sc->vge_head = sc->vge_tail = NULL; 1135 1136 return (0); 1137 } 1138 1139 #ifdef VGE_FIXUP_RX 1140 static __inline void 1141 vge_fixup_rx(m) 1142 struct mbuf *m; 1143 { 1144 int i; 1145 uint16_t *src, *dst; 1146 1147 src = mtod(m, uint16_t *); 1148 dst = src - 1; 1149 1150 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1151 *dst++ = *src++; 1152 1153 m->m_data -= ETHER_ALIGN; 1154 1155 return; 1156 } 1157 #endif 1158 1159 /* 1160 * RX handler. We support the reception of jumbo frames that have 1161 * been fragmented across multiple 2K mbuf cluster buffers. 1162 */ 1163 static void 1164 vge_rxeof(sc) 1165 struct vge_softc *sc; 1166 { 1167 struct mbuf *m; 1168 struct ifnet *ifp; 1169 int i, total_len; 1170 int lim = 0; 1171 struct vge_rx_desc *cur_rx; 1172 u_int32_t rxstat, rxctl; 1173 1174 VGE_LOCK_ASSERT(sc); 1175 ifp = &sc->sc_ethercom.ec_if; 1176 i = sc->vge_ldata.vge_rx_prodidx; 1177 1178 /* Invalidate the descriptor memory */ 1179 1180 bus_dmamap_sync(sc->vge_dmat, 1181 sc->vge_ldata.vge_rx_list_map, 1182 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 1183 BUS_DMASYNC_POSTREAD); 1184 1185 while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { 1186 1187 #ifdef DEVICE_POLLING 1188 if (ifp->if_flags & IFF_POLLING) { 1189 if (sc->rxcycles <= 0) 1190 break; 1191 sc->rxcycles--; 1192 } 1193 #endif /* DEVICE_POLLING */ 1194 1195 cur_rx = &sc->vge_ldata.vge_rx_list[i]; 1196 m = sc->vge_ldata.vge_rx_mbuf[i]; 1197 total_len = VGE_RXBYTES(cur_rx); 1198 rxstat = le32toh(cur_rx->vge_sts); 1199 rxctl = le32toh(cur_rx->vge_ctl); 1200 1201 /* Invalidate the RX mbuf and unload its map */ 1202 1203 bus_dmamap_sync(sc->vge_dmat, 1204 sc->vge_ldata.vge_rx_dmamap[i], 1205 0, sc->vge_ldata.vge_rx_dmamap[i]->dm_mapsize, 1206 BUS_DMASYNC_POSTWRITE); 1207 bus_dmamap_unload(sc->vge_dmat, 1208 sc->vge_ldata.vge_rx_dmamap[i]); 1209 1210 /* 1211 * If the 'start of frame' bit is set, this indicates 1212 * either the first fragment in a multi-fragment receive, 1213 * or an intermediate fragment. Either way, we want to 1214 * accumulate the buffers. 1215 */ 1216 if (rxstat & VGE_RXPKT_SOF) { 1217 m->m_len = MCLBYTES - VGE_ETHER_ALIGN; 1218 if (sc->vge_head == NULL) 1219 sc->vge_head = sc->vge_tail = m; 1220 else { 1221 m->m_flags &= ~M_PKTHDR; 1222 sc->vge_tail->m_next = m; 1223 sc->vge_tail = m; 1224 } 1225 vge_newbuf(sc, i, NULL); 1226 VGE_RX_DESC_INC(i); 1227 continue; 1228 } 1229 1230 /* 1231 * Bad/error frames will have the RXOK bit cleared. 1232 * However, there's one error case we want to allow: 1233 * if a VLAN tagged frame arrives and the chip can't 1234 * match it against the CAM filter, it considers this 1235 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1236 * We don't want to drop the frame though: our VLAN 1237 * filtering is done in software. 1238 */ 1239 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1240 && !(rxstat & VGE_RDSTS_CSUMERR)) { 1241 ifp->if_ierrors++; 1242 /* 1243 * If this is part of a multi-fragment packet, 1244 * discard all the pieces. 1245 */ 1246 if (sc->vge_head != NULL) { 1247 m_freem(sc->vge_head); 1248 sc->vge_head = sc->vge_tail = NULL; 1249 } 1250 vge_newbuf(sc, i, m); 1251 VGE_RX_DESC_INC(i); 1252 continue; 1253 } 1254 1255 /* 1256 * If allocating a replacement mbuf fails, 1257 * reload the current one. 1258 */ 1259 1260 if (vge_newbuf(sc, i, NULL)) { 1261 ifp->if_ierrors++; 1262 if (sc->vge_head != NULL) { 1263 m_freem(sc->vge_head); 1264 sc->vge_head = sc->vge_tail = NULL; 1265 } 1266 vge_newbuf(sc, i, m); 1267 VGE_RX_DESC_INC(i); 1268 continue; 1269 } 1270 1271 VGE_RX_DESC_INC(i); 1272 1273 if (sc->vge_head != NULL) { 1274 m->m_len = total_len % (MCLBYTES - VGE_ETHER_ALIGN); 1275 /* 1276 * Special case: if there's 4 bytes or less 1277 * in this buffer, the mbuf can be discarded: 1278 * the last 4 bytes is the CRC, which we don't 1279 * care about anyway. 1280 */ 1281 if (m->m_len <= ETHER_CRC_LEN) { 1282 sc->vge_tail->m_len -= 1283 (ETHER_CRC_LEN - m->m_len); 1284 m_freem(m); 1285 } else { 1286 m->m_len -= ETHER_CRC_LEN; 1287 m->m_flags &= ~M_PKTHDR; 1288 sc->vge_tail->m_next = m; 1289 } 1290 m = sc->vge_head; 1291 sc->vge_head = sc->vge_tail = NULL; 1292 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1293 } else 1294 m->m_pkthdr.len = m->m_len = 1295 (total_len - ETHER_CRC_LEN); 1296 1297 #ifdef VGE_FIXUP_RX 1298 vge_fixup_rx(m); 1299 #endif 1300 ifp->if_ipackets++; 1301 m->m_pkthdr.rcvif = ifp; 1302 1303 /* Do RX checksumming if enabled */ 1304 if (ifp->if_csum_flags_rx & M_CSUM_IPv4) { 1305 1306 /* Check IP header checksum */ 1307 if (rxctl & VGE_RDCTL_IPPKT) 1308 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1309 if ((rxctl & VGE_RDCTL_IPCSUMOK) == 0) 1310 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1311 } 1312 1313 if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) { 1314 /* Check UDP checksum */ 1315 if (rxctl & VGE_RDCTL_TCPPKT) 1316 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1317 1318 if ((rxctl & VGE_RDCTL_PROTOCSUMOK) == 0) 1319 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1320 } 1321 1322 if (ifp->if_csum_flags_rx & M_CSUM_UDPv4) { 1323 /* Check UDP checksum */ 1324 if (rxctl & VGE_RDCTL_UDPPKT) 1325 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1326 1327 if ((rxctl & VGE_RDCTL_PROTOCSUMOK) == 0) 1328 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1329 } 1330 1331 if (rxstat & VGE_RDSTS_VTAG) 1332 VLAN_INPUT_TAG(ifp, m, 1333 ntohs((rxctl & VGE_RDCTL_VLANID)), continue); 1334 1335 #if NBPFILTER > 0 1336 /* 1337 * Handle BPF listeners. 1338 */ 1339 if (ifp->if_bpf) 1340 bpf_mtap(ifp->if_bpf, m); 1341 #endif 1342 1343 VGE_UNLOCK(sc); 1344 (*ifp->if_input)(ifp, m); 1345 VGE_LOCK(sc); 1346 1347 lim++; 1348 if (lim == VGE_RX_DESC_CNT) 1349 break; 1350 1351 } 1352 1353 /* Flush the RX DMA ring */ 1354 1355 bus_dmamap_sync(sc->vge_dmat, 1356 sc->vge_ldata.vge_rx_list_map, 1357 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 1358 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1359 1360 sc->vge_ldata.vge_rx_prodidx = i; 1361 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1362 1363 1364 return; 1365 } 1366 1367 static void 1368 vge_txeof(sc) 1369 struct vge_softc *sc; 1370 { 1371 struct ifnet *ifp; 1372 u_int32_t txstat; 1373 int idx; 1374 1375 ifp = &sc->sc_ethercom.ec_if; 1376 idx = sc->vge_ldata.vge_tx_considx; 1377 1378 /* Invalidate the TX descriptor list */ 1379 1380 bus_dmamap_sync(sc->vge_dmat, 1381 sc->vge_ldata.vge_tx_list_map, 1382 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1383 BUS_DMASYNC_POSTREAD); 1384 1385 while (idx != sc->vge_ldata.vge_tx_prodidx) { 1386 1387 txstat = le32toh(sc->vge_ldata.vge_tx_list[idx].vge_sts); 1388 if (txstat & VGE_TDSTS_OWN) 1389 break; 1390 1391 m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); 1392 sc->vge_ldata.vge_tx_mbuf[idx] = NULL; 1393 bus_dmamap_unload(sc->vge_dmat, 1394 sc->vge_ldata.vge_tx_dmamap[idx]); 1395 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1396 ifp->if_collisions++; 1397 if (txstat & VGE_TDSTS_TXERR) 1398 ifp->if_oerrors++; 1399 else 1400 ifp->if_opackets++; 1401 1402 sc->vge_ldata.vge_tx_free++; 1403 VGE_TX_DESC_INC(idx); 1404 } 1405 1406 /* No changes made to the TX ring, so no flush needed */ 1407 1408 if (idx != sc->vge_ldata.vge_tx_considx) { 1409 sc->vge_ldata.vge_tx_considx = idx; 1410 ifp->if_flags &= ~IFF_OACTIVE; 1411 ifp->if_timer = 0; 1412 } 1413 1414 /* 1415 * If not all descriptors have been released reaped yet, 1416 * reload the timer so that we will eventually get another 1417 * interrupt that will cause us to re-enter this routine. 1418 * This is done in case the transmitter has gone idle. 1419 */ 1420 if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) { 1421 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1422 } 1423 1424 return; 1425 } 1426 1427 static void 1428 vge_tick(xsc) 1429 void *xsc; 1430 { 1431 struct vge_softc *sc = xsc; 1432 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1433 struct mii_data *mii = &sc->sc_mii; 1434 int s; 1435 1436 s = splnet(); 1437 1438 VGE_LOCK(sc); 1439 1440 callout_schedule(&sc->vge_timeout, hz); 1441 1442 mii_tick(mii); 1443 if (sc->vge_link) { 1444 if (!(mii->mii_media_status & IFM_ACTIVE)) 1445 sc->vge_link = 0; 1446 } else { 1447 if (mii->mii_media_status & IFM_ACTIVE && 1448 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1449 sc->vge_link = 1; 1450 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1451 vge_start(ifp); 1452 } 1453 } 1454 1455 VGE_UNLOCK(sc); 1456 1457 splx(s); 1458 } 1459 1460 #ifdef DEVICE_POLLING 1461 static void 1462 vge_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1463 { 1464 struct vge_softc *sc = ifp->if_softc; 1465 1466 VGE_LOCK(sc); 1467 #ifdef IFCAP_POLLING 1468 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1469 ether_poll_deregister(ifp); 1470 cmd = POLL_DEREGISTER; 1471 } 1472 #endif 1473 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1474 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1475 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 1476 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1477 goto done; 1478 } 1479 1480 sc->rxcycles = count; 1481 vge_rxeof(sc); 1482 vge_txeof(sc); 1483 1484 #if __FreeBSD_version < 502114 1485 if (ifp->if_snd.ifq_head != NULL) 1486 #else 1487 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1488 #endif 1489 taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); 1490 1491 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1492 u_int32_t status; 1493 status = CSR_READ_4(sc, VGE_ISR); 1494 if (status == 0xFFFFFFFF) 1495 goto done; 1496 if (status) 1497 CSR_WRITE_4(sc, VGE_ISR, status); 1498 1499 /* 1500 * XXX check behaviour on receiver stalls. 1501 */ 1502 1503 if (status & VGE_ISR_TXDMA_STALL || 1504 status & VGE_ISR_RXDMA_STALL) 1505 vge_init(sc); 1506 1507 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1508 vge_rxeof(sc); 1509 ifp->if_ierrors++; 1510 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1511 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1512 } 1513 } 1514 done: 1515 VGE_UNLOCK(sc); 1516 } 1517 #endif /* DEVICE_POLLING */ 1518 1519 static int 1520 vge_intr(arg) 1521 void *arg; 1522 { 1523 struct vge_softc *sc = arg; 1524 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1525 u_int32_t status; 1526 int claim = 0; 1527 1528 if (sc->suspended) { 1529 return claim; 1530 } 1531 1532 VGE_LOCK(sc); 1533 1534 if (!(ifp->if_flags & IFF_UP)) { 1535 VGE_UNLOCK(sc); 1536 return claim; 1537 } 1538 1539 #ifdef DEVICE_POLLING 1540 if (ifp->if_flags & IFF_POLLING) 1541 goto done; 1542 if ( 1543 #ifdef IFCAP_POLLING 1544 (ifp->if_capenable & IFCAP_POLLING) && 1545 #endif 1546 ether_poll_register(vge_poll, ifp)) { /* ok, disable interrupts */ 1547 CSR_WRITE_4(sc, VGE_IMR, 0); 1548 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1549 vge_poll(ifp, 0, 1); 1550 goto done; 1551 } 1552 1553 #endif /* DEVICE_POLLING */ 1554 1555 /* Disable interrupts */ 1556 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1557 1558 for (;;) { 1559 1560 status = CSR_READ_4(sc, VGE_ISR); 1561 /* If the card has gone away the read returns 0xffff. */ 1562 if (status == 0xFFFFFFFF) 1563 break; 1564 1565 if (status) { 1566 claim = 1; 1567 CSR_WRITE_4(sc, VGE_ISR, status); 1568 } 1569 1570 if ((status & VGE_INTRS) == 0) 1571 break; 1572 1573 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1574 vge_rxeof(sc); 1575 1576 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1577 vge_rxeof(sc); 1578 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1579 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1580 } 1581 1582 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1583 vge_txeof(sc); 1584 1585 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) 1586 vge_init(ifp); 1587 1588 if (status & VGE_ISR_LINKSTS) 1589 vge_tick(sc); 1590 } 1591 1592 /* Re-enable interrupts */ 1593 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1594 1595 #ifdef DEVICE_POLLING 1596 done: 1597 #endif 1598 VGE_UNLOCK(sc); 1599 1600 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1601 vge_start(ifp); 1602 1603 return claim; 1604 } 1605 1606 static int 1607 vge_encap(sc, m_head, idx) 1608 struct vge_softc *sc; 1609 struct mbuf *m_head; 1610 int idx; 1611 { 1612 struct mbuf *m_new = NULL; 1613 bus_dmamap_t map; 1614 int error, flags; 1615 struct m_tag *mtag; 1616 1617 /* If this descriptor is still owned by the chip, bail. */ 1618 if (sc->vge_ldata.vge_tx_free <= 2 1619 || le32toh(sc->vge_ldata.vge_tx_list[idx].vge_sts) & VGE_TDSTS_OWN) 1620 return (ENOBUFS); 1621 1622 flags = 0; 1623 1624 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 1625 flags |= VGE_TDCTL_IPCSUM; 1626 if (m_head->m_pkthdr.csum_flags & M_CSUM_TCPv4) 1627 flags |= VGE_TDCTL_TCPCSUM; 1628 if (m_head->m_pkthdr.csum_flags & M_CSUM_UDPv4) 1629 flags |= VGE_TDCTL_UDPCSUM; 1630 1631 map = sc->vge_ldata.vge_tx_dmamap[idx]; 1632 error = bus_dmamap_load_mbuf(sc->vge_dmat, map, 1633 m_head, BUS_DMA_NOWAIT); 1634 1635 /* If too many segments to map, coalesce */ 1636 if (error == EFBIG) { 1637 m_new = m_defrag(m_head, M_DONTWAIT); 1638 if (m_new == NULL) 1639 return (error); 1640 1641 error = bus_dmamap_load_mbuf(sc->vge_dmat, map, 1642 m_new, BUS_DMA_NOWAIT); 1643 if (error) { 1644 m_freem(m_new); 1645 return (error); 1646 } 1647 1648 m_head = m_new; 1649 } else if (error) 1650 return (error); 1651 1652 vge_dma_map_tx_desc(sc, m_head, idx, flags); 1653 1654 sc->vge_ldata.vge_tx_mbuf[idx] = m_head; 1655 sc->vge_ldata.vge_tx_free--; 1656 1657 /* 1658 * Set up hardware VLAN tagging. 1659 */ 1660 1661 mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m_head); 1662 if (mtag != NULL) 1663 sc->vge_ldata.vge_tx_list[idx].vge_ctl |= 1664 htole32(htons(VLAN_TAG_VALUE(mtag)) | VGE_TDCTL_VTAG); 1665 1666 sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); 1667 1668 return (0); 1669 } 1670 1671 /* 1672 * Main transmit routine. 1673 */ 1674 1675 static void 1676 vge_start(ifp) 1677 struct ifnet *ifp; 1678 { 1679 struct vge_softc *sc; 1680 struct mbuf *m_head = NULL; 1681 int idx, pidx = 0, error; 1682 1683 sc = ifp->if_softc; 1684 VGE_LOCK(sc); 1685 1686 if (!sc->vge_link 1687 || (ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) { 1688 VGE_UNLOCK(sc); 1689 return; 1690 } 1691 1692 idx = sc->vge_ldata.vge_tx_prodidx; 1693 1694 pidx = idx - 1; 1695 if (pidx < 0) 1696 pidx = VGE_TX_DESC_CNT - 1; 1697 1698 /* 1699 * Loop through the send queue, setting up transmit descriptors 1700 * until we drain the queue, or use up all available transmit 1701 * descriptors. 1702 */ 1703 for(;;) { 1704 /* Grab a packet off the queue. */ 1705 IFQ_POLL(&ifp->if_snd, m_head); 1706 if (m_head == NULL) 1707 break; 1708 1709 if (sc->vge_ldata.vge_tx_mbuf[idx] != NULL) { 1710 /* 1711 * Slot already used, stop for now. 1712 */ 1713 ifp->if_flags |= IFF_OACTIVE; 1714 break; 1715 } 1716 1717 if ((error = vge_encap(sc, m_head, idx))) { 1718 if (error == EFBIG) { 1719 printf("%s: Tx packet consumes too many " 1720 "DMA segments, dropping...\n", 1721 sc->sc_dev.dv_xname); 1722 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1723 m_freem(m_head); 1724 continue; 1725 } 1726 1727 /* 1728 * Short on resources, just stop for now. 1729 */ 1730 if (error == ENOBUFS) 1731 ifp->if_flags |= IFF_OACTIVE; 1732 break; 1733 } 1734 1735 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1736 1737 /* 1738 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1739 */ 1740 1741 sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= 1742 htole16(VGE_TXDESC_Q); 1743 1744 if (sc->vge_ldata.vge_tx_mbuf[idx] != m_head) { 1745 m_freem(m_head); 1746 m_head = sc->vge_ldata.vge_tx_mbuf[idx]; 1747 } 1748 1749 pidx = idx; 1750 VGE_TX_DESC_INC(idx); 1751 1752 /* 1753 * If there's a BPF listener, bounce a copy of this frame 1754 * to him. 1755 */ 1756 #if NBPFILTER > 0 1757 if (ifp->if_bpf) 1758 bpf_mtap(ifp->if_bpf, m_head); 1759 #endif 1760 } 1761 1762 if (idx == sc->vge_ldata.vge_tx_prodidx) { 1763 VGE_UNLOCK(sc); 1764 return; 1765 } 1766 1767 /* Flush the TX descriptors */ 1768 1769 bus_dmamap_sync(sc->vge_dmat, 1770 sc->vge_ldata.vge_tx_list_map, 1771 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1772 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1773 1774 /* Issue a transmit command. */ 1775 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1776 1777 sc->vge_ldata.vge_tx_prodidx = idx; 1778 1779 /* 1780 * Use the countdown timer for interrupt moderation. 1781 * 'TX done' interrupts are disabled. Instead, we reset the 1782 * countdown timer, which will begin counting until it hits 1783 * the value in the SSTIMER register, and then trigger an 1784 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1785 * the timer count is reloaded. Only when the transmitter 1786 * is idle will the timer hit 0 and an interrupt fire. 1787 */ 1788 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1789 1790 VGE_UNLOCK(sc); 1791 1792 /* 1793 * Set a timeout in case the chip goes out to lunch. 1794 */ 1795 ifp->if_timer = 5; 1796 1797 return; 1798 } 1799 1800 static int 1801 vge_init(ifp) 1802 struct ifnet *ifp; 1803 { 1804 struct vge_softc *sc = ifp->if_softc; 1805 struct mii_data *mii = &sc->sc_mii; 1806 int i; 1807 1808 VGE_LOCK(sc); 1809 1810 /* 1811 * Cancel pending I/O and free all RX/TX buffers. 1812 */ 1813 vge_stop(sc); 1814 vge_reset(sc); 1815 1816 /* 1817 * Initialize the RX and TX descriptors and mbufs. 1818 */ 1819 1820 vge_rx_list_init(sc); 1821 vge_tx_list_init(sc); 1822 1823 /* Set our station address */ 1824 for (i = 0; i < ETHER_ADDR_LEN; i++) 1825 CSR_WRITE_1(sc, VGE_PAR0 + i, sc->vge_eaddr[i]); 1826 1827 /* 1828 * Set receive FIFO threshold. Also allow transmission and 1829 * reception of VLAN tagged frames. 1830 */ 1831 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 1832 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 1833 1834 /* Set DMA burst length */ 1835 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1836 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1837 1838 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1839 1840 /* Set collision backoff algorithm */ 1841 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1842 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1843 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1844 1845 /* Disable LPSEL field in priority resolution */ 1846 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1847 1848 /* 1849 * Load the addresses of the DMA queues into the chip. 1850 * Note that we only use one transmit queue. 1851 */ 1852 1853 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 1854 VGE_ADDR_LO(sc->vge_ldata.vge_tx_list_addr)); 1855 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 1856 1857 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 1858 VGE_ADDR_LO(sc->vge_ldata.vge_rx_list_addr)); 1859 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 1860 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 1861 1862 /* Enable and wake up the RX descriptor queue */ 1863 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1864 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1865 1866 /* Enable the TX descriptor queue */ 1867 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 1868 1869 /* Set up the receive filter -- allow large frames for VLANs. */ 1870 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 1871 1872 /* If we want promiscuous mode, set the allframes bit. */ 1873 if (ifp->if_flags & IFF_PROMISC) { 1874 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 1875 } 1876 1877 /* Set capture broadcast bit to capture broadcast frames. */ 1878 if (ifp->if_flags & IFF_BROADCAST) { 1879 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 1880 } 1881 1882 /* Set multicast bit to capture multicast frames. */ 1883 if (ifp->if_flags & IFF_MULTICAST) { 1884 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 1885 } 1886 1887 /* Init the cam filter. */ 1888 vge_cam_clear(sc); 1889 1890 /* Init the multicast filter. */ 1891 vge_setmulti(sc); 1892 1893 /* Enable flow control */ 1894 1895 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 1896 1897 /* Enable jumbo frame reception (if desired) */ 1898 1899 /* Start the MAC. */ 1900 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 1901 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 1902 CSR_WRITE_1(sc, VGE_CRS0, 1903 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 1904 1905 /* 1906 * Configure one-shot timer for microsecond 1907 * resulution and load it for 500 usecs. 1908 */ 1909 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 1910 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 1911 1912 /* 1913 * Configure interrupt moderation for receive. Enable 1914 * the holdoff counter and load it, and set the RX 1915 * suppression count to the number of descriptors we 1916 * want to allow before triggering an interrupt. 1917 * The holdoff timer is in units of 20 usecs. 1918 */ 1919 1920 #ifdef notyet 1921 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 1922 /* Select the interrupt holdoff timer page. */ 1923 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1924 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 1925 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 1926 1927 /* Enable use of the holdoff timer. */ 1928 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 1929 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 1930 1931 /* Select the RX suppression threshold page. */ 1932 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1933 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 1934 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 1935 1936 /* Restore the page select bits. */ 1937 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1938 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 1939 #endif 1940 1941 #ifdef DEVICE_POLLING 1942 /* 1943 * Disable interrupts if we are polling. 1944 */ 1945 if (ifp->if_flags & IFF_POLLING) { 1946 CSR_WRITE_4(sc, VGE_IMR, 0); 1947 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1948 } else /* otherwise ... */ 1949 #endif /* DEVICE_POLLING */ 1950 { 1951 /* 1952 * Enable interrupts. 1953 */ 1954 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1955 CSR_WRITE_4(sc, VGE_ISR, 0); 1956 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1957 } 1958 1959 mii_mediachg(mii); 1960 1961 ifp->if_flags |= IFF_RUNNING; 1962 ifp->if_flags &= ~IFF_OACTIVE; 1963 1964 sc->vge_if_flags = 0; 1965 sc->vge_link = 0; 1966 1967 VGE_UNLOCK(sc); 1968 1969 callout_schedule(&sc->vge_timeout, hz); 1970 1971 return (0); 1972 } 1973 1974 /* 1975 * Set media options. 1976 */ 1977 static int 1978 vge_ifmedia_upd(ifp) 1979 struct ifnet *ifp; 1980 { 1981 struct vge_softc *sc = ifp->if_softc; 1982 struct mii_data *mii = &sc->sc_mii; 1983 1984 mii_mediachg(mii); 1985 1986 return (0); 1987 } 1988 1989 /* 1990 * Report current media status. 1991 */ 1992 static void 1993 vge_ifmedia_sts(ifp, ifmr) 1994 struct ifnet *ifp; 1995 struct ifmediareq *ifmr; 1996 { 1997 struct vge_softc *sc = ifp->if_softc; 1998 struct mii_data *mii = &sc->sc_mii; 1999 2000 mii_pollstat(mii); 2001 ifmr->ifm_active = mii->mii_media_active; 2002 ifmr->ifm_status = mii->mii_media_status; 2003 2004 return; 2005 } 2006 2007 static void 2008 vge_miibus_statchg(self) 2009 struct device *self; 2010 { 2011 struct vge_softc *sc = (struct vge_softc *) self; 2012 struct mii_data *mii = &sc->sc_mii; 2013 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 2014 2015 /* 2016 * If the user manually selects a media mode, we need to turn 2017 * on the forced MAC mode bit in the DIAGCTL register. If the 2018 * user happens to choose a full duplex mode, we also need to 2019 * set the 'force full duplex' bit. This applies only to 2020 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 2021 * mode is disabled, and in 1000baseT mode, full duplex is 2022 * always implied, so we turn on the forced mode bit but leave 2023 * the FDX bit cleared. 2024 */ 2025 2026 switch (IFM_SUBTYPE(ife->ifm_media)) { 2027 case IFM_AUTO: 2028 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2029 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2030 break; 2031 case IFM_1000_T: 2032 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2033 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2034 break; 2035 case IFM_100_TX: 2036 case IFM_10_T: 2037 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2038 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 2039 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2040 } else { 2041 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2042 } 2043 break; 2044 default: 2045 printf("%s: unknown media type: %x\n", 2046 sc->sc_dev.dv_xname, 2047 IFM_SUBTYPE(ife->ifm_media)); 2048 break; 2049 } 2050 2051 return; 2052 } 2053 2054 static int 2055 vge_ioctl(ifp, command, data) 2056 struct ifnet *ifp; 2057 u_long command; 2058 caddr_t data; 2059 { 2060 struct vge_softc *sc = ifp->if_softc; 2061 struct ifreq *ifr = (struct ifreq *) data; 2062 struct mii_data *mii; 2063 int error = 0; 2064 2065 switch (command) { 2066 case SIOCSIFMTU: 2067 if (ifr->ifr_mtu > VGE_JUMBO_MTU) 2068 error = EINVAL; 2069 ifp->if_mtu = ifr->ifr_mtu; 2070 break; 2071 case SIOCSIFFLAGS: 2072 if (ifp->if_flags & IFF_UP) { 2073 if (ifp->if_flags & IFF_RUNNING && 2074 ifp->if_flags & IFF_PROMISC && 2075 !(sc->vge_if_flags & IFF_PROMISC)) { 2076 CSR_SETBIT_1(sc, VGE_RXCTL, 2077 VGE_RXCTL_RX_PROMISC); 2078 vge_setmulti(sc); 2079 } else if (ifp->if_flags & IFF_RUNNING && 2080 !(ifp->if_flags & IFF_PROMISC) && 2081 sc->vge_if_flags & IFF_PROMISC) { 2082 CSR_CLRBIT_1(sc, VGE_RXCTL, 2083 VGE_RXCTL_RX_PROMISC); 2084 vge_setmulti(sc); 2085 } else 2086 vge_init(ifp); 2087 } else { 2088 if (ifp->if_flags & IFF_RUNNING) 2089 vge_stop(sc); 2090 } 2091 sc->vge_if_flags = ifp->if_flags; 2092 break; 2093 case SIOCADDMULTI: 2094 case SIOCDELMULTI: 2095 vge_setmulti(sc); 2096 break; 2097 case SIOCGIFMEDIA: 2098 case SIOCSIFMEDIA: 2099 mii = &sc->sc_mii; 2100 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2101 break; 2102 default: 2103 error = ether_ioctl(ifp, command, data); 2104 break; 2105 } 2106 2107 return (error); 2108 } 2109 2110 static void 2111 vge_watchdog(ifp) 2112 struct ifnet *ifp; 2113 { 2114 struct vge_softc *sc; 2115 2116 sc = ifp->if_softc; 2117 VGE_LOCK(sc); 2118 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 2119 ifp->if_oerrors++; 2120 2121 vge_txeof(sc); 2122 vge_rxeof(sc); 2123 2124 vge_init(ifp); 2125 2126 VGE_UNLOCK(sc); 2127 2128 return; 2129 } 2130 2131 /* 2132 * Stop the adapter and free any mbufs allocated to the 2133 * RX and TX lists. 2134 */ 2135 static void 2136 vge_stop(sc) 2137 struct vge_softc *sc; 2138 { 2139 register int i; 2140 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2141 2142 VGE_LOCK(sc); 2143 ifp->if_timer = 0; 2144 2145 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2146 #ifdef DEVICE_POLLING 2147 ether_poll_deregister(ifp); 2148 #endif /* DEVICE_POLLING */ 2149 2150 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2151 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2152 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2153 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2154 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2155 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2156 2157 if (sc->vge_head != NULL) { 2158 m_freem(sc->vge_head); 2159 sc->vge_head = sc->vge_tail = NULL; 2160 } 2161 2162 /* Free the TX list buffers. */ 2163 2164 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 2165 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { 2166 bus_dmamap_unload(sc->vge_dmat, 2167 sc->vge_ldata.vge_tx_dmamap[i]); 2168 m_freem(sc->vge_ldata.vge_tx_mbuf[i]); 2169 sc->vge_ldata.vge_tx_mbuf[i] = NULL; 2170 } 2171 } 2172 2173 /* Free the RX list buffers. */ 2174 2175 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 2176 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { 2177 bus_dmamap_unload(sc->vge_dmat, 2178 sc->vge_ldata.vge_rx_dmamap[i]); 2179 m_freem(sc->vge_ldata.vge_rx_mbuf[i]); 2180 sc->vge_ldata.vge_rx_mbuf[i] = NULL; 2181 } 2182 } 2183 2184 VGE_UNLOCK(sc); 2185 2186 return; 2187 } 2188 2189 #if VGE_POWER_MANAGEMENT 2190 /* 2191 * Device suspend routine. Stop the interface and save some PCI 2192 * settings in case the BIOS doesn't restore them properly on 2193 * resume. 2194 */ 2195 static int 2196 vge_suspend(dev) 2197 struct device * dev; 2198 { 2199 struct vge_softc *sc; 2200 int i; 2201 2202 sc = device_get_softc(dev); 2203 2204 vge_stop(sc); 2205 2206 for (i = 0; i < 5; i++) 2207 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2208 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2209 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2210 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2211 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2212 2213 sc->suspended = 1; 2214 2215 return (0); 2216 } 2217 2218 /* 2219 * Device resume routine. Restore some PCI settings in case the BIOS 2220 * doesn't, re-enable busmastering, and restart the interface if 2221 * appropriate. 2222 */ 2223 static int 2224 vge_resume(dev) 2225 struct device * dev; 2226 { 2227 struct vge_softc *sc = (struct vge_softc *)dev; 2228 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2229 int i; 2230 2231 /* better way to do this? */ 2232 for (i = 0; i < 5; i++) 2233 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 2234 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 2235 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 2236 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 2237 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 2238 2239 /* reenable busmastering */ 2240 pci_enable_busmaster(dev); 2241 pci_enable_io(dev, SYS_RES_MEMORY); 2242 2243 /* reinitialize interface if necessary */ 2244 if (ifp->if_flags & IFF_UP) 2245 vge_init(sc); 2246 2247 sc->suspended = 0; 2248 2249 return (0); 2250 } 2251 #endif 2252 2253 /* 2254 * Stop all chip I/O so that the kernel's probe routines don't 2255 * get confused by errant DMAs when rebooting. 2256 */ 2257 static void 2258 vge_shutdown(arg) 2259 void *arg; 2260 { 2261 struct vge_softc *sc = (struct vge_softc *)arg; 2262 2263 vge_stop(sc); 2264 } 2265