1 /* $NetBSD: if_vge.c,v 1.63 2018/06/26 06:48:01 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD: src/sys/dev/vge/if_vge.c,v 1.5 2005/02/07 19:39:29 glebius Exp 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_vge.c,v 1.63 2018/06/26 06:48:01 msaitoh Exp $"); 39 40 /* 41 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 42 * 43 * Written by Bill Paul <wpaul@windriver.com> 44 * Senior Networking Software Engineer 45 * Wind River Systems 46 */ 47 48 /* 49 * The VIA Networking VT6122 is a 32bit, 33/66 MHz PCI device that 50 * combines a tri-speed ethernet MAC and PHY, with the following 51 * features: 52 * 53 * o Jumbo frame support up to 16K 54 * o Transmit and receive flow control 55 * o IPv4 checksum offload 56 * o VLAN tag insertion and stripping 57 * o TCP large send 58 * o 64-bit multicast hash table filter 59 * o 64 entry CAM filter 60 * o 16K RX FIFO and 48K TX FIFO memory 61 * o Interrupt moderation 62 * 63 * The VT6122 supports up to four transmit DMA queues. The descriptors 64 * in the transmit ring can address up to 7 data fragments; frames which 65 * span more than 7 data buffers must be coalesced, but in general the 66 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 67 * long. The receive descriptors address only a single buffer. 68 * 69 * There are two peculiar design issues with the VT6122. One is that 70 * receive data buffers must be aligned on a 32-bit boundary. This is 71 * not a problem where the VT6122 is used as a LOM device in x86-based 72 * systems, but on architectures that generate unaligned access traps, we 73 * have to do some copying. 74 * 75 * The other issue has to do with the way 64-bit addresses are handled. 76 * The DMA descriptors only allow you to specify 48 bits of addressing 77 * information. The remaining 16 bits are specified using one of the 78 * I/O registers. If you only have a 32-bit system, then this isn't 79 * an issue, but if you have a 64-bit system and more than 4GB of 80 * memory, you must have to make sure your network data buffers reside 81 * in the same 48-bit 'segment.' 82 * 83 * Special thanks to Ryan Fu at VIA Networking for providing documentation 84 * and sample NICs for testing. 85 */ 86 87 88 #include <sys/param.h> 89 #include <sys/endian.h> 90 #include <sys/systm.h> 91 #include <sys/device.h> 92 #include <sys/sockio.h> 93 #include <sys/mbuf.h> 94 #include <sys/malloc.h> 95 #include <sys/kernel.h> 96 #include <sys/socket.h> 97 98 #include <net/if.h> 99 #include <net/if_arp.h> 100 #include <net/if_ether.h> 101 #include <net/if_dl.h> 102 #include <net/if_media.h> 103 104 #include <net/bpf.h> 105 106 #include <sys/bus.h> 107 108 #include <dev/mii/mii.h> 109 #include <dev/mii/miivar.h> 110 111 #include <dev/pci/pcireg.h> 112 #include <dev/pci/pcivar.h> 113 #include <dev/pci/pcidevs.h> 114 115 #include <dev/pci/if_vgereg.h> 116 117 #define VGE_IFQ_MAXLEN 64 118 119 #define VGE_RING_ALIGN 256 120 121 #define VGE_NTXDESC 256 122 #define VGE_NTXDESC_MASK (VGE_NTXDESC - 1) 123 #define VGE_NEXT_TXDESC(x) ((x + 1) & VGE_NTXDESC_MASK) 124 #define VGE_PREV_TXDESC(x) ((x - 1) & VGE_NTXDESC_MASK) 125 126 #define VGE_NRXDESC 256 /* Must be a multiple of 4!! */ 127 #define VGE_NRXDESC_MASK (VGE_NRXDESC - 1) 128 #define VGE_NEXT_RXDESC(x) ((x + 1) & VGE_NRXDESC_MASK) 129 #define VGE_PREV_RXDESC(x) ((x - 1) & VGE_NRXDESC_MASK) 130 131 #define VGE_ADDR_LO(y) ((uint64_t)(y) & 0xFFFFFFFF) 132 #define VGE_ADDR_HI(y) ((uint64_t)(y) >> 32) 133 #define VGE_BUFLEN(y) ((y) & 0x7FFF) 134 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 135 136 #define VGE_POWER_MANAGEMENT 0 /* disabled for now */ 137 138 /* 139 * Mbuf adjust factor to force 32-bit alignment of IP header. 140 * Drivers should pad ETHER_ALIGN bytes when setting up a 141 * RX mbuf so the upper layers get the IP header properly aligned 142 * past the 14-byte Ethernet header. 143 * 144 * See also comment in vge_encap(). 145 */ 146 #define ETHER_ALIGN 2 147 148 #ifdef __NO_STRICT_ALIGNMENT 149 #define VGE_RX_BUFSIZE MCLBYTES 150 #else 151 #define VGE_RX_PAD sizeof(uint32_t) 152 #define VGE_RX_BUFSIZE (MCLBYTES - VGE_RX_PAD) 153 #endif 154 155 /* 156 * Control structures are DMA'd to the vge chip. We allocate them in 157 * a single clump that maps to a single DMA segment to make several things 158 * easier. 159 */ 160 struct vge_control_data { 161 /* TX descriptors */ 162 struct vge_txdesc vcd_txdescs[VGE_NTXDESC]; 163 /* RX descriptors */ 164 struct vge_rxdesc vcd_rxdescs[VGE_NRXDESC]; 165 /* dummy data for TX padding */ 166 uint8_t vcd_pad[ETHER_PAD_LEN]; 167 }; 168 169 #define VGE_CDOFF(x) offsetof(struct vge_control_data, x) 170 #define VGE_CDTXOFF(x) VGE_CDOFF(vcd_txdescs[(x)]) 171 #define VGE_CDRXOFF(x) VGE_CDOFF(vcd_rxdescs[(x)]) 172 #define VGE_CDPADOFF() VGE_CDOFF(vcd_pad[0]) 173 174 /* 175 * Software state for TX jobs. 176 */ 177 struct vge_txsoft { 178 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 179 bus_dmamap_t txs_dmamap; /* our DMA map */ 180 }; 181 182 /* 183 * Software state for RX jobs. 184 */ 185 struct vge_rxsoft { 186 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 187 bus_dmamap_t rxs_dmamap; /* our DMA map */ 188 }; 189 190 191 struct vge_softc { 192 device_t sc_dev; 193 194 bus_space_tag_t sc_bst; /* bus space tag */ 195 bus_space_handle_t sc_bsh; /* bus space handle */ 196 bus_dma_tag_t sc_dmat; 197 198 struct ethercom sc_ethercom; /* interface info */ 199 uint8_t sc_eaddr[ETHER_ADDR_LEN]; 200 201 void *sc_intrhand; 202 struct mii_data sc_mii; 203 uint8_t sc_type; 204 int sc_if_flags; 205 int sc_link; 206 int sc_camidx; 207 callout_t sc_timeout; 208 209 bus_dmamap_t sc_cddmamap; 210 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 211 212 struct vge_txsoft sc_txsoft[VGE_NTXDESC]; 213 struct vge_rxsoft sc_rxsoft[VGE_NRXDESC]; 214 struct vge_control_data *sc_control_data; 215 #define sc_txdescs sc_control_data->vcd_txdescs 216 #define sc_rxdescs sc_control_data->vcd_rxdescs 217 218 int sc_tx_prodidx; 219 int sc_tx_considx; 220 int sc_tx_free; 221 222 struct mbuf *sc_rx_mhead; 223 struct mbuf *sc_rx_mtail; 224 int sc_rx_prodidx; 225 int sc_rx_consumed; 226 227 int sc_suspended; /* 0 = normal 1 = suspended */ 228 uint32_t sc_saved_maps[5]; /* pci data */ 229 uint32_t sc_saved_biosaddr; 230 uint8_t sc_saved_intline; 231 uint8_t sc_saved_cachelnsz; 232 uint8_t sc_saved_lattimer; 233 }; 234 235 #define VGE_CDTXADDR(sc, x) ((sc)->sc_cddma + VGE_CDTXOFF(x)) 236 #define VGE_CDRXADDR(sc, x) ((sc)->sc_cddma + VGE_CDRXOFF(x)) 237 #define VGE_CDPADADDR(sc) ((sc)->sc_cddma + VGE_CDPADOFF()) 238 239 #define VGE_TXDESCSYNC(sc, idx, ops) \ 240 bus_dmamap_sync((sc)->sc_dmat,(sc)->sc_cddmamap, \ 241 VGE_CDTXOFF(idx), \ 242 offsetof(struct vge_txdesc, td_frag[0]), \ 243 (ops)) 244 #define VGE_TXFRAGSYNC(sc, idx, nsegs, ops) \ 245 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 246 VGE_CDTXOFF(idx) + \ 247 offsetof(struct vge_txdesc, td_frag[0]), \ 248 sizeof(struct vge_txfrag) * (nsegs), \ 249 (ops)) 250 #define VGE_RXDESCSYNC(sc, idx, ops) \ 251 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 252 VGE_CDRXOFF(idx), \ 253 sizeof(struct vge_rxdesc), \ 254 (ops)) 255 256 /* 257 * register space access macros 258 */ 259 #define CSR_WRITE_4(sc, reg, val) \ 260 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 261 #define CSR_WRITE_2(sc, reg, val) \ 262 bus_space_write_2((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 263 #define CSR_WRITE_1(sc, reg, val) \ 264 bus_space_write_1((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 265 266 #define CSR_READ_4(sc, reg) \ 267 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 268 #define CSR_READ_2(sc, reg) \ 269 bus_space_read_2((sc)->sc_bst, (sc)->sc_bsh, (reg)) 270 #define CSR_READ_1(sc, reg) \ 271 bus_space_read_1((sc)->sc_bst, (sc)->sc_bsh, (reg)) 272 273 #define CSR_SETBIT_1(sc, reg, x) \ 274 CSR_WRITE_1((sc), (reg), CSR_READ_1((sc), (reg)) | (x)) 275 #define CSR_SETBIT_2(sc, reg, x) \ 276 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (x)) 277 #define CSR_SETBIT_4(sc, reg, x) \ 278 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (x)) 279 280 #define CSR_CLRBIT_1(sc, reg, x) \ 281 CSR_WRITE_1((sc), (reg), CSR_READ_1((sc), (reg)) & ~(x)) 282 #define CSR_CLRBIT_2(sc, reg, x) \ 283 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(x)) 284 #define CSR_CLRBIT_4(sc, reg, x) \ 285 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(x)) 286 287 #define VGE_TIMEOUT 10000 288 289 #define VGE_PCI_LOIO 0x10 290 #define VGE_PCI_LOMEM 0x14 291 292 static inline void vge_set_txaddr(struct vge_txfrag *, bus_addr_t); 293 static inline void vge_set_rxaddr(struct vge_rxdesc *, bus_addr_t); 294 295 static int vge_ifflags_cb(struct ethercom *); 296 297 static int vge_match(device_t, cfdata_t, void *); 298 static void vge_attach(device_t, device_t, void *); 299 300 static int vge_encap(struct vge_softc *, struct mbuf *, int); 301 302 static int vge_allocmem(struct vge_softc *); 303 static int vge_newbuf(struct vge_softc *, int, struct mbuf *); 304 #ifndef __NO_STRICT_ALIGNMENT 305 static inline void vge_fixup_rx(struct mbuf *); 306 #endif 307 static void vge_rxeof(struct vge_softc *); 308 static void vge_txeof(struct vge_softc *); 309 static int vge_intr(void *); 310 static void vge_tick(void *); 311 static void vge_start(struct ifnet *); 312 static int vge_ioctl(struct ifnet *, u_long, void *); 313 static int vge_init(struct ifnet *); 314 static void vge_stop(struct ifnet *, int); 315 static void vge_watchdog(struct ifnet *); 316 #if VGE_POWER_MANAGEMENT 317 static int vge_suspend(device_t); 318 static int vge_resume(device_t); 319 #endif 320 static bool vge_shutdown(device_t, int); 321 322 static uint16_t vge_read_eeprom(struct vge_softc *, int); 323 324 static void vge_miipoll_start(struct vge_softc *); 325 static void vge_miipoll_stop(struct vge_softc *); 326 static int vge_miibus_readreg(device_t, int, int); 327 static void vge_miibus_writereg(device_t, int, int, int); 328 static void vge_miibus_statchg(struct ifnet *); 329 330 static void vge_cam_clear(struct vge_softc *); 331 static int vge_cam_set(struct vge_softc *, uint8_t *); 332 static void vge_setmulti(struct vge_softc *); 333 static void vge_reset(struct vge_softc *); 334 335 CFATTACH_DECL_NEW(vge, sizeof(struct vge_softc), 336 vge_match, vge_attach, NULL, NULL); 337 338 static inline void 339 vge_set_txaddr(struct vge_txfrag *f, bus_addr_t daddr) 340 { 341 342 f->tf_addrlo = htole32((uint32_t)daddr); 343 if (sizeof(bus_addr_t) == sizeof(uint64_t)) 344 f->tf_addrhi = htole16(((uint64_t)daddr >> 32) & 0xFFFF); 345 else 346 f->tf_addrhi = 0; 347 } 348 349 static inline void 350 vge_set_rxaddr(struct vge_rxdesc *rxd, bus_addr_t daddr) 351 { 352 353 rxd->rd_addrlo = htole32((uint32_t)daddr); 354 if (sizeof(bus_addr_t) == sizeof(uint64_t)) 355 rxd->rd_addrhi = htole16(((uint64_t)daddr >> 32) & 0xFFFF); 356 else 357 rxd->rd_addrhi = 0; 358 } 359 360 /* 361 * Read a word of data stored in the EEPROM at address 'addr.' 362 */ 363 static uint16_t 364 vge_read_eeprom(struct vge_softc *sc, int addr) 365 { 366 int i; 367 uint16_t word = 0; 368 369 /* 370 * Enter EEPROM embedded programming mode. In order to 371 * access the EEPROM at all, we first have to set the 372 * EELOAD bit in the CHIPCFG2 register. 373 */ 374 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 375 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 376 377 /* Select the address of the word we want to read */ 378 CSR_WRITE_1(sc, VGE_EEADDR, addr); 379 380 /* Issue read command */ 381 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 382 383 /* Wait for the done bit to be set. */ 384 for (i = 0; i < VGE_TIMEOUT; i++) { 385 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 386 break; 387 } 388 389 if (i == VGE_TIMEOUT) { 390 printf("%s: EEPROM read timed out\n", device_xname(sc->sc_dev)); 391 return 0; 392 } 393 394 /* Read the result */ 395 word = CSR_READ_2(sc, VGE_EERDDAT); 396 397 /* Turn off EEPROM access mode. */ 398 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 399 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 400 401 return word; 402 } 403 404 static void 405 vge_miipoll_stop(struct vge_softc *sc) 406 { 407 int i; 408 409 CSR_WRITE_1(sc, VGE_MIICMD, 0); 410 411 for (i = 0; i < VGE_TIMEOUT; i++) { 412 DELAY(1); 413 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 414 break; 415 } 416 417 if (i == VGE_TIMEOUT) { 418 printf("%s: failed to idle MII autopoll\n", 419 device_xname(sc->sc_dev)); 420 } 421 } 422 423 static void 424 vge_miipoll_start(struct vge_softc *sc) 425 { 426 int i; 427 428 /* First, make sure we're idle. */ 429 430 CSR_WRITE_1(sc, VGE_MIICMD, 0); 431 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 432 433 for (i = 0; i < VGE_TIMEOUT; i++) { 434 DELAY(1); 435 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 436 break; 437 } 438 439 if (i == VGE_TIMEOUT) { 440 printf("%s: failed to idle MII autopoll\n", 441 device_xname(sc->sc_dev)); 442 return; 443 } 444 445 /* Now enable auto poll mode. */ 446 447 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 448 449 /* And make sure it started. */ 450 451 for (i = 0; i < VGE_TIMEOUT; i++) { 452 DELAY(1); 453 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 454 break; 455 } 456 457 if (i == VGE_TIMEOUT) { 458 printf("%s: failed to start MII autopoll\n", 459 device_xname(sc->sc_dev)); 460 } 461 } 462 463 static int 464 vge_miibus_readreg(device_t dev, int phy, int reg) 465 { 466 struct vge_softc *sc; 467 int i, s; 468 uint16_t rval; 469 470 sc = device_private(dev); 471 rval = 0; 472 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 473 return 0; 474 475 s = splnet(); 476 vge_miipoll_stop(sc); 477 478 /* Specify the register we want to read. */ 479 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 480 481 /* Issue read command. */ 482 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 483 484 /* Wait for the read command bit to self-clear. */ 485 for (i = 0; i < VGE_TIMEOUT; i++) { 486 DELAY(1); 487 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 488 break; 489 } 490 491 if (i == VGE_TIMEOUT) 492 printf("%s: MII read timed out\n", device_xname(sc->sc_dev)); 493 else 494 rval = CSR_READ_2(sc, VGE_MIIDATA); 495 496 vge_miipoll_start(sc); 497 splx(s); 498 499 return rval; 500 } 501 502 static void 503 vge_miibus_writereg(device_t dev, int phy, int reg, int data) 504 { 505 struct vge_softc *sc; 506 int i, s; 507 508 sc = device_private(dev); 509 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 510 return; 511 512 s = splnet(); 513 vge_miipoll_stop(sc); 514 515 /* Specify the register we want to write. */ 516 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 517 518 /* Specify the data we want to write. */ 519 CSR_WRITE_2(sc, VGE_MIIDATA, data); 520 521 /* Issue write command. */ 522 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 523 524 /* Wait for the write command bit to self-clear. */ 525 for (i = 0; i < VGE_TIMEOUT; i++) { 526 DELAY(1); 527 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 528 break; 529 } 530 531 if (i == VGE_TIMEOUT) { 532 printf("%s: MII write timed out\n", device_xname(sc->sc_dev)); 533 } 534 535 vge_miipoll_start(sc); 536 splx(s); 537 } 538 539 static void 540 vge_cam_clear(struct vge_softc *sc) 541 { 542 int i; 543 544 /* 545 * Turn off all the mask bits. This tells the chip 546 * that none of the entries in the CAM filter are valid. 547 * desired entries will be enabled as we fill the filter in. 548 */ 549 550 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 551 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 552 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 553 for (i = 0; i < 8; i++) 554 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 555 556 /* Clear the VLAN filter too. */ 557 558 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 559 for (i = 0; i < 8; i++) 560 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 561 562 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 563 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 564 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 565 566 sc->sc_camidx = 0; 567 } 568 569 static int 570 vge_cam_set(struct vge_softc *sc, uint8_t *addr) 571 { 572 int i, error; 573 574 error = 0; 575 576 if (sc->sc_camidx == VGE_CAM_MAXADDRS) 577 return ENOSPC; 578 579 /* Select the CAM data page. */ 580 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 581 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 582 583 /* Set the filter entry we want to update and enable writing. */ 584 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE | sc->sc_camidx); 585 586 /* Write the address to the CAM registers */ 587 for (i = 0; i < ETHER_ADDR_LEN; i++) 588 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 589 590 /* Issue a write command. */ 591 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 592 593 /* Wake for it to clear. */ 594 for (i = 0; i < VGE_TIMEOUT; i++) { 595 DELAY(1); 596 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 597 break; 598 } 599 600 if (i == VGE_TIMEOUT) { 601 printf("%s: setting CAM filter failed\n", 602 device_xname(sc->sc_dev)); 603 error = EIO; 604 goto fail; 605 } 606 607 /* Select the CAM mask page. */ 608 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 609 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 610 611 /* Set the mask bit that enables this filter. */ 612 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->sc_camidx / 8), 613 1 << (sc->sc_camidx & 7)); 614 615 sc->sc_camidx++; 616 617 fail: 618 /* Turn off access to CAM. */ 619 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 620 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 621 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 622 623 return error; 624 } 625 626 /* 627 * Program the multicast filter. We use the 64-entry CAM filter 628 * for perfect filtering. If there's more than 64 multicast addresses, 629 * we use the hash filter instead. 630 */ 631 static void 632 vge_setmulti(struct vge_softc *sc) 633 { 634 struct ifnet *ifp; 635 int error; 636 uint32_t h, hashes[2] = { 0, 0 }; 637 struct ether_multi *enm; 638 struct ether_multistep step; 639 640 error = 0; 641 ifp = &sc->sc_ethercom.ec_if; 642 643 /* First, zot all the multicast entries. */ 644 vge_cam_clear(sc); 645 CSR_WRITE_4(sc, VGE_MAR0, 0); 646 CSR_WRITE_4(sc, VGE_MAR1, 0); 647 ifp->if_flags &= ~IFF_ALLMULTI; 648 649 /* 650 * If the user wants allmulti or promisc mode, enable reception 651 * of all multicast frames. 652 */ 653 if (ifp->if_flags & IFF_PROMISC) { 654 allmulti: 655 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 656 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 657 ifp->if_flags |= IFF_ALLMULTI; 658 return; 659 } 660 661 /* Now program new ones */ 662 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 663 while (enm != NULL) { 664 /* 665 * If multicast range, fall back to ALLMULTI. 666 */ 667 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 668 ETHER_ADDR_LEN) != 0) 669 goto allmulti; 670 671 error = vge_cam_set(sc, enm->enm_addrlo); 672 if (error) 673 break; 674 675 ETHER_NEXT_MULTI(step, enm); 676 } 677 678 /* If there were too many addresses, use the hash filter. */ 679 if (error) { 680 vge_cam_clear(sc); 681 682 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 683 while (enm != NULL) { 684 /* 685 * If multicast range, fall back to ALLMULTI. 686 */ 687 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 688 ETHER_ADDR_LEN) != 0) 689 goto allmulti; 690 691 h = ether_crc32_be(enm->enm_addrlo, 692 ETHER_ADDR_LEN) >> 26; 693 hashes[h >> 5] |= 1 << (h & 0x1f); 694 695 ETHER_NEXT_MULTI(step, enm); 696 } 697 698 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 699 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 700 } 701 } 702 703 static void 704 vge_reset(struct vge_softc *sc) 705 { 706 int i; 707 708 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 709 710 for (i = 0; i < VGE_TIMEOUT; i++) { 711 DELAY(5); 712 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 713 break; 714 } 715 716 if (i == VGE_TIMEOUT) { 717 printf("%s: soft reset timed out", device_xname(sc->sc_dev)); 718 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 719 DELAY(2000); 720 } 721 722 DELAY(5000); 723 724 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 725 726 for (i = 0; i < VGE_TIMEOUT; i++) { 727 DELAY(5); 728 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 729 break; 730 } 731 732 if (i == VGE_TIMEOUT) { 733 printf("%s: EEPROM reload timed out\n", 734 device_xname(sc->sc_dev)); 735 return; 736 } 737 738 /* 739 * On some machine, the first read data from EEPROM could be 740 * messed up, so read one dummy data here to avoid the mess. 741 */ 742 (void)vge_read_eeprom(sc, 0); 743 744 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 745 } 746 747 /* 748 * Probe for a VIA gigabit chip. Check the PCI vendor and device 749 * IDs against our list and return a device name if we find a match. 750 */ 751 static int 752 vge_match(device_t parent, cfdata_t match, void *aux) 753 { 754 struct pci_attach_args *pa = aux; 755 756 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH 757 && PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_VIATECH_VT612X) 758 return 1; 759 760 return 0; 761 } 762 763 static int 764 vge_allocmem(struct vge_softc *sc) 765 { 766 int error; 767 int nseg; 768 int i; 769 bus_dma_segment_t seg; 770 771 /* 772 * Allocate memory for control data. 773 */ 774 775 error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct vge_control_data), 776 VGE_RING_ALIGN, 0, &seg, 1, &nseg, BUS_DMA_NOWAIT); 777 if (error) { 778 aprint_error_dev(sc->sc_dev, 779 "could not allocate control data dma memory\n"); 780 goto fail_1; 781 } 782 783 /* Map the memory to kernel VA space */ 784 785 error = bus_dmamem_map(sc->sc_dmat, &seg, nseg, 786 sizeof(struct vge_control_data), (void **)&sc->sc_control_data, 787 BUS_DMA_NOWAIT); 788 if (error) { 789 aprint_error_dev(sc->sc_dev, 790 "could not map control data dma memory\n"); 791 goto fail_2; 792 } 793 memset(sc->sc_control_data, 0, sizeof(struct vge_control_data)); 794 795 /* 796 * Create map for control data. 797 */ 798 error = bus_dmamap_create(sc->sc_dmat, 799 sizeof(struct vge_control_data), 1, 800 sizeof(struct vge_control_data), 0, BUS_DMA_NOWAIT, 801 &sc->sc_cddmamap); 802 if (error) { 803 aprint_error_dev(sc->sc_dev, 804 "could not create control data dmamap\n"); 805 goto fail_3; 806 } 807 808 /* Load the map for the control data. */ 809 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 810 sc->sc_control_data, sizeof(struct vge_control_data), NULL, 811 BUS_DMA_NOWAIT); 812 if (error) { 813 aprint_error_dev(sc->sc_dev, 814 "could not load control data dma memory\n"); 815 goto fail_4; 816 } 817 818 /* Create DMA maps for TX buffers */ 819 820 for (i = 0; i < VGE_NTXDESC; i++) { 821 error = bus_dmamap_create(sc->sc_dmat, VGE_TX_MAXLEN, 822 VGE_TX_FRAGS, VGE_TX_MAXLEN, 0, BUS_DMA_NOWAIT, 823 &sc->sc_txsoft[i].txs_dmamap); 824 if (error) { 825 aprint_error_dev(sc->sc_dev, 826 "can't create DMA map for TX descs\n"); 827 goto fail_5; 828 } 829 } 830 831 /* Create DMA maps for RX buffers */ 832 833 for (i = 0; i < VGE_NRXDESC; i++) { 834 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 835 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 836 &sc->sc_rxsoft[i].rxs_dmamap); 837 if (error) { 838 aprint_error_dev(sc->sc_dev, 839 "can't create DMA map for RX descs\n"); 840 goto fail_6; 841 } 842 sc->sc_rxsoft[i].rxs_mbuf = NULL; 843 } 844 845 return 0; 846 847 fail_6: 848 for (i = 0; i < VGE_NRXDESC; i++) { 849 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 850 bus_dmamap_destroy(sc->sc_dmat, 851 sc->sc_rxsoft[i].rxs_dmamap); 852 } 853 fail_5: 854 for (i = 0; i < VGE_NTXDESC; i++) { 855 if (sc->sc_txsoft[i].txs_dmamap != NULL) 856 bus_dmamap_destroy(sc->sc_dmat, 857 sc->sc_txsoft[i].txs_dmamap); 858 } 859 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 860 fail_4: 861 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 862 fail_3: 863 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 864 sizeof(struct vge_control_data)); 865 fail_2: 866 bus_dmamem_free(sc->sc_dmat, &seg, nseg); 867 fail_1: 868 return ENOMEM; 869 } 870 871 /* 872 * Attach the interface. Allocate softc structures, do ifmedia 873 * setup and ethernet/BPF attach. 874 */ 875 static void 876 vge_attach(device_t parent, device_t self, void *aux) 877 { 878 uint8_t *eaddr; 879 struct vge_softc *sc = device_private(self); 880 struct ifnet *ifp; 881 struct pci_attach_args *pa = aux; 882 pci_chipset_tag_t pc = pa->pa_pc; 883 const char *intrstr; 884 pci_intr_handle_t ih; 885 uint16_t val; 886 char intrbuf[PCI_INTRSTR_LEN]; 887 888 sc->sc_dev = self; 889 890 pci_aprint_devinfo_fancy(pa, NULL, "VIA VT612X Gigabit Ethernet", 1); 891 892 /* Make sure bus-mastering is enabled */ 893 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 894 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 895 PCI_COMMAND_MASTER_ENABLE); 896 897 /* 898 * Map control/status registers. 899 */ 900 if (pci_mapreg_map(pa, VGE_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 901 &sc->sc_bst, &sc->sc_bsh, NULL, NULL) != 0) { 902 aprint_error_dev(self, "couldn't map memory\n"); 903 return; 904 } 905 906 /* 907 * Map and establish our interrupt. 908 */ 909 if (pci_intr_map(pa, &ih)) { 910 aprint_error_dev(self, "unable to map interrupt\n"); 911 return; 912 } 913 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 914 sc->sc_intrhand = pci_intr_establish(pc, ih, IPL_NET, vge_intr, sc); 915 if (sc->sc_intrhand == NULL) { 916 aprint_error_dev(self, "unable to establish interrupt"); 917 if (intrstr != NULL) 918 aprint_error(" at %s", intrstr); 919 aprint_error("\n"); 920 return; 921 } 922 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 923 924 /* Reset the adapter. */ 925 vge_reset(sc); 926 927 /* 928 * Get station address from the EEPROM. 929 */ 930 eaddr = sc->sc_eaddr; 931 val = vge_read_eeprom(sc, VGE_EE_EADDR + 0); 932 eaddr[0] = val & 0xff; 933 eaddr[1] = val >> 8; 934 val = vge_read_eeprom(sc, VGE_EE_EADDR + 1); 935 eaddr[2] = val & 0xff; 936 eaddr[3] = val >> 8; 937 val = vge_read_eeprom(sc, VGE_EE_EADDR + 2); 938 eaddr[4] = val & 0xff; 939 eaddr[5] = val >> 8; 940 941 aprint_normal_dev(self, "Ethernet address: %s\n", 942 ether_sprintf(eaddr)); 943 944 /* 945 * Use the 32bit tag. Hardware supports 48bit physical addresses, 946 * but we don't use that for now. 947 */ 948 sc->sc_dmat = pa->pa_dmat; 949 950 if (vge_allocmem(sc) != 0) 951 return; 952 953 ifp = &sc->sc_ethercom.ec_if; 954 ifp->if_softc = sc; 955 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 956 ifp->if_mtu = ETHERMTU; 957 ifp->if_baudrate = IF_Gbps(1); 958 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 959 ifp->if_ioctl = vge_ioctl; 960 ifp->if_start = vge_start; 961 ifp->if_init = vge_init; 962 ifp->if_stop = vge_stop; 963 964 /* 965 * We can support 802.1Q VLAN-sized frames and jumbo 966 * Ethernet frames. 967 */ 968 sc->sc_ethercom.ec_capabilities |= 969 ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU | 970 ETHERCAP_VLAN_HWTAGGING; 971 972 /* 973 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 974 */ 975 ifp->if_capabilities |= 976 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 977 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 978 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 979 980 #ifdef DEVICE_POLLING 981 #ifdef IFCAP_POLLING 982 ifp->if_capabilities |= IFCAP_POLLING; 983 #endif 984 #endif 985 ifp->if_watchdog = vge_watchdog; 986 IFQ_SET_MAXLEN(&ifp->if_snd, max(VGE_IFQ_MAXLEN, IFQ_MAXLEN)); 987 IFQ_SET_READY(&ifp->if_snd); 988 989 /* 990 * Initialize our media structures and probe the MII. 991 */ 992 sc->sc_mii.mii_ifp = ifp; 993 sc->sc_mii.mii_readreg = vge_miibus_readreg; 994 sc->sc_mii.mii_writereg = vge_miibus_writereg; 995 sc->sc_mii.mii_statchg = vge_miibus_statchg; 996 997 sc->sc_ethercom.ec_mii = &sc->sc_mii; 998 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 999 ether_mediastatus); 1000 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1001 MII_OFFSET_ANY, MIIF_DOPAUSE); 1002 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1003 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1004 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1005 } else 1006 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1007 1008 /* 1009 * Attach the interface. 1010 */ 1011 if_attach(ifp); 1012 if_deferred_start_init(ifp, NULL); 1013 ether_ifattach(ifp, eaddr); 1014 ether_set_ifflags_cb(&sc->sc_ethercom, vge_ifflags_cb); 1015 1016 callout_init(&sc->sc_timeout, 0); 1017 callout_setfunc(&sc->sc_timeout, vge_tick, sc); 1018 1019 /* 1020 * Make sure the interface is shutdown during reboot. 1021 */ 1022 if (pmf_device_register1(self, NULL, NULL, vge_shutdown)) 1023 pmf_class_network_register(self, ifp); 1024 else 1025 aprint_error_dev(self, "couldn't establish power handler\n"); 1026 } 1027 1028 static int 1029 vge_newbuf(struct vge_softc *sc, int idx, struct mbuf *m) 1030 { 1031 struct mbuf *m_new; 1032 struct vge_rxdesc *rxd; 1033 struct vge_rxsoft *rxs; 1034 bus_dmamap_t map; 1035 int i; 1036 #ifdef DIAGNOSTIC 1037 uint32_t rd_sts; 1038 #endif 1039 1040 m_new = NULL; 1041 if (m == NULL) { 1042 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1043 if (m_new == NULL) 1044 return ENOBUFS; 1045 1046 MCLGET(m_new, M_DONTWAIT); 1047 if ((m_new->m_flags & M_EXT) == 0) { 1048 m_freem(m_new); 1049 return ENOBUFS; 1050 } 1051 1052 m = m_new; 1053 } else 1054 m->m_data = m->m_ext.ext_buf; 1055 1056 1057 /* 1058 * This is part of an evil trick to deal with non-x86 platforms. 1059 * The VIA chip requires RX buffers to be aligned on 32-bit 1060 * boundaries, but that will hose non-x86 machines. To get around 1061 * this, we leave some empty space at the start of each buffer 1062 * and for non-x86 hosts, we copy the buffer back two bytes 1063 * to achieve word alignment. This is slightly more efficient 1064 * than allocating a new buffer, copying the contents, and 1065 * discarding the old buffer. 1066 */ 1067 m->m_len = m->m_pkthdr.len = VGE_RX_BUFSIZE; 1068 #ifndef __NO_STRICT_ALIGNMENT 1069 m->m_data += VGE_RX_PAD; 1070 #endif 1071 rxs = &sc->sc_rxsoft[idx]; 1072 map = rxs->rxs_dmamap; 1073 1074 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT) != 0) 1075 goto out; 1076 1077 rxd = &sc->sc_rxdescs[idx]; 1078 1079 #ifdef DIAGNOSTIC 1080 /* If this descriptor is still owned by the chip, bail. */ 1081 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1082 rd_sts = le32toh(rxd->rd_sts); 1083 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1084 if (rd_sts & VGE_RDSTS_OWN) { 1085 panic("%s: tried to map busy RX descriptor", 1086 device_xname(sc->sc_dev)); 1087 } 1088 #endif 1089 1090 rxs->rxs_mbuf = m; 1091 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1092 BUS_DMASYNC_PREREAD); 1093 1094 rxd->rd_buflen = 1095 htole16(VGE_BUFLEN(map->dm_segs[0].ds_len) | VGE_RXDESC_I); 1096 vge_set_rxaddr(rxd, map->dm_segs[0].ds_addr); 1097 rxd->rd_sts = 0; 1098 rxd->rd_ctl = 0; 1099 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1100 1101 /* 1102 * Note: the manual fails to document the fact that for 1103 * proper opration, the driver needs to replentish the RX 1104 * DMA ring 4 descriptors at a time (rather than one at a 1105 * time, like most chips). We can allocate the new buffers 1106 * but we should not set the OWN bits until we're ready 1107 * to hand back 4 of them in one shot. 1108 */ 1109 1110 #define VGE_RXCHUNK 4 1111 sc->sc_rx_consumed++; 1112 if (sc->sc_rx_consumed == VGE_RXCHUNK) { 1113 for (i = idx; i != idx - VGE_RXCHUNK; i--) { 1114 KASSERT(i >= 0); 1115 sc->sc_rxdescs[i].rd_sts |= htole32(VGE_RDSTS_OWN); 1116 VGE_RXDESCSYNC(sc, i, 1117 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1118 } 1119 sc->sc_rx_consumed = 0; 1120 } 1121 1122 return 0; 1123 out: 1124 if (m_new != NULL) 1125 m_freem(m_new); 1126 return ENOMEM; 1127 } 1128 1129 #ifndef __NO_STRICT_ALIGNMENT 1130 static inline void 1131 vge_fixup_rx(struct mbuf *m) 1132 { 1133 int i; 1134 uint16_t *src, *dst; 1135 1136 src = mtod(m, uint16_t *); 1137 dst = src - 1; 1138 1139 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1140 *dst++ = *src++; 1141 1142 m->m_data -= ETHER_ALIGN; 1143 } 1144 #endif 1145 1146 /* 1147 * RX handler. We support the reception of jumbo frames that have 1148 * been fragmented across multiple 2K mbuf cluster buffers. 1149 */ 1150 static void 1151 vge_rxeof(struct vge_softc *sc) 1152 { 1153 struct mbuf *m; 1154 struct ifnet *ifp; 1155 int idx, total_len, lim; 1156 struct vge_rxdesc *cur_rxd; 1157 struct vge_rxsoft *rxs; 1158 uint32_t rxstat, rxctl; 1159 1160 ifp = &sc->sc_ethercom.ec_if; 1161 lim = 0; 1162 1163 /* Invalidate the descriptor memory */ 1164 1165 for (idx = sc->sc_rx_prodidx;; idx = VGE_NEXT_RXDESC(idx)) { 1166 cur_rxd = &sc->sc_rxdescs[idx]; 1167 1168 VGE_RXDESCSYNC(sc, idx, 1169 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1170 rxstat = le32toh(cur_rxd->rd_sts); 1171 if ((rxstat & VGE_RDSTS_OWN) != 0) { 1172 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1173 break; 1174 } 1175 1176 rxctl = le32toh(cur_rxd->rd_ctl); 1177 rxs = &sc->sc_rxsoft[idx]; 1178 m = rxs->rxs_mbuf; 1179 total_len = (rxstat & VGE_RDSTS_BUFSIZ) >> 16; 1180 1181 /* Invalidate the RX mbuf and unload its map */ 1182 1183 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 1184 0, rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1185 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1186 1187 /* 1188 * If the 'start of frame' bit is set, this indicates 1189 * either the first fragment in a multi-fragment receive, 1190 * or an intermediate fragment. Either way, we want to 1191 * accumulate the buffers. 1192 */ 1193 if (rxstat & VGE_RXPKT_SOF) { 1194 m->m_len = VGE_RX_BUFSIZE; 1195 if (sc->sc_rx_mhead == NULL) 1196 sc->sc_rx_mhead = sc->sc_rx_mtail = m; 1197 else { 1198 m->m_flags &= ~M_PKTHDR; 1199 sc->sc_rx_mtail->m_next = m; 1200 sc->sc_rx_mtail = m; 1201 } 1202 vge_newbuf(sc, idx, NULL); 1203 continue; 1204 } 1205 1206 /* 1207 * Bad/error frames will have the RXOK bit cleared. 1208 * However, there's one error case we want to allow: 1209 * if a VLAN tagged frame arrives and the chip can't 1210 * match it against the CAM filter, it considers this 1211 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1212 * We don't want to drop the frame though: our VLAN 1213 * filtering is done in software. 1214 */ 1215 if ((rxstat & VGE_RDSTS_RXOK) == 0 && 1216 (rxstat & VGE_RDSTS_VIDM) == 0 && 1217 (rxstat & VGE_RDSTS_CSUMERR) == 0) { 1218 ifp->if_ierrors++; 1219 /* 1220 * If this is part of a multi-fragment packet, 1221 * discard all the pieces. 1222 */ 1223 if (sc->sc_rx_mhead != NULL) { 1224 m_freem(sc->sc_rx_mhead); 1225 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL; 1226 } 1227 vge_newbuf(sc, idx, m); 1228 continue; 1229 } 1230 1231 /* 1232 * If allocating a replacement mbuf fails, 1233 * reload the current one. 1234 */ 1235 1236 if (vge_newbuf(sc, idx, NULL)) { 1237 ifp->if_ierrors++; 1238 if (sc->sc_rx_mhead != NULL) { 1239 m_freem(sc->sc_rx_mhead); 1240 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL; 1241 } 1242 vge_newbuf(sc, idx, m); 1243 continue; 1244 } 1245 1246 if (sc->sc_rx_mhead != NULL) { 1247 m->m_len = total_len % VGE_RX_BUFSIZE; 1248 /* 1249 * Special case: if there's 4 bytes or less 1250 * in this buffer, the mbuf can be discarded: 1251 * the last 4 bytes is the CRC, which we don't 1252 * care about anyway. 1253 */ 1254 if (m->m_len <= ETHER_CRC_LEN) { 1255 sc->sc_rx_mtail->m_len -= 1256 (ETHER_CRC_LEN - m->m_len); 1257 m_freem(m); 1258 } else { 1259 m->m_len -= ETHER_CRC_LEN; 1260 m->m_flags &= ~M_PKTHDR; 1261 sc->sc_rx_mtail->m_next = m; 1262 } 1263 m = sc->sc_rx_mhead; 1264 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL; 1265 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1266 } else 1267 m->m_pkthdr.len = m->m_len = total_len - ETHER_CRC_LEN; 1268 1269 #ifndef __NO_STRICT_ALIGNMENT 1270 vge_fixup_rx(m); 1271 #endif 1272 m_set_rcvif(m, ifp); 1273 1274 /* Do RX checksumming if enabled */ 1275 if (ifp->if_csum_flags_rx & M_CSUM_IPv4) { 1276 1277 /* Check IP header checksum */ 1278 if (rxctl & VGE_RDCTL_IPPKT) 1279 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1280 if ((rxctl & VGE_RDCTL_IPCSUMOK) == 0) 1281 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1282 } 1283 1284 if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) { 1285 /* Check UDP checksum */ 1286 if (rxctl & VGE_RDCTL_TCPPKT) 1287 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1288 1289 if ((rxctl & VGE_RDCTL_PROTOCSUMOK) == 0) 1290 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1291 } 1292 1293 if (ifp->if_csum_flags_rx & M_CSUM_UDPv4) { 1294 /* Check UDP checksum */ 1295 if (rxctl & VGE_RDCTL_UDPPKT) 1296 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1297 1298 if ((rxctl & VGE_RDCTL_PROTOCSUMOK) == 0) 1299 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1300 } 1301 1302 if (rxstat & VGE_RDSTS_VTAG) { 1303 /* 1304 * We use bswap16() here because: 1305 * On LE machines, tag is stored in BE as stream data. 1306 * On BE machines, tag is stored in BE as stream data 1307 * but it was already swapped by le32toh() above. 1308 */ 1309 vlan_set_tag(m, bswap16(rxctl & VGE_RDCTL_VLANID)); 1310 } 1311 1312 if_percpuq_enqueue(ifp->if_percpuq, m); 1313 1314 lim++; 1315 if (lim == VGE_NRXDESC) 1316 break; 1317 } 1318 1319 sc->sc_rx_prodidx = idx; 1320 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1321 } 1322 1323 static void 1324 vge_txeof(struct vge_softc *sc) 1325 { 1326 struct ifnet *ifp; 1327 struct vge_txsoft *txs; 1328 uint32_t txstat; 1329 int idx; 1330 1331 ifp = &sc->sc_ethercom.ec_if; 1332 1333 for (idx = sc->sc_tx_considx; 1334 sc->sc_tx_free < VGE_NTXDESC; 1335 idx = VGE_NEXT_TXDESC(idx), sc->sc_tx_free++) { 1336 VGE_TXDESCSYNC(sc, idx, 1337 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1338 txstat = le32toh(sc->sc_txdescs[idx].td_sts); 1339 VGE_TXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1340 if (txstat & VGE_TDSTS_OWN) { 1341 break; 1342 } 1343 1344 txs = &sc->sc_txsoft[idx]; 1345 m_freem(txs->txs_mbuf); 1346 txs->txs_mbuf = NULL; 1347 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 0, 1348 txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1349 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1350 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1351 ifp->if_collisions++; 1352 if (txstat & VGE_TDSTS_TXERR) 1353 ifp->if_oerrors++; 1354 else 1355 ifp->if_opackets++; 1356 } 1357 1358 sc->sc_tx_considx = idx; 1359 1360 if (sc->sc_tx_free > 0) { 1361 ifp->if_flags &= ~IFF_OACTIVE; 1362 } 1363 1364 /* 1365 * If not all descriptors have been released reaped yet, 1366 * reload the timer so that we will eventually get another 1367 * interrupt that will cause us to re-enter this routine. 1368 * This is done in case the transmitter has gone idle. 1369 */ 1370 if (sc->sc_tx_free < VGE_NTXDESC) 1371 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1372 else 1373 ifp->if_timer = 0; 1374 } 1375 1376 static void 1377 vge_tick(void *arg) 1378 { 1379 struct vge_softc *sc; 1380 struct ifnet *ifp; 1381 struct mii_data *mii; 1382 int s; 1383 1384 sc = arg; 1385 ifp = &sc->sc_ethercom.ec_if; 1386 mii = &sc->sc_mii; 1387 1388 s = splnet(); 1389 1390 callout_schedule(&sc->sc_timeout, hz); 1391 1392 mii_tick(mii); 1393 if (sc->sc_link) { 1394 if ((mii->mii_media_status & IFM_ACTIVE) == 0) 1395 sc->sc_link = 0; 1396 } else { 1397 if (mii->mii_media_status & IFM_ACTIVE && 1398 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1399 sc->sc_link = 1; 1400 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1401 vge_start(ifp); 1402 } 1403 } 1404 1405 splx(s); 1406 } 1407 1408 static int 1409 vge_intr(void *arg) 1410 { 1411 struct vge_softc *sc; 1412 struct ifnet *ifp; 1413 uint32_t status; 1414 int claim; 1415 1416 sc = arg; 1417 claim = 0; 1418 if (sc->sc_suspended) { 1419 return claim; 1420 } 1421 1422 ifp = &sc->sc_ethercom.ec_if; 1423 1424 if ((ifp->if_flags & IFF_UP) == 0) { 1425 return claim; 1426 } 1427 1428 /* Disable interrupts */ 1429 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1430 1431 for (;;) { 1432 1433 status = CSR_READ_4(sc, VGE_ISR); 1434 /* If the card has gone away the read returns 0xffffffff. */ 1435 if (status == 0xFFFFFFFF) 1436 break; 1437 1438 if (status) { 1439 claim = 1; 1440 CSR_WRITE_4(sc, VGE_ISR, status); 1441 } 1442 1443 if ((status & VGE_INTRS) == 0) 1444 break; 1445 1446 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1447 vge_rxeof(sc); 1448 1449 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1450 vge_rxeof(sc); 1451 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1452 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1453 } 1454 1455 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1456 vge_txeof(sc); 1457 1458 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) 1459 vge_init(ifp); 1460 1461 if (status & VGE_ISR_LINKSTS) 1462 vge_tick(sc); 1463 } 1464 1465 /* Re-enable interrupts */ 1466 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1467 1468 if (claim) 1469 if_schedule_deferred_start(ifp); 1470 1471 return claim; 1472 } 1473 1474 static int 1475 vge_encap(struct vge_softc *sc, struct mbuf *m_head, int idx) 1476 { 1477 struct vge_txsoft *txs; 1478 struct vge_txdesc *txd; 1479 struct vge_txfrag *f; 1480 struct mbuf *m_new; 1481 bus_dmamap_t map; 1482 int m_csumflags, seg, error, flags; 1483 size_t sz; 1484 uint32_t td_sts, td_ctl; 1485 1486 KASSERT(sc->sc_tx_free > 0); 1487 1488 txd = &sc->sc_txdescs[idx]; 1489 1490 #ifdef DIAGNOSTIC 1491 /* If this descriptor is still owned by the chip, bail. */ 1492 VGE_TXDESCSYNC(sc, idx, 1493 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1494 td_sts = le32toh(txd->td_sts); 1495 VGE_TXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1496 if (td_sts & VGE_TDSTS_OWN) { 1497 return ENOBUFS; 1498 } 1499 #endif 1500 1501 /* 1502 * Preserve m_pkthdr.csum_flags here since m_head might be 1503 * updated by m_defrag() 1504 */ 1505 m_csumflags = m_head->m_pkthdr.csum_flags; 1506 1507 txs = &sc->sc_txsoft[idx]; 1508 map = txs->txs_dmamap; 1509 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m_head, BUS_DMA_NOWAIT); 1510 1511 /* If too many segments to map, coalesce */ 1512 if (error == EFBIG || 1513 (m_head->m_pkthdr.len < ETHER_PAD_LEN && 1514 map->dm_nsegs == VGE_TX_FRAGS)) { 1515 m_new = m_defrag(m_head, M_DONTWAIT); 1516 if (m_new == NULL) 1517 return EFBIG; 1518 1519 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, 1520 m_new, BUS_DMA_NOWAIT); 1521 if (error) { 1522 m_freem(m_new); 1523 return error; 1524 } 1525 1526 m_head = m_new; 1527 } else if (error) 1528 return error; 1529 1530 txs->txs_mbuf = m_head; 1531 1532 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1533 BUS_DMASYNC_PREWRITE); 1534 1535 for (seg = 0, f = &txd->td_frag[0]; seg < map->dm_nsegs; seg++, f++) { 1536 f->tf_buflen = htole16(VGE_BUFLEN(map->dm_segs[seg].ds_len)); 1537 vge_set_txaddr(f, map->dm_segs[seg].ds_addr); 1538 } 1539 1540 /* Argh. This chip does not autopad short frames */ 1541 sz = m_head->m_pkthdr.len; 1542 if (sz < ETHER_PAD_LEN) { 1543 f->tf_buflen = htole16(VGE_BUFLEN(ETHER_PAD_LEN - sz)); 1544 vge_set_txaddr(f, VGE_CDPADADDR(sc)); 1545 sz = ETHER_PAD_LEN; 1546 seg++; 1547 } 1548 VGE_TXFRAGSYNC(sc, idx, seg, BUS_DMASYNC_PREWRITE); 1549 1550 /* 1551 * When telling the chip how many segments there are, we 1552 * must use nsegs + 1 instead of just nsegs. Darned if I 1553 * know why. 1554 */ 1555 seg++; 1556 1557 flags = 0; 1558 if (m_csumflags & M_CSUM_IPv4) 1559 flags |= VGE_TDCTL_IPCSUM; 1560 if (m_csumflags & M_CSUM_TCPv4) 1561 flags |= VGE_TDCTL_TCPCSUM; 1562 if (m_csumflags & M_CSUM_UDPv4) 1563 flags |= VGE_TDCTL_UDPCSUM; 1564 td_sts = sz << 16; 1565 td_ctl = flags | (seg << 28) | VGE_TD_LS_NORM; 1566 1567 if (sz > ETHERMTU + ETHER_HDR_LEN) 1568 td_ctl |= VGE_TDCTL_JUMBO; 1569 1570 /* 1571 * Set up hardware VLAN tagging. 1572 */ 1573 if (vlan_has_tag(m_head)) { 1574 /* 1575 * No need htons() here since vge(4) chip assumes 1576 * that tags are written in little endian and 1577 * we already use htole32() here. 1578 */ 1579 td_ctl |= vlan_get_tag(m_head) | VGE_TDCTL_VTAG; 1580 } 1581 txd->td_ctl = htole32(td_ctl); 1582 txd->td_sts = htole32(td_sts); 1583 VGE_TXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1584 1585 txd->td_sts = htole32(VGE_TDSTS_OWN | td_sts); 1586 VGE_TXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1587 1588 sc->sc_tx_free--; 1589 1590 return 0; 1591 } 1592 1593 /* 1594 * Main transmit routine. 1595 */ 1596 1597 static void 1598 vge_start(struct ifnet *ifp) 1599 { 1600 struct vge_softc *sc; 1601 struct vge_txsoft *txs; 1602 struct mbuf *m_head; 1603 int idx, pidx, ofree, error; 1604 1605 sc = ifp->if_softc; 1606 1607 if (!sc->sc_link || 1608 (ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) { 1609 return; 1610 } 1611 1612 m_head = NULL; 1613 idx = sc->sc_tx_prodidx; 1614 pidx = VGE_PREV_TXDESC(idx); 1615 ofree = sc->sc_tx_free; 1616 1617 /* 1618 * Loop through the send queue, setting up transmit descriptors 1619 * until we drain the queue, or use up all available transmit 1620 * descriptors. 1621 */ 1622 for (;;) { 1623 /* Grab a packet off the queue. */ 1624 IFQ_POLL(&ifp->if_snd, m_head); 1625 if (m_head == NULL) 1626 break; 1627 1628 if (sc->sc_tx_free == 0) { 1629 /* 1630 * All slots used, stop for now. 1631 */ 1632 ifp->if_flags |= IFF_OACTIVE; 1633 break; 1634 } 1635 1636 txs = &sc->sc_txsoft[idx]; 1637 KASSERT(txs->txs_mbuf == NULL); 1638 1639 if ((error = vge_encap(sc, m_head, idx))) { 1640 if (error == EFBIG) { 1641 printf("%s: Tx packet consumes too many " 1642 "DMA segments, dropping...\n", 1643 device_xname(sc->sc_dev)); 1644 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1645 m_freem(m_head); 1646 continue; 1647 } 1648 1649 /* 1650 * Short on resources, just stop for now. 1651 */ 1652 if (error == ENOBUFS) 1653 ifp->if_flags |= IFF_OACTIVE; 1654 break; 1655 } 1656 1657 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1658 1659 /* 1660 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1661 */ 1662 1663 sc->sc_txdescs[pidx].td_frag[0].tf_buflen |= 1664 htole16(VGE_TXDESC_Q); 1665 VGE_TXFRAGSYNC(sc, pidx, 1, 1666 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1667 1668 if (txs->txs_mbuf != m_head) { 1669 m_freem(m_head); 1670 m_head = txs->txs_mbuf; 1671 } 1672 1673 pidx = idx; 1674 idx = VGE_NEXT_TXDESC(idx); 1675 1676 /* 1677 * If there's a BPF listener, bounce a copy of this frame 1678 * to him. 1679 */ 1680 bpf_mtap(ifp, m_head, BPF_D_OUT); 1681 } 1682 1683 if (sc->sc_tx_free < ofree) { 1684 /* TX packet queued */ 1685 1686 sc->sc_tx_prodidx = idx; 1687 1688 /* Issue a transmit command. */ 1689 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1690 1691 /* 1692 * Use the countdown timer for interrupt moderation. 1693 * 'TX done' interrupts are disabled. Instead, we reset the 1694 * countdown timer, which will begin counting until it hits 1695 * the value in the SSTIMER register, and then trigger an 1696 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1697 * the timer count is reloaded. Only when the transmitter 1698 * is idle will the timer hit 0 and an interrupt fire. 1699 */ 1700 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1701 1702 /* 1703 * Set a timeout in case the chip goes out to lunch. 1704 */ 1705 ifp->if_timer = 5; 1706 } 1707 } 1708 1709 static int 1710 vge_init(struct ifnet *ifp) 1711 { 1712 struct vge_softc *sc; 1713 int i, rc = 0; 1714 1715 sc = ifp->if_softc; 1716 1717 /* 1718 * Cancel pending I/O and free all RX/TX buffers. 1719 */ 1720 vge_stop(ifp, 0); 1721 vge_reset(sc); 1722 1723 /* Initialize the RX descriptors and mbufs. */ 1724 memset(sc->sc_rxdescs, 0, sizeof(sc->sc_rxdescs)); 1725 sc->sc_rx_consumed = 0; 1726 for (i = 0; i < VGE_NRXDESC; i++) { 1727 if (vge_newbuf(sc, i, NULL) == ENOBUFS) { 1728 printf("%s: unable to allocate or map rx buffer\n", 1729 device_xname(sc->sc_dev)); 1730 return 1; /* XXX */ 1731 } 1732 } 1733 sc->sc_rx_prodidx = 0; 1734 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL; 1735 1736 /* Initialize the TX descriptors and mbufs. */ 1737 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1738 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 1739 VGE_CDTXOFF(0), sizeof(sc->sc_txdescs), 1740 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1741 for (i = 0; i < VGE_NTXDESC; i++) 1742 sc->sc_txsoft[i].txs_mbuf = NULL; 1743 1744 sc->sc_tx_prodidx = 0; 1745 sc->sc_tx_considx = 0; 1746 sc->sc_tx_free = VGE_NTXDESC; 1747 1748 /* Set our station address */ 1749 for (i = 0; i < ETHER_ADDR_LEN; i++) 1750 CSR_WRITE_1(sc, VGE_PAR0 + i, sc->sc_eaddr[i]); 1751 1752 /* 1753 * Set receive FIFO threshold. Also allow transmission and 1754 * reception of VLAN tagged frames. 1755 */ 1756 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 1757 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 1758 1759 /* Set DMA burst length */ 1760 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1761 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1762 1763 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1764 1765 /* Set collision backoff algorithm */ 1766 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1767 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1768 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1769 1770 /* Disable LPSEL field in priority resolution */ 1771 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1772 1773 /* 1774 * Load the addresses of the DMA queues into the chip. 1775 * Note that we only use one transmit queue. 1776 */ 1777 1778 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, VGE_ADDR_LO(VGE_CDTXADDR(sc, 0))); 1779 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_NTXDESC - 1); 1780 1781 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, VGE_ADDR_LO(VGE_CDRXADDR(sc, 0))); 1782 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_NRXDESC - 1); 1783 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_NRXDESC); 1784 1785 /* Enable and wake up the RX descriptor queue */ 1786 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1787 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1788 1789 /* Enable the TX descriptor queue */ 1790 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 1791 1792 /* Set up the receive filter -- allow large frames for VLANs. */ 1793 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 1794 1795 /* If we want promiscuous mode, set the allframes bit. */ 1796 if (ifp->if_flags & IFF_PROMISC) { 1797 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 1798 } 1799 1800 /* Set capture broadcast bit to capture broadcast frames. */ 1801 if (ifp->if_flags & IFF_BROADCAST) { 1802 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 1803 } 1804 1805 /* Set multicast bit to capture multicast frames. */ 1806 if (ifp->if_flags & IFF_MULTICAST) { 1807 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 1808 } 1809 1810 /* Init the cam filter. */ 1811 vge_cam_clear(sc); 1812 1813 /* Init the multicast filter. */ 1814 vge_setmulti(sc); 1815 1816 /* Enable flow control */ 1817 1818 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 1819 1820 /* Enable jumbo frame reception (if desired) */ 1821 1822 /* Start the MAC. */ 1823 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 1824 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 1825 CSR_WRITE_1(sc, VGE_CRS0, 1826 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 1827 1828 /* 1829 * Configure one-shot timer for microsecond 1830 * resulution and load it for 500 usecs. 1831 */ 1832 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 1833 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 1834 1835 /* 1836 * Configure interrupt moderation for receive. Enable 1837 * the holdoff counter and load it, and set the RX 1838 * suppression count to the number of descriptors we 1839 * want to allow before triggering an interrupt. 1840 * The holdoff timer is in units of 20 usecs. 1841 */ 1842 1843 #ifdef notyet 1844 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 1845 /* Select the interrupt holdoff timer page. */ 1846 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1847 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 1848 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 1849 1850 /* Enable use of the holdoff timer. */ 1851 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 1852 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 1853 1854 /* Select the RX suppression threshold page. */ 1855 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1856 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 1857 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 1858 1859 /* Restore the page select bits. */ 1860 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1861 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 1862 #endif 1863 1864 #ifdef DEVICE_POLLING 1865 /* 1866 * Disable interrupts if we are polling. 1867 */ 1868 if (ifp->if_flags & IFF_POLLING) { 1869 CSR_WRITE_4(sc, VGE_IMR, 0); 1870 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1871 } else /* otherwise ... */ 1872 #endif /* DEVICE_POLLING */ 1873 { 1874 /* 1875 * Enable interrupts. 1876 */ 1877 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1878 CSR_WRITE_4(sc, VGE_ISR, 0); 1879 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1880 } 1881 1882 if ((rc = ether_mediachange(ifp)) != 0) 1883 goto out; 1884 1885 ifp->if_flags |= IFF_RUNNING; 1886 ifp->if_flags &= ~IFF_OACTIVE; 1887 1888 sc->sc_if_flags = 0; 1889 sc->sc_link = 0; 1890 1891 callout_schedule(&sc->sc_timeout, hz); 1892 1893 out: 1894 return rc; 1895 } 1896 1897 static void 1898 vge_miibus_statchg(struct ifnet *ifp) 1899 { 1900 struct vge_softc *sc = ifp->if_softc; 1901 struct mii_data *mii = &sc->sc_mii; 1902 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 1903 1904 /* 1905 * If the user manually selects a media mode, we need to turn 1906 * on the forced MAC mode bit in the DIAGCTL register. If the 1907 * user happens to choose a full duplex mode, we also need to 1908 * set the 'force full duplex' bit. This applies only to 1909 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 1910 * mode is disabled, and in 1000baseT mode, full duplex is 1911 * always implied, so we turn on the forced mode bit but leave 1912 * the FDX bit cleared. 1913 */ 1914 1915 switch (IFM_SUBTYPE(ife->ifm_media)) { 1916 case IFM_AUTO: 1917 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1918 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1919 break; 1920 case IFM_1000_T: 1921 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1922 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1923 break; 1924 case IFM_100_TX: 1925 case IFM_10_T: 1926 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1927 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 1928 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1929 } else { 1930 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1931 } 1932 break; 1933 default: 1934 printf("%s: unknown media type: %x\n", 1935 device_xname(sc->sc_dev), 1936 IFM_SUBTYPE(ife->ifm_media)); 1937 break; 1938 } 1939 } 1940 1941 static int 1942 vge_ifflags_cb(struct ethercom *ec) 1943 { 1944 struct ifnet *ifp = &ec->ec_if; 1945 struct vge_softc *sc = ifp->if_softc; 1946 int change = ifp->if_flags ^ sc->sc_if_flags; 1947 1948 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 1949 return ENETRESET; 1950 else if ((change & IFF_PROMISC) == 0) 1951 return 0; 1952 1953 if ((ifp->if_flags & IFF_PROMISC) == 0) 1954 CSR_CLRBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 1955 else 1956 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 1957 vge_setmulti(sc); 1958 return 0; 1959 } 1960 1961 static int 1962 vge_ioctl(struct ifnet *ifp, u_long command, void *data) 1963 { 1964 struct vge_softc *sc; 1965 int s, error; 1966 1967 sc = ifp->if_softc; 1968 error = 0; 1969 1970 s = splnet(); 1971 1972 if ((error = ether_ioctl(ifp, command, data)) == ENETRESET) { 1973 error = 0; 1974 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1975 ; 1976 else if (ifp->if_flags & IFF_RUNNING) { 1977 /* 1978 * Multicast list has changed; set the hardware filter 1979 * accordingly. 1980 */ 1981 vge_setmulti(sc); 1982 } 1983 } 1984 sc->sc_if_flags = ifp->if_flags; 1985 1986 splx(s); 1987 return error; 1988 } 1989 1990 static void 1991 vge_watchdog(struct ifnet *ifp) 1992 { 1993 struct vge_softc *sc; 1994 int s; 1995 1996 sc = ifp->if_softc; 1997 s = splnet(); 1998 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1999 ifp->if_oerrors++; 2000 2001 vge_txeof(sc); 2002 vge_rxeof(sc); 2003 2004 vge_init(ifp); 2005 2006 splx(s); 2007 } 2008 2009 /* 2010 * Stop the adapter and free any mbufs allocated to the 2011 * RX and TX lists. 2012 */ 2013 static void 2014 vge_stop(struct ifnet *ifp, int disable) 2015 { 2016 struct vge_softc *sc = ifp->if_softc; 2017 struct vge_txsoft *txs; 2018 struct vge_rxsoft *rxs; 2019 int i, s; 2020 2021 s = splnet(); 2022 ifp->if_timer = 0; 2023 2024 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2025 #ifdef DEVICE_POLLING 2026 ether_poll_deregister(ifp); 2027 #endif /* DEVICE_POLLING */ 2028 2029 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2030 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2031 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2032 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2033 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2034 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2035 2036 if (sc->sc_rx_mhead != NULL) { 2037 m_freem(sc->sc_rx_mhead); 2038 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL; 2039 } 2040 2041 /* Free the TX list buffers. */ 2042 2043 for (i = 0; i < VGE_NTXDESC; i++) { 2044 txs = &sc->sc_txsoft[i]; 2045 if (txs->txs_mbuf != NULL) { 2046 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2047 m_freem(txs->txs_mbuf); 2048 txs->txs_mbuf = NULL; 2049 } 2050 } 2051 2052 /* Free the RX list buffers. */ 2053 2054 for (i = 0; i < VGE_NRXDESC; i++) { 2055 rxs = &sc->sc_rxsoft[i]; 2056 if (rxs->rxs_mbuf != NULL) { 2057 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2058 m_freem(rxs->rxs_mbuf); 2059 rxs->rxs_mbuf = NULL; 2060 } 2061 } 2062 2063 splx(s); 2064 } 2065 2066 #if VGE_POWER_MANAGEMENT 2067 /* 2068 * Device suspend routine. Stop the interface and save some PCI 2069 * settings in case the BIOS doesn't restore them properly on 2070 * resume. 2071 */ 2072 static int 2073 vge_suspend(device_t dev) 2074 { 2075 struct vge_softc *sc; 2076 int i; 2077 2078 sc = device_get_softc(dev); 2079 2080 vge_stop(sc); 2081 2082 for (i = 0; i < 5; i++) 2083 sc->sc_saved_maps[i] = 2084 pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2085 sc->sc_saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2086 sc->sc_saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2087 sc->sc_saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2088 sc->sc_saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2089 2090 sc->suspended = 1; 2091 2092 return 0; 2093 } 2094 2095 /* 2096 * Device resume routine. Restore some PCI settings in case the BIOS 2097 * doesn't, re-enable busmastering, and restart the interface if 2098 * appropriate. 2099 */ 2100 static int 2101 vge_resume(device_t dev) 2102 { 2103 struct vge_softc *sc; 2104 struct ifnet *ifp; 2105 int i; 2106 2107 sc = device_private(dev); 2108 ifp = &sc->sc_ethercom.ec_if; 2109 2110 /* better way to do this? */ 2111 for (i = 0; i < 5; i++) 2112 pci_write_config(dev, PCIR_MAPS + i * 4, 2113 sc->sc_saved_maps[i], 4); 2114 pci_write_config(dev, PCIR_BIOS, sc->sc_saved_biosaddr, 4); 2115 pci_write_config(dev, PCIR_INTLINE, sc->sc_saved_intline, 1); 2116 pci_write_config(dev, PCIR_CACHELNSZ, sc->sc_saved_cachelnsz, 1); 2117 pci_write_config(dev, PCIR_LATTIMER, sc->sc_saved_lattimer, 1); 2118 2119 /* reenable busmastering */ 2120 pci_enable_busmaster(dev); 2121 pci_enable_io(dev, SYS_RES_MEMORY); 2122 2123 /* reinitialize interface if necessary */ 2124 if (ifp->if_flags & IFF_UP) 2125 vge_init(sc); 2126 2127 sc->suspended = 0; 2128 2129 return 0; 2130 } 2131 #endif 2132 2133 /* 2134 * Stop all chip I/O so that the kernel's probe routines don't 2135 * get confused by errant DMAs when rebooting. 2136 */ 2137 static bool 2138 vge_shutdown(device_t self, int howto) 2139 { 2140 struct vge_softc *sc; 2141 2142 sc = device_private(self); 2143 vge_stop(&sc->sc_ethercom.ec_if, 1); 2144 2145 return true; 2146 } 2147