1 /* $NetBSD: if_vge.c,v 1.2 2005/02/27 00:27:33 perry Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD: src/sys/dev/vge/if_vge.c,v 1.5 2005/02/07 19:39:29 glebius Exp 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_vge.c,v 1.2 2005/02/27 00:27:33 perry Exp $"); 39 40 /* 41 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 42 * 43 * Written by Bill Paul <wpaul@windriver.com> 44 * Senior Networking Software Engineer 45 * Wind River Systems 46 */ 47 48 /* 49 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that 50 * combines a tri-speed ethernet MAC and PHY, with the following 51 * features: 52 * 53 * o Jumbo frame support up to 16K 54 * o Transmit and receive flow control 55 * o IPv4 checksum offload 56 * o VLAN tag insertion and stripping 57 * o TCP large send 58 * o 64-bit multicast hash table filter 59 * o 64 entry CAM filter 60 * o 16K RX FIFO and 48K TX FIFO memory 61 * o Interrupt moderation 62 * 63 * The VT6122 supports up to four transmit DMA queues. The descriptors 64 * in the transmit ring can address up to 7 data fragments; frames which 65 * span more than 7 data buffers must be coalesced, but in general the 66 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 67 * long. The receive descriptors address only a single buffer. 68 * 69 * There are two peculiar design issues with the VT6122. One is that 70 * receive data buffers must be aligned on a 32-bit boundary. This is 71 * not a problem where the VT6122 is used as a LOM device in x86-based 72 * systems, but on architectures that generate unaligned access traps, we 73 * have to do some copying. 74 * 75 * The other issue has to do with the way 64-bit addresses are handled. 76 * The DMA descriptors only allow you to specify 48 bits of addressing 77 * information. The remaining 16 bits are specified using one of the 78 * I/O registers. If you only have a 32-bit system, then this isn't 79 * an issue, but if you have a 64-bit system and more than 4GB of 80 * memory, you must have to make sure your network data buffers reside 81 * in the same 48-bit 'segment.' 82 * 83 * Special thanks to Ryan Fu at VIA Networking for providing documentation 84 * and sample NICs for testing. 85 */ 86 87 #include "bpfilter.h" 88 89 #include <sys/param.h> 90 #include <sys/endian.h> 91 #include <sys/systm.h> 92 #include <sys/sockio.h> 93 #include <sys/mbuf.h> 94 #include <sys/malloc.h> 95 #include <sys/kernel.h> 96 #include <sys/socket.h> 97 98 #include <net/if.h> 99 #include <net/if_arp.h> 100 #include <net/if_ether.h> 101 #include <net/if_dl.h> 102 #include <net/if_media.h> 103 104 #include <net/bpf.h> 105 106 #include <machine/bus.h> 107 108 #include <dev/mii/mii.h> 109 #include <dev/mii/miivar.h> 110 111 #include <dev/pci/pcireg.h> 112 #include <dev/pci/pcivar.h> 113 #include <dev/pci/pcidevs.h> 114 115 #include <dev/pci/if_vgereg.h> 116 #include <dev/pci/if_vgevar.h> 117 118 static int vge_probe (struct device *, struct cfdata *, void *); 119 static void vge_attach (struct device *, struct device *, void *); 120 121 static int vge_encap (struct vge_softc *, struct mbuf *, int); 122 123 static int vge_dma_map_rx_desc (struct vge_softc *, int); 124 static int vge_dma_map_tx_desc (struct vge_softc *, struct mbuf *, int, int); 125 static int vge_allocmem (struct vge_softc *); 126 static int vge_newbuf (struct vge_softc *, int, struct mbuf *); 127 static int vge_rx_list_init (struct vge_softc *); 128 static int vge_tx_list_init (struct vge_softc *); 129 #ifdef VGE_FIXUP_RX 130 static __inline void vge_fixup_rx 131 (struct mbuf *); 132 #endif 133 static void vge_rxeof (struct vge_softc *); 134 static void vge_txeof (struct vge_softc *); 135 static int vge_intr (void *); 136 static void vge_tick (void *); 137 static void vge_start (struct ifnet *); 138 static int vge_ioctl (struct ifnet *, u_long, caddr_t); 139 static int vge_init (struct ifnet *); 140 static void vge_stop (struct vge_softc *); 141 static void vge_watchdog (struct ifnet *); 142 #if VGE_POWER_MANAGEMENT 143 static int vge_suspend (struct device *); 144 static int vge_resume (struct device *); 145 #endif 146 static void vge_shutdown (void *); 147 static int vge_ifmedia_upd (struct ifnet *); 148 static void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 149 150 static void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 151 static void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 152 153 static void vge_miipoll_start (struct vge_softc *); 154 static void vge_miipoll_stop (struct vge_softc *); 155 static int vge_miibus_readreg (struct device *, int, int); 156 static void vge_miibus_writereg (struct device *, int, int, int); 157 static void vge_miibus_statchg (struct device *); 158 159 static void vge_cam_clear (struct vge_softc *); 160 static int vge_cam_set (struct vge_softc *, uint8_t *); 161 static void vge_setmulti (struct vge_softc *); 162 static void vge_reset (struct vge_softc *); 163 164 #define VGE_PCI_LOIO 0x10 165 #define VGE_PCI_LOMEM 0x14 166 167 CFATTACH_DECL(vge, sizeof(struct vge_softc), 168 vge_probe, vge_attach, NULL, NULL); 169 170 /* 171 * Defragment mbuf chain contents to be as linear as possible. 172 * Returns new mbuf chain on success, NULL on failure. Old mbuf 173 * chain is always freed. 174 * XXX temporary until there would be generic function doing this. 175 */ 176 #define m_defrag vge_m_defrag 177 struct mbuf * vge_m_defrag(struct mbuf *, int); 178 179 struct mbuf * 180 vge_m_defrag(struct mbuf *m0, int flags) 181 { 182 struct mbuf *m; 183 184 #ifdef DIAGNOSTIC 185 if ((m0->m_flags & M_PKTHDR) == 0) 186 panic("m_defrag: not a mbuf chain header"); 187 #endif 188 189 if (m0->m_pkthdr.len > MCLBYTES) { 190 /* XXX TODO no defragmentation for JUMBO packets, yet */ 191 m = NULL; 192 goto out; 193 } 194 195 MGETHDR(m, flags, MT_DATA); 196 if (m == NULL) 197 goto out; 198 199 if (m0->m_pkthdr.len > MHLEN) { 200 MCLGET(m, M_DONTWAIT); 201 if ((m->m_flags & M_EXT) == 0) { 202 m_freem(m); 203 m = NULL; 204 goto out; 205 } 206 } 207 208 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 209 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 210 211 out: 212 m_freem(m0); 213 return m; 214 } 215 216 /* 217 * Read a word of data stored in the EEPROM at address 'addr.' 218 */ 219 static void 220 vge_eeprom_getword(sc, addr, dest) 221 struct vge_softc *sc; 222 int addr; 223 u_int16_t *dest; 224 { 225 register int i; 226 u_int16_t word = 0; 227 228 /* 229 * Enter EEPROM embedded programming mode. In order to 230 * access the EEPROM at all, we first have to set the 231 * EELOAD bit in the CHIPCFG2 register. 232 */ 233 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 234 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 235 236 /* Select the address of the word we want to read */ 237 CSR_WRITE_1(sc, VGE_EEADDR, addr); 238 239 /* Issue read command */ 240 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 241 242 /* Wait for the done bit to be set. */ 243 for (i = 0; i < VGE_TIMEOUT; i++) { 244 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 245 break; 246 } 247 248 if (i == VGE_TIMEOUT) { 249 printf("%s: EEPROM read timed out\n", sc->sc_dev.dv_xname); 250 *dest = 0; 251 return; 252 } 253 254 /* Read the result */ 255 word = CSR_READ_2(sc, VGE_EERDDAT); 256 257 /* Turn off EEPROM access mode. */ 258 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 259 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 260 261 *dest = word; 262 263 return; 264 } 265 266 /* 267 * Read a sequence of words from the EEPROM. 268 */ 269 static void 270 vge_read_eeprom(sc, dest, off, cnt, swap) 271 struct vge_softc *sc; 272 caddr_t dest; 273 int off; 274 int cnt; 275 int swap; 276 { 277 int i; 278 u_int16_t word = 0, *ptr; 279 280 for (i = 0; i < cnt; i++) { 281 vge_eeprom_getword(sc, off + i, &word); 282 ptr = (u_int16_t *)(dest + (i * 2)); 283 if (swap) 284 *ptr = ntohs(word); 285 else 286 *ptr = word; 287 } 288 } 289 290 static void 291 vge_miipoll_stop(sc) 292 struct vge_softc *sc; 293 { 294 int i; 295 296 CSR_WRITE_1(sc, VGE_MIICMD, 0); 297 298 for (i = 0; i < VGE_TIMEOUT; i++) { 299 DELAY(1); 300 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 301 break; 302 } 303 304 if (i == VGE_TIMEOUT) { 305 printf("%s: failed to idle MII autopoll\n", 306 sc->sc_dev.dv_xname); 307 } 308 309 return; 310 } 311 312 static void 313 vge_miipoll_start(sc) 314 struct vge_softc *sc; 315 { 316 int i; 317 318 /* First, make sure we're idle. */ 319 320 CSR_WRITE_1(sc, VGE_MIICMD, 0); 321 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 322 323 for (i = 0; i < VGE_TIMEOUT; i++) { 324 DELAY(1); 325 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 326 break; 327 } 328 329 if (i == VGE_TIMEOUT) { 330 printf("%s: failed to idle MII autopoll\n", 331 sc->sc_dev.dv_xname); 332 return; 333 } 334 335 /* Now enable auto poll mode. */ 336 337 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 338 339 /* And make sure it started. */ 340 341 for (i = 0; i < VGE_TIMEOUT; i++) { 342 DELAY(1); 343 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 344 break; 345 } 346 347 if (i == VGE_TIMEOUT) { 348 printf("%s: failed to start MII autopoll\n", 349 sc->sc_dev.dv_xname); 350 } 351 } 352 353 static int 354 vge_miibus_readreg(dev, phy, reg) 355 struct device *dev; 356 int phy, reg; 357 { 358 struct vge_softc *sc = (struct vge_softc *)dev; 359 int i; 360 u_int16_t rval = 0; 361 362 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 363 return(0); 364 365 VGE_LOCK(sc); 366 vge_miipoll_stop(sc); 367 368 /* Specify the register we want to read. */ 369 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 370 371 /* Issue read command. */ 372 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 373 374 /* Wait for the read command bit to self-clear. */ 375 for (i = 0; i < VGE_TIMEOUT; i++) { 376 DELAY(1); 377 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 378 break; 379 } 380 381 if (i == VGE_TIMEOUT) 382 printf("%s: MII read timed out\n", sc->sc_dev.dv_xname); 383 else 384 rval = CSR_READ_2(sc, VGE_MIIDATA); 385 386 vge_miipoll_start(sc); 387 VGE_UNLOCK(sc); 388 389 return (rval); 390 } 391 392 static void 393 vge_miibus_writereg(dev, phy, reg, data) 394 struct device *dev; 395 int phy, reg, data; 396 { 397 struct vge_softc *sc = (struct vge_softc *)dev; 398 int i; 399 400 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 401 return; 402 403 VGE_LOCK(sc); 404 vge_miipoll_stop(sc); 405 406 /* Specify the register we want to write. */ 407 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 408 409 /* Specify the data we want to write. */ 410 CSR_WRITE_2(sc, VGE_MIIDATA, data); 411 412 /* Issue write command. */ 413 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 414 415 /* Wait for the write command bit to self-clear. */ 416 for (i = 0; i < VGE_TIMEOUT; i++) { 417 DELAY(1); 418 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 419 break; 420 } 421 422 if (i == VGE_TIMEOUT) { 423 printf("%s: MII write timed out\n", sc->sc_dev.dv_xname); 424 } 425 426 vge_miipoll_start(sc); 427 VGE_UNLOCK(sc); 428 } 429 430 static void 431 vge_cam_clear(sc) 432 struct vge_softc *sc; 433 { 434 int i; 435 436 /* 437 * Turn off all the mask bits. This tells the chip 438 * that none of the entries in the CAM filter are valid. 439 * desired entries will be enabled as we fill the filter in. 440 */ 441 442 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 443 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 444 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 445 for (i = 0; i < 8; i++) 446 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 447 448 /* Clear the VLAN filter too. */ 449 450 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 451 for (i = 0; i < 8; i++) 452 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 453 454 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 455 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 456 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 457 458 sc->vge_camidx = 0; 459 460 return; 461 } 462 463 static int 464 vge_cam_set(sc, addr) 465 struct vge_softc *sc; 466 uint8_t *addr; 467 { 468 int i, error = 0; 469 470 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 471 return(ENOSPC); 472 473 /* Select the CAM data page. */ 474 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 475 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 476 477 /* Set the filter entry we want to update and enable writing. */ 478 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 479 480 /* Write the address to the CAM registers */ 481 for (i = 0; i < ETHER_ADDR_LEN; i++) 482 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 483 484 /* Issue a write command. */ 485 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 486 487 /* Wake for it to clear. */ 488 for (i = 0; i < VGE_TIMEOUT; i++) { 489 DELAY(1); 490 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 491 break; 492 } 493 494 if (i == VGE_TIMEOUT) { 495 printf("%s: setting CAM filter failed\n", sc->sc_dev.dv_xname); 496 error = EIO; 497 goto fail; 498 } 499 500 /* Select the CAM mask page. */ 501 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 502 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 503 504 /* Set the mask bit that enables this filter. */ 505 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 506 1<<(sc->vge_camidx & 7)); 507 508 sc->vge_camidx++; 509 510 fail: 511 /* Turn off access to CAM. */ 512 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 513 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 514 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 515 516 return (error); 517 } 518 519 /* 520 * Program the multicast filter. We use the 64-entry CAM filter 521 * for perfect filtering. If there's more than 64 multicast addresses, 522 * we use the hash filter insted. 523 */ 524 static void 525 vge_setmulti(sc) 526 struct vge_softc *sc; 527 { 528 struct ifnet *ifp; 529 int error = 0; 530 u_int32_t h, hashes[2] = { 0, 0 }; 531 struct ether_multi *enm; 532 struct ether_multistep step; 533 534 ifp = &sc->sc_ethercom.ec_if; 535 536 /* First, zot all the multicast entries. */ 537 vge_cam_clear(sc); 538 CSR_WRITE_4(sc, VGE_MAR0, 0); 539 CSR_WRITE_4(sc, VGE_MAR1, 0); 540 541 /* 542 * If the user wants allmulti or promisc mode, enable reception 543 * of all multicast frames. 544 */ 545 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 546 allmulti: 547 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 548 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 549 return; 550 } 551 552 /* Now program new ones */ 553 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 554 while(enm != NULL) { 555 /* 556 * If multicast range, fall back to ALLMULTI. 557 */ 558 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 559 ETHER_ADDR_LEN) != 0) 560 goto allmulti; 561 562 error = vge_cam_set(sc, 563 LLADDR((struct sockaddr_dl *)enm->enm_addrlo)); 564 if (error) 565 break; 566 567 ETHER_NEXT_MULTI(step, enm); 568 } 569 570 /* If there were too many addresses, use the hash filter. */ 571 if (error) { 572 vge_cam_clear(sc); 573 574 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 575 while(enm != NULL) { 576 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 577 enm->enm_addrlo), ETHER_ADDR_LEN) >> 26; 578 if (h < 32) 579 hashes[0] |= (1 << h); 580 else 581 hashes[1] |= (1 << (h - 32)); 582 } 583 584 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 585 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 586 } 587 588 return; 589 } 590 591 static void 592 vge_reset(sc) 593 struct vge_softc *sc; 594 { 595 register int i; 596 597 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 598 599 for (i = 0; i < VGE_TIMEOUT; i++) { 600 DELAY(5); 601 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 602 break; 603 } 604 605 if (i == VGE_TIMEOUT) { 606 printf("%s: soft reset timed out", sc->sc_dev.dv_xname); 607 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 608 DELAY(2000); 609 } 610 611 DELAY(5000); 612 613 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 614 615 for (i = 0; i < VGE_TIMEOUT; i++) { 616 DELAY(5); 617 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 618 break; 619 } 620 621 if (i == VGE_TIMEOUT) { 622 printf("%s: EEPROM reload timed out\n", sc->sc_dev.dv_xname); 623 return; 624 } 625 626 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 627 628 return; 629 } 630 631 /* 632 * Probe for a VIA gigabit chip. Check the PCI vendor and device 633 * IDs against our list and return a device name if we find a match. 634 */ 635 static int 636 vge_probe(struct device *parent, struct cfdata *match, void *aux) 637 { 638 struct pci_attach_args *pa = aux; 639 640 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH 641 && PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_VIATECH_VT612X) 642 return 1; 643 644 return (0); 645 } 646 647 static int 648 vge_dma_map_rx_desc(sc, idx) 649 struct vge_softc *sc; 650 int idx; 651 { 652 struct vge_rx_desc *d = NULL; 653 bus_dma_segment_t *segs; 654 655 /* 656 * Map the segment array into descriptors. 657 */ 658 659 d = &sc->vge_ldata.vge_rx_list[idx]; 660 661 /* If this descriptor is still owned by the chip, bail. */ 662 663 if (le32toh(d->vge_sts) & VGE_RDSTS_OWN) { 664 printf("%s: tried to map busy descriptor\n", 665 sc->sc_dev.dv_xname); 666 return (EBUSY); 667 } 668 669 segs = sc->vge_ldata.vge_rx_dmamap[idx]->dm_segs; 670 671 d->vge_buflen = htole16(VGE_BUFLEN(segs[0].ds_len) | VGE_RXDESC_I); 672 d->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 673 d->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 674 d->vge_sts = 0; 675 d->vge_ctl = 0; 676 677 return (0); 678 } 679 680 static int 681 vge_dma_map_tx_desc(sc, m0, idx, flags) 682 struct vge_softc *sc; 683 struct mbuf *m0; 684 int idx, flags; 685 { 686 struct vge_tx_desc *d = NULL; 687 struct vge_tx_frag *f; 688 int i = 0; 689 bus_dma_segment_t *segs; 690 size_t sz; 691 bus_dmamap_t map = sc->vge_ldata.vge_tx_dmamap[idx]; 692 693 /* Map the segment array into descriptors. */ 694 695 d = &sc->vge_ldata.vge_tx_list[idx]; 696 697 /* If this descriptor is still owned by the chip, bail. */ 698 699 if (le32toh(d->vge_sts) & VGE_TDSTS_OWN) 700 return (EBUSY); 701 702 segs = map->dm_segs; 703 for (i = 0; i < map->dm_nsegs; i++) { 704 f = &d->vge_frag[i]; 705 f->vge_buflen = htole16(VGE_BUFLEN(segs[i].ds_len)); 706 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[i].ds_addr)); 707 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[i].ds_addr) & 0xFFFF); 708 } 709 710 /* Argh. This chip does not autopad short frames */ 711 712 sz = m0->m_pkthdr.len; 713 if (m0->m_pkthdr.len < VGE_MIN_FRAMELEN) { 714 f = &d->vge_frag[i]; 715 f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - sz)); 716 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 717 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 718 sz = VGE_MIN_FRAMELEN; 719 i++; 720 } 721 722 /* 723 * When telling the chip how many segments there are, we 724 * must use nsegs + 1 instead of just nsegs. Darned if I 725 * know why. 726 */ 727 i++; 728 729 d->vge_sts = sz << 16; 730 d->vge_ctl = flags|(i << 28)|VGE_TD_LS_NORM; 731 732 if (sz > ETHERMTU + ETHER_HDR_LEN) 733 d->vge_ctl |= VGE_TDCTL_JUMBO; 734 735 return (0); 736 } 737 738 static int 739 vge_allocmem(sc) 740 struct vge_softc *sc; 741 { 742 int error; 743 int nseg; 744 int i; 745 bus_dma_segment_t seg; 746 747 /* 748 * Allocate map for TX descriptor list. 749 */ 750 error = bus_dmamap_create(sc->vge_dmat, 751 round_page(VGE_TX_LIST_SZ), 1, round_page(VGE_TX_LIST_SZ), 752 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, 753 &sc->vge_ldata.vge_tx_list_map); 754 if (error) { 755 printf("%s: could not allocate TX dma list map\n", 756 sc->sc_dev.dv_xname); 757 return (ENOMEM); 758 } 759 760 /* 761 * Allocate memory for TX descriptor list. 762 */ 763 764 error = bus_dmamem_alloc(sc->vge_dmat, VGE_TX_LIST_SZ, VGE_RING_ALIGN, 765 0, &seg, 1, &nseg, BUS_DMA_NOWAIT); 766 if (error) { 767 printf("%s: could not allocate TX ring dma memory\n", 768 sc->sc_dev.dv_xname); 769 return (ENOMEM); 770 } 771 772 /* Map the memory to kernel VA space */ 773 774 error = bus_dmamem_map(sc->vge_dmat, &seg, nseg, seg.ds_len, 775 (caddr_t *) &sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT); 776 if (error) { 777 printf("%s: could not map TX ring dma memory\n", 778 sc->sc_dev.dv_xname); 779 return (ENOMEM); 780 } 781 782 /* Load the map for the TX ring. */ 783 error = bus_dmamap_load(sc->vge_dmat, sc->vge_ldata.vge_tx_list_map, 784 sc->vge_ldata.vge_tx_list, seg.ds_len, NULL, BUS_DMA_NOWAIT); 785 if (error) { 786 printf("%s: could not load TX ring dma memory\n", 787 sc->sc_dev.dv_xname); 788 return (ENOMEM); 789 } 790 791 sc->vge_ldata.vge_tx_list_addr = 792 sc->vge_ldata.vge_tx_list_map->dm_segs[0].ds_addr; 793 794 /* Create DMA maps for TX buffers */ 795 796 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 797 error = bus_dmamap_create(sc->vge_dmat, VGE_TX_MAXLEN, 798 VGE_TX_FRAGS, VGE_TX_MAXLEN, 0, 799 BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW, 800 &sc->vge_ldata.vge_tx_dmamap[i]); 801 if (error) { 802 printf("%s: can't create DMA map for TX\n", 803 sc->sc_dev.dv_xname); 804 return (ENOMEM); 805 } 806 } 807 808 /* 809 * Allocate map for RX descriptor list. 810 */ 811 error = bus_dmamap_create(sc->vge_dmat, 812 round_page(VGE_RX_LIST_SZ), 1, round_page(VGE_RX_LIST_SZ), 813 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, 814 &sc->vge_ldata.vge_rx_list_map); 815 if (error) { 816 printf("%s: could not allocate RX dma list map\n", 817 sc->sc_dev.dv_xname); 818 return (ENOMEM); 819 } 820 821 /* Allocate DMA'able memory for the RX ring */ 822 823 error = bus_dmamem_alloc(sc->vge_dmat, VGE_RX_LIST_SZ, VGE_RING_ALIGN, 824 0, &seg, 1, &nseg, BUS_DMA_NOWAIT); 825 if (error) 826 return (ENOMEM); 827 828 /* Map the memory to kernel VA space */ 829 830 error = bus_dmamem_map(sc->vge_dmat, &seg, nseg, seg.ds_len, 831 (caddr_t *) &sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT); 832 if (error) 833 return (ENOMEM); 834 835 /* Load the map for the RX ring. */ 836 error = bus_dmamap_load(sc->vge_dmat, sc->vge_ldata.vge_rx_list_map, 837 sc->vge_ldata.vge_rx_list, seg.ds_len, NULL, BUS_DMA_NOWAIT); 838 if (error) { 839 printf("%s: could not load RX ring dma memory\n", 840 sc->sc_dev.dv_xname); 841 return (ENOMEM); 842 } 843 844 sc->vge_ldata.vge_rx_list_addr = 845 sc->vge_ldata.vge_rx_list_map->dm_segs[0].ds_addr; 846 847 /* Create DMA maps for RX buffers */ 848 849 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 850 error = bus_dmamap_create(sc->vge_dmat, MCLBYTES, 851 1, MCLBYTES, 0, BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW, 852 &sc->vge_ldata.vge_rx_dmamap[i]); 853 if (error) { 854 printf("%s: can't create DMA map for RX\n", 855 sc->sc_dev.dv_xname); 856 return (ENOMEM); 857 } 858 } 859 860 return (0); 861 } 862 863 /* 864 * Attach the interface. Allocate softc structures, do ifmedia 865 * setup and ethernet/BPF attach. 866 */ 867 static void 868 vge_attach(struct device *parent, struct device *self, void *aux) 869 { 870 u_char eaddr[ETHER_ADDR_LEN]; 871 struct vge_softc *sc = (struct vge_softc *)self; 872 struct ifnet *ifp; 873 int error = 0; 874 struct pci_attach_args *pa = aux; 875 pci_chipset_tag_t pc = pa->pa_pc; 876 const char *intrstr; 877 pci_intr_handle_t ih; 878 879 aprint_normal(": VIA VT612X Gigabit Ethernet (rev. %#x)\n", 880 PCI_REVISION(pa->pa_class)); 881 882 /* Make sure bus-mastering is enabled */ 883 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 884 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 885 PCI_COMMAND_MASTER_ENABLE); 886 887 /* 888 * Map control/status registers. 889 */ 890 if (0 != pci_mapreg_map(pa, VGE_PCI_LOMEM, 891 PCI_MAPREG_TYPE_MEM, BUS_SPACE_MAP_LINEAR, 892 &sc->vge_btag, &sc->vge_bhandle, NULL, NULL)) { 893 aprint_error("%s: couldn't map memory\n", 894 sc->sc_dev.dv_xname); 895 return; 896 } 897 898 /* 899 * Map and establish our interrupt. 900 */ 901 if (pci_intr_map(pa, &ih)) { 902 aprint_error("%s: unable to map interrupt\n", 903 sc->sc_dev.dv_xname); 904 return; 905 } 906 intrstr = pci_intr_string(pc, ih); 907 sc->vge_intrhand = pci_intr_establish(pc, ih, IPL_NET, vge_intr, sc); 908 if (sc->vge_intrhand == NULL) { 909 printf("%s: unable to establish interrupt", 910 sc->sc_dev.dv_xname); 911 if (intrstr != NULL) 912 printf(" at %s", intrstr); 913 printf("\n"); 914 return; 915 } 916 aprint_normal("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 917 918 /* Reset the adapter. */ 919 vge_reset(sc); 920 921 /* 922 * Get station address from the EEPROM. 923 */ 924 vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0); 925 bcopy(eaddr, (char *)&sc->vge_eaddr, ETHER_ADDR_LEN); 926 927 printf("%s: Ethernet address: %s\n", sc->sc_dev.dv_xname, 928 ether_sprintf(eaddr)); 929 930 /* 931 * Use the 32bit tag. Hardware supports 48bit physical addresses, 932 * but we don't use that for now. 933 */ 934 sc->vge_dmat = pa->pa_dmat; 935 936 error = vge_allocmem(sc); 937 938 if (error) { 939 printf("allocmem err %d\n", error); 940 return; 941 } 942 943 ifp = &sc->sc_ethercom.ec_if; 944 ifp->if_softc = sc; 945 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 946 ifp->if_mtu = ETHERMTU; 947 ifp->if_baudrate = IF_Gbps(1); 948 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 949 ifp->if_ioctl = vge_ioctl; 950 ifp->if_start = vge_start; 951 952 /* 953 * We can support 802.1Q VLAN-sized frames and jumbo 954 * Ethernet frames. 955 */ 956 sc->sc_ethercom.ec_capabilities |= 957 ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU | 958 ETHERCAP_VLAN_HWTAGGING; 959 960 /* 961 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 962 */ 963 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | 964 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 965 966 #ifdef DEVICE_POLLING 967 #ifdef IFCAP_POLLING 968 ifp->if_capabilities |= IFCAP_POLLING; 969 #endif 970 #endif 971 ifp->if_watchdog = vge_watchdog; 972 ifp->if_init = vge_init; 973 IFQ_SET_MAXLEN(&ifp->if_snd, max(VGE_IFQ_MAXLEN, IFQ_MAXLEN)); 974 975 /* 976 * Initialize our media structures and probe the MII. 977 */ 978 sc->sc_mii.mii_ifp = ifp; 979 sc->sc_mii.mii_readreg = vge_miibus_readreg; 980 sc->sc_mii.mii_writereg = vge_miibus_writereg; 981 sc->sc_mii.mii_statchg = vge_miibus_statchg; 982 ifmedia_init(&sc->sc_mii.mii_media, 0, vge_ifmedia_upd, 983 vge_ifmedia_sts); 984 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 985 MII_OFFSET_ANY, MIIF_DOPAUSE); 986 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 987 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 988 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 989 } else 990 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 991 992 /* 993 * Attach the interface. 994 */ 995 if_attach(ifp); 996 ether_ifattach(ifp, eaddr); 997 998 callout_init(&sc->vge_timeout); 999 callout_setfunc(&sc->vge_timeout, vge_tick, sc); 1000 1001 /* 1002 * Make sure the interface is shutdown during reboot. 1003 */ 1004 if (shutdownhook_establish(vge_shutdown, sc) == NULL) { 1005 printf("%s: WARNING: unable to establish shutdown hook\n", 1006 sc->sc_dev.dv_xname); 1007 } 1008 } 1009 1010 static int 1011 vge_newbuf(sc, idx, m) 1012 struct vge_softc *sc; 1013 int idx; 1014 struct mbuf *m; 1015 { 1016 struct mbuf *n = NULL; 1017 int i, error; 1018 1019 if (m == NULL) { 1020 n = m_gethdr(M_DONTWAIT, MT_DATA); 1021 if (n == NULL) 1022 return (ENOBUFS); 1023 1024 m_clget(n, M_DONTWAIT); 1025 if ((n->m_flags & M_EXT) == 0) { 1026 m_freem(n); 1027 return (ENOBUFS); 1028 } 1029 1030 m = n; 1031 } else 1032 m->m_data = m->m_ext.ext_buf; 1033 1034 1035 #ifdef VGE_FIXUP_RX 1036 /* 1037 * This is part of an evil trick to deal with non-x86 platforms. 1038 * The VIA chip requires RX buffers to be aligned on 32-bit 1039 * boundaries, but that will hose non-x86 machines. To get around 1040 * this, we leave some empty space at the start of each buffer 1041 * and for non-x86 hosts, we copy the buffer back two bytes 1042 * to achieve word alignment. This is slightly more efficient 1043 * than allocating a new buffer, copying the contents, and 1044 * discarding the old buffer. 1045 */ 1046 m->m_len = m->m_pkthdr.len = MCLBYTES - VGE_ETHER_ALIGN; 1047 m_adj(m, VGE_ETHER_ALIGN); 1048 #else 1049 m->m_len = m->m_pkthdr.len = MCLBYTES; 1050 #endif 1051 1052 error = bus_dmamap_load_mbuf(sc->vge_dmat, 1053 sc->vge_ldata.vge_rx_dmamap[idx], m, BUS_DMA_NOWAIT); 1054 if (error || vge_dma_map_rx_desc(sc, idx)) { 1055 if (n != NULL) 1056 m_freem(n); 1057 return (ENOMEM); 1058 } 1059 1060 /* 1061 * Note: the manual fails to document the fact that for 1062 * proper opration, the driver needs to replentish the RX 1063 * DMA ring 4 descriptors at a time (rather than one at a 1064 * time, like most chips). We can allocate the new buffers 1065 * but we should not set the OWN bits until we're ready 1066 * to hand back 4 of them in one shot. 1067 */ 1068 1069 #define VGE_RXCHUNK 4 1070 sc->vge_rx_consumed++; 1071 if (sc->vge_rx_consumed == VGE_RXCHUNK) { 1072 for (i = idx; i != idx - sc->vge_rx_consumed; i--) 1073 sc->vge_ldata.vge_rx_list[i].vge_sts |= 1074 htole32(VGE_RDSTS_OWN); 1075 sc->vge_rx_consumed = 0; 1076 } 1077 1078 sc->vge_ldata.vge_rx_mbuf[idx] = m; 1079 1080 bus_dmamap_sync(sc->vge_dmat, 1081 sc->vge_ldata.vge_rx_dmamap[idx], 1082 0, sc->vge_ldata.vge_rx_dmamap[idx]->dm_mapsize, 1083 BUS_DMASYNC_PREREAD); 1084 1085 return (0); 1086 } 1087 1088 static int 1089 vge_tx_list_init(sc) 1090 struct vge_softc *sc; 1091 { 1092 bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); 1093 bzero ((char *)&sc->vge_ldata.vge_tx_mbuf, 1094 (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); 1095 1096 bus_dmamap_sync(sc->vge_dmat, 1097 sc->vge_ldata.vge_tx_list_map, 1098 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1099 BUS_DMASYNC_PREWRITE); 1100 1101 sc->vge_ldata.vge_tx_prodidx = 0; 1102 sc->vge_ldata.vge_tx_considx = 0; 1103 sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; 1104 1105 return (0); 1106 } 1107 1108 static int 1109 vge_rx_list_init(sc) 1110 struct vge_softc *sc; 1111 { 1112 int i; 1113 1114 bzero ((char *)sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); 1115 bzero ((char *)&sc->vge_ldata.vge_rx_mbuf, 1116 (VGE_RX_DESC_CNT * sizeof(struct mbuf *))); 1117 1118 sc->vge_rx_consumed = 0; 1119 1120 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1121 if (vge_newbuf(sc, i, NULL) == ENOBUFS) 1122 return (ENOBUFS); 1123 } 1124 1125 /* Flush the RX descriptors */ 1126 1127 bus_dmamap_sync(sc->vge_dmat, 1128 sc->vge_ldata.vge_rx_list_map, 1129 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 1130 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1131 1132 sc->vge_ldata.vge_rx_prodidx = 0; 1133 sc->vge_rx_consumed = 0; 1134 sc->vge_head = sc->vge_tail = NULL; 1135 1136 return (0); 1137 } 1138 1139 #ifdef VGE_FIXUP_RX 1140 static __inline void 1141 vge_fixup_rx(m) 1142 struct mbuf *m; 1143 { 1144 int i; 1145 uint16_t *src, *dst; 1146 1147 src = mtod(m, uint16_t *); 1148 dst = src - 1; 1149 1150 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1151 *dst++ = *src++; 1152 1153 m->m_data -= ETHER_ALIGN; 1154 1155 return; 1156 } 1157 #endif 1158 1159 /* 1160 * RX handler. We support the reception of jumbo frames that have 1161 * been fragmented across multiple 2K mbuf cluster buffers. 1162 */ 1163 static void 1164 vge_rxeof(sc) 1165 struct vge_softc *sc; 1166 { 1167 struct mbuf *m; 1168 struct ifnet *ifp; 1169 int i, total_len; 1170 int lim = 0; 1171 struct vge_rx_desc *cur_rx; 1172 u_int32_t rxstat, rxctl; 1173 1174 VGE_LOCK_ASSERT(sc); 1175 ifp = &sc->sc_ethercom.ec_if; 1176 i = sc->vge_ldata.vge_rx_prodidx; 1177 1178 /* Invalidate the descriptor memory */ 1179 1180 bus_dmamap_sync(sc->vge_dmat, 1181 sc->vge_ldata.vge_rx_list_map, 1182 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 1183 BUS_DMASYNC_POSTREAD); 1184 1185 while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { 1186 1187 #ifdef DEVICE_POLLING 1188 if (ifp->if_flags & IFF_POLLING) { 1189 if (sc->rxcycles <= 0) 1190 break; 1191 sc->rxcycles--; 1192 } 1193 #endif /* DEVICE_POLLING */ 1194 1195 cur_rx = &sc->vge_ldata.vge_rx_list[i]; 1196 m = sc->vge_ldata.vge_rx_mbuf[i]; 1197 total_len = VGE_RXBYTES(cur_rx); 1198 rxstat = le32toh(cur_rx->vge_sts); 1199 rxctl = le32toh(cur_rx->vge_ctl); 1200 1201 /* Invalidate the RX mbuf and unload its map */ 1202 1203 bus_dmamap_sync(sc->vge_dmat, 1204 sc->vge_ldata.vge_rx_dmamap[i], 1205 0, sc->vge_ldata.vge_rx_dmamap[i]->dm_mapsize, 1206 BUS_DMASYNC_POSTWRITE); 1207 bus_dmamap_unload(sc->vge_dmat, 1208 sc->vge_ldata.vge_rx_dmamap[i]); 1209 1210 /* 1211 * If the 'start of frame' bit is set, this indicates 1212 * either the first fragment in a multi-fragment receive, 1213 * or an intermediate fragment. Either way, we want to 1214 * accumulate the buffers. 1215 */ 1216 if (rxstat & VGE_RXPKT_SOF) { 1217 m->m_len = MCLBYTES - VGE_ETHER_ALIGN; 1218 if (sc->vge_head == NULL) 1219 sc->vge_head = sc->vge_tail = m; 1220 else { 1221 m->m_flags &= ~M_PKTHDR; 1222 sc->vge_tail->m_next = m; 1223 sc->vge_tail = m; 1224 } 1225 vge_newbuf(sc, i, NULL); 1226 VGE_RX_DESC_INC(i); 1227 continue; 1228 } 1229 1230 /* 1231 * Bad/error frames will have the RXOK bit cleared. 1232 * However, there's one error case we want to allow: 1233 * if a VLAN tagged frame arrives and the chip can't 1234 * match it against the CAM filter, it considers this 1235 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1236 * We don't want to drop the frame though: our VLAN 1237 * filtering is done in software. 1238 */ 1239 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1240 && !(rxstat & VGE_RDSTS_CSUMERR)) { 1241 ifp->if_ierrors++; 1242 /* 1243 * If this is part of a multi-fragment packet, 1244 * discard all the pieces. 1245 */ 1246 if (sc->vge_head != NULL) { 1247 m_freem(sc->vge_head); 1248 sc->vge_head = sc->vge_tail = NULL; 1249 } 1250 vge_newbuf(sc, i, m); 1251 VGE_RX_DESC_INC(i); 1252 continue; 1253 } 1254 1255 /* 1256 * If allocating a replacement mbuf fails, 1257 * reload the current one. 1258 */ 1259 1260 if (vge_newbuf(sc, i, NULL)) { 1261 ifp->if_ierrors++; 1262 if (sc->vge_head != NULL) { 1263 m_freem(sc->vge_head); 1264 sc->vge_head = sc->vge_tail = NULL; 1265 } 1266 vge_newbuf(sc, i, m); 1267 VGE_RX_DESC_INC(i); 1268 continue; 1269 } 1270 1271 VGE_RX_DESC_INC(i); 1272 1273 if (sc->vge_head != NULL) { 1274 m->m_len = total_len % (MCLBYTES - VGE_ETHER_ALIGN); 1275 /* 1276 * Special case: if there's 4 bytes or less 1277 * in this buffer, the mbuf can be discarded: 1278 * the last 4 bytes is the CRC, which we don't 1279 * care about anyway. 1280 */ 1281 if (m->m_len <= ETHER_CRC_LEN) { 1282 sc->vge_tail->m_len -= 1283 (ETHER_CRC_LEN - m->m_len); 1284 m_freem(m); 1285 } else { 1286 m->m_len -= ETHER_CRC_LEN; 1287 m->m_flags &= ~M_PKTHDR; 1288 sc->vge_tail->m_next = m; 1289 } 1290 m = sc->vge_head; 1291 sc->vge_head = sc->vge_tail = NULL; 1292 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1293 } else 1294 m->m_pkthdr.len = m->m_len = 1295 (total_len - ETHER_CRC_LEN); 1296 1297 #ifdef VGE_FIXUP_RX 1298 vge_fixup_rx(m); 1299 #endif 1300 ifp->if_ipackets++; 1301 m->m_pkthdr.rcvif = ifp; 1302 1303 /* Do RX checksumming if enabled */ 1304 if (ifp->if_csum_flags_rx & M_CSUM_IPv4) { 1305 1306 /* Check IP header checksum */ 1307 if (rxctl & VGE_RDCTL_IPPKT) 1308 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1309 if ((rxctl & VGE_RDCTL_IPCSUMOK) == 0) 1310 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1311 } 1312 1313 if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) { 1314 /* Check UDP checksum */ 1315 if (rxctl & VGE_RDCTL_TCPPKT) 1316 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1317 1318 if ((rxctl & VGE_RDCTL_PROTOCSUMOK) == 0) 1319 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1320 } 1321 1322 if (ifp->if_csum_flags_rx & M_CSUM_UDPv4) { 1323 /* Check UDP checksum */ 1324 if (rxctl & VGE_RDCTL_UDPPKT) 1325 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1326 1327 if ((rxctl & VGE_RDCTL_PROTOCSUMOK) == 0) 1328 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1329 } 1330 1331 if (rxstat & VGE_RDSTS_VTAG) 1332 VLAN_INPUT_TAG(ifp, m, 1333 ntohs((rxctl & VGE_RDCTL_VLANID)), continue); 1334 1335 #if NBPFILTER > 0 1336 /* 1337 * Handle BPF listeners. 1338 */ 1339 if (ifp->if_bpf) 1340 bpf_mtap(ifp->if_bpf, m); 1341 #endif 1342 1343 VGE_UNLOCK(sc); 1344 (*ifp->if_input)(ifp, m); 1345 VGE_LOCK(sc); 1346 1347 lim++; 1348 if (lim == VGE_RX_DESC_CNT) 1349 break; 1350 1351 } 1352 1353 /* Flush the RX DMA ring */ 1354 1355 bus_dmamap_sync(sc->vge_dmat, 1356 sc->vge_ldata.vge_rx_list_map, 1357 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 1358 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1359 1360 sc->vge_ldata.vge_rx_prodidx = i; 1361 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1362 1363 1364 return; 1365 } 1366 1367 static void 1368 vge_txeof(sc) 1369 struct vge_softc *sc; 1370 { 1371 struct ifnet *ifp; 1372 u_int32_t txstat; 1373 int idx; 1374 1375 ifp = &sc->sc_ethercom.ec_if; 1376 idx = sc->vge_ldata.vge_tx_considx; 1377 1378 /* Invalidate the TX descriptor list */ 1379 1380 bus_dmamap_sync(sc->vge_dmat, 1381 sc->vge_ldata.vge_tx_list_map, 1382 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1383 BUS_DMASYNC_POSTREAD); 1384 1385 while (idx != sc->vge_ldata.vge_tx_prodidx) { 1386 1387 txstat = le32toh(sc->vge_ldata.vge_tx_list[idx].vge_sts); 1388 if (txstat & VGE_TDSTS_OWN) 1389 break; 1390 1391 m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); 1392 sc->vge_ldata.vge_tx_mbuf[idx] = NULL; 1393 bus_dmamap_unload(sc->vge_dmat, 1394 sc->vge_ldata.vge_tx_dmamap[idx]); 1395 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1396 ifp->if_collisions++; 1397 if (txstat & VGE_TDSTS_TXERR) 1398 ifp->if_oerrors++; 1399 else 1400 ifp->if_opackets++; 1401 1402 sc->vge_ldata.vge_tx_free++; 1403 VGE_TX_DESC_INC(idx); 1404 } 1405 1406 /* No changes made to the TX ring, so no flush needed */ 1407 1408 if (idx != sc->vge_ldata.vge_tx_considx) { 1409 sc->vge_ldata.vge_tx_considx = idx; 1410 ifp->if_flags &= ~IFF_OACTIVE; 1411 ifp->if_timer = 0; 1412 } 1413 1414 /* 1415 * If not all descriptors have been released reaped yet, 1416 * reload the timer so that we will eventually get another 1417 * interrupt that will cause us to re-enter this routine. 1418 * This is done in case the transmitter has gone idle. 1419 */ 1420 if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) { 1421 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1422 } 1423 1424 return; 1425 } 1426 1427 static void 1428 vge_tick(xsc) 1429 void *xsc; 1430 { 1431 struct vge_softc *sc = xsc; 1432 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1433 struct mii_data *mii = &sc->sc_mii; 1434 int s; 1435 1436 s = splnet(); 1437 1438 VGE_LOCK(sc); 1439 1440 callout_schedule(&sc->vge_timeout, hz); 1441 1442 mii_tick(mii); 1443 if (sc->vge_link) { 1444 if (!(mii->mii_media_status & IFM_ACTIVE)) 1445 sc->vge_link = 0; 1446 } else { 1447 if (mii->mii_media_status & IFM_ACTIVE && 1448 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1449 sc->vge_link = 1; 1450 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1451 vge_start(ifp); 1452 } 1453 } 1454 1455 VGE_UNLOCK(sc); 1456 1457 splx(s); 1458 } 1459 1460 #ifdef DEVICE_POLLING 1461 static void 1462 vge_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1463 { 1464 struct vge_softc *sc = ifp->if_softc; 1465 1466 VGE_LOCK(sc); 1467 #ifdef IFCAP_POLLING 1468 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1469 ether_poll_deregister(ifp); 1470 cmd = POLL_DEREGISTER; 1471 } 1472 #endif 1473 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1474 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1475 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 1476 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1477 goto done; 1478 } 1479 1480 sc->rxcycles = count; 1481 vge_rxeof(sc); 1482 vge_txeof(sc); 1483 1484 #if __FreeBSD_version < 502114 1485 if (ifp->if_snd.ifq_head != NULL) 1486 #else 1487 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1488 #endif 1489 taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); 1490 1491 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1492 u_int32_t status; 1493 status = CSR_READ_4(sc, VGE_ISR); 1494 if (status == 0xFFFFFFFF) 1495 goto done; 1496 if (status) 1497 CSR_WRITE_4(sc, VGE_ISR, status); 1498 1499 /* 1500 * XXX check behaviour on receiver stalls. 1501 */ 1502 1503 if (status & VGE_ISR_TXDMA_STALL || 1504 status & VGE_ISR_RXDMA_STALL) 1505 vge_init(sc); 1506 1507 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1508 vge_rxeof(sc); 1509 ifp->if_ierrors++; 1510 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1511 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1512 } 1513 } 1514 done: 1515 VGE_UNLOCK(sc); 1516 } 1517 #endif /* DEVICE_POLLING */ 1518 1519 static int 1520 vge_intr(arg) 1521 void *arg; 1522 { 1523 struct vge_softc *sc = arg; 1524 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1525 u_int32_t status; 1526 int claim = 0; 1527 1528 if (sc->suspended) { 1529 return claim; 1530 } 1531 1532 VGE_LOCK(sc); 1533 1534 if (!(ifp->if_flags & IFF_UP)) { 1535 VGE_UNLOCK(sc); 1536 return claim; 1537 } 1538 1539 #ifdef DEVICE_POLLING 1540 if (ifp->if_flags & IFF_POLLING) 1541 goto done; 1542 if ( 1543 #ifdef IFCAP_POLLING 1544 (ifp->if_capenable & IFCAP_POLLING) && 1545 #endif 1546 ether_poll_register(vge_poll, ifp)) { /* ok, disable interrupts */ 1547 CSR_WRITE_4(sc, VGE_IMR, 0); 1548 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1549 vge_poll(ifp, 0, 1); 1550 goto done; 1551 } 1552 1553 #endif /* DEVICE_POLLING */ 1554 1555 /* Disable interrupts */ 1556 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1557 1558 for (;;) { 1559 1560 status = CSR_READ_4(sc, VGE_ISR); 1561 /* If the card has gone away the read returns 0xffff. */ 1562 if (status == 0xFFFFFFFF) 1563 break; 1564 1565 if (status) { 1566 claim = 1; 1567 CSR_WRITE_4(sc, VGE_ISR, status); 1568 } 1569 1570 if ((status & VGE_INTRS) == 0) 1571 break; 1572 1573 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1574 vge_rxeof(sc); 1575 1576 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1577 vge_rxeof(sc); 1578 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1579 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1580 } 1581 1582 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1583 vge_txeof(sc); 1584 1585 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) 1586 vge_init(ifp); 1587 1588 if (status & VGE_ISR_LINKSTS) 1589 vge_tick(sc); 1590 } 1591 1592 /* Re-enable interrupts */ 1593 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1594 1595 #ifdef DEVICE_POLLING 1596 done: 1597 #endif 1598 VGE_UNLOCK(sc); 1599 1600 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1601 vge_start(ifp); 1602 1603 return claim; 1604 } 1605 1606 static int 1607 vge_encap(sc, m_head, idx) 1608 struct vge_softc *sc; 1609 struct mbuf *m_head; 1610 int idx; 1611 { 1612 struct mbuf *m_new = NULL; 1613 bus_dmamap_t map; 1614 int error, flags; 1615 struct m_tag *mtag; 1616 1617 if (sc->vge_ldata.vge_tx_free <= 2) 1618 return (EFBIG); 1619 1620 flags = 0; 1621 1622 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 1623 flags |= VGE_TDCTL_IPCSUM; 1624 if (m_head->m_pkthdr.csum_flags & M_CSUM_TCPv4) 1625 flags |= VGE_TDCTL_TCPCSUM; 1626 if (m_head->m_pkthdr.csum_flags & M_CSUM_UDPv4) 1627 flags |= VGE_TDCTL_UDPCSUM; 1628 1629 map = sc->vge_ldata.vge_tx_dmamap[idx]; 1630 error = bus_dmamap_load_mbuf(sc->vge_dmat, map, 1631 m_head, BUS_DMA_NOWAIT); 1632 1633 if ((error && error != EFBIG) 1634 || vge_dma_map_tx_desc(sc, m_head, idx, flags)) { 1635 if (error) { 1636 printf("%s: can't map mbuf (error %d)\n", 1637 sc->sc_dev.dv_xname, error); 1638 } 1639 return (ENOBUFS); 1640 } 1641 1642 /* Too many segments to map, coalesce into a single mbuf */ 1643 1644 if (error) { 1645 m_new = m_defrag(m_head, M_DONTWAIT); 1646 if (m_new == NULL) 1647 return (1); 1648 else 1649 m_head = m_new; 1650 1651 error = bus_dmamap_load_mbuf(sc->vge_dmat, map, 1652 m_head, BUS_DMA_NOWAIT); 1653 if (error || vge_dma_map_tx_desc(sc, m_head, idx, flags)) { 1654 if (error) { 1655 printf("%s: can't map defrag mbuf (error %d)\n", 1656 sc->sc_dev.dv_xname, error); 1657 } 1658 m_freem(m_head); 1659 return (EFBIG); 1660 } 1661 } 1662 1663 sc->vge_ldata.vge_tx_mbuf[idx] = m_head; 1664 sc->vge_ldata.vge_tx_free--; 1665 1666 /* 1667 * Set up hardware VLAN tagging. 1668 */ 1669 1670 mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m_head); 1671 if (mtag != NULL) 1672 sc->vge_ldata.vge_tx_list[idx].vge_ctl |= 1673 htole32(htons(VLAN_TAG_VALUE(mtag)) | VGE_TDCTL_VTAG); 1674 1675 sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); 1676 1677 return (0); 1678 } 1679 1680 /* 1681 * Main transmit routine. 1682 */ 1683 1684 static void 1685 vge_start(ifp) 1686 struct ifnet *ifp; 1687 { 1688 struct vge_softc *sc; 1689 struct mbuf *m_head = NULL; 1690 int idx, pidx = 0; 1691 1692 sc = ifp->if_softc; 1693 VGE_LOCK(sc); 1694 1695 if (!sc->vge_link || ifp->if_flags & IFF_OACTIVE) { 1696 VGE_UNLOCK(sc); 1697 return; 1698 } 1699 1700 #if __FreeBSD_version < 502114 1701 if (ifp->if_snd.ifq_head == NULL) { 1702 #else 1703 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 1704 #endif 1705 VGE_UNLOCK(sc); 1706 return; 1707 } 1708 1709 idx = sc->vge_ldata.vge_tx_prodidx; 1710 1711 pidx = idx - 1; 1712 if (pidx < 0) 1713 pidx = VGE_TX_DESC_CNT - 1; 1714 1715 1716 while (sc->vge_ldata.vge_tx_mbuf[idx] == NULL) { 1717 #if __FreeBSD_version < 502114 1718 IF_DEQUEUE(&ifp->if_snd, m_head); 1719 #else 1720 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1721 #endif 1722 if (m_head == NULL) 1723 break; 1724 1725 if (vge_encap(sc, m_head, idx)) { 1726 #if __FreeBSD_version >= 502114 1727 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1728 #else 1729 IF_PREPEND(&ifp->if_snd, m_head); 1730 #endif 1731 ifp->if_flags |= IFF_OACTIVE; 1732 break; 1733 } 1734 1735 sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= 1736 htole16(VGE_TXDESC_Q); 1737 1738 pidx = idx; 1739 VGE_TX_DESC_INC(idx); 1740 1741 /* 1742 * If there's a BPF listener, bounce a copy of this frame 1743 * to him. 1744 */ 1745 #if NBPFILTER > 0 1746 if (ifp->if_bpf) 1747 bpf_mtap(ifp->if_bpf, m_head); 1748 #endif 1749 } 1750 1751 if (idx == sc->vge_ldata.vge_tx_prodidx) { 1752 VGE_UNLOCK(sc); 1753 return; 1754 } 1755 1756 /* Flush the TX descriptors */ 1757 1758 bus_dmamap_sync(sc->vge_dmat, 1759 sc->vge_ldata.vge_tx_list_map, 1760 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1761 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1762 1763 /* Issue a transmit command. */ 1764 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1765 1766 sc->vge_ldata.vge_tx_prodidx = idx; 1767 1768 /* 1769 * Use the countdown timer for interrupt moderation. 1770 * 'TX done' interrupts are disabled. Instead, we reset the 1771 * countdown timer, which will begin counting until it hits 1772 * the value in the SSTIMER register, and then trigger an 1773 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1774 * the timer count is reloaded. Only when the transmitter 1775 * is idle will the timer hit 0 and an interrupt fire. 1776 */ 1777 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1778 1779 VGE_UNLOCK(sc); 1780 1781 /* 1782 * Set a timeout in case the chip goes out to lunch. 1783 */ 1784 ifp->if_timer = 5; 1785 1786 return; 1787 } 1788 1789 static int 1790 vge_init(ifp) 1791 struct ifnet *ifp; 1792 { 1793 struct vge_softc *sc = ifp->if_softc; 1794 struct mii_data *mii = &sc->sc_mii; 1795 int i; 1796 1797 VGE_LOCK(sc); 1798 1799 /* 1800 * Cancel pending I/O and free all RX/TX buffers. 1801 */ 1802 vge_stop(sc); 1803 vge_reset(sc); 1804 1805 /* 1806 * Initialize the RX and TX descriptors and mbufs. 1807 */ 1808 1809 vge_rx_list_init(sc); 1810 vge_tx_list_init(sc); 1811 1812 /* Set our station address */ 1813 for (i = 0; i < ETHER_ADDR_LEN; i++) 1814 CSR_WRITE_1(sc, VGE_PAR0 + i, sc->vge_eaddr[i]); 1815 1816 /* 1817 * Set receive FIFO threshold. Also allow transmission and 1818 * reception of VLAN tagged frames. 1819 */ 1820 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 1821 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 1822 1823 /* Set DMA burst length */ 1824 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1825 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1826 1827 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1828 1829 /* Set collision backoff algorithm */ 1830 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1831 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1832 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1833 1834 /* Disable LPSEL field in priority resolution */ 1835 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1836 1837 /* 1838 * Load the addresses of the DMA queues into the chip. 1839 * Note that we only use one transmit queue. 1840 */ 1841 1842 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 1843 VGE_ADDR_LO(sc->vge_ldata.vge_tx_list_addr)); 1844 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 1845 1846 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 1847 VGE_ADDR_LO(sc->vge_ldata.vge_rx_list_addr)); 1848 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 1849 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 1850 1851 /* Enable and wake up the RX descriptor queue */ 1852 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1853 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1854 1855 /* Enable the TX descriptor queue */ 1856 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 1857 1858 /* Set up the receive filter -- allow large frames for VLANs. */ 1859 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 1860 1861 /* If we want promiscuous mode, set the allframes bit. */ 1862 if (ifp->if_flags & IFF_PROMISC) { 1863 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 1864 } 1865 1866 /* Set capture broadcast bit to capture broadcast frames. */ 1867 if (ifp->if_flags & IFF_BROADCAST) { 1868 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 1869 } 1870 1871 /* Set multicast bit to capture multicast frames. */ 1872 if (ifp->if_flags & IFF_MULTICAST) { 1873 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 1874 } 1875 1876 /* Init the cam filter. */ 1877 vge_cam_clear(sc); 1878 1879 /* Init the multicast filter. */ 1880 vge_setmulti(sc); 1881 1882 /* Enable flow control */ 1883 1884 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 1885 1886 /* Enable jumbo frame reception (if desired) */ 1887 1888 /* Start the MAC. */ 1889 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 1890 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 1891 CSR_WRITE_1(sc, VGE_CRS0, 1892 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 1893 1894 /* 1895 * Configure one-shot timer for microsecond 1896 * resulution and load it for 500 usecs. 1897 */ 1898 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 1899 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 1900 1901 /* 1902 * Configure interrupt moderation for receive. Enable 1903 * the holdoff counter and load it, and set the RX 1904 * suppression count to the number of descriptors we 1905 * want to allow before triggering an interrupt. 1906 * The holdoff timer is in units of 20 usecs. 1907 */ 1908 1909 #ifdef notyet 1910 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 1911 /* Select the interrupt holdoff timer page. */ 1912 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1913 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 1914 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 1915 1916 /* Enable use of the holdoff timer. */ 1917 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 1918 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 1919 1920 /* Select the RX suppression threshold page. */ 1921 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1922 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 1923 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 1924 1925 /* Restore the page select bits. */ 1926 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1927 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 1928 #endif 1929 1930 #ifdef DEVICE_POLLING 1931 /* 1932 * Disable interrupts if we are polling. 1933 */ 1934 if (ifp->if_flags & IFF_POLLING) { 1935 CSR_WRITE_4(sc, VGE_IMR, 0); 1936 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1937 } else /* otherwise ... */ 1938 #endif /* DEVICE_POLLING */ 1939 { 1940 /* 1941 * Enable interrupts. 1942 */ 1943 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1944 CSR_WRITE_4(sc, VGE_ISR, 0); 1945 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1946 } 1947 1948 mii_mediachg(mii); 1949 1950 ifp->if_flags |= IFF_RUNNING; 1951 ifp->if_flags &= ~IFF_OACTIVE; 1952 1953 sc->vge_if_flags = 0; 1954 sc->vge_link = 0; 1955 1956 VGE_UNLOCK(sc); 1957 1958 callout_schedule(&sc->vge_timeout, hz); 1959 1960 return (0); 1961 } 1962 1963 /* 1964 * Set media options. 1965 */ 1966 static int 1967 vge_ifmedia_upd(ifp) 1968 struct ifnet *ifp; 1969 { 1970 struct vge_softc *sc = ifp->if_softc; 1971 struct mii_data *mii = &sc->sc_mii; 1972 1973 mii_mediachg(mii); 1974 1975 return (0); 1976 } 1977 1978 /* 1979 * Report current media status. 1980 */ 1981 static void 1982 vge_ifmedia_sts(ifp, ifmr) 1983 struct ifnet *ifp; 1984 struct ifmediareq *ifmr; 1985 { 1986 struct vge_softc *sc = ifp->if_softc; 1987 struct mii_data *mii = &sc->sc_mii; 1988 1989 mii_pollstat(mii); 1990 ifmr->ifm_active = mii->mii_media_active; 1991 ifmr->ifm_status = mii->mii_media_status; 1992 1993 return; 1994 } 1995 1996 static void 1997 vge_miibus_statchg(self) 1998 struct device *self; 1999 { 2000 struct vge_softc *sc = (struct vge_softc *) self; 2001 struct mii_data *mii = &sc->sc_mii; 2002 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 2003 2004 /* 2005 * If the user manually selects a media mode, we need to turn 2006 * on the forced MAC mode bit in the DIAGCTL register. If the 2007 * user happens to choose a full duplex mode, we also need to 2008 * set the 'force full duplex' bit. This applies only to 2009 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 2010 * mode is disabled, and in 1000baseT mode, full duplex is 2011 * always implied, so we turn on the forced mode bit but leave 2012 * the FDX bit cleared. 2013 */ 2014 2015 switch (IFM_SUBTYPE(ife->ifm_media)) { 2016 case IFM_AUTO: 2017 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2018 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2019 break; 2020 case IFM_1000_T: 2021 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2022 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2023 break; 2024 case IFM_100_TX: 2025 case IFM_10_T: 2026 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2027 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 2028 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2029 } else { 2030 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2031 } 2032 break; 2033 default: 2034 printf("%s: unknown media type: %x\n", 2035 sc->sc_dev.dv_xname, 2036 IFM_SUBTYPE(ife->ifm_media)); 2037 break; 2038 } 2039 2040 return; 2041 } 2042 2043 static int 2044 vge_ioctl(ifp, command, data) 2045 struct ifnet *ifp; 2046 u_long command; 2047 caddr_t data; 2048 { 2049 struct vge_softc *sc = ifp->if_softc; 2050 struct ifreq *ifr = (struct ifreq *) data; 2051 struct mii_data *mii; 2052 int error = 0; 2053 2054 switch (command) { 2055 case SIOCSIFMTU: 2056 if (ifr->ifr_mtu > VGE_JUMBO_MTU) 2057 error = EINVAL; 2058 ifp->if_mtu = ifr->ifr_mtu; 2059 break; 2060 case SIOCSIFFLAGS: 2061 if (ifp->if_flags & IFF_UP) { 2062 if (ifp->if_flags & IFF_RUNNING && 2063 ifp->if_flags & IFF_PROMISC && 2064 !(sc->vge_if_flags & IFF_PROMISC)) { 2065 CSR_SETBIT_1(sc, VGE_RXCTL, 2066 VGE_RXCTL_RX_PROMISC); 2067 vge_setmulti(sc); 2068 } else if (ifp->if_flags & IFF_RUNNING && 2069 !(ifp->if_flags & IFF_PROMISC) && 2070 sc->vge_if_flags & IFF_PROMISC) { 2071 CSR_CLRBIT_1(sc, VGE_RXCTL, 2072 VGE_RXCTL_RX_PROMISC); 2073 vge_setmulti(sc); 2074 } else 2075 vge_init(ifp); 2076 } else { 2077 if (ifp->if_flags & IFF_RUNNING) 2078 vge_stop(sc); 2079 } 2080 sc->vge_if_flags = ifp->if_flags; 2081 break; 2082 case SIOCADDMULTI: 2083 case SIOCDELMULTI: 2084 vge_setmulti(sc); 2085 break; 2086 case SIOCGIFMEDIA: 2087 case SIOCSIFMEDIA: 2088 mii = &sc->sc_mii; 2089 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2090 break; 2091 default: 2092 error = ether_ioctl(ifp, command, data); 2093 break; 2094 } 2095 2096 return (error); 2097 } 2098 2099 static void 2100 vge_watchdog(ifp) 2101 struct ifnet *ifp; 2102 { 2103 struct vge_softc *sc; 2104 2105 sc = ifp->if_softc; 2106 VGE_LOCK(sc); 2107 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 2108 ifp->if_oerrors++; 2109 2110 vge_txeof(sc); 2111 vge_rxeof(sc); 2112 2113 vge_init(ifp); 2114 2115 VGE_UNLOCK(sc); 2116 2117 return; 2118 } 2119 2120 /* 2121 * Stop the adapter and free any mbufs allocated to the 2122 * RX and TX lists. 2123 */ 2124 static void 2125 vge_stop(sc) 2126 struct vge_softc *sc; 2127 { 2128 register int i; 2129 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2130 2131 VGE_LOCK(sc); 2132 ifp->if_timer = 0; 2133 2134 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2135 #ifdef DEVICE_POLLING 2136 ether_poll_deregister(ifp); 2137 #endif /* DEVICE_POLLING */ 2138 2139 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2140 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2141 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2142 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2143 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2144 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2145 2146 if (sc->vge_head != NULL) { 2147 m_freem(sc->vge_head); 2148 sc->vge_head = sc->vge_tail = NULL; 2149 } 2150 2151 /* Free the TX list buffers. */ 2152 2153 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 2154 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { 2155 bus_dmamap_unload(sc->vge_dmat, 2156 sc->vge_ldata.vge_tx_dmamap[i]); 2157 m_freem(sc->vge_ldata.vge_tx_mbuf[i]); 2158 sc->vge_ldata.vge_tx_mbuf[i] = NULL; 2159 } 2160 } 2161 2162 /* Free the RX list buffers. */ 2163 2164 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 2165 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { 2166 bus_dmamap_unload(sc->vge_dmat, 2167 sc->vge_ldata.vge_rx_dmamap[i]); 2168 m_freem(sc->vge_ldata.vge_rx_mbuf[i]); 2169 sc->vge_ldata.vge_rx_mbuf[i] = NULL; 2170 } 2171 } 2172 2173 VGE_UNLOCK(sc); 2174 2175 return; 2176 } 2177 2178 #if VGE_POWER_MANAGEMENT 2179 /* 2180 * Device suspend routine. Stop the interface and save some PCI 2181 * settings in case the BIOS doesn't restore them properly on 2182 * resume. 2183 */ 2184 static int 2185 vge_suspend(dev) 2186 struct device * dev; 2187 { 2188 struct vge_softc *sc; 2189 int i; 2190 2191 sc = device_get_softc(dev); 2192 2193 vge_stop(sc); 2194 2195 for (i = 0; i < 5; i++) 2196 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2197 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2198 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2199 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2200 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2201 2202 sc->suspended = 1; 2203 2204 return (0); 2205 } 2206 2207 /* 2208 * Device resume routine. Restore some PCI settings in case the BIOS 2209 * doesn't, re-enable busmastering, and restart the interface if 2210 * appropriate. 2211 */ 2212 static int 2213 vge_resume(dev) 2214 struct device * dev; 2215 { 2216 struct vge_softc *sc = (struct vge_softc *)dev; 2217 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2218 int i; 2219 2220 /* better way to do this? */ 2221 for (i = 0; i < 5; i++) 2222 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 2223 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 2224 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 2225 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 2226 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 2227 2228 /* reenable busmastering */ 2229 pci_enable_busmaster(dev); 2230 pci_enable_io(dev, SYS_RES_MEMORY); 2231 2232 /* reinitialize interface if necessary */ 2233 if (ifp->if_flags & IFF_UP) 2234 vge_init(sc); 2235 2236 sc->suspended = 0; 2237 2238 return (0); 2239 } 2240 #endif 2241 2242 /* 2243 * Stop all chip I/O so that the kernel's probe routines don't 2244 * get confused by errant DMAs when rebooting. 2245 */ 2246 static void 2247 vge_shutdown(arg) 2248 void *arg; 2249 { 2250 struct vge_softc *sc = (struct vge_softc *)arg; 2251 2252 vge_stop(sc); 2253 } 2254