1 /* $NetBSD: if_vge.c,v 1.43 2008/11/26 21:34:07 joerg Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD: src/sys/dev/vge/if_vge.c,v 1.5 2005/02/07 19:39:29 glebius Exp 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_vge.c,v 1.43 2008/11/26 21:34:07 joerg Exp $"); 39 40 /* 41 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 42 * 43 * Written by Bill Paul <wpaul@windriver.com> 44 * Senior Networking Software Engineer 45 * Wind River Systems 46 */ 47 48 /* 49 * The VIA Networking VT6122 is a 32bit, 33/66 MHz PCI device that 50 * combines a tri-speed ethernet MAC and PHY, with the following 51 * features: 52 * 53 * o Jumbo frame support up to 16K 54 * o Transmit and receive flow control 55 * o IPv4 checksum offload 56 * o VLAN tag insertion and stripping 57 * o TCP large send 58 * o 64-bit multicast hash table filter 59 * o 64 entry CAM filter 60 * o 16K RX FIFO and 48K TX FIFO memory 61 * o Interrupt moderation 62 * 63 * The VT6122 supports up to four transmit DMA queues. The descriptors 64 * in the transmit ring can address up to 7 data fragments; frames which 65 * span more than 7 data buffers must be coalesced, but in general the 66 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 67 * long. The receive descriptors address only a single buffer. 68 * 69 * There are two peculiar design issues with the VT6122. One is that 70 * receive data buffers must be aligned on a 32-bit boundary. This is 71 * not a problem where the VT6122 is used as a LOM device in x86-based 72 * systems, but on architectures that generate unaligned access traps, we 73 * have to do some copying. 74 * 75 * The other issue has to do with the way 64-bit addresses are handled. 76 * The DMA descriptors only allow you to specify 48 bits of addressing 77 * information. The remaining 16 bits are specified using one of the 78 * I/O registers. If you only have a 32-bit system, then this isn't 79 * an issue, but if you have a 64-bit system and more than 4GB of 80 * memory, you must have to make sure your network data buffers reside 81 * in the same 48-bit 'segment.' 82 * 83 * Special thanks to Ryan Fu at VIA Networking for providing documentation 84 * and sample NICs for testing. 85 */ 86 87 #include "bpfilter.h" 88 89 #include <sys/param.h> 90 #include <sys/endian.h> 91 #include <sys/systm.h> 92 #include <sys/device.h> 93 #include <sys/sockio.h> 94 #include <sys/mbuf.h> 95 #include <sys/malloc.h> 96 #include <sys/kernel.h> 97 #include <sys/socket.h> 98 99 #include <net/if.h> 100 #include <net/if_arp.h> 101 #include <net/if_ether.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 105 #include <net/bpf.h> 106 107 #include <sys/bus.h> 108 109 #include <dev/mii/mii.h> 110 #include <dev/mii/miivar.h> 111 112 #include <dev/pci/pcireg.h> 113 #include <dev/pci/pcivar.h> 114 #include <dev/pci/pcidevs.h> 115 116 #include <dev/pci/if_vgereg.h> 117 118 #define VGE_IFQ_MAXLEN 64 119 120 #define VGE_RING_ALIGN 256 121 122 #define VGE_NTXDESC 256 123 #define VGE_NTXDESC_MASK (VGE_NTXDESC - 1) 124 #define VGE_NEXT_TXDESC(x) ((x + 1) & VGE_NTXDESC_MASK) 125 #define VGE_PREV_TXDESC(x) ((x - 1) & VGE_NTXDESC_MASK) 126 127 #define VGE_NRXDESC 256 /* Must be a multiple of 4!! */ 128 #define VGE_NRXDESC_MASK (VGE_NRXDESC - 1) 129 #define VGE_NEXT_RXDESC(x) ((x + 1) & VGE_NRXDESC_MASK) 130 #define VGE_PREV_RXDESC(x) ((x - 1) & VGE_NRXDESC_MASK) 131 132 #define VGE_ADDR_LO(y) ((uint64_t)(y) & 0xFFFFFFFF) 133 #define VGE_ADDR_HI(y) ((uint64_t)(y) >> 32) 134 #define VGE_BUFLEN(y) ((y) & 0x7FFF) 135 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 136 137 #define VGE_POWER_MANAGEMENT 0 /* disabled for now */ 138 139 /* 140 * Mbuf adjust factor to force 32-bit alignment of IP header. 141 * Drivers should pad ETHER_ALIGN bytes when setting up a 142 * RX mbuf so the upper layers get the IP header properly aligned 143 * past the 14-byte Ethernet header. 144 * 145 * See also comment in vge_encap(). 146 */ 147 #define ETHER_ALIGN 2 148 149 #ifdef __NO_STRICT_ALIGNMENT 150 #define VGE_RX_BUFSIZE MCLBYTES 151 #else 152 #define VGE_RX_PAD sizeof(uint32_t) 153 #define VGE_RX_BUFSIZE (MCLBYTES - VGE_RX_PAD) 154 #endif 155 156 /* 157 * Control structures are DMA'd to the vge chip. We allocate them in 158 * a single clump that maps to a single DMA segment to make several things 159 * easier. 160 */ 161 struct vge_control_data { 162 /* TX descriptors */ 163 struct vge_txdesc vcd_txdescs[VGE_NTXDESC]; 164 /* RX descriptors */ 165 struct vge_rxdesc vcd_rxdescs[VGE_NRXDESC]; 166 /* dummy data for TX padding */ 167 uint8_t vcd_pad[ETHER_PAD_LEN]; 168 }; 169 170 #define VGE_CDOFF(x) offsetof(struct vge_control_data, x) 171 #define VGE_CDTXOFF(x) VGE_CDOFF(vcd_txdescs[(x)]) 172 #define VGE_CDRXOFF(x) VGE_CDOFF(vcd_rxdescs[(x)]) 173 #define VGE_CDPADOFF() VGE_CDOFF(vcd_pad[0]) 174 175 /* 176 * Software state for TX jobs. 177 */ 178 struct vge_txsoft { 179 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 180 bus_dmamap_t txs_dmamap; /* our DMA map */ 181 }; 182 183 /* 184 * Software state for RX jobs. 185 */ 186 struct vge_rxsoft { 187 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 188 bus_dmamap_t rxs_dmamap; /* our DMA map */ 189 }; 190 191 192 struct vge_softc { 193 struct device sc_dev; 194 195 bus_space_tag_t sc_bst; /* bus space tag */ 196 bus_space_handle_t sc_bsh; /* bus space handle */ 197 bus_dma_tag_t sc_dmat; 198 199 struct ethercom sc_ethercom; /* interface info */ 200 uint8_t sc_eaddr[ETHER_ADDR_LEN]; 201 202 void *sc_intrhand; 203 struct mii_data sc_mii; 204 uint8_t sc_type; 205 int sc_if_flags; 206 int sc_link; 207 int sc_camidx; 208 callout_t sc_timeout; 209 210 bus_dmamap_t sc_cddmamap; 211 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 212 213 struct vge_txsoft sc_txsoft[VGE_NTXDESC]; 214 struct vge_rxsoft sc_rxsoft[VGE_NRXDESC]; 215 struct vge_control_data *sc_control_data; 216 #define sc_txdescs sc_control_data->vcd_txdescs 217 #define sc_rxdescs sc_control_data->vcd_rxdescs 218 219 int sc_tx_prodidx; 220 int sc_tx_considx; 221 int sc_tx_free; 222 223 struct mbuf *sc_rx_mhead; 224 struct mbuf *sc_rx_mtail; 225 int sc_rx_prodidx; 226 int sc_rx_consumed; 227 228 int sc_suspended; /* 0 = normal 1 = suspended */ 229 uint32_t sc_saved_maps[5]; /* pci data */ 230 uint32_t sc_saved_biosaddr; 231 uint8_t sc_saved_intline; 232 uint8_t sc_saved_cachelnsz; 233 uint8_t sc_saved_lattimer; 234 }; 235 236 #define VGE_CDTXADDR(sc, x) ((sc)->sc_cddma + VGE_CDTXOFF(x)) 237 #define VGE_CDRXADDR(sc, x) ((sc)->sc_cddma + VGE_CDRXOFF(x)) 238 #define VGE_CDPADADDR(sc) ((sc)->sc_cddma + VGE_CDPADOFF()) 239 240 #define VGE_TXDESCSYNC(sc, idx, ops) \ 241 bus_dmamap_sync((sc)->sc_dmat,(sc)->sc_cddmamap, \ 242 VGE_CDTXOFF(idx), \ 243 offsetof(struct vge_txdesc, td_frag[0]), \ 244 (ops)) 245 #define VGE_TXFRAGSYNC(sc, idx, nsegs, ops) \ 246 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 247 VGE_CDTXOFF(idx) + \ 248 offsetof(struct vge_txdesc, td_frag[0]), \ 249 sizeof(struct vge_txfrag) * (nsegs), \ 250 (ops)) 251 #define VGE_RXDESCSYNC(sc, idx, ops) \ 252 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 253 VGE_CDRXOFF(idx), \ 254 sizeof(struct vge_rxdesc), \ 255 (ops)) 256 257 /* 258 * register space access macros 259 */ 260 #define CSR_WRITE_4(sc, reg, val) \ 261 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 262 #define CSR_WRITE_2(sc, reg, val) \ 263 bus_space_write_2((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 264 #define CSR_WRITE_1(sc, reg, val) \ 265 bus_space_write_1((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 266 267 #define CSR_READ_4(sc, reg) \ 268 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 269 #define CSR_READ_2(sc, reg) \ 270 bus_space_read_2((sc)->sc_bst, (sc)->sc_bsh, (reg)) 271 #define CSR_READ_1(sc, reg) \ 272 bus_space_read_1((sc)->sc_bst, (sc)->sc_bsh, (reg)) 273 274 #define CSR_SETBIT_1(sc, reg, x) \ 275 CSR_WRITE_1((sc), (reg), CSR_READ_1((sc), (reg)) | (x)) 276 #define CSR_SETBIT_2(sc, reg, x) \ 277 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (x)) 278 #define CSR_SETBIT_4(sc, reg, x) \ 279 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (x)) 280 281 #define CSR_CLRBIT_1(sc, reg, x) \ 282 CSR_WRITE_1((sc), (reg), CSR_READ_1((sc), (reg)) & ~(x)) 283 #define CSR_CLRBIT_2(sc, reg, x) \ 284 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(x)) 285 #define CSR_CLRBIT_4(sc, reg, x) \ 286 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(x)) 287 288 #define VGE_TIMEOUT 10000 289 290 #define VGE_PCI_LOIO 0x10 291 #define VGE_PCI_LOMEM 0x14 292 293 static inline void vge_set_txaddr(struct vge_txfrag *, bus_addr_t); 294 static inline void vge_set_rxaddr(struct vge_rxdesc *, bus_addr_t); 295 296 static int vge_ifflags_cb(struct ethercom *); 297 298 static int vge_match(struct device *, struct cfdata *, void *); 299 static void vge_attach(struct device *, struct device *, void *); 300 301 static int vge_encap(struct vge_softc *, struct mbuf *, int); 302 303 static int vge_allocmem(struct vge_softc *); 304 static int vge_newbuf(struct vge_softc *, int, struct mbuf *); 305 #ifndef __NO_STRICT_ALIGNMENT 306 static inline void vge_fixup_rx(struct mbuf *); 307 #endif 308 static void vge_rxeof(struct vge_softc *); 309 static void vge_txeof(struct vge_softc *); 310 static int vge_intr(void *); 311 static void vge_tick(void *); 312 static void vge_start(struct ifnet *); 313 static int vge_ioctl(struct ifnet *, u_long, void *); 314 static int vge_init(struct ifnet *); 315 static void vge_stop(struct ifnet *, int); 316 static void vge_watchdog(struct ifnet *); 317 #if VGE_POWER_MANAGEMENT 318 static int vge_suspend(struct device *); 319 static int vge_resume(struct device *); 320 #endif 321 static void vge_shutdown(void *); 322 323 static uint16_t vge_read_eeprom(struct vge_softc *, int); 324 325 static void vge_miipoll_start(struct vge_softc *); 326 static void vge_miipoll_stop(struct vge_softc *); 327 static int vge_miibus_readreg(struct device *, int, int); 328 static void vge_miibus_writereg(struct device *, int, int, int); 329 static void vge_miibus_statchg(struct device *); 330 331 static void vge_cam_clear(struct vge_softc *); 332 static int vge_cam_set(struct vge_softc *, uint8_t *); 333 static void vge_setmulti(struct vge_softc *); 334 static void vge_reset(struct vge_softc *); 335 336 CFATTACH_DECL(vge, sizeof(struct vge_softc), 337 vge_match, vge_attach, NULL, NULL); 338 339 static inline void 340 vge_set_txaddr(struct vge_txfrag *f, bus_addr_t daddr) 341 { 342 343 f->tf_addrlo = htole32((uint32_t)daddr); 344 if (sizeof(bus_addr_t) == sizeof(uint64_t)) 345 f->tf_addrhi = htole16(((uint64_t)daddr >> 32) & 0xFFFF); 346 else 347 f->tf_addrhi = 0; 348 } 349 350 static inline void 351 vge_set_rxaddr(struct vge_rxdesc *rxd, bus_addr_t daddr) 352 { 353 354 rxd->rd_addrlo = htole32((uint32_t)daddr); 355 if (sizeof(bus_addr_t) == sizeof(uint64_t)) 356 rxd->rd_addrhi = htole16(((uint64_t)daddr >> 32) & 0xFFFF); 357 else 358 rxd->rd_addrhi = 0; 359 } 360 361 /* 362 * Defragment mbuf chain contents to be as linear as possible. 363 * Returns new mbuf chain on success, NULL on failure. Old mbuf 364 * chain is always freed. 365 * XXX temporary until there would be generic function doing this. 366 */ 367 #define m_defrag vge_m_defrag 368 struct mbuf * vge_m_defrag(struct mbuf *, int); 369 370 struct mbuf * 371 vge_m_defrag(struct mbuf *mold, int flags) 372 { 373 struct mbuf *m0, *mn, *n; 374 size_t sz = mold->m_pkthdr.len; 375 376 #ifdef DIAGNOSTIC 377 if ((mold->m_flags & M_PKTHDR) == 0) 378 panic("m_defrag: not a mbuf chain header"); 379 #endif 380 381 MGETHDR(m0, flags, MT_DATA); 382 if (m0 == NULL) 383 return NULL; 384 m0->m_pkthdr.len = mold->m_pkthdr.len; 385 mn = m0; 386 387 do { 388 if (sz > MHLEN) { 389 MCLGET(mn, M_DONTWAIT); 390 if ((mn->m_flags & M_EXT) == 0) { 391 m_freem(m0); 392 return NULL; 393 } 394 } 395 396 mn->m_len = MIN(sz, MCLBYTES); 397 398 m_copydata(mold, mold->m_pkthdr.len - sz, mn->m_len, 399 mtod(mn, void *)); 400 401 sz -= mn->m_len; 402 403 if (sz > 0) { 404 /* need more mbufs */ 405 MGET(n, M_NOWAIT, MT_DATA); 406 if (n == NULL) { 407 m_freem(m0); 408 return NULL; 409 } 410 411 mn->m_next = n; 412 mn = n; 413 } 414 } while (sz > 0); 415 416 return m0; 417 } 418 419 /* 420 * Read a word of data stored in the EEPROM at address 'addr.' 421 */ 422 static uint16_t 423 vge_read_eeprom(struct vge_softc *sc, int addr) 424 { 425 int i; 426 uint16_t word = 0; 427 428 /* 429 * Enter EEPROM embedded programming mode. In order to 430 * access the EEPROM at all, we first have to set the 431 * EELOAD bit in the CHIPCFG2 register. 432 */ 433 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 434 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 435 436 /* Select the address of the word we want to read */ 437 CSR_WRITE_1(sc, VGE_EEADDR, addr); 438 439 /* Issue read command */ 440 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 441 442 /* Wait for the done bit to be set. */ 443 for (i = 0; i < VGE_TIMEOUT; i++) { 444 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 445 break; 446 } 447 448 if (i == VGE_TIMEOUT) { 449 aprint_error_dev(&sc->sc_dev, "EEPROM read timed out\n"); 450 return 0; 451 } 452 453 /* Read the result */ 454 word = CSR_READ_2(sc, VGE_EERDDAT); 455 456 /* Turn off EEPROM access mode. */ 457 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 458 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 459 460 return word; 461 } 462 463 static void 464 vge_miipoll_stop(struct vge_softc *sc) 465 { 466 int i; 467 468 CSR_WRITE_1(sc, VGE_MIICMD, 0); 469 470 for (i = 0; i < VGE_TIMEOUT; i++) { 471 DELAY(1); 472 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 473 break; 474 } 475 476 if (i == VGE_TIMEOUT) { 477 aprint_error_dev(&sc->sc_dev, "failed to idle MII autopoll\n"); 478 } 479 } 480 481 static void 482 vge_miipoll_start(struct vge_softc *sc) 483 { 484 int i; 485 486 /* First, make sure we're idle. */ 487 488 CSR_WRITE_1(sc, VGE_MIICMD, 0); 489 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 490 491 for (i = 0; i < VGE_TIMEOUT; i++) { 492 DELAY(1); 493 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 494 break; 495 } 496 497 if (i == VGE_TIMEOUT) { 498 aprint_error_dev(&sc->sc_dev, "failed to idle MII autopoll\n"); 499 return; 500 } 501 502 /* Now enable auto poll mode. */ 503 504 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 505 506 /* And make sure it started. */ 507 508 for (i = 0; i < VGE_TIMEOUT; i++) { 509 DELAY(1); 510 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 511 break; 512 } 513 514 if (i == VGE_TIMEOUT) { 515 aprint_error_dev(&sc->sc_dev, "failed to start MII autopoll\n"); 516 } 517 } 518 519 static int 520 vge_miibus_readreg(struct device *dev, int phy, int reg) 521 { 522 struct vge_softc *sc; 523 int i, s; 524 uint16_t rval; 525 526 sc = (void *)dev; 527 rval = 0; 528 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 529 return 0; 530 531 s = splnet(); 532 vge_miipoll_stop(sc); 533 534 /* Specify the register we want to read. */ 535 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 536 537 /* Issue read command. */ 538 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 539 540 /* Wait for the read command bit to self-clear. */ 541 for (i = 0; i < VGE_TIMEOUT; i++) { 542 DELAY(1); 543 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 544 break; 545 } 546 547 if (i == VGE_TIMEOUT) 548 aprint_error_dev(&sc->sc_dev, "MII read timed out\n"); 549 else 550 rval = CSR_READ_2(sc, VGE_MIIDATA); 551 552 vge_miipoll_start(sc); 553 splx(s); 554 555 return rval; 556 } 557 558 static void 559 vge_miibus_writereg(struct device *dev, int phy, int reg, int data) 560 { 561 struct vge_softc *sc; 562 int i, s; 563 564 sc = (void *)dev; 565 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 566 return; 567 568 s = splnet(); 569 vge_miipoll_stop(sc); 570 571 /* Specify the register we want to write. */ 572 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 573 574 /* Specify the data we want to write. */ 575 CSR_WRITE_2(sc, VGE_MIIDATA, data); 576 577 /* Issue write command. */ 578 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 579 580 /* Wait for the write command bit to self-clear. */ 581 for (i = 0; i < VGE_TIMEOUT; i++) { 582 DELAY(1); 583 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 584 break; 585 } 586 587 if (i == VGE_TIMEOUT) { 588 aprint_error_dev(&sc->sc_dev, "MII write timed out\n"); 589 } 590 591 vge_miipoll_start(sc); 592 splx(s); 593 } 594 595 static void 596 vge_cam_clear(struct vge_softc *sc) 597 { 598 int i; 599 600 /* 601 * Turn off all the mask bits. This tells the chip 602 * that none of the entries in the CAM filter are valid. 603 * desired entries will be enabled as we fill the filter in. 604 */ 605 606 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 607 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 608 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 609 for (i = 0; i < 8; i++) 610 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 611 612 /* Clear the VLAN filter too. */ 613 614 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 615 for (i = 0; i < 8; i++) 616 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 617 618 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 619 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 620 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 621 622 sc->sc_camidx = 0; 623 } 624 625 static int 626 vge_cam_set(struct vge_softc *sc, uint8_t *addr) 627 { 628 int i, error; 629 630 error = 0; 631 632 if (sc->sc_camidx == VGE_CAM_MAXADDRS) 633 return ENOSPC; 634 635 /* Select the CAM data page. */ 636 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 637 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 638 639 /* Set the filter entry we want to update and enable writing. */ 640 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE | sc->sc_camidx); 641 642 /* Write the address to the CAM registers */ 643 for (i = 0; i < ETHER_ADDR_LEN; i++) 644 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 645 646 /* Issue a write command. */ 647 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 648 649 /* Wake for it to clear. */ 650 for (i = 0; i < VGE_TIMEOUT; i++) { 651 DELAY(1); 652 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 653 break; 654 } 655 656 if (i == VGE_TIMEOUT) { 657 aprint_error_dev(&sc->sc_dev, "setting CAM filter failed\n"); 658 error = EIO; 659 goto fail; 660 } 661 662 /* Select the CAM mask page. */ 663 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 664 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 665 666 /* Set the mask bit that enables this filter. */ 667 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->sc_camidx / 8), 668 1 << (sc->sc_camidx & 7)); 669 670 sc->sc_camidx++; 671 672 fail: 673 /* Turn off access to CAM. */ 674 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 675 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 676 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 677 678 return error; 679 } 680 681 /* 682 * Program the multicast filter. We use the 64-entry CAM filter 683 * for perfect filtering. If there's more than 64 multicast addresses, 684 * we use the hash filter instead. 685 */ 686 static void 687 vge_setmulti(struct vge_softc *sc) 688 { 689 struct ifnet *ifp; 690 int error; 691 uint32_t h, hashes[2] = { 0, 0 }; 692 struct ether_multi *enm; 693 struct ether_multistep step; 694 695 error = 0; 696 ifp = &sc->sc_ethercom.ec_if; 697 698 /* First, zot all the multicast entries. */ 699 vge_cam_clear(sc); 700 CSR_WRITE_4(sc, VGE_MAR0, 0); 701 CSR_WRITE_4(sc, VGE_MAR1, 0); 702 ifp->if_flags &= ~IFF_ALLMULTI; 703 704 /* 705 * If the user wants allmulti or promisc mode, enable reception 706 * of all multicast frames. 707 */ 708 if (ifp->if_flags & IFF_PROMISC) { 709 allmulti: 710 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 711 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 712 ifp->if_flags |= IFF_ALLMULTI; 713 return; 714 } 715 716 /* Now program new ones */ 717 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 718 while (enm != NULL) { 719 /* 720 * If multicast range, fall back to ALLMULTI. 721 */ 722 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 723 ETHER_ADDR_LEN) != 0) 724 goto allmulti; 725 726 error = vge_cam_set(sc, enm->enm_addrlo); 727 if (error) 728 break; 729 730 ETHER_NEXT_MULTI(step, enm); 731 } 732 733 /* If there were too many addresses, use the hash filter. */ 734 if (error) { 735 vge_cam_clear(sc); 736 737 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 738 while (enm != NULL) { 739 /* 740 * If multicast range, fall back to ALLMULTI. 741 */ 742 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 743 ETHER_ADDR_LEN) != 0) 744 goto allmulti; 745 746 h = ether_crc32_be(enm->enm_addrlo, 747 ETHER_ADDR_LEN) >> 26; 748 hashes[h >> 5] |= 1 << (h & 0x1f); 749 750 ETHER_NEXT_MULTI(step, enm); 751 } 752 753 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 754 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 755 } 756 } 757 758 static void 759 vge_reset(struct vge_softc *sc) 760 { 761 int i; 762 763 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 764 765 for (i = 0; i < VGE_TIMEOUT; i++) { 766 DELAY(5); 767 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 768 break; 769 } 770 771 if (i == VGE_TIMEOUT) { 772 aprint_error_dev(&sc->sc_dev, "soft reset timed out"); 773 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 774 DELAY(2000); 775 } 776 777 DELAY(5000); 778 779 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 780 781 for (i = 0; i < VGE_TIMEOUT; i++) { 782 DELAY(5); 783 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 784 break; 785 } 786 787 if (i == VGE_TIMEOUT) { 788 aprint_error_dev(&sc->sc_dev, "EEPROM reload timed out\n"); 789 return; 790 } 791 792 /* 793 * On some machine, the first read data from EEPROM could be 794 * messed up, so read one dummy data here to avoid the mess. 795 */ 796 (void)vge_read_eeprom(sc, 0); 797 798 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 799 } 800 801 /* 802 * Probe for a VIA gigabit chip. Check the PCI vendor and device 803 * IDs against our list and return a device name if we find a match. 804 */ 805 static int 806 vge_match(struct device *parent, struct cfdata *match, void *aux) 807 { 808 struct pci_attach_args *pa = aux; 809 810 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH 811 && PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_VIATECH_VT612X) 812 return 1; 813 814 return 0; 815 } 816 817 static int 818 vge_allocmem(struct vge_softc *sc) 819 { 820 int error; 821 int nseg; 822 int i; 823 bus_dma_segment_t seg; 824 825 /* 826 * Allocate memory for control data. 827 */ 828 829 error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct vge_control_data), 830 VGE_RING_ALIGN, 0, &seg, 1, &nseg, BUS_DMA_NOWAIT); 831 if (error) { 832 aprint_error_dev(&sc->sc_dev, "could not allocate control data dma memory\n"); 833 goto fail_1; 834 } 835 836 /* Map the memory to kernel VA space */ 837 838 error = bus_dmamem_map(sc->sc_dmat, &seg, nseg, 839 sizeof(struct vge_control_data), (void **)&sc->sc_control_data, 840 BUS_DMA_NOWAIT); 841 if (error) { 842 aprint_error_dev(&sc->sc_dev, "could not map control data dma memory\n"); 843 goto fail_2; 844 } 845 memset(sc->sc_control_data, 0, sizeof(struct vge_control_data)); 846 847 /* 848 * Create map for control data. 849 */ 850 error = bus_dmamap_create(sc->sc_dmat, 851 sizeof(struct vge_control_data), 1, 852 sizeof(struct vge_control_data), 0, BUS_DMA_NOWAIT, 853 &sc->sc_cddmamap); 854 if (error) { 855 aprint_error_dev(&sc->sc_dev, "could not create control data dmamap\n"); 856 goto fail_3; 857 } 858 859 /* Load the map for the control data. */ 860 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 861 sc->sc_control_data, sizeof(struct vge_control_data), NULL, 862 BUS_DMA_NOWAIT); 863 if (error) { 864 aprint_error_dev(&sc->sc_dev, "could not load control data dma memory\n"); 865 goto fail_4; 866 } 867 868 /* Create DMA maps for TX buffers */ 869 870 for (i = 0; i < VGE_NTXDESC; i++) { 871 error = bus_dmamap_create(sc->sc_dmat, VGE_TX_MAXLEN, 872 VGE_TX_FRAGS, VGE_TX_MAXLEN, 0, BUS_DMA_NOWAIT, 873 &sc->sc_txsoft[i].txs_dmamap); 874 if (error) { 875 aprint_error_dev(&sc->sc_dev, "can't create DMA map for TX descs\n"); 876 goto fail_5; 877 } 878 } 879 880 /* Create DMA maps for RX buffers */ 881 882 for (i = 0; i < VGE_NRXDESC; i++) { 883 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 884 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 885 &sc->sc_rxsoft[i].rxs_dmamap); 886 if (error) { 887 aprint_error_dev(&sc->sc_dev, "can't create DMA map for RX descs\n"); 888 goto fail_6; 889 } 890 sc->sc_rxsoft[i].rxs_mbuf = NULL; 891 } 892 893 return 0; 894 895 fail_6: 896 for (i = 0; i < VGE_NRXDESC; i++) { 897 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 898 bus_dmamap_destroy(sc->sc_dmat, 899 sc->sc_rxsoft[i].rxs_dmamap); 900 } 901 fail_5: 902 for (i = 0; i < VGE_NTXDESC; i++) { 903 if (sc->sc_txsoft[i].txs_dmamap != NULL) 904 bus_dmamap_destroy(sc->sc_dmat, 905 sc->sc_txsoft[i].txs_dmamap); 906 } 907 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 908 fail_4: 909 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 910 fail_3: 911 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 912 sizeof(struct vge_control_data)); 913 fail_2: 914 bus_dmamem_free(sc->sc_dmat, &seg, nseg); 915 fail_1: 916 return ENOMEM; 917 } 918 919 /* 920 * Attach the interface. Allocate softc structures, do ifmedia 921 * setup and ethernet/BPF attach. 922 */ 923 static void 924 vge_attach(struct device *parent, struct device *self, void *aux) 925 { 926 uint8_t *eaddr; 927 struct vge_softc *sc = (void *)self; 928 struct ifnet *ifp; 929 struct pci_attach_args *pa = aux; 930 pci_chipset_tag_t pc = pa->pa_pc; 931 const char *intrstr; 932 pci_intr_handle_t ih; 933 uint16_t val; 934 935 aprint_normal(": VIA VT612X Gigabit Ethernet (rev. %#x)\n", 936 PCI_REVISION(pa->pa_class)); 937 938 /* Make sure bus-mastering is enabled */ 939 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 940 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 941 PCI_COMMAND_MASTER_ENABLE); 942 943 /* 944 * Map control/status registers. 945 */ 946 if (pci_mapreg_map(pa, VGE_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 947 &sc->sc_bst, &sc->sc_bsh, NULL, NULL) != 0) { 948 aprint_error_dev(&sc->sc_dev, "couldn't map memory\n"); 949 return; 950 } 951 952 /* 953 * Map and establish our interrupt. 954 */ 955 if (pci_intr_map(pa, &ih)) { 956 aprint_error_dev(&sc->sc_dev, "unable to map interrupt\n"); 957 return; 958 } 959 intrstr = pci_intr_string(pc, ih); 960 sc->sc_intrhand = pci_intr_establish(pc, ih, IPL_NET, vge_intr, sc); 961 if (sc->sc_intrhand == NULL) { 962 aprint_error_dev(&sc->sc_dev, "unable to establish interrupt"); 963 if (intrstr != NULL) 964 aprint_error(" at %s", intrstr); 965 aprint_error("\n"); 966 return; 967 } 968 aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", intrstr); 969 970 /* Reset the adapter. */ 971 vge_reset(sc); 972 973 /* 974 * Get station address from the EEPROM. 975 */ 976 eaddr = sc->sc_eaddr; 977 val = vge_read_eeprom(sc, VGE_EE_EADDR + 0); 978 eaddr[0] = val & 0xff; 979 eaddr[1] = val >> 8; 980 val = vge_read_eeprom(sc, VGE_EE_EADDR + 1); 981 eaddr[2] = val & 0xff; 982 eaddr[3] = val >> 8; 983 val = vge_read_eeprom(sc, VGE_EE_EADDR + 2); 984 eaddr[4] = val & 0xff; 985 eaddr[5] = val >> 8; 986 987 aprint_normal_dev(&sc->sc_dev, "Ethernet address: %s\n", 988 ether_sprintf(eaddr)); 989 990 /* 991 * Use the 32bit tag. Hardware supports 48bit physical addresses, 992 * but we don't use that for now. 993 */ 994 sc->sc_dmat = pa->pa_dmat; 995 996 if (vge_allocmem(sc) != 0) 997 return; 998 999 ifp = &sc->sc_ethercom.ec_if; 1000 ifp->if_softc = sc; 1001 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 1002 ifp->if_mtu = ETHERMTU; 1003 ifp->if_baudrate = IF_Gbps(1); 1004 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1005 ifp->if_ioctl = vge_ioctl; 1006 ifp->if_start = vge_start; 1007 ifp->if_init = vge_init; 1008 ifp->if_stop = vge_stop; 1009 1010 /* 1011 * We can support 802.1Q VLAN-sized frames and jumbo 1012 * Ethernet frames. 1013 */ 1014 sc->sc_ethercom.ec_capabilities |= 1015 ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU | 1016 ETHERCAP_VLAN_HWTAGGING; 1017 1018 /* 1019 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 1020 */ 1021 ifp->if_capabilities |= 1022 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1023 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1024 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1025 1026 #ifdef DEVICE_POLLING 1027 #ifdef IFCAP_POLLING 1028 ifp->if_capabilities |= IFCAP_POLLING; 1029 #endif 1030 #endif 1031 ifp->if_watchdog = vge_watchdog; 1032 IFQ_SET_MAXLEN(&ifp->if_snd, max(VGE_IFQ_MAXLEN, IFQ_MAXLEN)); 1033 IFQ_SET_READY(&ifp->if_snd); 1034 1035 /* 1036 * Initialize our media structures and probe the MII. 1037 */ 1038 sc->sc_mii.mii_ifp = ifp; 1039 sc->sc_mii.mii_readreg = vge_miibus_readreg; 1040 sc->sc_mii.mii_writereg = vge_miibus_writereg; 1041 sc->sc_mii.mii_statchg = vge_miibus_statchg; 1042 1043 sc->sc_ethercom.ec_mii = &sc->sc_mii; 1044 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 1045 ether_mediastatus); 1046 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1047 MII_OFFSET_ANY, MIIF_DOPAUSE); 1048 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1049 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1050 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1051 } else 1052 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1053 1054 /* 1055 * Attach the interface. 1056 */ 1057 if_attach(ifp); 1058 ether_ifattach(ifp, eaddr); 1059 ether_set_ifflags_cb(&sc->sc_ethercom, vge_ifflags_cb); 1060 1061 callout_init(&sc->sc_timeout, 0); 1062 callout_setfunc(&sc->sc_timeout, vge_tick, sc); 1063 1064 /* 1065 * Make sure the interface is shutdown during reboot. 1066 */ 1067 if (shutdownhook_establish(vge_shutdown, sc) == NULL) { 1068 aprint_error_dev(&sc->sc_dev, "WARNING: unable to establish shutdown hook\n"); 1069 } 1070 } 1071 1072 static int 1073 vge_newbuf(struct vge_softc *sc, int idx, struct mbuf *m) 1074 { 1075 struct mbuf *m_new; 1076 struct vge_rxdesc *rxd; 1077 struct vge_rxsoft *rxs; 1078 bus_dmamap_t map; 1079 int i; 1080 #ifdef DIAGNOSTIC 1081 uint32_t rd_sts; 1082 #endif 1083 1084 m_new = NULL; 1085 if (m == NULL) { 1086 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1087 if (m_new == NULL) 1088 return ENOBUFS; 1089 1090 MCLGET(m_new, M_DONTWAIT); 1091 if ((m_new->m_flags & M_EXT) == 0) { 1092 m_freem(m_new); 1093 return ENOBUFS; 1094 } 1095 1096 m = m_new; 1097 } else 1098 m->m_data = m->m_ext.ext_buf; 1099 1100 1101 /* 1102 * This is part of an evil trick to deal with non-x86 platforms. 1103 * The VIA chip requires RX buffers to be aligned on 32-bit 1104 * boundaries, but that will hose non-x86 machines. To get around 1105 * this, we leave some empty space at the start of each buffer 1106 * and for non-x86 hosts, we copy the buffer back two bytes 1107 * to achieve word alignment. This is slightly more efficient 1108 * than allocating a new buffer, copying the contents, and 1109 * discarding the old buffer. 1110 */ 1111 m->m_len = m->m_pkthdr.len = VGE_RX_BUFSIZE; 1112 #ifndef __NO_STRICT_ALIGNMENT 1113 m->m_data += VGE_RX_PAD; 1114 #endif 1115 rxs = &sc->sc_rxsoft[idx]; 1116 map = rxs->rxs_dmamap; 1117 1118 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT) != 0) 1119 goto out; 1120 1121 rxd = &sc->sc_rxdescs[idx]; 1122 1123 #ifdef DIAGNOSTIC 1124 /* If this descriptor is still owned by the chip, bail. */ 1125 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1126 rd_sts = le32toh(rxd->rd_sts); 1127 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1128 if (rd_sts & VGE_RDSTS_OWN) { 1129 panic("%s: tried to map busy RX descriptor", 1130 device_xname(&sc->sc_dev)); 1131 } 1132 #endif 1133 1134 rxs->rxs_mbuf = m; 1135 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1136 BUS_DMASYNC_PREREAD); 1137 1138 rxd->rd_buflen = 1139 htole16(VGE_BUFLEN(map->dm_segs[0].ds_len) | VGE_RXDESC_I); 1140 vge_set_rxaddr(rxd, map->dm_segs[0].ds_addr); 1141 rxd->rd_sts = 0; 1142 rxd->rd_ctl = 0; 1143 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1144 1145 /* 1146 * Note: the manual fails to document the fact that for 1147 * proper opration, the driver needs to replentish the RX 1148 * DMA ring 4 descriptors at a time (rather than one at a 1149 * time, like most chips). We can allocate the new buffers 1150 * but we should not set the OWN bits until we're ready 1151 * to hand back 4 of them in one shot. 1152 */ 1153 1154 #define VGE_RXCHUNK 4 1155 sc->sc_rx_consumed++; 1156 if (sc->sc_rx_consumed == VGE_RXCHUNK) { 1157 for (i = idx; i != idx - VGE_RXCHUNK; i--) { 1158 KASSERT(i >= 0); 1159 sc->sc_rxdescs[i].rd_sts |= htole32(VGE_RDSTS_OWN); 1160 VGE_RXDESCSYNC(sc, i, 1161 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1162 } 1163 sc->sc_rx_consumed = 0; 1164 } 1165 1166 return 0; 1167 out: 1168 if (m_new != NULL) 1169 m_freem(m_new); 1170 return ENOMEM; 1171 } 1172 1173 #ifndef __NO_STRICT_ALIGNMENT 1174 static inline void 1175 vge_fixup_rx(struct mbuf *m) 1176 { 1177 int i; 1178 uint16_t *src, *dst; 1179 1180 src = mtod(m, uint16_t *); 1181 dst = src - 1; 1182 1183 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1184 *dst++ = *src++; 1185 1186 m->m_data -= ETHER_ALIGN; 1187 } 1188 #endif 1189 1190 /* 1191 * RX handler. We support the reception of jumbo frames that have 1192 * been fragmented across multiple 2K mbuf cluster buffers. 1193 */ 1194 static void 1195 vge_rxeof(struct vge_softc *sc) 1196 { 1197 struct mbuf *m; 1198 struct ifnet *ifp; 1199 int idx, total_len, lim; 1200 struct vge_rxdesc *cur_rxd; 1201 struct vge_rxsoft *rxs; 1202 uint32_t rxstat, rxctl; 1203 1204 ifp = &sc->sc_ethercom.ec_if; 1205 lim = 0; 1206 1207 /* Invalidate the descriptor memory */ 1208 1209 for (idx = sc->sc_rx_prodidx;; idx = VGE_NEXT_RXDESC(idx)) { 1210 cur_rxd = &sc->sc_rxdescs[idx]; 1211 1212 VGE_RXDESCSYNC(sc, idx, 1213 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1214 rxstat = le32toh(cur_rxd->rd_sts); 1215 if ((rxstat & VGE_RDSTS_OWN) != 0) { 1216 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1217 break; 1218 } 1219 1220 rxctl = le32toh(cur_rxd->rd_ctl); 1221 rxs = &sc->sc_rxsoft[idx]; 1222 m = rxs->rxs_mbuf; 1223 total_len = (rxstat & VGE_RDSTS_BUFSIZ) >> 16; 1224 1225 /* Invalidate the RX mbuf and unload its map */ 1226 1227 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 1228 0, rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1229 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1230 1231 /* 1232 * If the 'start of frame' bit is set, this indicates 1233 * either the first fragment in a multi-fragment receive, 1234 * or an intermediate fragment. Either way, we want to 1235 * accumulate the buffers. 1236 */ 1237 if (rxstat & VGE_RXPKT_SOF) { 1238 m->m_len = VGE_RX_BUFSIZE; 1239 if (sc->sc_rx_mhead == NULL) 1240 sc->sc_rx_mhead = sc->sc_rx_mtail = m; 1241 else { 1242 m->m_flags &= ~M_PKTHDR; 1243 sc->sc_rx_mtail->m_next = m; 1244 sc->sc_rx_mtail = m; 1245 } 1246 vge_newbuf(sc, idx, NULL); 1247 continue; 1248 } 1249 1250 /* 1251 * Bad/error frames will have the RXOK bit cleared. 1252 * However, there's one error case we want to allow: 1253 * if a VLAN tagged frame arrives and the chip can't 1254 * match it against the CAM filter, it considers this 1255 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1256 * We don't want to drop the frame though: our VLAN 1257 * filtering is done in software. 1258 */ 1259 if ((rxstat & VGE_RDSTS_RXOK) == 0 && 1260 (rxstat & VGE_RDSTS_VIDM) == 0 && 1261 (rxstat & VGE_RDSTS_CSUMERR) == 0) { 1262 ifp->if_ierrors++; 1263 /* 1264 * If this is part of a multi-fragment packet, 1265 * discard all the pieces. 1266 */ 1267 if (sc->sc_rx_mhead != NULL) { 1268 m_freem(sc->sc_rx_mhead); 1269 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL; 1270 } 1271 vge_newbuf(sc, idx, m); 1272 continue; 1273 } 1274 1275 /* 1276 * If allocating a replacement mbuf fails, 1277 * reload the current one. 1278 */ 1279 1280 if (vge_newbuf(sc, idx, NULL)) { 1281 ifp->if_ierrors++; 1282 if (sc->sc_rx_mhead != NULL) { 1283 m_freem(sc->sc_rx_mhead); 1284 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL; 1285 } 1286 vge_newbuf(sc, idx, m); 1287 continue; 1288 } 1289 1290 if (sc->sc_rx_mhead != NULL) { 1291 m->m_len = total_len % VGE_RX_BUFSIZE; 1292 /* 1293 * Special case: if there's 4 bytes or less 1294 * in this buffer, the mbuf can be discarded: 1295 * the last 4 bytes is the CRC, which we don't 1296 * care about anyway. 1297 */ 1298 if (m->m_len <= ETHER_CRC_LEN) { 1299 sc->sc_rx_mtail->m_len -= 1300 (ETHER_CRC_LEN - m->m_len); 1301 m_freem(m); 1302 } else { 1303 m->m_len -= ETHER_CRC_LEN; 1304 m->m_flags &= ~M_PKTHDR; 1305 sc->sc_rx_mtail->m_next = m; 1306 } 1307 m = sc->sc_rx_mhead; 1308 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL; 1309 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1310 } else 1311 m->m_pkthdr.len = m->m_len = total_len - ETHER_CRC_LEN; 1312 1313 #ifndef __NO_STRICT_ALIGNMENT 1314 vge_fixup_rx(m); 1315 #endif 1316 ifp->if_ipackets++; 1317 m->m_pkthdr.rcvif = ifp; 1318 1319 /* Do RX checksumming if enabled */ 1320 if (ifp->if_csum_flags_rx & M_CSUM_IPv4) { 1321 1322 /* Check IP header checksum */ 1323 if (rxctl & VGE_RDCTL_IPPKT) 1324 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1325 if ((rxctl & VGE_RDCTL_IPCSUMOK) == 0) 1326 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1327 } 1328 1329 if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) { 1330 /* Check UDP checksum */ 1331 if (rxctl & VGE_RDCTL_TCPPKT) 1332 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1333 1334 if ((rxctl & VGE_RDCTL_PROTOCSUMOK) == 0) 1335 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1336 } 1337 1338 if (ifp->if_csum_flags_rx & M_CSUM_UDPv4) { 1339 /* Check UDP checksum */ 1340 if (rxctl & VGE_RDCTL_UDPPKT) 1341 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1342 1343 if ((rxctl & VGE_RDCTL_PROTOCSUMOK) == 0) 1344 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1345 } 1346 1347 if (rxstat & VGE_RDSTS_VTAG) { 1348 /* 1349 * We use bswap16() here because: 1350 * On LE machines, tag is stored in BE as stream data. 1351 * On BE machines, tag is stored in BE as stream data 1352 * but it was already swapped by le32toh() above. 1353 */ 1354 VLAN_INPUT_TAG(ifp, m, 1355 bswap16(rxctl & VGE_RDCTL_VLANID), continue); 1356 } 1357 1358 #if NBPFILTER > 0 1359 /* 1360 * Handle BPF listeners. 1361 */ 1362 if (ifp->if_bpf) 1363 bpf_mtap(ifp->if_bpf, m); 1364 #endif 1365 1366 (*ifp->if_input)(ifp, m); 1367 1368 lim++; 1369 if (lim == VGE_NRXDESC) 1370 break; 1371 } 1372 1373 sc->sc_rx_prodidx = idx; 1374 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1375 } 1376 1377 static void 1378 vge_txeof(struct vge_softc *sc) 1379 { 1380 struct ifnet *ifp; 1381 struct vge_txsoft *txs; 1382 uint32_t txstat; 1383 int idx; 1384 1385 ifp = &sc->sc_ethercom.ec_if; 1386 1387 for (idx = sc->sc_tx_considx; 1388 sc->sc_tx_free < VGE_NTXDESC; 1389 idx = VGE_NEXT_TXDESC(idx), sc->sc_tx_free++) { 1390 VGE_TXDESCSYNC(sc, idx, 1391 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1392 txstat = le32toh(sc->sc_txdescs[idx].td_sts); 1393 VGE_TXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1394 if (txstat & VGE_TDSTS_OWN) { 1395 break; 1396 } 1397 1398 txs = &sc->sc_txsoft[idx]; 1399 m_freem(txs->txs_mbuf); 1400 txs->txs_mbuf = NULL; 1401 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 0, 1402 txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1403 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1404 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1405 ifp->if_collisions++; 1406 if (txstat & VGE_TDSTS_TXERR) 1407 ifp->if_oerrors++; 1408 else 1409 ifp->if_opackets++; 1410 } 1411 1412 sc->sc_tx_considx = idx; 1413 1414 if (sc->sc_tx_free > 0) { 1415 ifp->if_flags &= ~IFF_OACTIVE; 1416 } 1417 1418 /* 1419 * If not all descriptors have been released reaped yet, 1420 * reload the timer so that we will eventually get another 1421 * interrupt that will cause us to re-enter this routine. 1422 * This is done in case the transmitter has gone idle. 1423 */ 1424 if (sc->sc_tx_free < VGE_NTXDESC) 1425 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1426 else 1427 ifp->if_timer = 0; 1428 } 1429 1430 static void 1431 vge_tick(void *xsc) 1432 { 1433 struct vge_softc *sc; 1434 struct ifnet *ifp; 1435 struct mii_data *mii; 1436 int s; 1437 1438 sc = xsc; 1439 ifp = &sc->sc_ethercom.ec_if; 1440 mii = &sc->sc_mii; 1441 1442 s = splnet(); 1443 1444 callout_schedule(&sc->sc_timeout, hz); 1445 1446 mii_tick(mii); 1447 if (sc->sc_link) { 1448 if ((mii->mii_media_status & IFM_ACTIVE) == 0) 1449 sc->sc_link = 0; 1450 } else { 1451 if (mii->mii_media_status & IFM_ACTIVE && 1452 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1453 sc->sc_link = 1; 1454 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1455 vge_start(ifp); 1456 } 1457 } 1458 1459 splx(s); 1460 } 1461 1462 static int 1463 vge_intr(void *arg) 1464 { 1465 struct vge_softc *sc; 1466 struct ifnet *ifp; 1467 uint32_t status; 1468 int claim; 1469 1470 sc = arg; 1471 claim = 0; 1472 if (sc->sc_suspended) { 1473 return claim; 1474 } 1475 1476 ifp = &sc->sc_ethercom.ec_if; 1477 1478 if ((ifp->if_flags & IFF_UP) == 0) { 1479 return claim; 1480 } 1481 1482 /* Disable interrupts */ 1483 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1484 1485 for (;;) { 1486 1487 status = CSR_READ_4(sc, VGE_ISR); 1488 /* If the card has gone away the read returns 0xffff. */ 1489 if (status == 0xFFFFFFFF) 1490 break; 1491 1492 if (status) { 1493 claim = 1; 1494 CSR_WRITE_4(sc, VGE_ISR, status); 1495 } 1496 1497 if ((status & VGE_INTRS) == 0) 1498 break; 1499 1500 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1501 vge_rxeof(sc); 1502 1503 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1504 vge_rxeof(sc); 1505 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1506 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1507 } 1508 1509 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1510 vge_txeof(sc); 1511 1512 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) 1513 vge_init(ifp); 1514 1515 if (status & VGE_ISR_LINKSTS) 1516 vge_tick(sc); 1517 } 1518 1519 /* Re-enable interrupts */ 1520 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1521 1522 if (claim && !IFQ_IS_EMPTY(&ifp->if_snd)) 1523 vge_start(ifp); 1524 1525 return claim; 1526 } 1527 1528 static int 1529 vge_encap(struct vge_softc *sc, struct mbuf *m_head, int idx) 1530 { 1531 struct vge_txsoft *txs; 1532 struct vge_txdesc *txd; 1533 struct vge_txfrag *f; 1534 struct mbuf *m_new; 1535 bus_dmamap_t map; 1536 int m_csumflags, seg, error, flags; 1537 struct m_tag *mtag; 1538 size_t sz; 1539 uint32_t td_sts, td_ctl; 1540 1541 KASSERT(sc->sc_tx_free > 0); 1542 1543 txd = &sc->sc_txdescs[idx]; 1544 1545 #ifdef DIAGNOSTIC 1546 /* If this descriptor is still owned by the chip, bail. */ 1547 VGE_TXDESCSYNC(sc, idx, 1548 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1549 td_sts = le32toh(txd->td_sts); 1550 VGE_TXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1551 if (td_sts & VGE_TDSTS_OWN) { 1552 return ENOBUFS; 1553 } 1554 #endif 1555 1556 /* 1557 * Preserve m_pkthdr.csum_flags here since m_head might be 1558 * updated by m_defrag() 1559 */ 1560 m_csumflags = m_head->m_pkthdr.csum_flags; 1561 1562 txs = &sc->sc_txsoft[idx]; 1563 map = txs->txs_dmamap; 1564 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m_head, BUS_DMA_NOWAIT); 1565 1566 /* If too many segments to map, coalesce */ 1567 if (error == EFBIG || 1568 (m_head->m_pkthdr.len < ETHER_PAD_LEN && 1569 map->dm_nsegs == VGE_TX_FRAGS)) { 1570 m_new = m_defrag(m_head, M_DONTWAIT); 1571 if (m_new == NULL) 1572 return EFBIG; 1573 1574 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, 1575 m_new, BUS_DMA_NOWAIT); 1576 if (error) { 1577 m_freem(m_new); 1578 return error; 1579 } 1580 1581 m_head = m_new; 1582 } else if (error) 1583 return error; 1584 1585 txs->txs_mbuf = m_head; 1586 1587 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1588 BUS_DMASYNC_PREWRITE); 1589 1590 for (seg = 0, f = &txd->td_frag[0]; seg < map->dm_nsegs; seg++, f++) { 1591 f->tf_buflen = htole16(VGE_BUFLEN(map->dm_segs[seg].ds_len)); 1592 vge_set_txaddr(f, map->dm_segs[seg].ds_addr); 1593 } 1594 1595 /* Argh. This chip does not autopad short frames */ 1596 sz = m_head->m_pkthdr.len; 1597 if (sz < ETHER_PAD_LEN) { 1598 f->tf_buflen = htole16(VGE_BUFLEN(ETHER_PAD_LEN - sz)); 1599 vge_set_txaddr(f, VGE_CDPADADDR(sc)); 1600 sz = ETHER_PAD_LEN; 1601 seg++; 1602 } 1603 VGE_TXFRAGSYNC(sc, idx, seg, BUS_DMASYNC_PREWRITE); 1604 1605 /* 1606 * When telling the chip how many segments there are, we 1607 * must use nsegs + 1 instead of just nsegs. Darned if I 1608 * know why. 1609 */ 1610 seg++; 1611 1612 flags = 0; 1613 if (m_csumflags & M_CSUM_IPv4) 1614 flags |= VGE_TDCTL_IPCSUM; 1615 if (m_csumflags & M_CSUM_TCPv4) 1616 flags |= VGE_TDCTL_TCPCSUM; 1617 if (m_csumflags & M_CSUM_UDPv4) 1618 flags |= VGE_TDCTL_UDPCSUM; 1619 td_sts = sz << 16; 1620 td_ctl = flags | (seg << 28) | VGE_TD_LS_NORM; 1621 1622 if (sz > ETHERMTU + ETHER_HDR_LEN) 1623 td_ctl |= VGE_TDCTL_JUMBO; 1624 1625 /* 1626 * Set up hardware VLAN tagging. 1627 */ 1628 mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m_head); 1629 if (mtag != NULL) { 1630 /* 1631 * No need htons() here since vge(4) chip assumes 1632 * that tags are written in little endian and 1633 * we already use htole32() here. 1634 */ 1635 td_ctl |= VLAN_TAG_VALUE(mtag) | VGE_TDCTL_VTAG; 1636 } 1637 txd->td_ctl = htole32(td_ctl); 1638 txd->td_sts = htole32(td_sts); 1639 VGE_TXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1640 1641 txd->td_sts = htole32(VGE_TDSTS_OWN | td_sts); 1642 VGE_TXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1643 1644 sc->sc_tx_free--; 1645 1646 return 0; 1647 } 1648 1649 /* 1650 * Main transmit routine. 1651 */ 1652 1653 static void 1654 vge_start(struct ifnet *ifp) 1655 { 1656 struct vge_softc *sc; 1657 struct vge_txsoft *txs; 1658 struct mbuf *m_head; 1659 int idx, pidx, ofree, error; 1660 1661 sc = ifp->if_softc; 1662 1663 if (!sc->sc_link || 1664 (ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) { 1665 return; 1666 } 1667 1668 m_head = NULL; 1669 idx = sc->sc_tx_prodidx; 1670 pidx = VGE_PREV_TXDESC(idx); 1671 ofree = sc->sc_tx_free; 1672 1673 /* 1674 * Loop through the send queue, setting up transmit descriptors 1675 * until we drain the queue, or use up all available transmit 1676 * descriptors. 1677 */ 1678 for (;;) { 1679 /* Grab a packet off the queue. */ 1680 IFQ_POLL(&ifp->if_snd, m_head); 1681 if (m_head == NULL) 1682 break; 1683 1684 if (sc->sc_tx_free == 0) { 1685 /* 1686 * All slots used, stop for now. 1687 */ 1688 ifp->if_flags |= IFF_OACTIVE; 1689 break; 1690 } 1691 1692 txs = &sc->sc_txsoft[idx]; 1693 KASSERT(txs->txs_mbuf == NULL); 1694 1695 if ((error = vge_encap(sc, m_head, idx))) { 1696 if (error == EFBIG) { 1697 aprint_error_dev(&sc->sc_dev, "Tx packet consumes too many " 1698 "DMA segments, dropping...\n"); 1699 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1700 m_freem(m_head); 1701 continue; 1702 } 1703 1704 /* 1705 * Short on resources, just stop for now. 1706 */ 1707 if (error == ENOBUFS) 1708 ifp->if_flags |= IFF_OACTIVE; 1709 break; 1710 } 1711 1712 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1713 1714 /* 1715 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1716 */ 1717 1718 sc->sc_txdescs[pidx].td_frag[0].tf_buflen |= 1719 htole16(VGE_TXDESC_Q); 1720 VGE_TXFRAGSYNC(sc, pidx, 1, 1721 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1722 1723 if (txs->txs_mbuf != m_head) { 1724 m_freem(m_head); 1725 m_head = txs->txs_mbuf; 1726 } 1727 1728 pidx = idx; 1729 idx = VGE_NEXT_TXDESC(idx); 1730 1731 /* 1732 * If there's a BPF listener, bounce a copy of this frame 1733 * to him. 1734 */ 1735 #if NBPFILTER > 0 1736 if (ifp->if_bpf) 1737 bpf_mtap(ifp->if_bpf, m_head); 1738 #endif 1739 } 1740 1741 if (sc->sc_tx_free < ofree) { 1742 /* TX packet queued */ 1743 1744 sc->sc_tx_prodidx = idx; 1745 1746 /* Issue a transmit command. */ 1747 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1748 1749 /* 1750 * Use the countdown timer for interrupt moderation. 1751 * 'TX done' interrupts are disabled. Instead, we reset the 1752 * countdown timer, which will begin counting until it hits 1753 * the value in the SSTIMER register, and then trigger an 1754 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1755 * the timer count is reloaded. Only when the transmitter 1756 * is idle will the timer hit 0 and an interrupt fire. 1757 */ 1758 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1759 1760 /* 1761 * Set a timeout in case the chip goes out to lunch. 1762 */ 1763 ifp->if_timer = 5; 1764 } 1765 } 1766 1767 static int 1768 vge_init(struct ifnet *ifp) 1769 { 1770 struct vge_softc *sc; 1771 int i, rc = 0; 1772 1773 sc = ifp->if_softc; 1774 1775 /* 1776 * Cancel pending I/O and free all RX/TX buffers. 1777 */ 1778 vge_stop(ifp, 0); 1779 vge_reset(sc); 1780 1781 /* Initialize the RX descriptors and mbufs. */ 1782 memset(sc->sc_rxdescs, 0, sizeof(sc->sc_rxdescs)); 1783 sc->sc_rx_consumed = 0; 1784 for (i = 0; i < VGE_NRXDESC; i++) { 1785 if (vge_newbuf(sc, i, NULL) == ENOBUFS) { 1786 aprint_error_dev(&sc->sc_dev, "unable to allocate or map " 1787 "rx buffer\n"); 1788 return 1; /* XXX */ 1789 } 1790 } 1791 sc->sc_rx_prodidx = 0; 1792 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL; 1793 1794 /* Initialize the TX descriptors and mbufs. */ 1795 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1796 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 1797 VGE_CDTXOFF(0), sizeof(sc->sc_txdescs), 1798 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1799 for (i = 0; i < VGE_NTXDESC; i++) 1800 sc->sc_txsoft[i].txs_mbuf = NULL; 1801 1802 sc->sc_tx_prodidx = 0; 1803 sc->sc_tx_considx = 0; 1804 sc->sc_tx_free = VGE_NTXDESC; 1805 1806 /* Set our station address */ 1807 for (i = 0; i < ETHER_ADDR_LEN; i++) 1808 CSR_WRITE_1(sc, VGE_PAR0 + i, sc->sc_eaddr[i]); 1809 1810 /* 1811 * Set receive FIFO threshold. Also allow transmission and 1812 * reception of VLAN tagged frames. 1813 */ 1814 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 1815 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 1816 1817 /* Set DMA burst length */ 1818 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1819 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1820 1821 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1822 1823 /* Set collision backoff algorithm */ 1824 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1825 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1826 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1827 1828 /* Disable LPSEL field in priority resolution */ 1829 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1830 1831 /* 1832 * Load the addresses of the DMA queues into the chip. 1833 * Note that we only use one transmit queue. 1834 */ 1835 1836 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, VGE_ADDR_LO(VGE_CDTXADDR(sc, 0))); 1837 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_NTXDESC - 1); 1838 1839 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, VGE_ADDR_LO(VGE_CDRXADDR(sc, 0))); 1840 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_NRXDESC - 1); 1841 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_NRXDESC); 1842 1843 /* Enable and wake up the RX descriptor queue */ 1844 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1845 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1846 1847 /* Enable the TX descriptor queue */ 1848 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 1849 1850 /* Set up the receive filter -- allow large frames for VLANs. */ 1851 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 1852 1853 /* If we want promiscuous mode, set the allframes bit. */ 1854 if (ifp->if_flags & IFF_PROMISC) { 1855 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 1856 } 1857 1858 /* Set capture broadcast bit to capture broadcast frames. */ 1859 if (ifp->if_flags & IFF_BROADCAST) { 1860 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 1861 } 1862 1863 /* Set multicast bit to capture multicast frames. */ 1864 if (ifp->if_flags & IFF_MULTICAST) { 1865 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 1866 } 1867 1868 /* Init the cam filter. */ 1869 vge_cam_clear(sc); 1870 1871 /* Init the multicast filter. */ 1872 vge_setmulti(sc); 1873 1874 /* Enable flow control */ 1875 1876 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 1877 1878 /* Enable jumbo frame reception (if desired) */ 1879 1880 /* Start the MAC. */ 1881 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 1882 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 1883 CSR_WRITE_1(sc, VGE_CRS0, 1884 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 1885 1886 /* 1887 * Configure one-shot timer for microsecond 1888 * resulution and load it for 500 usecs. 1889 */ 1890 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 1891 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 1892 1893 /* 1894 * Configure interrupt moderation for receive. Enable 1895 * the holdoff counter and load it, and set the RX 1896 * suppression count to the number of descriptors we 1897 * want to allow before triggering an interrupt. 1898 * The holdoff timer is in units of 20 usecs. 1899 */ 1900 1901 #ifdef notyet 1902 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 1903 /* Select the interrupt holdoff timer page. */ 1904 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1905 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 1906 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 1907 1908 /* Enable use of the holdoff timer. */ 1909 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 1910 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 1911 1912 /* Select the RX suppression threshold page. */ 1913 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1914 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 1915 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 1916 1917 /* Restore the page select bits. */ 1918 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1919 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 1920 #endif 1921 1922 #ifdef DEVICE_POLLING 1923 /* 1924 * Disable interrupts if we are polling. 1925 */ 1926 if (ifp->if_flags & IFF_POLLING) { 1927 CSR_WRITE_4(sc, VGE_IMR, 0); 1928 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1929 } else /* otherwise ... */ 1930 #endif /* DEVICE_POLLING */ 1931 { 1932 /* 1933 * Enable interrupts. 1934 */ 1935 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1936 CSR_WRITE_4(sc, VGE_ISR, 0); 1937 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1938 } 1939 1940 if ((rc = ether_mediachange(ifp)) != 0) 1941 goto out; 1942 1943 ifp->if_flags |= IFF_RUNNING; 1944 ifp->if_flags &= ~IFF_OACTIVE; 1945 1946 sc->sc_if_flags = 0; 1947 sc->sc_link = 0; 1948 1949 callout_schedule(&sc->sc_timeout, hz); 1950 1951 out: 1952 return rc; 1953 } 1954 1955 static void 1956 vge_miibus_statchg(struct device *self) 1957 { 1958 struct vge_softc *sc; 1959 struct mii_data *mii; 1960 struct ifmedia_entry *ife; 1961 1962 sc = (void *)self; 1963 mii = &sc->sc_mii; 1964 ife = mii->mii_media.ifm_cur; 1965 /* 1966 * If the user manually selects a media mode, we need to turn 1967 * on the forced MAC mode bit in the DIAGCTL register. If the 1968 * user happens to choose a full duplex mode, we also need to 1969 * set the 'force full duplex' bit. This applies only to 1970 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 1971 * mode is disabled, and in 1000baseT mode, full duplex is 1972 * always implied, so we turn on the forced mode bit but leave 1973 * the FDX bit cleared. 1974 */ 1975 1976 switch (IFM_SUBTYPE(ife->ifm_media)) { 1977 case IFM_AUTO: 1978 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1979 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1980 break; 1981 case IFM_1000_T: 1982 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1983 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1984 break; 1985 case IFM_100_TX: 1986 case IFM_10_T: 1987 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1988 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 1989 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1990 } else { 1991 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1992 } 1993 break; 1994 default: 1995 aprint_error_dev(&sc->sc_dev, "unknown media type: %x\n", 1996 IFM_SUBTYPE(ife->ifm_media)); 1997 break; 1998 } 1999 } 2000 2001 static int 2002 vge_ifflags_cb(struct ethercom *ec) 2003 { 2004 struct ifnet *ifp = &ec->ec_if; 2005 struct vge_softc *sc = ifp->if_softc; 2006 int change = ifp->if_flags ^ sc->sc_if_flags; 2007 2008 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 2009 return ENETRESET; 2010 else if ((change & IFF_PROMISC) == 0) 2011 return 0; 2012 2013 if ((ifp->if_flags & IFF_PROMISC) == 0) 2014 CSR_CLRBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 2015 else 2016 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 2017 vge_setmulti(sc); 2018 return 0; 2019 } 2020 2021 static int 2022 vge_ioctl(struct ifnet *ifp, u_long command, void *data) 2023 { 2024 struct vge_softc *sc; 2025 struct ifreq *ifr; 2026 int s, error; 2027 2028 sc = ifp->if_softc; 2029 ifr = (struct ifreq *)data; 2030 error = 0; 2031 2032 s = splnet(); 2033 2034 if ((error = ether_ioctl(ifp, command, data)) == ENETRESET) { 2035 error = 0; 2036 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 2037 ; 2038 else if (ifp->if_flags & IFF_RUNNING) { 2039 /* 2040 * Multicast list has changed; set the hardware filter 2041 * accordingly. 2042 */ 2043 vge_setmulti(sc); 2044 } 2045 } 2046 sc->sc_if_flags = ifp->if_flags; 2047 2048 splx(s); 2049 return error; 2050 } 2051 2052 static void 2053 vge_watchdog(struct ifnet *ifp) 2054 { 2055 struct vge_softc *sc; 2056 int s; 2057 2058 sc = ifp->if_softc; 2059 s = splnet(); 2060 aprint_error_dev(&sc->sc_dev, "watchdog timeout\n"); 2061 ifp->if_oerrors++; 2062 2063 vge_txeof(sc); 2064 vge_rxeof(sc); 2065 2066 vge_init(ifp); 2067 2068 splx(s); 2069 } 2070 2071 /* 2072 * Stop the adapter and free any mbufs allocated to the 2073 * RX and TX lists. 2074 */ 2075 static void 2076 vge_stop(struct ifnet *ifp, int disable) 2077 { 2078 struct vge_softc *sc = ifp->if_softc; 2079 struct vge_txsoft *txs; 2080 struct vge_rxsoft *rxs; 2081 int i, s; 2082 2083 s = splnet(); 2084 ifp->if_timer = 0; 2085 2086 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2087 #ifdef DEVICE_POLLING 2088 ether_poll_deregister(ifp); 2089 #endif /* DEVICE_POLLING */ 2090 2091 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2092 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2093 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2094 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2095 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2096 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2097 2098 if (sc->sc_rx_mhead != NULL) { 2099 m_freem(sc->sc_rx_mhead); 2100 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL; 2101 } 2102 2103 /* Free the TX list buffers. */ 2104 2105 for (i = 0; i < VGE_NTXDESC; i++) { 2106 txs = &sc->sc_txsoft[i]; 2107 if (txs->txs_mbuf != NULL) { 2108 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2109 m_freem(txs->txs_mbuf); 2110 txs->txs_mbuf = NULL; 2111 } 2112 } 2113 2114 /* Free the RX list buffers. */ 2115 2116 for (i = 0; i < VGE_NRXDESC; i++) { 2117 rxs = &sc->sc_rxsoft[i]; 2118 if (rxs->rxs_mbuf != NULL) { 2119 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2120 m_freem(rxs->rxs_mbuf); 2121 rxs->rxs_mbuf = NULL; 2122 } 2123 } 2124 2125 splx(s); 2126 } 2127 2128 #if VGE_POWER_MANAGEMENT 2129 /* 2130 * Device suspend routine. Stop the interface and save some PCI 2131 * settings in case the BIOS doesn't restore them properly on 2132 * resume. 2133 */ 2134 static int 2135 vge_suspend(struct device *dev) 2136 { 2137 struct vge_softc *sc; 2138 int i; 2139 2140 sc = device_get_softc(dev); 2141 2142 vge_stop(sc); 2143 2144 for (i = 0; i < 5; i++) 2145 sc->sc_saved_maps[i] = 2146 pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2147 sc->sc_saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2148 sc->sc_saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2149 sc->sc_saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2150 sc->sc_saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2151 2152 sc->suspended = 1; 2153 2154 return 0; 2155 } 2156 2157 /* 2158 * Device resume routine. Restore some PCI settings in case the BIOS 2159 * doesn't, re-enable busmastering, and restart the interface if 2160 * appropriate. 2161 */ 2162 static int 2163 vge_resume(struct device *dev) 2164 { 2165 struct vge_softc *sc; 2166 struct ifnet *ifp; 2167 int i; 2168 2169 sc = (void *)dev; 2170 ifp = &sc->sc_ethercom.ec_if; 2171 2172 /* better way to do this? */ 2173 for (i = 0; i < 5; i++) 2174 pci_write_config(dev, PCIR_MAPS + i * 4, 2175 sc->sc_saved_maps[i], 4); 2176 pci_write_config(dev, PCIR_BIOS, sc->sc_saved_biosaddr, 4); 2177 pci_write_config(dev, PCIR_INTLINE, sc->sc_saved_intline, 1); 2178 pci_write_config(dev, PCIR_CACHELNSZ, sc->sc_saved_cachelnsz, 1); 2179 pci_write_config(dev, PCIR_LATTIMER, sc->sc_saved_lattimer, 1); 2180 2181 /* reenable busmastering */ 2182 pci_enable_busmaster(dev); 2183 pci_enable_io(dev, SYS_RES_MEMORY); 2184 2185 /* reinitialize interface if necessary */ 2186 if (ifp->if_flags & IFF_UP) 2187 vge_init(sc); 2188 2189 sc->suspended = 0; 2190 2191 return 0; 2192 } 2193 #endif 2194 2195 /* 2196 * Stop all chip I/O so that the kernel's probe routines don't 2197 * get confused by errant DMAs when rebooting. 2198 */ 2199 static void 2200 vge_shutdown(void *arg) 2201 { 2202 struct vge_softc *sc; 2203 2204 sc = arg; 2205 vge_stop(&sc->sc_ethercom.ec_if, 1); 2206 } 2207