1 /* $NetBSD: if_vge.c,v 1.49 2009/09/07 12:44:29 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD: src/sys/dev/vge/if_vge.c,v 1.5 2005/02/07 19:39:29 glebius Exp 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: if_vge.c,v 1.49 2009/09/07 12:44:29 tsutsui Exp $"); 39 40 /* 41 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 42 * 43 * Written by Bill Paul <wpaul@windriver.com> 44 * Senior Networking Software Engineer 45 * Wind River Systems 46 */ 47 48 /* 49 * The VIA Networking VT6122 is a 32bit, 33/66 MHz PCI device that 50 * combines a tri-speed ethernet MAC and PHY, with the following 51 * features: 52 * 53 * o Jumbo frame support up to 16K 54 * o Transmit and receive flow control 55 * o IPv4 checksum offload 56 * o VLAN tag insertion and stripping 57 * o TCP large send 58 * o 64-bit multicast hash table filter 59 * o 64 entry CAM filter 60 * o 16K RX FIFO and 48K TX FIFO memory 61 * o Interrupt moderation 62 * 63 * The VT6122 supports up to four transmit DMA queues. The descriptors 64 * in the transmit ring can address up to 7 data fragments; frames which 65 * span more than 7 data buffers must be coalesced, but in general the 66 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 67 * long. The receive descriptors address only a single buffer. 68 * 69 * There are two peculiar design issues with the VT6122. One is that 70 * receive data buffers must be aligned on a 32-bit boundary. This is 71 * not a problem where the VT6122 is used as a LOM device in x86-based 72 * systems, but on architectures that generate unaligned access traps, we 73 * have to do some copying. 74 * 75 * The other issue has to do with the way 64-bit addresses are handled. 76 * The DMA descriptors only allow you to specify 48 bits of addressing 77 * information. The remaining 16 bits are specified using one of the 78 * I/O registers. If you only have a 32-bit system, then this isn't 79 * an issue, but if you have a 64-bit system and more than 4GB of 80 * memory, you must have to make sure your network data buffers reside 81 * in the same 48-bit 'segment.' 82 * 83 * Special thanks to Ryan Fu at VIA Networking for providing documentation 84 * and sample NICs for testing. 85 */ 86 87 #include "bpfilter.h" 88 89 #include <sys/param.h> 90 #include <sys/endian.h> 91 #include <sys/systm.h> 92 #include <sys/device.h> 93 #include <sys/sockio.h> 94 #include <sys/mbuf.h> 95 #include <sys/malloc.h> 96 #include <sys/kernel.h> 97 #include <sys/socket.h> 98 99 #include <net/if.h> 100 #include <net/if_arp.h> 101 #include <net/if_ether.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 105 #include <net/bpf.h> 106 107 #include <sys/bus.h> 108 109 #include <dev/mii/mii.h> 110 #include <dev/mii/miivar.h> 111 112 #include <dev/pci/pcireg.h> 113 #include <dev/pci/pcivar.h> 114 #include <dev/pci/pcidevs.h> 115 116 #include <dev/pci/if_vgereg.h> 117 118 #define VGE_IFQ_MAXLEN 64 119 120 #define VGE_RING_ALIGN 256 121 122 #define VGE_NTXDESC 256 123 #define VGE_NTXDESC_MASK (VGE_NTXDESC - 1) 124 #define VGE_NEXT_TXDESC(x) ((x + 1) & VGE_NTXDESC_MASK) 125 #define VGE_PREV_TXDESC(x) ((x - 1) & VGE_NTXDESC_MASK) 126 127 #define VGE_NRXDESC 256 /* Must be a multiple of 4!! */ 128 #define VGE_NRXDESC_MASK (VGE_NRXDESC - 1) 129 #define VGE_NEXT_RXDESC(x) ((x + 1) & VGE_NRXDESC_MASK) 130 #define VGE_PREV_RXDESC(x) ((x - 1) & VGE_NRXDESC_MASK) 131 132 #define VGE_ADDR_LO(y) ((uint64_t)(y) & 0xFFFFFFFF) 133 #define VGE_ADDR_HI(y) ((uint64_t)(y) >> 32) 134 #define VGE_BUFLEN(y) ((y) & 0x7FFF) 135 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 136 137 #define VGE_POWER_MANAGEMENT 0 /* disabled for now */ 138 139 /* 140 * Mbuf adjust factor to force 32-bit alignment of IP header. 141 * Drivers should pad ETHER_ALIGN bytes when setting up a 142 * RX mbuf so the upper layers get the IP header properly aligned 143 * past the 14-byte Ethernet header. 144 * 145 * See also comment in vge_encap(). 146 */ 147 #define ETHER_ALIGN 2 148 149 #ifdef __NO_STRICT_ALIGNMENT 150 #define VGE_RX_BUFSIZE MCLBYTES 151 #else 152 #define VGE_RX_PAD sizeof(uint32_t) 153 #define VGE_RX_BUFSIZE (MCLBYTES - VGE_RX_PAD) 154 #endif 155 156 /* 157 * Control structures are DMA'd to the vge chip. We allocate them in 158 * a single clump that maps to a single DMA segment to make several things 159 * easier. 160 */ 161 struct vge_control_data { 162 /* TX descriptors */ 163 struct vge_txdesc vcd_txdescs[VGE_NTXDESC]; 164 /* RX descriptors */ 165 struct vge_rxdesc vcd_rxdescs[VGE_NRXDESC]; 166 /* dummy data for TX padding */ 167 uint8_t vcd_pad[ETHER_PAD_LEN]; 168 }; 169 170 #define VGE_CDOFF(x) offsetof(struct vge_control_data, x) 171 #define VGE_CDTXOFF(x) VGE_CDOFF(vcd_txdescs[(x)]) 172 #define VGE_CDRXOFF(x) VGE_CDOFF(vcd_rxdescs[(x)]) 173 #define VGE_CDPADOFF() VGE_CDOFF(vcd_pad[0]) 174 175 /* 176 * Software state for TX jobs. 177 */ 178 struct vge_txsoft { 179 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 180 bus_dmamap_t txs_dmamap; /* our DMA map */ 181 }; 182 183 /* 184 * Software state for RX jobs. 185 */ 186 struct vge_rxsoft { 187 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 188 bus_dmamap_t rxs_dmamap; /* our DMA map */ 189 }; 190 191 192 struct vge_softc { 193 device_t sc_dev; 194 195 bus_space_tag_t sc_bst; /* bus space tag */ 196 bus_space_handle_t sc_bsh; /* bus space handle */ 197 bus_dma_tag_t sc_dmat; 198 199 struct ethercom sc_ethercom; /* interface info */ 200 uint8_t sc_eaddr[ETHER_ADDR_LEN]; 201 202 void *sc_intrhand; 203 struct mii_data sc_mii; 204 uint8_t sc_type; 205 int sc_if_flags; 206 int sc_link; 207 int sc_camidx; 208 callout_t sc_timeout; 209 210 bus_dmamap_t sc_cddmamap; 211 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 212 213 struct vge_txsoft sc_txsoft[VGE_NTXDESC]; 214 struct vge_rxsoft sc_rxsoft[VGE_NRXDESC]; 215 struct vge_control_data *sc_control_data; 216 #define sc_txdescs sc_control_data->vcd_txdescs 217 #define sc_rxdescs sc_control_data->vcd_rxdescs 218 219 int sc_tx_prodidx; 220 int sc_tx_considx; 221 int sc_tx_free; 222 223 struct mbuf *sc_rx_mhead; 224 struct mbuf *sc_rx_mtail; 225 int sc_rx_prodidx; 226 int sc_rx_consumed; 227 228 int sc_suspended; /* 0 = normal 1 = suspended */ 229 uint32_t sc_saved_maps[5]; /* pci data */ 230 uint32_t sc_saved_biosaddr; 231 uint8_t sc_saved_intline; 232 uint8_t sc_saved_cachelnsz; 233 uint8_t sc_saved_lattimer; 234 }; 235 236 #define VGE_CDTXADDR(sc, x) ((sc)->sc_cddma + VGE_CDTXOFF(x)) 237 #define VGE_CDRXADDR(sc, x) ((sc)->sc_cddma + VGE_CDRXOFF(x)) 238 #define VGE_CDPADADDR(sc) ((sc)->sc_cddma + VGE_CDPADOFF()) 239 240 #define VGE_TXDESCSYNC(sc, idx, ops) \ 241 bus_dmamap_sync((sc)->sc_dmat,(sc)->sc_cddmamap, \ 242 VGE_CDTXOFF(idx), \ 243 offsetof(struct vge_txdesc, td_frag[0]), \ 244 (ops)) 245 #define VGE_TXFRAGSYNC(sc, idx, nsegs, ops) \ 246 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 247 VGE_CDTXOFF(idx) + \ 248 offsetof(struct vge_txdesc, td_frag[0]), \ 249 sizeof(struct vge_txfrag) * (nsegs), \ 250 (ops)) 251 #define VGE_RXDESCSYNC(sc, idx, ops) \ 252 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 253 VGE_CDRXOFF(idx), \ 254 sizeof(struct vge_rxdesc), \ 255 (ops)) 256 257 /* 258 * register space access macros 259 */ 260 #define CSR_WRITE_4(sc, reg, val) \ 261 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 262 #define CSR_WRITE_2(sc, reg, val) \ 263 bus_space_write_2((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 264 #define CSR_WRITE_1(sc, reg, val) \ 265 bus_space_write_1((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 266 267 #define CSR_READ_4(sc, reg) \ 268 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 269 #define CSR_READ_2(sc, reg) \ 270 bus_space_read_2((sc)->sc_bst, (sc)->sc_bsh, (reg)) 271 #define CSR_READ_1(sc, reg) \ 272 bus_space_read_1((sc)->sc_bst, (sc)->sc_bsh, (reg)) 273 274 #define CSR_SETBIT_1(sc, reg, x) \ 275 CSR_WRITE_1((sc), (reg), CSR_READ_1((sc), (reg)) | (x)) 276 #define CSR_SETBIT_2(sc, reg, x) \ 277 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (x)) 278 #define CSR_SETBIT_4(sc, reg, x) \ 279 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (x)) 280 281 #define CSR_CLRBIT_1(sc, reg, x) \ 282 CSR_WRITE_1((sc), (reg), CSR_READ_1((sc), (reg)) & ~(x)) 283 #define CSR_CLRBIT_2(sc, reg, x) \ 284 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(x)) 285 #define CSR_CLRBIT_4(sc, reg, x) \ 286 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(x)) 287 288 #define VGE_TIMEOUT 10000 289 290 #define VGE_PCI_LOIO 0x10 291 #define VGE_PCI_LOMEM 0x14 292 293 static inline void vge_set_txaddr(struct vge_txfrag *, bus_addr_t); 294 static inline void vge_set_rxaddr(struct vge_rxdesc *, bus_addr_t); 295 296 static int vge_ifflags_cb(struct ethercom *); 297 298 static int vge_match(device_t, cfdata_t, void *); 299 static void vge_attach(device_t, device_t, void *); 300 301 static int vge_encap(struct vge_softc *, struct mbuf *, int); 302 303 static int vge_allocmem(struct vge_softc *); 304 static int vge_newbuf(struct vge_softc *, int, struct mbuf *); 305 #ifndef __NO_STRICT_ALIGNMENT 306 static inline void vge_fixup_rx(struct mbuf *); 307 #endif 308 static void vge_rxeof(struct vge_softc *); 309 static void vge_txeof(struct vge_softc *); 310 static int vge_intr(void *); 311 static void vge_tick(void *); 312 static void vge_start(struct ifnet *); 313 static int vge_ioctl(struct ifnet *, u_long, void *); 314 static int vge_init(struct ifnet *); 315 static void vge_stop(struct ifnet *, int); 316 static void vge_watchdog(struct ifnet *); 317 #if VGE_POWER_MANAGEMENT 318 static int vge_suspend(device_t); 319 static int vge_resume(device_t); 320 #endif 321 static bool vge_shutdown(device_t, int); 322 323 static uint16_t vge_read_eeprom(struct vge_softc *, int); 324 325 static void vge_miipoll_start(struct vge_softc *); 326 static void vge_miipoll_stop(struct vge_softc *); 327 static int vge_miibus_readreg(device_t, int, int); 328 static void vge_miibus_writereg(device_t, int, int, int); 329 static void vge_miibus_statchg(device_t); 330 331 static void vge_cam_clear(struct vge_softc *); 332 static int vge_cam_set(struct vge_softc *, uint8_t *); 333 static void vge_setmulti(struct vge_softc *); 334 static void vge_reset(struct vge_softc *); 335 336 CFATTACH_DECL_NEW(vge, sizeof(struct vge_softc), 337 vge_match, vge_attach, NULL, NULL); 338 339 static inline void 340 vge_set_txaddr(struct vge_txfrag *f, bus_addr_t daddr) 341 { 342 343 f->tf_addrlo = htole32((uint32_t)daddr); 344 if (sizeof(bus_addr_t) == sizeof(uint64_t)) 345 f->tf_addrhi = htole16(((uint64_t)daddr >> 32) & 0xFFFF); 346 else 347 f->tf_addrhi = 0; 348 } 349 350 static inline void 351 vge_set_rxaddr(struct vge_rxdesc *rxd, bus_addr_t daddr) 352 { 353 354 rxd->rd_addrlo = htole32((uint32_t)daddr); 355 if (sizeof(bus_addr_t) == sizeof(uint64_t)) 356 rxd->rd_addrhi = htole16(((uint64_t)daddr >> 32) & 0xFFFF); 357 else 358 rxd->rd_addrhi = 0; 359 } 360 361 /* 362 * Defragment mbuf chain contents to be as linear as possible. 363 * Returns new mbuf chain on success, NULL on failure. Old mbuf 364 * chain is always freed. 365 * XXX temporary until there would be generic function doing this. 366 */ 367 #define m_defrag vge_m_defrag 368 struct mbuf * vge_m_defrag(struct mbuf *, int); 369 370 struct mbuf * 371 vge_m_defrag(struct mbuf *mold, int flags) 372 { 373 struct mbuf *m0, *mn, *n; 374 size_t sz = mold->m_pkthdr.len; 375 376 #ifdef DIAGNOSTIC 377 if ((mold->m_flags & M_PKTHDR) == 0) 378 panic("m_defrag: not a mbuf chain header"); 379 #endif 380 381 MGETHDR(m0, flags, MT_DATA); 382 if (m0 == NULL) 383 return NULL; 384 m0->m_pkthdr.len = mold->m_pkthdr.len; 385 mn = m0; 386 387 do { 388 if (sz > MHLEN) { 389 MCLGET(mn, M_DONTWAIT); 390 if ((mn->m_flags & M_EXT) == 0) { 391 m_freem(m0); 392 return NULL; 393 } 394 } 395 396 mn->m_len = MIN(sz, MCLBYTES); 397 398 m_copydata(mold, mold->m_pkthdr.len - sz, mn->m_len, 399 mtod(mn, void *)); 400 401 sz -= mn->m_len; 402 403 if (sz > 0) { 404 /* need more mbufs */ 405 MGET(n, M_NOWAIT, MT_DATA); 406 if (n == NULL) { 407 m_freem(m0); 408 return NULL; 409 } 410 411 mn->m_next = n; 412 mn = n; 413 } 414 } while (sz > 0); 415 416 return m0; 417 } 418 419 /* 420 * Read a word of data stored in the EEPROM at address 'addr.' 421 */ 422 static uint16_t 423 vge_read_eeprom(struct vge_softc *sc, int addr) 424 { 425 int i; 426 uint16_t word = 0; 427 428 /* 429 * Enter EEPROM embedded programming mode. In order to 430 * access the EEPROM at all, we first have to set the 431 * EELOAD bit in the CHIPCFG2 register. 432 */ 433 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 434 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 435 436 /* Select the address of the word we want to read */ 437 CSR_WRITE_1(sc, VGE_EEADDR, addr); 438 439 /* Issue read command */ 440 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 441 442 /* Wait for the done bit to be set. */ 443 for (i = 0; i < VGE_TIMEOUT; i++) { 444 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 445 break; 446 } 447 448 if (i == VGE_TIMEOUT) { 449 printf("%s: EEPROM read timed out\n", device_xname(sc->sc_dev)); 450 return 0; 451 } 452 453 /* Read the result */ 454 word = CSR_READ_2(sc, VGE_EERDDAT); 455 456 /* Turn off EEPROM access mode. */ 457 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 458 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 459 460 return word; 461 } 462 463 static void 464 vge_miipoll_stop(struct vge_softc *sc) 465 { 466 int i; 467 468 CSR_WRITE_1(sc, VGE_MIICMD, 0); 469 470 for (i = 0; i < VGE_TIMEOUT; i++) { 471 DELAY(1); 472 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 473 break; 474 } 475 476 if (i == VGE_TIMEOUT) { 477 printf("%s: failed to idle MII autopoll\n", 478 device_xname(sc->sc_dev)); 479 } 480 } 481 482 static void 483 vge_miipoll_start(struct vge_softc *sc) 484 { 485 int i; 486 487 /* First, make sure we're idle. */ 488 489 CSR_WRITE_1(sc, VGE_MIICMD, 0); 490 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 491 492 for (i = 0; i < VGE_TIMEOUT; i++) { 493 DELAY(1); 494 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 495 break; 496 } 497 498 if (i == VGE_TIMEOUT) { 499 printf("%s: failed to idle MII autopoll\n", 500 device_xname(sc->sc_dev)); 501 return; 502 } 503 504 /* Now enable auto poll mode. */ 505 506 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 507 508 /* And make sure it started. */ 509 510 for (i = 0; i < VGE_TIMEOUT; i++) { 511 DELAY(1); 512 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 513 break; 514 } 515 516 if (i == VGE_TIMEOUT) { 517 printf("%s: failed to start MII autopoll\n", 518 device_xname(sc->sc_dev)); 519 } 520 } 521 522 static int 523 vge_miibus_readreg(device_t dev, int phy, int reg) 524 { 525 struct vge_softc *sc; 526 int i, s; 527 uint16_t rval; 528 529 sc = device_private(dev); 530 rval = 0; 531 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 532 return 0; 533 534 s = splnet(); 535 vge_miipoll_stop(sc); 536 537 /* Specify the register we want to read. */ 538 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 539 540 /* Issue read command. */ 541 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 542 543 /* Wait for the read command bit to self-clear. */ 544 for (i = 0; i < VGE_TIMEOUT; i++) { 545 DELAY(1); 546 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 547 break; 548 } 549 550 if (i == VGE_TIMEOUT) 551 printf("%s: MII read timed out\n", device_xname(sc->sc_dev)); 552 else 553 rval = CSR_READ_2(sc, VGE_MIIDATA); 554 555 vge_miipoll_start(sc); 556 splx(s); 557 558 return rval; 559 } 560 561 static void 562 vge_miibus_writereg(device_t dev, int phy, int reg, int data) 563 { 564 struct vge_softc *sc; 565 int i, s; 566 567 sc = device_private(dev); 568 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 569 return; 570 571 s = splnet(); 572 vge_miipoll_stop(sc); 573 574 /* Specify the register we want to write. */ 575 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 576 577 /* Specify the data we want to write. */ 578 CSR_WRITE_2(sc, VGE_MIIDATA, data); 579 580 /* Issue write command. */ 581 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 582 583 /* Wait for the write command bit to self-clear. */ 584 for (i = 0; i < VGE_TIMEOUT; i++) { 585 DELAY(1); 586 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 587 break; 588 } 589 590 if (i == VGE_TIMEOUT) { 591 printf("%s: MII write timed out\n", device_xname(sc->sc_dev)); 592 } 593 594 vge_miipoll_start(sc); 595 splx(s); 596 } 597 598 static void 599 vge_cam_clear(struct vge_softc *sc) 600 { 601 int i; 602 603 /* 604 * Turn off all the mask bits. This tells the chip 605 * that none of the entries in the CAM filter are valid. 606 * desired entries will be enabled as we fill the filter in. 607 */ 608 609 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 610 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 611 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 612 for (i = 0; i < 8; i++) 613 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 614 615 /* Clear the VLAN filter too. */ 616 617 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 618 for (i = 0; i < 8; i++) 619 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 620 621 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 622 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 623 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 624 625 sc->sc_camidx = 0; 626 } 627 628 static int 629 vge_cam_set(struct vge_softc *sc, uint8_t *addr) 630 { 631 int i, error; 632 633 error = 0; 634 635 if (sc->sc_camidx == VGE_CAM_MAXADDRS) 636 return ENOSPC; 637 638 /* Select the CAM data page. */ 639 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 640 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 641 642 /* Set the filter entry we want to update and enable writing. */ 643 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE | sc->sc_camidx); 644 645 /* Write the address to the CAM registers */ 646 for (i = 0; i < ETHER_ADDR_LEN; i++) 647 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 648 649 /* Issue a write command. */ 650 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 651 652 /* Wake for it to clear. */ 653 for (i = 0; i < VGE_TIMEOUT; i++) { 654 DELAY(1); 655 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 656 break; 657 } 658 659 if (i == VGE_TIMEOUT) { 660 printf("%s: setting CAM filter failed\n", 661 device_xname(sc->sc_dev)); 662 error = EIO; 663 goto fail; 664 } 665 666 /* Select the CAM mask page. */ 667 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 668 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 669 670 /* Set the mask bit that enables this filter. */ 671 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->sc_camidx / 8), 672 1 << (sc->sc_camidx & 7)); 673 674 sc->sc_camidx++; 675 676 fail: 677 /* Turn off access to CAM. */ 678 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 679 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 680 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 681 682 return error; 683 } 684 685 /* 686 * Program the multicast filter. We use the 64-entry CAM filter 687 * for perfect filtering. If there's more than 64 multicast addresses, 688 * we use the hash filter instead. 689 */ 690 static void 691 vge_setmulti(struct vge_softc *sc) 692 { 693 struct ifnet *ifp; 694 int error; 695 uint32_t h, hashes[2] = { 0, 0 }; 696 struct ether_multi *enm; 697 struct ether_multistep step; 698 699 error = 0; 700 ifp = &sc->sc_ethercom.ec_if; 701 702 /* First, zot all the multicast entries. */ 703 vge_cam_clear(sc); 704 CSR_WRITE_4(sc, VGE_MAR0, 0); 705 CSR_WRITE_4(sc, VGE_MAR1, 0); 706 ifp->if_flags &= ~IFF_ALLMULTI; 707 708 /* 709 * If the user wants allmulti or promisc mode, enable reception 710 * of all multicast frames. 711 */ 712 if (ifp->if_flags & IFF_PROMISC) { 713 allmulti: 714 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 715 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 716 ifp->if_flags |= IFF_ALLMULTI; 717 return; 718 } 719 720 /* Now program new ones */ 721 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 722 while (enm != NULL) { 723 /* 724 * If multicast range, fall back to ALLMULTI. 725 */ 726 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 727 ETHER_ADDR_LEN) != 0) 728 goto allmulti; 729 730 error = vge_cam_set(sc, enm->enm_addrlo); 731 if (error) 732 break; 733 734 ETHER_NEXT_MULTI(step, enm); 735 } 736 737 /* If there were too many addresses, use the hash filter. */ 738 if (error) { 739 vge_cam_clear(sc); 740 741 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 742 while (enm != NULL) { 743 /* 744 * If multicast range, fall back to ALLMULTI. 745 */ 746 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 747 ETHER_ADDR_LEN) != 0) 748 goto allmulti; 749 750 h = ether_crc32_be(enm->enm_addrlo, 751 ETHER_ADDR_LEN) >> 26; 752 hashes[h >> 5] |= 1 << (h & 0x1f); 753 754 ETHER_NEXT_MULTI(step, enm); 755 } 756 757 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 758 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 759 } 760 } 761 762 static void 763 vge_reset(struct vge_softc *sc) 764 { 765 int i; 766 767 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 768 769 for (i = 0; i < VGE_TIMEOUT; i++) { 770 DELAY(5); 771 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 772 break; 773 } 774 775 if (i == VGE_TIMEOUT) { 776 printf("%s: soft reset timed out", device_xname(sc->sc_dev)); 777 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 778 DELAY(2000); 779 } 780 781 DELAY(5000); 782 783 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 784 785 for (i = 0; i < VGE_TIMEOUT; i++) { 786 DELAY(5); 787 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 788 break; 789 } 790 791 if (i == VGE_TIMEOUT) { 792 printf("%s: EEPROM reload timed out\n", 793 device_xname(sc->sc_dev)); 794 return; 795 } 796 797 /* 798 * On some machine, the first read data from EEPROM could be 799 * messed up, so read one dummy data here to avoid the mess. 800 */ 801 (void)vge_read_eeprom(sc, 0); 802 803 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 804 } 805 806 /* 807 * Probe for a VIA gigabit chip. Check the PCI vendor and device 808 * IDs against our list and return a device name if we find a match. 809 */ 810 static int 811 vge_match(device_t parent, cfdata_t match, void *aux) 812 { 813 struct pci_attach_args *pa = aux; 814 815 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH 816 && PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_VIATECH_VT612X) 817 return 1; 818 819 return 0; 820 } 821 822 static int 823 vge_allocmem(struct vge_softc *sc) 824 { 825 int error; 826 int nseg; 827 int i; 828 bus_dma_segment_t seg; 829 830 /* 831 * Allocate memory for control data. 832 */ 833 834 error = bus_dmamem_alloc(sc->sc_dmat, sizeof(struct vge_control_data), 835 VGE_RING_ALIGN, 0, &seg, 1, &nseg, BUS_DMA_NOWAIT); 836 if (error) { 837 aprint_error_dev(sc->sc_dev, 838 "could not allocate control data dma memory\n"); 839 goto fail_1; 840 } 841 842 /* Map the memory to kernel VA space */ 843 844 error = bus_dmamem_map(sc->sc_dmat, &seg, nseg, 845 sizeof(struct vge_control_data), (void **)&sc->sc_control_data, 846 BUS_DMA_NOWAIT); 847 if (error) { 848 aprint_error_dev(sc->sc_dev, 849 "could not map control data dma memory\n"); 850 goto fail_2; 851 } 852 memset(sc->sc_control_data, 0, sizeof(struct vge_control_data)); 853 854 /* 855 * Create map for control data. 856 */ 857 error = bus_dmamap_create(sc->sc_dmat, 858 sizeof(struct vge_control_data), 1, 859 sizeof(struct vge_control_data), 0, BUS_DMA_NOWAIT, 860 &sc->sc_cddmamap); 861 if (error) { 862 aprint_error_dev(sc->sc_dev, 863 "could not create control data dmamap\n"); 864 goto fail_3; 865 } 866 867 /* Load the map for the control data. */ 868 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 869 sc->sc_control_data, sizeof(struct vge_control_data), NULL, 870 BUS_DMA_NOWAIT); 871 if (error) { 872 aprint_error_dev(sc->sc_dev, 873 "could not load control data dma memory\n"); 874 goto fail_4; 875 } 876 877 /* Create DMA maps for TX buffers */ 878 879 for (i = 0; i < VGE_NTXDESC; i++) { 880 error = bus_dmamap_create(sc->sc_dmat, VGE_TX_MAXLEN, 881 VGE_TX_FRAGS, VGE_TX_MAXLEN, 0, BUS_DMA_NOWAIT, 882 &sc->sc_txsoft[i].txs_dmamap); 883 if (error) { 884 aprint_error_dev(sc->sc_dev, 885 "can't create DMA map for TX descs\n"); 886 goto fail_5; 887 } 888 } 889 890 /* Create DMA maps for RX buffers */ 891 892 for (i = 0; i < VGE_NRXDESC; i++) { 893 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 894 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 895 &sc->sc_rxsoft[i].rxs_dmamap); 896 if (error) { 897 aprint_error_dev(sc->sc_dev, 898 "can't create DMA map for RX descs\n"); 899 goto fail_6; 900 } 901 sc->sc_rxsoft[i].rxs_mbuf = NULL; 902 } 903 904 return 0; 905 906 fail_6: 907 for (i = 0; i < VGE_NRXDESC; i++) { 908 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 909 bus_dmamap_destroy(sc->sc_dmat, 910 sc->sc_rxsoft[i].rxs_dmamap); 911 } 912 fail_5: 913 for (i = 0; i < VGE_NTXDESC; i++) { 914 if (sc->sc_txsoft[i].txs_dmamap != NULL) 915 bus_dmamap_destroy(sc->sc_dmat, 916 sc->sc_txsoft[i].txs_dmamap); 917 } 918 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 919 fail_4: 920 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 921 fail_3: 922 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 923 sizeof(struct vge_control_data)); 924 fail_2: 925 bus_dmamem_free(sc->sc_dmat, &seg, nseg); 926 fail_1: 927 return ENOMEM; 928 } 929 930 /* 931 * Attach the interface. Allocate softc structures, do ifmedia 932 * setup and ethernet/BPF attach. 933 */ 934 static void 935 vge_attach(device_t parent, device_t self, void *aux) 936 { 937 uint8_t *eaddr; 938 struct vge_softc *sc = device_private(self); 939 struct ifnet *ifp; 940 struct pci_attach_args *pa = aux; 941 pci_chipset_tag_t pc = pa->pa_pc; 942 const char *intrstr; 943 pci_intr_handle_t ih; 944 uint16_t val; 945 946 sc->sc_dev = self; 947 948 aprint_normal(": VIA VT612X Gigabit Ethernet (rev. %#x)\n", 949 PCI_REVISION(pa->pa_class)); 950 951 /* Make sure bus-mastering is enabled */ 952 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 953 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 954 PCI_COMMAND_MASTER_ENABLE); 955 956 /* 957 * Map control/status registers. 958 */ 959 if (pci_mapreg_map(pa, VGE_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 960 &sc->sc_bst, &sc->sc_bsh, NULL, NULL) != 0) { 961 aprint_error_dev(self, "couldn't map memory\n"); 962 return; 963 } 964 965 /* 966 * Map and establish our interrupt. 967 */ 968 if (pci_intr_map(pa, &ih)) { 969 aprint_error_dev(self, "unable to map interrupt\n"); 970 return; 971 } 972 intrstr = pci_intr_string(pc, ih); 973 sc->sc_intrhand = pci_intr_establish(pc, ih, IPL_NET, vge_intr, sc); 974 if (sc->sc_intrhand == NULL) { 975 aprint_error_dev(self, "unable to establish interrupt"); 976 if (intrstr != NULL) 977 aprint_error(" at %s", intrstr); 978 aprint_error("\n"); 979 return; 980 } 981 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 982 983 /* Reset the adapter. */ 984 vge_reset(sc); 985 986 /* 987 * Get station address from the EEPROM. 988 */ 989 eaddr = sc->sc_eaddr; 990 val = vge_read_eeprom(sc, VGE_EE_EADDR + 0); 991 eaddr[0] = val & 0xff; 992 eaddr[1] = val >> 8; 993 val = vge_read_eeprom(sc, VGE_EE_EADDR + 1); 994 eaddr[2] = val & 0xff; 995 eaddr[3] = val >> 8; 996 val = vge_read_eeprom(sc, VGE_EE_EADDR + 2); 997 eaddr[4] = val & 0xff; 998 eaddr[5] = val >> 8; 999 1000 aprint_normal_dev(self, "Ethernet address: %s\n", 1001 ether_sprintf(eaddr)); 1002 1003 /* 1004 * Use the 32bit tag. Hardware supports 48bit physical addresses, 1005 * but we don't use that for now. 1006 */ 1007 sc->sc_dmat = pa->pa_dmat; 1008 1009 if (vge_allocmem(sc) != 0) 1010 return; 1011 1012 ifp = &sc->sc_ethercom.ec_if; 1013 ifp->if_softc = sc; 1014 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 1015 ifp->if_mtu = ETHERMTU; 1016 ifp->if_baudrate = IF_Gbps(1); 1017 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1018 ifp->if_ioctl = vge_ioctl; 1019 ifp->if_start = vge_start; 1020 ifp->if_init = vge_init; 1021 ifp->if_stop = vge_stop; 1022 1023 /* 1024 * We can support 802.1Q VLAN-sized frames and jumbo 1025 * Ethernet frames. 1026 */ 1027 sc->sc_ethercom.ec_capabilities |= 1028 ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU | 1029 ETHERCAP_VLAN_HWTAGGING; 1030 1031 /* 1032 * We can do IPv4/TCPv4/UDPv4 checksums in hardware. 1033 */ 1034 ifp->if_capabilities |= 1035 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1036 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1037 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1038 1039 #ifdef DEVICE_POLLING 1040 #ifdef IFCAP_POLLING 1041 ifp->if_capabilities |= IFCAP_POLLING; 1042 #endif 1043 #endif 1044 ifp->if_watchdog = vge_watchdog; 1045 IFQ_SET_MAXLEN(&ifp->if_snd, max(VGE_IFQ_MAXLEN, IFQ_MAXLEN)); 1046 IFQ_SET_READY(&ifp->if_snd); 1047 1048 /* 1049 * Initialize our media structures and probe the MII. 1050 */ 1051 sc->sc_mii.mii_ifp = ifp; 1052 sc->sc_mii.mii_readreg = vge_miibus_readreg; 1053 sc->sc_mii.mii_writereg = vge_miibus_writereg; 1054 sc->sc_mii.mii_statchg = vge_miibus_statchg; 1055 1056 sc->sc_ethercom.ec_mii = &sc->sc_mii; 1057 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 1058 ether_mediastatus); 1059 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 1060 MII_OFFSET_ANY, MIIF_DOPAUSE); 1061 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 1062 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 1063 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 1064 } else 1065 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 1066 1067 /* 1068 * Attach the interface. 1069 */ 1070 if_attach(ifp); 1071 ether_ifattach(ifp, eaddr); 1072 ether_set_ifflags_cb(&sc->sc_ethercom, vge_ifflags_cb); 1073 1074 callout_init(&sc->sc_timeout, 0); 1075 callout_setfunc(&sc->sc_timeout, vge_tick, sc); 1076 1077 /* 1078 * Make sure the interface is shutdown during reboot. 1079 */ 1080 if (pmf_device_register1(self, NULL, NULL, vge_shutdown)) 1081 pmf_class_network_register(self, ifp); 1082 else 1083 aprint_error_dev(self, "couldn't establish power handler\n"); 1084 } 1085 1086 static int 1087 vge_newbuf(struct vge_softc *sc, int idx, struct mbuf *m) 1088 { 1089 struct mbuf *m_new; 1090 struct vge_rxdesc *rxd; 1091 struct vge_rxsoft *rxs; 1092 bus_dmamap_t map; 1093 int i; 1094 #ifdef DIAGNOSTIC 1095 uint32_t rd_sts; 1096 #endif 1097 1098 m_new = NULL; 1099 if (m == NULL) { 1100 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1101 if (m_new == NULL) 1102 return ENOBUFS; 1103 1104 MCLGET(m_new, M_DONTWAIT); 1105 if ((m_new->m_flags & M_EXT) == 0) { 1106 m_freem(m_new); 1107 return ENOBUFS; 1108 } 1109 1110 m = m_new; 1111 } else 1112 m->m_data = m->m_ext.ext_buf; 1113 1114 1115 /* 1116 * This is part of an evil trick to deal with non-x86 platforms. 1117 * The VIA chip requires RX buffers to be aligned on 32-bit 1118 * boundaries, but that will hose non-x86 machines. To get around 1119 * this, we leave some empty space at the start of each buffer 1120 * and for non-x86 hosts, we copy the buffer back two bytes 1121 * to achieve word alignment. This is slightly more efficient 1122 * than allocating a new buffer, copying the contents, and 1123 * discarding the old buffer. 1124 */ 1125 m->m_len = m->m_pkthdr.len = VGE_RX_BUFSIZE; 1126 #ifndef __NO_STRICT_ALIGNMENT 1127 m->m_data += VGE_RX_PAD; 1128 #endif 1129 rxs = &sc->sc_rxsoft[idx]; 1130 map = rxs->rxs_dmamap; 1131 1132 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT) != 0) 1133 goto out; 1134 1135 rxd = &sc->sc_rxdescs[idx]; 1136 1137 #ifdef DIAGNOSTIC 1138 /* If this descriptor is still owned by the chip, bail. */ 1139 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1140 rd_sts = le32toh(rxd->rd_sts); 1141 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1142 if (rd_sts & VGE_RDSTS_OWN) { 1143 panic("%s: tried to map busy RX descriptor", 1144 device_xname(sc->sc_dev)); 1145 } 1146 #endif 1147 1148 rxs->rxs_mbuf = m; 1149 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1150 BUS_DMASYNC_PREREAD); 1151 1152 rxd->rd_buflen = 1153 htole16(VGE_BUFLEN(map->dm_segs[0].ds_len) | VGE_RXDESC_I); 1154 vge_set_rxaddr(rxd, map->dm_segs[0].ds_addr); 1155 rxd->rd_sts = 0; 1156 rxd->rd_ctl = 0; 1157 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1158 1159 /* 1160 * Note: the manual fails to document the fact that for 1161 * proper opration, the driver needs to replentish the RX 1162 * DMA ring 4 descriptors at a time (rather than one at a 1163 * time, like most chips). We can allocate the new buffers 1164 * but we should not set the OWN bits until we're ready 1165 * to hand back 4 of them in one shot. 1166 */ 1167 1168 #define VGE_RXCHUNK 4 1169 sc->sc_rx_consumed++; 1170 if (sc->sc_rx_consumed == VGE_RXCHUNK) { 1171 for (i = idx; i != idx - VGE_RXCHUNK; i--) { 1172 KASSERT(i >= 0); 1173 sc->sc_rxdescs[i].rd_sts |= htole32(VGE_RDSTS_OWN); 1174 VGE_RXDESCSYNC(sc, i, 1175 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1176 } 1177 sc->sc_rx_consumed = 0; 1178 } 1179 1180 return 0; 1181 out: 1182 if (m_new != NULL) 1183 m_freem(m_new); 1184 return ENOMEM; 1185 } 1186 1187 #ifndef __NO_STRICT_ALIGNMENT 1188 static inline void 1189 vge_fixup_rx(struct mbuf *m) 1190 { 1191 int i; 1192 uint16_t *src, *dst; 1193 1194 src = mtod(m, uint16_t *); 1195 dst = src - 1; 1196 1197 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1198 *dst++ = *src++; 1199 1200 m->m_data -= ETHER_ALIGN; 1201 } 1202 #endif 1203 1204 /* 1205 * RX handler. We support the reception of jumbo frames that have 1206 * been fragmented across multiple 2K mbuf cluster buffers. 1207 */ 1208 static void 1209 vge_rxeof(struct vge_softc *sc) 1210 { 1211 struct mbuf *m; 1212 struct ifnet *ifp; 1213 int idx, total_len, lim; 1214 struct vge_rxdesc *cur_rxd; 1215 struct vge_rxsoft *rxs; 1216 uint32_t rxstat, rxctl; 1217 1218 ifp = &sc->sc_ethercom.ec_if; 1219 lim = 0; 1220 1221 /* Invalidate the descriptor memory */ 1222 1223 for (idx = sc->sc_rx_prodidx;; idx = VGE_NEXT_RXDESC(idx)) { 1224 cur_rxd = &sc->sc_rxdescs[idx]; 1225 1226 VGE_RXDESCSYNC(sc, idx, 1227 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1228 rxstat = le32toh(cur_rxd->rd_sts); 1229 if ((rxstat & VGE_RDSTS_OWN) != 0) { 1230 VGE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1231 break; 1232 } 1233 1234 rxctl = le32toh(cur_rxd->rd_ctl); 1235 rxs = &sc->sc_rxsoft[idx]; 1236 m = rxs->rxs_mbuf; 1237 total_len = (rxstat & VGE_RDSTS_BUFSIZ) >> 16; 1238 1239 /* Invalidate the RX mbuf and unload its map */ 1240 1241 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 1242 0, rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1243 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1244 1245 /* 1246 * If the 'start of frame' bit is set, this indicates 1247 * either the first fragment in a multi-fragment receive, 1248 * or an intermediate fragment. Either way, we want to 1249 * accumulate the buffers. 1250 */ 1251 if (rxstat & VGE_RXPKT_SOF) { 1252 m->m_len = VGE_RX_BUFSIZE; 1253 if (sc->sc_rx_mhead == NULL) 1254 sc->sc_rx_mhead = sc->sc_rx_mtail = m; 1255 else { 1256 m->m_flags &= ~M_PKTHDR; 1257 sc->sc_rx_mtail->m_next = m; 1258 sc->sc_rx_mtail = m; 1259 } 1260 vge_newbuf(sc, idx, NULL); 1261 continue; 1262 } 1263 1264 /* 1265 * Bad/error frames will have the RXOK bit cleared. 1266 * However, there's one error case we want to allow: 1267 * if a VLAN tagged frame arrives and the chip can't 1268 * match it against the CAM filter, it considers this 1269 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1270 * We don't want to drop the frame though: our VLAN 1271 * filtering is done in software. 1272 */ 1273 if ((rxstat & VGE_RDSTS_RXOK) == 0 && 1274 (rxstat & VGE_RDSTS_VIDM) == 0 && 1275 (rxstat & VGE_RDSTS_CSUMERR) == 0) { 1276 ifp->if_ierrors++; 1277 /* 1278 * If this is part of a multi-fragment packet, 1279 * discard all the pieces. 1280 */ 1281 if (sc->sc_rx_mhead != NULL) { 1282 m_freem(sc->sc_rx_mhead); 1283 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL; 1284 } 1285 vge_newbuf(sc, idx, m); 1286 continue; 1287 } 1288 1289 /* 1290 * If allocating a replacement mbuf fails, 1291 * reload the current one. 1292 */ 1293 1294 if (vge_newbuf(sc, idx, NULL)) { 1295 ifp->if_ierrors++; 1296 if (sc->sc_rx_mhead != NULL) { 1297 m_freem(sc->sc_rx_mhead); 1298 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL; 1299 } 1300 vge_newbuf(sc, idx, m); 1301 continue; 1302 } 1303 1304 if (sc->sc_rx_mhead != NULL) { 1305 m->m_len = total_len % VGE_RX_BUFSIZE; 1306 /* 1307 * Special case: if there's 4 bytes or less 1308 * in this buffer, the mbuf can be discarded: 1309 * the last 4 bytes is the CRC, which we don't 1310 * care about anyway. 1311 */ 1312 if (m->m_len <= ETHER_CRC_LEN) { 1313 sc->sc_rx_mtail->m_len -= 1314 (ETHER_CRC_LEN - m->m_len); 1315 m_freem(m); 1316 } else { 1317 m->m_len -= ETHER_CRC_LEN; 1318 m->m_flags &= ~M_PKTHDR; 1319 sc->sc_rx_mtail->m_next = m; 1320 } 1321 m = sc->sc_rx_mhead; 1322 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL; 1323 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1324 } else 1325 m->m_pkthdr.len = m->m_len = total_len - ETHER_CRC_LEN; 1326 1327 #ifndef __NO_STRICT_ALIGNMENT 1328 vge_fixup_rx(m); 1329 #endif 1330 ifp->if_ipackets++; 1331 m->m_pkthdr.rcvif = ifp; 1332 1333 /* Do RX checksumming if enabled */ 1334 if (ifp->if_csum_flags_rx & M_CSUM_IPv4) { 1335 1336 /* Check IP header checksum */ 1337 if (rxctl & VGE_RDCTL_IPPKT) 1338 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1339 if ((rxctl & VGE_RDCTL_IPCSUMOK) == 0) 1340 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1341 } 1342 1343 if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) { 1344 /* Check UDP checksum */ 1345 if (rxctl & VGE_RDCTL_TCPPKT) 1346 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1347 1348 if ((rxctl & VGE_RDCTL_PROTOCSUMOK) == 0) 1349 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1350 } 1351 1352 if (ifp->if_csum_flags_rx & M_CSUM_UDPv4) { 1353 /* Check UDP checksum */ 1354 if (rxctl & VGE_RDCTL_UDPPKT) 1355 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1356 1357 if ((rxctl & VGE_RDCTL_PROTOCSUMOK) == 0) 1358 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1359 } 1360 1361 if (rxstat & VGE_RDSTS_VTAG) { 1362 /* 1363 * We use bswap16() here because: 1364 * On LE machines, tag is stored in BE as stream data. 1365 * On BE machines, tag is stored in BE as stream data 1366 * but it was already swapped by le32toh() above. 1367 */ 1368 VLAN_INPUT_TAG(ifp, m, 1369 bswap16(rxctl & VGE_RDCTL_VLANID), continue); 1370 } 1371 1372 #if NBPFILTER > 0 1373 /* 1374 * Handle BPF listeners. 1375 */ 1376 if (ifp->if_bpf) 1377 bpf_mtap(ifp->if_bpf, m); 1378 #endif 1379 1380 (*ifp->if_input)(ifp, m); 1381 1382 lim++; 1383 if (lim == VGE_NRXDESC) 1384 break; 1385 } 1386 1387 sc->sc_rx_prodidx = idx; 1388 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1389 } 1390 1391 static void 1392 vge_txeof(struct vge_softc *sc) 1393 { 1394 struct ifnet *ifp; 1395 struct vge_txsoft *txs; 1396 uint32_t txstat; 1397 int idx; 1398 1399 ifp = &sc->sc_ethercom.ec_if; 1400 1401 for (idx = sc->sc_tx_considx; 1402 sc->sc_tx_free < VGE_NTXDESC; 1403 idx = VGE_NEXT_TXDESC(idx), sc->sc_tx_free++) { 1404 VGE_TXDESCSYNC(sc, idx, 1405 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1406 txstat = le32toh(sc->sc_txdescs[idx].td_sts); 1407 VGE_TXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1408 if (txstat & VGE_TDSTS_OWN) { 1409 break; 1410 } 1411 1412 txs = &sc->sc_txsoft[idx]; 1413 m_freem(txs->txs_mbuf); 1414 txs->txs_mbuf = NULL; 1415 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 0, 1416 txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1417 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1418 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1419 ifp->if_collisions++; 1420 if (txstat & VGE_TDSTS_TXERR) 1421 ifp->if_oerrors++; 1422 else 1423 ifp->if_opackets++; 1424 } 1425 1426 sc->sc_tx_considx = idx; 1427 1428 if (sc->sc_tx_free > 0) { 1429 ifp->if_flags &= ~IFF_OACTIVE; 1430 } 1431 1432 /* 1433 * If not all descriptors have been released reaped yet, 1434 * reload the timer so that we will eventually get another 1435 * interrupt that will cause us to re-enter this routine. 1436 * This is done in case the transmitter has gone idle. 1437 */ 1438 if (sc->sc_tx_free < VGE_NTXDESC) 1439 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1440 else 1441 ifp->if_timer = 0; 1442 } 1443 1444 static void 1445 vge_tick(void *arg) 1446 { 1447 struct vge_softc *sc; 1448 struct ifnet *ifp; 1449 struct mii_data *mii; 1450 int s; 1451 1452 sc = arg; 1453 ifp = &sc->sc_ethercom.ec_if; 1454 mii = &sc->sc_mii; 1455 1456 s = splnet(); 1457 1458 callout_schedule(&sc->sc_timeout, hz); 1459 1460 mii_tick(mii); 1461 if (sc->sc_link) { 1462 if ((mii->mii_media_status & IFM_ACTIVE) == 0) 1463 sc->sc_link = 0; 1464 } else { 1465 if (mii->mii_media_status & IFM_ACTIVE && 1466 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1467 sc->sc_link = 1; 1468 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1469 vge_start(ifp); 1470 } 1471 } 1472 1473 splx(s); 1474 } 1475 1476 static int 1477 vge_intr(void *arg) 1478 { 1479 struct vge_softc *sc; 1480 struct ifnet *ifp; 1481 uint32_t status; 1482 int claim; 1483 1484 sc = arg; 1485 claim = 0; 1486 if (sc->sc_suspended) { 1487 return claim; 1488 } 1489 1490 ifp = &sc->sc_ethercom.ec_if; 1491 1492 if ((ifp->if_flags & IFF_UP) == 0) { 1493 return claim; 1494 } 1495 1496 /* Disable interrupts */ 1497 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1498 1499 for (;;) { 1500 1501 status = CSR_READ_4(sc, VGE_ISR); 1502 /* If the card has gone away the read returns 0xffffffff. */ 1503 if (status == 0xFFFFFFFF) 1504 break; 1505 1506 if (status) { 1507 claim = 1; 1508 CSR_WRITE_4(sc, VGE_ISR, status); 1509 } 1510 1511 if ((status & VGE_INTRS) == 0) 1512 break; 1513 1514 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1515 vge_rxeof(sc); 1516 1517 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1518 vge_rxeof(sc); 1519 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1520 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1521 } 1522 1523 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1524 vge_txeof(sc); 1525 1526 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) 1527 vge_init(ifp); 1528 1529 if (status & VGE_ISR_LINKSTS) 1530 vge_tick(sc); 1531 } 1532 1533 /* Re-enable interrupts */ 1534 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1535 1536 if (claim && !IFQ_IS_EMPTY(&ifp->if_snd)) 1537 vge_start(ifp); 1538 1539 return claim; 1540 } 1541 1542 static int 1543 vge_encap(struct vge_softc *sc, struct mbuf *m_head, int idx) 1544 { 1545 struct vge_txsoft *txs; 1546 struct vge_txdesc *txd; 1547 struct vge_txfrag *f; 1548 struct mbuf *m_new; 1549 bus_dmamap_t map; 1550 int m_csumflags, seg, error, flags; 1551 struct m_tag *mtag; 1552 size_t sz; 1553 uint32_t td_sts, td_ctl; 1554 1555 KASSERT(sc->sc_tx_free > 0); 1556 1557 txd = &sc->sc_txdescs[idx]; 1558 1559 #ifdef DIAGNOSTIC 1560 /* If this descriptor is still owned by the chip, bail. */ 1561 VGE_TXDESCSYNC(sc, idx, 1562 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1563 td_sts = le32toh(txd->td_sts); 1564 VGE_TXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1565 if (td_sts & VGE_TDSTS_OWN) { 1566 return ENOBUFS; 1567 } 1568 #endif 1569 1570 /* 1571 * Preserve m_pkthdr.csum_flags here since m_head might be 1572 * updated by m_defrag() 1573 */ 1574 m_csumflags = m_head->m_pkthdr.csum_flags; 1575 1576 txs = &sc->sc_txsoft[idx]; 1577 map = txs->txs_dmamap; 1578 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m_head, BUS_DMA_NOWAIT); 1579 1580 /* If too many segments to map, coalesce */ 1581 if (error == EFBIG || 1582 (m_head->m_pkthdr.len < ETHER_PAD_LEN && 1583 map->dm_nsegs == VGE_TX_FRAGS)) { 1584 m_new = m_defrag(m_head, M_DONTWAIT); 1585 if (m_new == NULL) 1586 return EFBIG; 1587 1588 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, 1589 m_new, BUS_DMA_NOWAIT); 1590 if (error) { 1591 m_freem(m_new); 1592 return error; 1593 } 1594 1595 m_head = m_new; 1596 } else if (error) 1597 return error; 1598 1599 txs->txs_mbuf = m_head; 1600 1601 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1602 BUS_DMASYNC_PREWRITE); 1603 1604 for (seg = 0, f = &txd->td_frag[0]; seg < map->dm_nsegs; seg++, f++) { 1605 f->tf_buflen = htole16(VGE_BUFLEN(map->dm_segs[seg].ds_len)); 1606 vge_set_txaddr(f, map->dm_segs[seg].ds_addr); 1607 } 1608 1609 /* Argh. This chip does not autopad short frames */ 1610 sz = m_head->m_pkthdr.len; 1611 if (sz < ETHER_PAD_LEN) { 1612 f->tf_buflen = htole16(VGE_BUFLEN(ETHER_PAD_LEN - sz)); 1613 vge_set_txaddr(f, VGE_CDPADADDR(sc)); 1614 sz = ETHER_PAD_LEN; 1615 seg++; 1616 } 1617 VGE_TXFRAGSYNC(sc, idx, seg, BUS_DMASYNC_PREWRITE); 1618 1619 /* 1620 * When telling the chip how many segments there are, we 1621 * must use nsegs + 1 instead of just nsegs. Darned if I 1622 * know why. 1623 */ 1624 seg++; 1625 1626 flags = 0; 1627 if (m_csumflags & M_CSUM_IPv4) 1628 flags |= VGE_TDCTL_IPCSUM; 1629 if (m_csumflags & M_CSUM_TCPv4) 1630 flags |= VGE_TDCTL_TCPCSUM; 1631 if (m_csumflags & M_CSUM_UDPv4) 1632 flags |= VGE_TDCTL_UDPCSUM; 1633 td_sts = sz << 16; 1634 td_ctl = flags | (seg << 28) | VGE_TD_LS_NORM; 1635 1636 if (sz > ETHERMTU + ETHER_HDR_LEN) 1637 td_ctl |= VGE_TDCTL_JUMBO; 1638 1639 /* 1640 * Set up hardware VLAN tagging. 1641 */ 1642 mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m_head); 1643 if (mtag != NULL) { 1644 /* 1645 * No need htons() here since vge(4) chip assumes 1646 * that tags are written in little endian and 1647 * we already use htole32() here. 1648 */ 1649 td_ctl |= VLAN_TAG_VALUE(mtag) | VGE_TDCTL_VTAG; 1650 } 1651 txd->td_ctl = htole32(td_ctl); 1652 txd->td_sts = htole32(td_sts); 1653 VGE_TXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1654 1655 txd->td_sts = htole32(VGE_TDSTS_OWN | td_sts); 1656 VGE_TXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1657 1658 sc->sc_tx_free--; 1659 1660 return 0; 1661 } 1662 1663 /* 1664 * Main transmit routine. 1665 */ 1666 1667 static void 1668 vge_start(struct ifnet *ifp) 1669 { 1670 struct vge_softc *sc; 1671 struct vge_txsoft *txs; 1672 struct mbuf *m_head; 1673 int idx, pidx, ofree, error; 1674 1675 sc = ifp->if_softc; 1676 1677 if (!sc->sc_link || 1678 (ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) { 1679 return; 1680 } 1681 1682 m_head = NULL; 1683 idx = sc->sc_tx_prodidx; 1684 pidx = VGE_PREV_TXDESC(idx); 1685 ofree = sc->sc_tx_free; 1686 1687 /* 1688 * Loop through the send queue, setting up transmit descriptors 1689 * until we drain the queue, or use up all available transmit 1690 * descriptors. 1691 */ 1692 for (;;) { 1693 /* Grab a packet off the queue. */ 1694 IFQ_POLL(&ifp->if_snd, m_head); 1695 if (m_head == NULL) 1696 break; 1697 1698 if (sc->sc_tx_free == 0) { 1699 /* 1700 * All slots used, stop for now. 1701 */ 1702 ifp->if_flags |= IFF_OACTIVE; 1703 break; 1704 } 1705 1706 txs = &sc->sc_txsoft[idx]; 1707 KASSERT(txs->txs_mbuf == NULL); 1708 1709 if ((error = vge_encap(sc, m_head, idx))) { 1710 if (error == EFBIG) { 1711 printf("%s: Tx packet consumes too many " 1712 "DMA segments, dropping...\n", 1713 device_xname(sc->sc_dev)); 1714 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1715 m_freem(m_head); 1716 continue; 1717 } 1718 1719 /* 1720 * Short on resources, just stop for now. 1721 */ 1722 if (error == ENOBUFS) 1723 ifp->if_flags |= IFF_OACTIVE; 1724 break; 1725 } 1726 1727 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1728 1729 /* 1730 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1731 */ 1732 1733 sc->sc_txdescs[pidx].td_frag[0].tf_buflen |= 1734 htole16(VGE_TXDESC_Q); 1735 VGE_TXFRAGSYNC(sc, pidx, 1, 1736 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1737 1738 if (txs->txs_mbuf != m_head) { 1739 m_freem(m_head); 1740 m_head = txs->txs_mbuf; 1741 } 1742 1743 pidx = idx; 1744 idx = VGE_NEXT_TXDESC(idx); 1745 1746 /* 1747 * If there's a BPF listener, bounce a copy of this frame 1748 * to him. 1749 */ 1750 #if NBPFILTER > 0 1751 if (ifp->if_bpf) 1752 bpf_mtap(ifp->if_bpf, m_head); 1753 #endif 1754 } 1755 1756 if (sc->sc_tx_free < ofree) { 1757 /* TX packet queued */ 1758 1759 sc->sc_tx_prodidx = idx; 1760 1761 /* Issue a transmit command. */ 1762 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1763 1764 /* 1765 * Use the countdown timer for interrupt moderation. 1766 * 'TX done' interrupts are disabled. Instead, we reset the 1767 * countdown timer, which will begin counting until it hits 1768 * the value in the SSTIMER register, and then trigger an 1769 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1770 * the timer count is reloaded. Only when the transmitter 1771 * is idle will the timer hit 0 and an interrupt fire. 1772 */ 1773 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1774 1775 /* 1776 * Set a timeout in case the chip goes out to lunch. 1777 */ 1778 ifp->if_timer = 5; 1779 } 1780 } 1781 1782 static int 1783 vge_init(struct ifnet *ifp) 1784 { 1785 struct vge_softc *sc; 1786 int i, rc = 0; 1787 1788 sc = ifp->if_softc; 1789 1790 /* 1791 * Cancel pending I/O and free all RX/TX buffers. 1792 */ 1793 vge_stop(ifp, 0); 1794 vge_reset(sc); 1795 1796 /* Initialize the RX descriptors and mbufs. */ 1797 memset(sc->sc_rxdescs, 0, sizeof(sc->sc_rxdescs)); 1798 sc->sc_rx_consumed = 0; 1799 for (i = 0; i < VGE_NRXDESC; i++) { 1800 if (vge_newbuf(sc, i, NULL) == ENOBUFS) { 1801 printf("%s: unable to allocate or map rx buffer\n", 1802 device_xname(sc->sc_dev)); 1803 return 1; /* XXX */ 1804 } 1805 } 1806 sc->sc_rx_prodidx = 0; 1807 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL; 1808 1809 /* Initialize the TX descriptors and mbufs. */ 1810 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1811 bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap, 1812 VGE_CDTXOFF(0), sizeof(sc->sc_txdescs), 1813 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1814 for (i = 0; i < VGE_NTXDESC; i++) 1815 sc->sc_txsoft[i].txs_mbuf = NULL; 1816 1817 sc->sc_tx_prodidx = 0; 1818 sc->sc_tx_considx = 0; 1819 sc->sc_tx_free = VGE_NTXDESC; 1820 1821 /* Set our station address */ 1822 for (i = 0; i < ETHER_ADDR_LEN; i++) 1823 CSR_WRITE_1(sc, VGE_PAR0 + i, sc->sc_eaddr[i]); 1824 1825 /* 1826 * Set receive FIFO threshold. Also allow transmission and 1827 * reception of VLAN tagged frames. 1828 */ 1829 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 1830 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 1831 1832 /* Set DMA burst length */ 1833 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1834 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1835 1836 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1837 1838 /* Set collision backoff algorithm */ 1839 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1840 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1841 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1842 1843 /* Disable LPSEL field in priority resolution */ 1844 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1845 1846 /* 1847 * Load the addresses of the DMA queues into the chip. 1848 * Note that we only use one transmit queue. 1849 */ 1850 1851 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, VGE_ADDR_LO(VGE_CDTXADDR(sc, 0))); 1852 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_NTXDESC - 1); 1853 1854 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, VGE_ADDR_LO(VGE_CDRXADDR(sc, 0))); 1855 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_NRXDESC - 1); 1856 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_NRXDESC); 1857 1858 /* Enable and wake up the RX descriptor queue */ 1859 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1860 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1861 1862 /* Enable the TX descriptor queue */ 1863 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 1864 1865 /* Set up the receive filter -- allow large frames for VLANs. */ 1866 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 1867 1868 /* If we want promiscuous mode, set the allframes bit. */ 1869 if (ifp->if_flags & IFF_PROMISC) { 1870 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 1871 } 1872 1873 /* Set capture broadcast bit to capture broadcast frames. */ 1874 if (ifp->if_flags & IFF_BROADCAST) { 1875 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 1876 } 1877 1878 /* Set multicast bit to capture multicast frames. */ 1879 if (ifp->if_flags & IFF_MULTICAST) { 1880 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 1881 } 1882 1883 /* Init the cam filter. */ 1884 vge_cam_clear(sc); 1885 1886 /* Init the multicast filter. */ 1887 vge_setmulti(sc); 1888 1889 /* Enable flow control */ 1890 1891 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 1892 1893 /* Enable jumbo frame reception (if desired) */ 1894 1895 /* Start the MAC. */ 1896 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 1897 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 1898 CSR_WRITE_1(sc, VGE_CRS0, 1899 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 1900 1901 /* 1902 * Configure one-shot timer for microsecond 1903 * resulution and load it for 500 usecs. 1904 */ 1905 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 1906 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 1907 1908 /* 1909 * Configure interrupt moderation for receive. Enable 1910 * the holdoff counter and load it, and set the RX 1911 * suppression count to the number of descriptors we 1912 * want to allow before triggering an interrupt. 1913 * The holdoff timer is in units of 20 usecs. 1914 */ 1915 1916 #ifdef notyet 1917 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 1918 /* Select the interrupt holdoff timer page. */ 1919 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1920 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 1921 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 1922 1923 /* Enable use of the holdoff timer. */ 1924 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 1925 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 1926 1927 /* Select the RX suppression threshold page. */ 1928 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1929 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 1930 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 1931 1932 /* Restore the page select bits. */ 1933 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1934 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 1935 #endif 1936 1937 #ifdef DEVICE_POLLING 1938 /* 1939 * Disable interrupts if we are polling. 1940 */ 1941 if (ifp->if_flags & IFF_POLLING) { 1942 CSR_WRITE_4(sc, VGE_IMR, 0); 1943 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1944 } else /* otherwise ... */ 1945 #endif /* DEVICE_POLLING */ 1946 { 1947 /* 1948 * Enable interrupts. 1949 */ 1950 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1951 CSR_WRITE_4(sc, VGE_ISR, 0); 1952 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1953 } 1954 1955 if ((rc = ether_mediachange(ifp)) != 0) 1956 goto out; 1957 1958 ifp->if_flags |= IFF_RUNNING; 1959 ifp->if_flags &= ~IFF_OACTIVE; 1960 1961 sc->sc_if_flags = 0; 1962 sc->sc_link = 0; 1963 1964 callout_schedule(&sc->sc_timeout, hz); 1965 1966 out: 1967 return rc; 1968 } 1969 1970 static void 1971 vge_miibus_statchg(device_t self) 1972 { 1973 struct vge_softc *sc; 1974 struct mii_data *mii; 1975 struct ifmedia_entry *ife; 1976 1977 sc = device_private(self); 1978 mii = &sc->sc_mii; 1979 ife = mii->mii_media.ifm_cur; 1980 /* 1981 * If the user manually selects a media mode, we need to turn 1982 * on the forced MAC mode bit in the DIAGCTL register. If the 1983 * user happens to choose a full duplex mode, we also need to 1984 * set the 'force full duplex' bit. This applies only to 1985 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 1986 * mode is disabled, and in 1000baseT mode, full duplex is 1987 * always implied, so we turn on the forced mode bit but leave 1988 * the FDX bit cleared. 1989 */ 1990 1991 switch (IFM_SUBTYPE(ife->ifm_media)) { 1992 case IFM_AUTO: 1993 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1994 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1995 break; 1996 case IFM_1000_T: 1997 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1998 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1999 break; 2000 case IFM_100_TX: 2001 case IFM_10_T: 2002 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2003 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 2004 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2005 } else { 2006 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2007 } 2008 break; 2009 default: 2010 printf("%s: unknown media type: %x\n", 2011 device_xname(sc->sc_dev), 2012 IFM_SUBTYPE(ife->ifm_media)); 2013 break; 2014 } 2015 } 2016 2017 static int 2018 vge_ifflags_cb(struct ethercom *ec) 2019 { 2020 struct ifnet *ifp = &ec->ec_if; 2021 struct vge_softc *sc = ifp->if_softc; 2022 int change = ifp->if_flags ^ sc->sc_if_flags; 2023 2024 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 2025 return ENETRESET; 2026 else if ((change & IFF_PROMISC) == 0) 2027 return 0; 2028 2029 if ((ifp->if_flags & IFF_PROMISC) == 0) 2030 CSR_CLRBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 2031 else 2032 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 2033 vge_setmulti(sc); 2034 return 0; 2035 } 2036 2037 static int 2038 vge_ioctl(struct ifnet *ifp, u_long command, void *data) 2039 { 2040 struct vge_softc *sc; 2041 struct ifreq *ifr; 2042 int s, error; 2043 2044 sc = ifp->if_softc; 2045 ifr = (struct ifreq *)data; 2046 error = 0; 2047 2048 s = splnet(); 2049 2050 if ((error = ether_ioctl(ifp, command, data)) == ENETRESET) { 2051 error = 0; 2052 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 2053 ; 2054 else if (ifp->if_flags & IFF_RUNNING) { 2055 /* 2056 * Multicast list has changed; set the hardware filter 2057 * accordingly. 2058 */ 2059 vge_setmulti(sc); 2060 } 2061 } 2062 sc->sc_if_flags = ifp->if_flags; 2063 2064 splx(s); 2065 return error; 2066 } 2067 2068 static void 2069 vge_watchdog(struct ifnet *ifp) 2070 { 2071 struct vge_softc *sc; 2072 int s; 2073 2074 sc = ifp->if_softc; 2075 s = splnet(); 2076 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 2077 ifp->if_oerrors++; 2078 2079 vge_txeof(sc); 2080 vge_rxeof(sc); 2081 2082 vge_init(ifp); 2083 2084 splx(s); 2085 } 2086 2087 /* 2088 * Stop the adapter and free any mbufs allocated to the 2089 * RX and TX lists. 2090 */ 2091 static void 2092 vge_stop(struct ifnet *ifp, int disable) 2093 { 2094 struct vge_softc *sc = ifp->if_softc; 2095 struct vge_txsoft *txs; 2096 struct vge_rxsoft *rxs; 2097 int i, s; 2098 2099 s = splnet(); 2100 ifp->if_timer = 0; 2101 2102 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2103 #ifdef DEVICE_POLLING 2104 ether_poll_deregister(ifp); 2105 #endif /* DEVICE_POLLING */ 2106 2107 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2108 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2109 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2110 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2111 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2112 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2113 2114 if (sc->sc_rx_mhead != NULL) { 2115 m_freem(sc->sc_rx_mhead); 2116 sc->sc_rx_mhead = sc->sc_rx_mtail = NULL; 2117 } 2118 2119 /* Free the TX list buffers. */ 2120 2121 for (i = 0; i < VGE_NTXDESC; i++) { 2122 txs = &sc->sc_txsoft[i]; 2123 if (txs->txs_mbuf != NULL) { 2124 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2125 m_freem(txs->txs_mbuf); 2126 txs->txs_mbuf = NULL; 2127 } 2128 } 2129 2130 /* Free the RX list buffers. */ 2131 2132 for (i = 0; i < VGE_NRXDESC; i++) { 2133 rxs = &sc->sc_rxsoft[i]; 2134 if (rxs->rxs_mbuf != NULL) { 2135 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2136 m_freem(rxs->rxs_mbuf); 2137 rxs->rxs_mbuf = NULL; 2138 } 2139 } 2140 2141 splx(s); 2142 } 2143 2144 #if VGE_POWER_MANAGEMENT 2145 /* 2146 * Device suspend routine. Stop the interface and save some PCI 2147 * settings in case the BIOS doesn't restore them properly on 2148 * resume. 2149 */ 2150 static int 2151 vge_suspend(device_t dev) 2152 { 2153 struct vge_softc *sc; 2154 int i; 2155 2156 sc = device_get_softc(dev); 2157 2158 vge_stop(sc); 2159 2160 for (i = 0; i < 5; i++) 2161 sc->sc_saved_maps[i] = 2162 pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2163 sc->sc_saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2164 sc->sc_saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2165 sc->sc_saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2166 sc->sc_saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2167 2168 sc->suspended = 1; 2169 2170 return 0; 2171 } 2172 2173 /* 2174 * Device resume routine. Restore some PCI settings in case the BIOS 2175 * doesn't, re-enable busmastering, and restart the interface if 2176 * appropriate. 2177 */ 2178 static int 2179 vge_resume(device_t dev) 2180 { 2181 struct vge_softc *sc; 2182 struct ifnet *ifp; 2183 int i; 2184 2185 sc = device_private(dev); 2186 ifp = &sc->sc_ethercom.ec_if; 2187 2188 /* better way to do this? */ 2189 for (i = 0; i < 5; i++) 2190 pci_write_config(dev, PCIR_MAPS + i * 4, 2191 sc->sc_saved_maps[i], 4); 2192 pci_write_config(dev, PCIR_BIOS, sc->sc_saved_biosaddr, 4); 2193 pci_write_config(dev, PCIR_INTLINE, sc->sc_saved_intline, 1); 2194 pci_write_config(dev, PCIR_CACHELNSZ, sc->sc_saved_cachelnsz, 1); 2195 pci_write_config(dev, PCIR_LATTIMER, sc->sc_saved_lattimer, 1); 2196 2197 /* reenable busmastering */ 2198 pci_enable_busmaster(dev); 2199 pci_enable_io(dev, SYS_RES_MEMORY); 2200 2201 /* reinitialize interface if necessary */ 2202 if (ifp->if_flags & IFF_UP) 2203 vge_init(sc); 2204 2205 sc->suspended = 0; 2206 2207 return 0; 2208 } 2209 #endif 2210 2211 /* 2212 * Stop all chip I/O so that the kernel's probe routines don't 2213 * get confused by errant DMAs when rebooting. 2214 */ 2215 static bool 2216 vge_shutdown(device_t self, int howto) 2217 { 2218 struct vge_softc *sc; 2219 2220 sc = device_private(self); 2221 vge_stop(&sc->sc_ethercom.ec_if, 1); 2222 2223 return true; 2224 } 2225