1 /* $NetBSD: if_txp.c,v 1.3 2003/07/14 15:47:24 lukem Exp $ */ 2 3 /* 4 * Copyright (c) 2001 5 * Jason L. Wright <jason@thought.net>, Theo de Raadt, and 6 * Aaron Campbell <aaron@monkey.org>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR THE VOICES IN THEIR HEADS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Driver for 3c990 (Typhoon) Ethernet ASIC 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: if_txp.c,v 1.3 2003/07/14 15:47:24 lukem Exp $"); 36 37 #include "bpfilter.h" 38 /* #include "vlan.h" XXX notyet */ 39 #include "opt_inet.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/sockio.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/device.h> 49 #include <sys/callout.h> 50 51 #include <net/if.h> 52 #include <net/if_dl.h> 53 #include <net/if_types.h> 54 #include <net/if_ether.h> 55 #include <net/if_arp.h> 56 57 #ifdef INET 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 #include <netinet/in_var.h> 61 #include <netinet/ip.h> 62 #include <netinet/if_inarp.h> 63 #endif 64 65 #include <net/if_media.h> 66 67 #if NBPFILTER > 0 68 #include <net/bpf.h> 69 #endif 70 71 #if NVLAN > 0 72 #include <net/if_vlanvar.h> 73 #endif 74 75 #include <uvm/uvm_extern.h> /* for vtophys */ 76 #include <machine/bus.h> 77 78 #include <dev/mii/mii.h> 79 #include <dev/mii/miivar.h> 80 #include <dev/pci/pcireg.h> 81 #include <dev/pci/pcivar.h> 82 #include <dev/pci/pcidevs.h> 83 84 #include <dev/pci/if_txpreg.h> 85 86 #include <dev/microcode/typhoon/3c990img.h> 87 88 /* 89 * These currently break the 3c990 firmware, hopefully will be resolved 90 * at some point. 91 */ 92 #undef TRY_TX_UDP_CSUM 93 #undef TRY_TX_TCP_CSUM 94 95 int txp_probe(struct device *, struct cfdata *, void *); 96 void txp_attach(struct device *, struct device *, void *); 97 int txp_intr(void *); 98 void txp_tick(void *); 99 void txp_shutdown(void *); 100 int txp_ioctl(struct ifnet *, u_long, caddr_t); 101 void txp_start(struct ifnet *); 102 void txp_stop(struct txp_softc *); 103 void txp_init(struct txp_softc *); 104 void txp_watchdog(struct ifnet *); 105 106 int txp_chip_init(struct txp_softc *); 107 int txp_reset_adapter(struct txp_softc *); 108 int txp_download_fw(struct txp_softc *); 109 int txp_download_fw_wait(struct txp_softc *); 110 int txp_download_fw_section(struct txp_softc *, 111 struct txp_fw_section_header *, int); 112 int txp_alloc_rings(struct txp_softc *); 113 void txp_dma_free(struct txp_softc *, struct txp_dma_alloc *); 114 int txp_dma_malloc(struct txp_softc *, bus_size_t, struct txp_dma_alloc *, int); 115 void txp_set_filter(struct txp_softc *); 116 117 int txp_cmd_desc_numfree(struct txp_softc *); 118 int txp_command(struct txp_softc *, u_int16_t, u_int16_t, u_int32_t, 119 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int); 120 int txp_command2(struct txp_softc *, u_int16_t, u_int16_t, 121 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t, 122 struct txp_rsp_desc **, int); 123 int txp_response(struct txp_softc *, u_int32_t, u_int16_t, u_int16_t, 124 struct txp_rsp_desc **); 125 void txp_rsp_fixup(struct txp_softc *, struct txp_rsp_desc *, 126 struct txp_rsp_desc *); 127 void txp_capabilities(struct txp_softc *); 128 129 void txp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 130 int txp_ifmedia_upd(struct ifnet *); 131 void txp_show_descriptor(void *); 132 void txp_tx_reclaim(struct txp_softc *, struct txp_tx_ring *, 133 struct txp_dma_alloc *); 134 void txp_rxbuf_reclaim(struct txp_softc *); 135 void txp_rx_reclaim(struct txp_softc *, struct txp_rx_ring *, 136 struct txp_dma_alloc *); 137 138 CFATTACH_DECL(txp, sizeof(struct txp_softc), txp_probe, txp_attach, 139 NULL, NULL); 140 141 const struct txp_pci_match { 142 int vid, did, flags; 143 } txp_devices[] = { 144 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990, 0 }, 145 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX95, 0 }, 146 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX97, 0 }, 147 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR95, TXP_SERVERVERSION }, 148 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR97, TXP_SERVERVERSION }, 149 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990B, TXP_USESUBSYSTEM }, 150 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BSVR, TXP_SERVERVERSION }, 151 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990FX, TXP_USESUBSYSTEM }, 152 }; 153 154 static const struct txp_pci_match *txp_pcilookup(pcireg_t); 155 156 static const struct { 157 u_int16_t mask, value; 158 int flags; 159 } txp_subsysinfo[] = { 160 {0xf000, 0x2000, TXP_SERVERVERSION}, 161 {0x0100, 0x0100, TXP_FIBER}, 162 #if 0 /* information from 3com header, unused */ 163 {0x0010, 0x0010, /* secured firmware */}, 164 {0x0003, 0x0000, /* variable DES */}, 165 {0x0003, 0x0001, /* single DES - "95" */}, 166 {0x0003, 0x0002, /* triple DES - "97" */}, 167 #endif 168 }; 169 170 static const struct txp_pci_match * 171 txp_pcilookup(id) 172 pcireg_t id; 173 { 174 int i; 175 176 for (i = 0; i < sizeof(txp_devices) / sizeof(txp_devices[0]); i++) 177 if ((PCI_VENDOR(id) == txp_devices[i].vid) && 178 (PCI_PRODUCT(id) == txp_devices[i].did)) 179 return (&txp_devices[i]); 180 return (0); 181 } 182 183 int 184 txp_probe(parent, match, aux) 185 struct device *parent; 186 struct cfdata *match; 187 void *aux; 188 { 189 struct pci_attach_args *pa = aux; 190 191 if (txp_pcilookup(pa->pa_id)) 192 return (1); 193 return (0); 194 } 195 196 void 197 txp_attach(parent, self, aux) 198 struct device *parent, *self; 199 void *aux; 200 { 201 struct txp_softc *sc = (struct txp_softc *)self; 202 struct pci_attach_args *pa = aux; 203 pci_chipset_tag_t pc = pa->pa_pc; 204 pci_intr_handle_t ih; 205 const char *intrstr = NULL; 206 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 207 u_int32_t command; 208 u_int16_t p1; 209 u_int32_t p2; 210 u_char enaddr[6]; 211 const struct txp_pci_match *pcimatch; 212 u_int16_t subsys; 213 int i, flags; 214 char devinfo[256]; 215 216 sc->sc_cold = 1; 217 218 pcimatch = txp_pcilookup(pa->pa_id); 219 flags = pcimatch->flags; 220 if (pcimatch->flags & TXP_USESUBSYSTEM) { 221 subsys = PCI_PRODUCT(pci_conf_read(pc, pa->pa_tag, 222 PCI_SUBSYS_ID_REG)); 223 for (i = 0; 224 i < sizeof(txp_subsysinfo)/sizeof(txp_subsysinfo[0]); 225 i++) 226 if ((subsys & txp_subsysinfo[i].mask) == 227 txp_subsysinfo[i].value) 228 flags |= txp_subsysinfo[i].flags; 229 } 230 sc->sc_flags = flags; 231 232 pci_devinfo(pa->pa_id, 0, 0, devinfo); 233 #define TXP_EXTRAINFO ((flags & (TXP_USESUBSYSTEM|TXP_SERVERVERSION)) == \ 234 (TXP_USESUBSYSTEM|TXP_SERVERVERSION) ? " (SVR)" : "") 235 printf(": %s%s\n%s", devinfo, TXP_EXTRAINFO, sc->sc_dev.dv_xname); 236 237 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 238 239 if (!(command & PCI_COMMAND_MASTER_ENABLE)) { 240 printf(": failed to enable bus mastering\n"); 241 return; 242 } 243 244 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 245 printf(": failed to enable memory mapping\n"); 246 return; 247 } 248 if (pci_mapreg_map(pa, TXP_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 249 &sc->sc_bt, &sc->sc_bh, NULL, NULL)) { 250 printf(": can't map mem space %d\n", 0); 251 return; 252 } 253 254 sc->sc_dmat = pa->pa_dmat; 255 256 /* 257 * Allocate our interrupt. 258 */ 259 if (pci_intr_map(pa, &ih)) { 260 printf(": couldn't map interrupt\n"); 261 return; 262 } 263 264 intrstr = pci_intr_string(pc, ih); 265 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, txp_intr, sc); 266 if (sc->sc_ih == NULL) { 267 printf(": couldn't establish interrupt"); 268 if (intrstr != NULL) 269 printf(" at %s", intrstr); 270 printf("\n"); 271 return; 272 } 273 printf(": interrupting at %s\n", intrstr); 274 275 if (txp_chip_init(sc)) 276 return; 277 278 if (txp_download_fw(sc)) 279 return; 280 281 if (txp_alloc_rings(sc)) 282 return; 283 284 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 285 NULL, NULL, NULL, 1)) 286 return; 287 288 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 289 &p1, &p2, NULL, 1)) 290 return; 291 292 txp_set_filter(sc); 293 294 p1 = htole16(p1); 295 enaddr[0] = ((u_int8_t *)&p1)[1]; 296 enaddr[1] = ((u_int8_t *)&p1)[0]; 297 p2 = htole32(p2); 298 enaddr[2] = ((u_int8_t *)&p2)[3]; 299 enaddr[3] = ((u_int8_t *)&p2)[2]; 300 enaddr[4] = ((u_int8_t *)&p2)[1]; 301 enaddr[5] = ((u_int8_t *)&p2)[0]; 302 303 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 304 ether_sprintf(enaddr)); 305 sc->sc_cold = 0; 306 307 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 308 if (flags & TXP_FIBER) { 309 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX, 310 0, NULL); 311 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX|IFM_HDX, 312 0, NULL); 313 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX|IFM_FDX, 314 0, NULL); 315 } else { 316 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 317 0, NULL); 318 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 319 0, NULL); 320 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 321 0, NULL); 322 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 323 0, NULL); 324 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 325 0, NULL); 326 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 327 0, NULL); 328 } 329 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 330 331 sc->sc_xcvr = TXP_XCVR_AUTO; 332 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 333 NULL, NULL, NULL, 0); 334 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 335 336 ifp->if_softc = sc; 337 ifp->if_mtu = ETHERMTU; 338 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 339 ifp->if_ioctl = txp_ioctl; 340 ifp->if_start = txp_start; 341 ifp->if_watchdog = txp_watchdog; 342 ifp->if_baudrate = 10000000; 343 IFQ_SET_MAXLEN(&ifp->if_snd, TX_ENTRIES); 344 IFQ_SET_READY(&ifp->if_snd); 345 ifp->if_capabilities = 0; 346 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 347 348 txp_capabilities(sc); 349 350 callout_setfunc(&sc->sc_tick, txp_tick, sc); 351 352 /* 353 * Attach us everywhere 354 */ 355 if_attach(ifp); 356 ether_ifattach(ifp, enaddr); 357 358 shutdownhook_establish(txp_shutdown, sc); 359 } 360 361 int 362 txp_chip_init(sc) 363 struct txp_softc *sc; 364 { 365 /* disable interrupts */ 366 WRITE_REG(sc, TXP_IER, 0); 367 WRITE_REG(sc, TXP_IMR, 368 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 369 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 370 TXP_INT_LATCH); 371 372 /* ack all interrupts */ 373 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 374 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 375 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 376 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 377 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 378 379 if (txp_reset_adapter(sc)) 380 return (-1); 381 382 /* disable interrupts */ 383 WRITE_REG(sc, TXP_IER, 0); 384 WRITE_REG(sc, TXP_IMR, 385 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 386 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 387 TXP_INT_LATCH); 388 389 /* ack all interrupts */ 390 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 391 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 392 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 393 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 394 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 395 396 return (0); 397 } 398 399 int 400 txp_reset_adapter(sc) 401 struct txp_softc *sc; 402 { 403 u_int32_t r; 404 int i; 405 406 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 407 DELAY(1000); 408 WRITE_REG(sc, TXP_SRR, 0); 409 410 /* Should wait max 6 seconds */ 411 for (i = 0; i < 6000; i++) { 412 r = READ_REG(sc, TXP_A2H_0); 413 if (r == STAT_WAITING_FOR_HOST_REQUEST) 414 break; 415 DELAY(1000); 416 } 417 418 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 419 printf("%s: reset hung\n", TXP_DEVNAME(sc)); 420 return (-1); 421 } 422 423 return (0); 424 } 425 426 int 427 txp_download_fw(sc) 428 struct txp_softc *sc; 429 { 430 struct txp_fw_file_header *fileheader; 431 struct txp_fw_section_header *secthead; 432 int sect; 433 u_int32_t r, i, ier, imr; 434 435 ier = READ_REG(sc, TXP_IER); 436 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 437 438 imr = READ_REG(sc, TXP_IMR); 439 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 440 441 for (i = 0; i < 10000; i++) { 442 r = READ_REG(sc, TXP_A2H_0); 443 if (r == STAT_WAITING_FOR_HOST_REQUEST) 444 break; 445 DELAY(50); 446 } 447 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 448 printf(": not waiting for host request\n"); 449 return (-1); 450 } 451 452 /* Ack the status */ 453 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 454 455 fileheader = (struct txp_fw_file_header *)tc990image; 456 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) { 457 printf(": fw invalid magic\n"); 458 return (-1); 459 } 460 461 /* Tell boot firmware to get ready for image */ 462 WRITE_REG(sc, TXP_H2A_1, le32toh(fileheader->addr)); 463 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 464 465 if (txp_download_fw_wait(sc)) { 466 printf("%s: fw wait failed, initial\n", sc->sc_dev.dv_xname); 467 return (-1); 468 } 469 470 secthead = (struct txp_fw_section_header *)(((u_int8_t *)tc990image) + 471 sizeof(struct txp_fw_file_header)); 472 473 for (sect = 0; sect < le32toh(fileheader->nsections); sect++) { 474 if (txp_download_fw_section(sc, secthead, sect)) 475 return (-1); 476 secthead = (struct txp_fw_section_header *) 477 (((u_int8_t *)secthead) + le32toh(secthead->nbytes) + 478 sizeof(*secthead)); 479 } 480 481 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 482 483 for (i = 0; i < 10000; i++) { 484 r = READ_REG(sc, TXP_A2H_0); 485 if (r == STAT_WAITING_FOR_BOOT) 486 break; 487 DELAY(50); 488 } 489 if (r != STAT_WAITING_FOR_BOOT) { 490 printf(": not waiting for boot\n"); 491 return (-1); 492 } 493 494 WRITE_REG(sc, TXP_IER, ier); 495 WRITE_REG(sc, TXP_IMR, imr); 496 497 return (0); 498 } 499 500 int 501 txp_download_fw_wait(sc) 502 struct txp_softc *sc; 503 { 504 u_int32_t i, r; 505 506 for (i = 0; i < 10000; i++) { 507 r = READ_REG(sc, TXP_ISR); 508 if (r & TXP_INT_A2H_0) 509 break; 510 DELAY(50); 511 } 512 513 if (!(r & TXP_INT_A2H_0)) { 514 printf(": fw wait failed comm0\n"); 515 return (-1); 516 } 517 518 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 519 520 r = READ_REG(sc, TXP_A2H_0); 521 if (r != STAT_WAITING_FOR_SEGMENT) { 522 printf(": fw not waiting for segment\n"); 523 return (-1); 524 } 525 return (0); 526 } 527 528 int 529 txp_download_fw_section(sc, sect, sectnum) 530 struct txp_softc *sc; 531 struct txp_fw_section_header *sect; 532 int sectnum; 533 { 534 struct txp_dma_alloc dma; 535 int rseg, err = 0; 536 struct mbuf m; 537 u_int16_t csum; 538 539 /* Skip zero length sections */ 540 if (sect->nbytes == 0) 541 return (0); 542 543 /* Make sure we aren't past the end of the image */ 544 rseg = ((u_int8_t *)sect) - ((u_int8_t *)tc990image); 545 if (rseg >= sizeof(tc990image)) { 546 printf(": fw invalid section address, section %d\n", sectnum); 547 return (-1); 548 } 549 550 /* Make sure this section doesn't go past the end */ 551 rseg += le32toh(sect->nbytes); 552 if (rseg >= sizeof(tc990image)) { 553 printf(": fw truncated section %d\n", sectnum); 554 return (-1); 555 } 556 557 /* map a buffer, copy segment to it, get physaddr */ 558 if (txp_dma_malloc(sc, le32toh(sect->nbytes), &dma, 0)) { 559 printf(": fw dma malloc failed, section %d\n", sectnum); 560 return (-1); 561 } 562 563 bcopy(((u_int8_t *)sect) + sizeof(*sect), dma.dma_vaddr, 564 le32toh(sect->nbytes)); 565 566 /* 567 * dummy up mbuf and verify section checksum 568 */ 569 m.m_type = MT_DATA; 570 m.m_next = m.m_nextpkt = NULL; 571 m.m_len = le32toh(sect->nbytes); 572 m.m_data = dma.dma_vaddr; 573 m.m_flags = 0; 574 csum = in_cksum(&m, le32toh(sect->nbytes)); 575 if (csum != sect->cksum) { 576 printf(": fw section %d, bad cksum (expected 0x%x got 0x%x)\n", 577 sectnum, sect->cksum, csum); 578 err = -1; 579 goto bail; 580 } 581 582 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 583 dma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 584 585 WRITE_REG(sc, TXP_H2A_1, le32toh(sect->nbytes)); 586 WRITE_REG(sc, TXP_H2A_2, le32toh(sect->cksum)); 587 WRITE_REG(sc, TXP_H2A_3, le32toh(sect->addr)); 588 WRITE_REG(sc, TXP_H2A_4, dma.dma_paddr >> 32); 589 WRITE_REG(sc, TXP_H2A_5, dma.dma_paddr & 0xffffffff); 590 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 591 592 if (txp_download_fw_wait(sc)) { 593 printf("%s: fw wait failed, section %d\n", 594 sc->sc_dev.dv_xname, sectnum); 595 err = -1; 596 } 597 598 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 599 dma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 600 601 bail: 602 txp_dma_free(sc, &dma); 603 604 return (err); 605 } 606 607 int 608 txp_intr(vsc) 609 void *vsc; 610 { 611 struct txp_softc *sc = vsc; 612 struct txp_hostvar *hv = sc->sc_hostvar; 613 u_int32_t isr; 614 int claimed = 0; 615 616 /* mask all interrupts */ 617 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 618 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 619 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 620 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 621 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 622 623 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 624 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 625 626 isr = READ_REG(sc, TXP_ISR); 627 while (isr) { 628 claimed = 1; 629 WRITE_REG(sc, TXP_ISR, isr); 630 631 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 632 txp_rx_reclaim(sc, &sc->sc_rxhir, &sc->sc_rxhiring_dma); 633 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 634 txp_rx_reclaim(sc, &sc->sc_rxlor, &sc->sc_rxloring_dma); 635 636 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 637 txp_rxbuf_reclaim(sc); 638 639 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 640 TXP_OFFSET2IDX(le32toh(*(sc->sc_txhir.r_off))))) 641 txp_tx_reclaim(sc, &sc->sc_txhir, &sc->sc_txhiring_dma); 642 643 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 644 TXP_OFFSET2IDX(le32toh(*(sc->sc_txlor.r_off))))) 645 txp_tx_reclaim(sc, &sc->sc_txlor, &sc->sc_txloring_dma); 646 647 isr = READ_REG(sc, TXP_ISR); 648 } 649 650 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 651 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 652 653 /* unmask all interrupts */ 654 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 655 656 txp_start(&sc->sc_arpcom.ec_if); 657 658 return (claimed); 659 } 660 661 void 662 txp_rx_reclaim(sc, r, dma) 663 struct txp_softc *sc; 664 struct txp_rx_ring *r; 665 struct txp_dma_alloc *dma; 666 { 667 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 668 struct txp_rx_desc *rxd; 669 struct mbuf *m; 670 struct txp_swdesc *sd; 671 u_int32_t roff, woff; 672 int sumflags = 0; 673 int idx; 674 675 roff = le32toh(*r->r_roff); 676 woff = le32toh(*r->r_woff); 677 idx = roff / sizeof(struct txp_rx_desc); 678 rxd = r->r_desc + idx; 679 680 while (roff != woff) { 681 682 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 683 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 684 BUS_DMASYNC_POSTREAD); 685 686 if (rxd->rx_flags & RX_FLAGS_ERROR) { 687 printf("%s: error 0x%x\n", sc->sc_dev.dv_xname, 688 le32toh(rxd->rx_stat)); 689 ifp->if_ierrors++; 690 goto next; 691 } 692 693 /* retrieve stashed pointer */ 694 bcopy((u_long *)&rxd->rx_vaddrlo, &sd, sizeof(sd)); 695 696 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 697 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 698 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 699 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 700 m = sd->sd_mbuf; 701 free(sd, M_DEVBUF); 702 m->m_pkthdr.len = m->m_len = le16toh(rxd->rx_len); 703 704 #ifdef __STRICT_ALIGNMENT 705 { 706 /* 707 * XXX Nice chip, except it won't accept "off by 2" 708 * buffers, so we're force to copy. Supposedly 709 * this will be fixed in a newer firmware rev 710 * and this will be temporary. 711 */ 712 struct mbuf *mnew; 713 714 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 715 if (mnew == NULL) { 716 m_freem(m); 717 goto next; 718 } 719 if (m->m_len > (MHLEN - 2)) { 720 MCLGET(mnew, M_DONTWAIT); 721 if (!(mnew->m_flags & M_EXT)) { 722 m_freem(mnew); 723 m_freem(m); 724 goto next; 725 } 726 } 727 mnew->m_pkthdr.rcvif = ifp; 728 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 729 mnew->m_data += 2; 730 bcopy(m->m_data, mnew->m_data, m->m_len); 731 m_freem(m); 732 m = mnew; 733 } 734 #endif 735 736 #if NBPFILTER > 0 737 /* 738 * Handle BPF listeners. Let the BPF user see the packet. 739 */ 740 if (ifp->if_bpf) 741 bpf_mtap(ifp->if_bpf, m); 742 #endif 743 744 if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMBAD)) 745 sumflags |= (M_CSUM_IPv4|M_CSUM_IPv4_BAD); 746 else if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMGOOD)) 747 sumflags |= M_CSUM_IPv4; 748 749 if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMBAD)) 750 sumflags |= (M_CSUM_TCPv4|M_CSUM_TCP_UDP_BAD); 751 else if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMGOOD)) 752 sumflags |= M_CSUM_TCPv4; 753 754 if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMBAD)) 755 sumflags |= (M_CSUM_UDPv4|M_CSUM_TCP_UDP_BAD); 756 else if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMGOOD)) 757 sumflags |= M_CSUM_UDPv4; 758 759 m->m_pkthdr.csum_flags = sumflags; 760 761 #if NVLAN > 0 762 if (rxd->rx_stat & htole32(RX_STAT_VLAN)) { 763 if (vlan_input_tag(m, htons(rxd->rx_vlan >> 16)) < 0) 764 ifp->if_noproto++; 765 goto next; 766 } 767 #endif 768 769 (*ifp->if_input)(ifp, m); 770 771 next: 772 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 773 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 774 BUS_DMASYNC_PREREAD); 775 776 roff += sizeof(struct txp_rx_desc); 777 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 778 idx = 0; 779 roff = 0; 780 rxd = r->r_desc; 781 } else { 782 idx++; 783 rxd++; 784 } 785 woff = le32toh(*r->r_woff); 786 } 787 788 *r->r_roff = htole32(woff); 789 } 790 791 void 792 txp_rxbuf_reclaim(sc) 793 struct txp_softc *sc; 794 { 795 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 796 struct txp_hostvar *hv = sc->sc_hostvar; 797 struct txp_rxbuf_desc *rbd; 798 struct txp_swdesc *sd; 799 u_int32_t i, end; 800 801 end = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_read_idx)); 802 i = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_write_idx)); 803 804 if (++i == RXBUF_ENTRIES) 805 i = 0; 806 807 rbd = sc->sc_rxbufs + i; 808 809 while (i != end) { 810 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 811 M_DEVBUF, M_NOWAIT); 812 if (sd == NULL) 813 break; 814 815 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 816 if (sd->sd_mbuf == NULL) 817 goto err_sd; 818 819 MCLGET(sd->sd_mbuf, M_DONTWAIT); 820 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 821 goto err_mbuf; 822 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 823 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 824 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 825 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) 826 goto err_mbuf; 827 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 828 BUS_DMA_NOWAIT)) { 829 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 830 goto err_mbuf; 831 } 832 833 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 834 i * sizeof(struct txp_rxbuf_desc), 835 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_POSTWRITE); 836 837 /* stash away pointer */ 838 bcopy(&sd, (u_long *)&rbd->rb_vaddrlo, sizeof(sd)); 839 840 rbd->rb_paddrlo = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 841 & 0xffffffff; 842 rbd->rb_paddrhi = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 843 >> 32; 844 845 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 846 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 847 848 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 849 i * sizeof(struct txp_rxbuf_desc), 850 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_PREWRITE); 851 852 hv->hv_rx_buf_write_idx = htole32(TXP_IDX2OFFSET(i)); 853 854 if (++i == RXBUF_ENTRIES) { 855 i = 0; 856 rbd = sc->sc_rxbufs; 857 } else 858 rbd++; 859 } 860 return; 861 862 err_mbuf: 863 m_freem(sd->sd_mbuf); 864 err_sd: 865 free(sd, M_DEVBUF); 866 } 867 868 /* 869 * Reclaim mbufs and entries from a transmit ring. 870 */ 871 void 872 txp_tx_reclaim(sc, r, dma) 873 struct txp_softc *sc; 874 struct txp_tx_ring *r; 875 struct txp_dma_alloc *dma; 876 { 877 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 878 u_int32_t idx = TXP_OFFSET2IDX(le32toh(*(r->r_off))); 879 u_int32_t cons = r->r_cons, cnt = r->r_cnt; 880 struct txp_tx_desc *txd = r->r_desc + cons; 881 struct txp_swdesc *sd = sc->sc_txd + cons; 882 struct mbuf *m; 883 884 while (cons != idx) { 885 if (cnt == 0) 886 break; 887 888 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 889 cons * sizeof(struct txp_tx_desc), 890 sizeof(struct txp_tx_desc), 891 BUS_DMASYNC_POSTWRITE); 892 893 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 894 TX_FLAGS_TYPE_DATA) { 895 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 896 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 897 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 898 m = sd->sd_mbuf; 899 if (m != NULL) { 900 m_freem(m); 901 txd->tx_addrlo = 0; 902 txd->tx_addrhi = 0; 903 ifp->if_opackets++; 904 } 905 } 906 ifp->if_flags &= ~IFF_OACTIVE; 907 908 if (++cons == TX_ENTRIES) { 909 txd = r->r_desc; 910 cons = 0; 911 sd = sc->sc_txd; 912 } else { 913 txd++; 914 sd++; 915 } 916 917 cnt--; 918 } 919 920 r->r_cons = cons; 921 r->r_cnt = cnt; 922 if (cnt == 0) 923 ifp->if_timer = 0; 924 } 925 926 void 927 txp_shutdown(vsc) 928 void *vsc; 929 { 930 struct txp_softc *sc = (struct txp_softc *)vsc; 931 932 /* mask all interrupts */ 933 WRITE_REG(sc, TXP_IMR, 934 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 935 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 936 TXP_INT_LATCH); 937 938 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 939 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 940 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 941 } 942 943 int 944 txp_alloc_rings(sc) 945 struct txp_softc *sc; 946 { 947 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 948 struct txp_boot_record *boot; 949 struct txp_swdesc *sd; 950 u_int32_t r; 951 int i, j; 952 953 /* boot record */ 954 if (txp_dma_malloc(sc, sizeof(struct txp_boot_record), &sc->sc_boot_dma, 955 BUS_DMA_COHERENT)) { 956 printf(": can't allocate boot record\n"); 957 return (-1); 958 } 959 boot = (struct txp_boot_record *)sc->sc_boot_dma.dma_vaddr; 960 bzero(boot, sizeof(*boot)); 961 sc->sc_boot = boot; 962 963 /* host variables */ 964 if (txp_dma_malloc(sc, sizeof(struct txp_hostvar), &sc->sc_host_dma, 965 BUS_DMA_COHERENT)) { 966 printf(": can't allocate host ring\n"); 967 goto bail_boot; 968 } 969 bzero(sc->sc_host_dma.dma_vaddr, sizeof(struct txp_hostvar)); 970 boot->br_hostvar_lo = htole32(sc->sc_host_dma.dma_paddr & 0xffffffff); 971 boot->br_hostvar_hi = htole32(sc->sc_host_dma.dma_paddr >> 32); 972 sc->sc_hostvar = (struct txp_hostvar *)sc->sc_host_dma.dma_vaddr; 973 974 /* high priority tx ring */ 975 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 976 &sc->sc_txhiring_dma, BUS_DMA_COHERENT)) { 977 printf(": can't allocate high tx ring\n"); 978 goto bail_host; 979 } 980 bzero(sc->sc_txhiring_dma.dma_vaddr, sizeof(struct txp_tx_desc) * TX_ENTRIES); 981 boot->br_txhipri_lo = htole32(sc->sc_txhiring_dma.dma_paddr & 0xffffffff); 982 boot->br_txhipri_hi = htole32(sc->sc_txhiring_dma.dma_paddr >> 32); 983 boot->br_txhipri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 984 sc->sc_txhir.r_reg = TXP_H2A_1; 985 sc->sc_txhir.r_desc = (struct txp_tx_desc *)sc->sc_txhiring_dma.dma_vaddr; 986 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 987 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 988 for (i = 0; i < TX_ENTRIES; i++) { 989 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 990 TX_ENTRIES - 4, TXP_MAX_SEGLEN, 0, 991 BUS_DMA_NOWAIT, &sc->sc_txd[i].sd_map) != 0) { 992 for (j = 0; j < i; j++) { 993 bus_dmamap_destroy(sc->sc_dmat, 994 sc->sc_txd[j].sd_map); 995 sc->sc_txd[j].sd_map = NULL; 996 } 997 goto bail_txhiring; 998 } 999 } 1000 1001 /* low priority tx ring */ 1002 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 1003 &sc->sc_txloring_dma, BUS_DMA_COHERENT)) { 1004 printf(": can't allocate low tx ring\n"); 1005 goto bail_txhiring; 1006 } 1007 bzero(sc->sc_txloring_dma.dma_vaddr, sizeof(struct txp_tx_desc) * TX_ENTRIES); 1008 boot->br_txlopri_lo = htole32(sc->sc_txloring_dma.dma_paddr & 0xffffffff); 1009 boot->br_txlopri_hi = htole32(sc->sc_txloring_dma.dma_paddr >> 32); 1010 boot->br_txlopri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 1011 sc->sc_txlor.r_reg = TXP_H2A_3; 1012 sc->sc_txlor.r_desc = (struct txp_tx_desc *)sc->sc_txloring_dma.dma_vaddr; 1013 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 1014 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 1015 1016 /* high priority rx ring */ 1017 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1018 &sc->sc_rxhiring_dma, BUS_DMA_COHERENT)) { 1019 printf(": can't allocate high rx ring\n"); 1020 goto bail_txloring; 1021 } 1022 bzero(sc->sc_rxhiring_dma.dma_vaddr, sizeof(struct txp_rx_desc) * RX_ENTRIES); 1023 boot->br_rxhipri_lo = htole32(sc->sc_rxhiring_dma.dma_paddr & 0xffffffff); 1024 boot->br_rxhipri_hi = htole32(sc->sc_rxhiring_dma.dma_paddr >> 32); 1025 boot->br_rxhipri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1026 sc->sc_rxhir.r_desc = 1027 (struct txp_rx_desc *)sc->sc_rxhiring_dma.dma_vaddr; 1028 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 1029 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 1030 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxhiring_dma.dma_map, 1031 0, sc->sc_rxhiring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1032 1033 /* low priority ring */ 1034 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1035 &sc->sc_rxloring_dma, BUS_DMA_COHERENT)) { 1036 printf(": can't allocate low rx ring\n"); 1037 goto bail_rxhiring; 1038 } 1039 bzero(sc->sc_rxloring_dma.dma_vaddr, sizeof(struct txp_rx_desc) * RX_ENTRIES); 1040 boot->br_rxlopri_lo = htole32(sc->sc_rxloring_dma.dma_paddr & 0xffffffff); 1041 boot->br_rxlopri_hi = htole32(sc->sc_rxloring_dma.dma_paddr >> 32); 1042 boot->br_rxlopri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1043 sc->sc_rxlor.r_desc = 1044 (struct txp_rx_desc *)sc->sc_rxloring_dma.dma_vaddr; 1045 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 1046 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 1047 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxloring_dma.dma_map, 1048 0, sc->sc_rxloring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1049 1050 /* command ring */ 1051 if (txp_dma_malloc(sc, sizeof(struct txp_cmd_desc) * CMD_ENTRIES, 1052 &sc->sc_cmdring_dma, BUS_DMA_COHERENT)) { 1053 printf(": can't allocate command ring\n"); 1054 goto bail_rxloring; 1055 } 1056 bzero(sc->sc_cmdring_dma.dma_vaddr, sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 1057 boot->br_cmd_lo = htole32(sc->sc_cmdring_dma.dma_paddr & 0xffffffff); 1058 boot->br_cmd_hi = htole32(sc->sc_cmdring_dma.dma_paddr >> 32); 1059 boot->br_cmd_siz = htole32(CMD_ENTRIES * sizeof(struct txp_cmd_desc)); 1060 sc->sc_cmdring.base = (struct txp_cmd_desc *)sc->sc_cmdring_dma.dma_vaddr; 1061 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1062 sc->sc_cmdring.lastwrite = 0; 1063 1064 /* response ring */ 1065 if (txp_dma_malloc(sc, sizeof(struct txp_rsp_desc) * RSP_ENTRIES, 1066 &sc->sc_rspring_dma, BUS_DMA_COHERENT)) { 1067 printf(": can't allocate response ring\n"); 1068 goto bail_cmdring; 1069 } 1070 bzero(sc->sc_rspring_dma.dma_vaddr, sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 1071 boot->br_resp_lo = htole32(sc->sc_rspring_dma.dma_paddr & 0xffffffff); 1072 boot->br_resp_hi = htole32(sc->sc_rspring_dma.dma_paddr >> 32); 1073 boot->br_resp_siz = htole32(CMD_ENTRIES * sizeof(struct txp_rsp_desc)); 1074 sc->sc_rspring.base = (struct txp_rsp_desc *)sc->sc_rspring_dma.dma_vaddr; 1075 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 1076 sc->sc_rspring.lastwrite = 0; 1077 1078 /* receive buffer ring */ 1079 if (txp_dma_malloc(sc, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES, 1080 &sc->sc_rxbufring_dma, BUS_DMA_COHERENT)) { 1081 printf(": can't allocate rx buffer ring\n"); 1082 goto bail_rspring; 1083 } 1084 bzero(sc->sc_rxbufring_dma.dma_vaddr, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES); 1085 boot->br_rxbuf_lo = htole32(sc->sc_rxbufring_dma.dma_paddr & 0xffffffff); 1086 boot->br_rxbuf_hi = htole32(sc->sc_rxbufring_dma.dma_paddr >> 32); 1087 boot->br_rxbuf_siz = htole32(RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc)); 1088 sc->sc_rxbufs = (struct txp_rxbuf_desc *)sc->sc_rxbufring_dma.dma_vaddr; 1089 for (i = 0; i < RXBUF_ENTRIES; i++) { 1090 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 1091 M_DEVBUF, M_NOWAIT); 1092 if (sd == NULL) 1093 break; 1094 1095 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 1096 if (sd->sd_mbuf == NULL) { 1097 goto bail_rxbufring; 1098 } 1099 1100 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1101 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1102 goto bail_rxbufring; 1103 } 1104 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1105 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 1106 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 1107 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) { 1108 goto bail_rxbufring; 1109 } 1110 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 1111 BUS_DMA_NOWAIT)) { 1112 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 1113 goto bail_rxbufring; 1114 } 1115 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1116 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1117 1118 /* stash away pointer */ 1119 bcopy(&sd, (u_long *)&sc->sc_rxbufs[i].rb_vaddrlo, sizeof(sd)); 1120 1121 sc->sc_rxbufs[i].rb_paddrlo = 1122 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) & 0xffffffff; 1123 sc->sc_rxbufs[i].rb_paddrhi = 1124 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) >> 32; 1125 } 1126 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 1127 0, sc->sc_rxbufring_dma.dma_map->dm_mapsize, 1128 BUS_DMASYNC_PREWRITE); 1129 sc->sc_hostvar->hv_rx_buf_write_idx = htole32((RXBUF_ENTRIES - 1) * 1130 sizeof(struct txp_rxbuf_desc)); 1131 1132 /* zero dma */ 1133 if (txp_dma_malloc(sc, sizeof(u_int32_t), &sc->sc_zero_dma, 1134 BUS_DMA_COHERENT)) { 1135 printf(": can't allocate response ring\n"); 1136 goto bail_rxbufring; 1137 } 1138 bzero(sc->sc_zero_dma.dma_vaddr, sizeof(u_int32_t)); 1139 boot->br_zero_lo = htole32(sc->sc_zero_dma.dma_paddr & 0xffffffff); 1140 boot->br_zero_hi = htole32(sc->sc_zero_dma.dma_paddr >> 32); 1141 1142 /* See if it's waiting for boot, and try to boot it */ 1143 for (i = 0; i < 10000; i++) { 1144 r = READ_REG(sc, TXP_A2H_0); 1145 if (r == STAT_WAITING_FOR_BOOT) 1146 break; 1147 DELAY(50); 1148 } 1149 if (r != STAT_WAITING_FOR_BOOT) { 1150 printf(": not waiting for boot\n"); 1151 goto bail; 1152 } 1153 WRITE_REG(sc, TXP_H2A_2, sc->sc_boot_dma.dma_paddr >> 32); 1154 WRITE_REG(sc, TXP_H2A_1, sc->sc_boot_dma.dma_paddr & 0xffffffff); 1155 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1156 1157 /* See if it booted */ 1158 for (i = 0; i < 10000; i++) { 1159 r = READ_REG(sc, TXP_A2H_0); 1160 if (r == STAT_RUNNING) 1161 break; 1162 DELAY(50); 1163 } 1164 if (r != STAT_RUNNING) { 1165 printf(": fw not running\n"); 1166 goto bail; 1167 } 1168 1169 /* Clear TX and CMD ring write registers */ 1170 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1171 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1172 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1173 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1174 1175 return (0); 1176 1177 bail: 1178 txp_dma_free(sc, &sc->sc_zero_dma); 1179 bail_rxbufring: 1180 txp_dma_free(sc, &sc->sc_rxbufring_dma); 1181 bail_rspring: 1182 txp_dma_free(sc, &sc->sc_rspring_dma); 1183 bail_cmdring: 1184 txp_dma_free(sc, &sc->sc_cmdring_dma); 1185 bail_rxloring: 1186 txp_dma_free(sc, &sc->sc_rxloring_dma); 1187 bail_rxhiring: 1188 txp_dma_free(sc, &sc->sc_rxhiring_dma); 1189 bail_txloring: 1190 txp_dma_free(sc, &sc->sc_txloring_dma); 1191 bail_txhiring: 1192 txp_dma_free(sc, &sc->sc_txhiring_dma); 1193 bail_host: 1194 txp_dma_free(sc, &sc->sc_host_dma); 1195 bail_boot: 1196 txp_dma_free(sc, &sc->sc_boot_dma); 1197 return (-1); 1198 } 1199 1200 int 1201 txp_dma_malloc(sc, size, dma, mapflags) 1202 struct txp_softc *sc; 1203 bus_size_t size; 1204 struct txp_dma_alloc *dma; 1205 int mapflags; 1206 { 1207 int r; 1208 1209 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 1210 &dma->dma_seg, 1, &dma->dma_nseg, 0)) != 0) 1211 goto fail_0; 1212 1213 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 1214 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 1215 goto fail_1; 1216 1217 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1218 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 1219 goto fail_2; 1220 1221 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 1222 size, NULL, BUS_DMA_NOWAIT)) != 0) 1223 goto fail_3; 1224 1225 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 1226 return (0); 1227 1228 fail_3: 1229 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1230 fail_2: 1231 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 1232 fail_1: 1233 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1234 fail_0: 1235 return (r); 1236 } 1237 1238 void 1239 txp_dma_free(sc, dma) 1240 struct txp_softc *sc; 1241 struct txp_dma_alloc *dma; 1242 { 1243 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 1244 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_map->dm_mapsize); 1245 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1246 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1247 } 1248 1249 int 1250 txp_ioctl(ifp, command, data) 1251 struct ifnet *ifp; 1252 u_long command; 1253 caddr_t data; 1254 { 1255 struct txp_softc *sc = ifp->if_softc; 1256 struct ifreq *ifr = (struct ifreq *)data; 1257 struct ifaddr *ifa = (struct ifaddr *)data; 1258 int s, error = 0; 1259 1260 s = splnet(); 1261 1262 #if 0 1263 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, command, data)) > 0) { 1264 splx(s); 1265 return error; 1266 } 1267 #endif 1268 1269 switch(command) { 1270 case SIOCSIFADDR: 1271 ifp->if_flags |= IFF_UP; 1272 switch (ifa->ifa_addr->sa_family) { 1273 #ifdef INET 1274 case AF_INET: 1275 txp_init(sc); 1276 arp_ifinit(ifp, ifa); 1277 break; 1278 #endif /* INET */ 1279 default: 1280 txp_init(sc); 1281 break; 1282 } 1283 break; 1284 case SIOCSIFFLAGS: 1285 if (ifp->if_flags & IFF_UP) { 1286 txp_init(sc); 1287 } else { 1288 if (ifp->if_flags & IFF_RUNNING) 1289 txp_stop(sc); 1290 } 1291 break; 1292 case SIOCADDMULTI: 1293 case SIOCDELMULTI: 1294 error = (command == SIOCADDMULTI) ? 1295 ether_addmulti(ifr, &sc->sc_arpcom) : 1296 ether_delmulti(ifr, &sc->sc_arpcom); 1297 1298 if (error == ENETRESET) { 1299 /* 1300 * Multicast list has changed; set the hardware 1301 * filter accordingly. 1302 */ 1303 txp_set_filter(sc); 1304 error = 0; 1305 } 1306 break; 1307 case SIOCGIFMEDIA: 1308 case SIOCSIFMEDIA: 1309 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command); 1310 break; 1311 default: 1312 error = EINVAL; 1313 break; 1314 } 1315 1316 splx(s); 1317 1318 return(error); 1319 } 1320 1321 void 1322 txp_init(sc) 1323 struct txp_softc *sc; 1324 { 1325 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1326 int s; 1327 1328 txp_stop(sc); 1329 1330 s = splnet(); 1331 1332 txp_set_filter(sc); 1333 1334 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1335 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1336 1337 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1338 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1339 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1340 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1341 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1342 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1343 1344 ifp->if_flags |= IFF_RUNNING; 1345 ifp->if_flags &= ~IFF_OACTIVE; 1346 ifp->if_timer = 0; 1347 1348 if (!callout_pending(&sc->sc_tick)) 1349 callout_schedule(&sc->sc_tick, hz); 1350 1351 splx(s); 1352 } 1353 1354 void 1355 txp_tick(vsc) 1356 void *vsc; 1357 { 1358 struct txp_softc *sc = vsc; 1359 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1360 struct txp_rsp_desc *rsp = NULL; 1361 struct txp_ext_desc *ext; 1362 int s; 1363 1364 s = splnet(); 1365 txp_rxbuf_reclaim(sc); 1366 1367 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1368 &rsp, 1)) 1369 goto out; 1370 if (rsp->rsp_numdesc != 6) 1371 goto out; 1372 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1373 NULL, NULL, NULL, 1)) 1374 goto out; 1375 ext = (struct txp_ext_desc *)(rsp + 1); 1376 1377 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1378 ext[4].ext_1 + ext[4].ext_4; 1379 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1380 ext[2].ext_1; 1381 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1382 ext[1].ext_3; 1383 ifp->if_opackets += rsp->rsp_par2; 1384 ifp->if_ipackets += ext[2].ext_3; 1385 1386 out: 1387 if (rsp != NULL) 1388 free(rsp, M_DEVBUF); 1389 1390 splx(s); 1391 callout_schedule(&sc->sc_tick, hz); 1392 } 1393 1394 void 1395 txp_start(ifp) 1396 struct ifnet *ifp; 1397 { 1398 struct txp_softc *sc = ifp->if_softc; 1399 struct txp_tx_ring *r = &sc->sc_txhir; 1400 struct txp_tx_desc *txd; 1401 int txdidx; 1402 struct txp_frag_desc *fxd; 1403 struct mbuf *m, *mnew; 1404 struct txp_swdesc *sd; 1405 u_int32_t firstprod, firstcnt, prod, cnt, i; 1406 #if NVLAN > 0 1407 struct ifvlan *ifv; 1408 #endif 1409 1410 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1411 return; 1412 1413 prod = r->r_prod; 1414 cnt = r->r_cnt; 1415 1416 while (1) { 1417 IFQ_POLL(&ifp->if_snd, m); 1418 if (m == NULL) 1419 break; 1420 mnew = NULL; 1421 1422 firstprod = prod; 1423 firstcnt = cnt; 1424 1425 sd = sc->sc_txd + prod; 1426 sd->sd_mbuf = m; 1427 1428 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1429 BUS_DMA_NOWAIT)) { 1430 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1431 if (mnew == NULL) 1432 goto oactive1; 1433 if (m->m_pkthdr.len > MHLEN) { 1434 MCLGET(mnew, M_DONTWAIT); 1435 if ((mnew->m_flags & M_EXT) == 0) { 1436 m_freem(mnew); 1437 goto oactive1; 1438 } 1439 } 1440 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, caddr_t)); 1441 mnew->m_pkthdr.len = mnew->m_len = m->m_pkthdr.len; 1442 IFQ_DEQUEUE(&ifp->if_snd, m); 1443 m_freem(m); 1444 m = mnew; 1445 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1446 BUS_DMA_NOWAIT)) 1447 goto oactive1; 1448 } 1449 1450 if ((TX_ENTRIES - cnt) < 4) 1451 goto oactive; 1452 1453 txd = r->r_desc + prod; 1454 txdidx = prod; 1455 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1456 txd->tx_numdesc = 0; 1457 txd->tx_addrlo = 0; 1458 txd->tx_addrhi = 0; 1459 txd->tx_totlen = m->m_pkthdr.len; 1460 txd->tx_pflags = 0; 1461 txd->tx_numdesc = sd->sd_map->dm_nsegs; 1462 1463 if (++prod == TX_ENTRIES) 1464 prod = 0; 1465 1466 if (++cnt >= (TX_ENTRIES - 4)) 1467 goto oactive; 1468 1469 #if NVLAN > 0 1470 if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1471 m->m_pkthdr.rcvif != NULL) { 1472 ifv = m->m_pkthdr.rcvif->if_softc; 1473 txd->tx_pflags = TX_PFLAGS_VLAN | 1474 (htons(ifv->ifv_tag) << TX_PFLAGS_VLANTAG_S); 1475 } 1476 #endif 1477 1478 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 1479 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1480 #ifdef TRY_TX_TCP_CSUM 1481 if (m->m_pkthdr.csum_flags & M_CSUM_TCPv4) 1482 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1483 #endif 1484 #ifdef TRY_TX_UDP_CSUM 1485 if (m->m_pkthdr.csum_flags & M_CSUM_UDPv4) 1486 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1487 #endif 1488 1489 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1490 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1491 1492 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1493 for (i = 0; i < sd->sd_map->dm_nsegs; i++) { 1494 if (++cnt >= (TX_ENTRIES - 4)) { 1495 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 1496 0, sd->sd_map->dm_mapsize, 1497 BUS_DMASYNC_POSTWRITE); 1498 goto oactive; 1499 } 1500 1501 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG | 1502 FRAG_FLAGS_VALID; 1503 fxd->frag_rsvd1 = 0; 1504 fxd->frag_len = sd->sd_map->dm_segs[i].ds_len; 1505 fxd->frag_addrlo = 1506 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) & 1507 0xffffffff; 1508 fxd->frag_addrhi = 1509 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) >> 1510 32; 1511 fxd->frag_rsvd2 = 0; 1512 1513 bus_dmamap_sync(sc->sc_dmat, 1514 sc->sc_txhiring_dma.dma_map, 1515 prod * sizeof(struct txp_frag_desc), 1516 sizeof(struct txp_frag_desc), BUS_DMASYNC_PREWRITE); 1517 1518 if (++prod == TX_ENTRIES) { 1519 fxd = (struct txp_frag_desc *)r->r_desc; 1520 prod = 0; 1521 } else 1522 fxd++; 1523 1524 } 1525 1526 /* 1527 * if mnew isn't NULL, we already dequeued and copied 1528 * the packet. 1529 */ 1530 if (mnew == NULL) 1531 IFQ_DEQUEUE(&ifp->if_snd, m); 1532 1533 ifp->if_timer = 5; 1534 1535 #if NBPFILTER > 0 1536 if (ifp->if_bpf) 1537 bpf_mtap(ifp->if_bpf, m); 1538 #endif 1539 1540 txd->tx_flags |= TX_FLAGS_VALID; 1541 bus_dmamap_sync(sc->sc_dmat, sc->sc_txhiring_dma.dma_map, 1542 txdidx * sizeof(struct txp_tx_desc), 1543 sizeof(struct txp_tx_desc), BUS_DMASYNC_PREWRITE); 1544 1545 #if 0 1546 { 1547 struct mbuf *mx; 1548 int i; 1549 1550 printf("txd: flags 0x%x ndesc %d totlen %d pflags 0x%x\n", 1551 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1552 txd->tx_pflags); 1553 for (mx = m; mx != NULL; mx = mx->m_next) { 1554 for (i = 0; i < mx->m_len; i++) { 1555 printf(":%02x", 1556 (u_int8_t)m->m_data[i]); 1557 } 1558 } 1559 printf("\n"); 1560 } 1561 #endif 1562 1563 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1564 } 1565 1566 r->r_prod = prod; 1567 r->r_cnt = cnt; 1568 return; 1569 1570 oactive: 1571 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 1572 oactive1: 1573 ifp->if_flags |= IFF_OACTIVE; 1574 r->r_prod = firstprod; 1575 r->r_cnt = firstcnt; 1576 } 1577 1578 /* 1579 * Handle simple commands sent to the typhoon 1580 */ 1581 int 1582 txp_command(sc, id, in1, in2, in3, out1, out2, out3, wait) 1583 struct txp_softc *sc; 1584 u_int16_t id, in1, *out1; 1585 u_int32_t in2, in3, *out2, *out3; 1586 int wait; 1587 { 1588 struct txp_rsp_desc *rsp = NULL; 1589 1590 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1591 return (-1); 1592 1593 if (!wait) 1594 return (0); 1595 1596 if (out1 != NULL) 1597 *out1 = le16toh(rsp->rsp_par1); 1598 if (out2 != NULL) 1599 *out2 = le32toh(rsp->rsp_par2); 1600 if (out3 != NULL) 1601 *out3 = le32toh(rsp->rsp_par3); 1602 free(rsp, M_DEVBUF); 1603 return (0); 1604 } 1605 1606 int 1607 txp_command2(sc, id, in1, in2, in3, in_extp, in_extn, rspp, wait) 1608 struct txp_softc *sc; 1609 u_int16_t id, in1; 1610 u_int32_t in2, in3; 1611 struct txp_ext_desc *in_extp; 1612 u_int8_t in_extn; 1613 struct txp_rsp_desc **rspp; 1614 int wait; 1615 { 1616 struct txp_hostvar *hv = sc->sc_hostvar; 1617 struct txp_cmd_desc *cmd; 1618 struct txp_ext_desc *ext; 1619 u_int32_t idx, i; 1620 u_int16_t seq; 1621 1622 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1623 printf("%s: no free cmd descriptors\n", TXP_DEVNAME(sc)); 1624 return (-1); 1625 } 1626 1627 idx = sc->sc_cmdring.lastwrite; 1628 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1629 bzero(cmd, sizeof(*cmd)); 1630 1631 cmd->cmd_numdesc = in_extn; 1632 seq = sc->sc_seq++; 1633 cmd->cmd_seq = htole16(seq); 1634 cmd->cmd_id = htole16(id); 1635 cmd->cmd_par1 = htole16(in1); 1636 cmd->cmd_par2 = htole32(in2); 1637 cmd->cmd_par3 = htole32(in3); 1638 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1639 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1640 1641 idx += sizeof(struct txp_cmd_desc); 1642 if (idx == sc->sc_cmdring.size) 1643 idx = 0; 1644 1645 for (i = 0; i < in_extn; i++) { 1646 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1647 bcopy(in_extp, ext, sizeof(struct txp_ext_desc)); 1648 in_extp++; 1649 idx += sizeof(struct txp_cmd_desc); 1650 if (idx == sc->sc_cmdring.size) 1651 idx = 0; 1652 } 1653 1654 sc->sc_cmdring.lastwrite = idx; 1655 1656 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1657 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1658 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1659 1660 if (!wait) 1661 return (0); 1662 1663 for (i = 0; i < 10000; i++) { 1664 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1665 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTREAD); 1666 idx = le32toh(hv->hv_resp_read_idx); 1667 if (idx != le32toh(hv->hv_resp_write_idx)) { 1668 *rspp = NULL; 1669 if (txp_response(sc, idx, id, seq, rspp)) 1670 return (-1); 1671 if (*rspp != NULL) 1672 break; 1673 } 1674 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1675 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1676 DELAY(50); 1677 } 1678 if (i == 1000 || (*rspp) == NULL) { 1679 printf("%s: 0x%x command failed\n", TXP_DEVNAME(sc), id); 1680 return (-1); 1681 } 1682 1683 return (0); 1684 } 1685 1686 int 1687 txp_response(sc, ridx, id, seq, rspp) 1688 struct txp_softc *sc; 1689 u_int32_t ridx; 1690 u_int16_t id; 1691 u_int16_t seq; 1692 struct txp_rsp_desc **rspp; 1693 { 1694 struct txp_hostvar *hv = sc->sc_hostvar; 1695 struct txp_rsp_desc *rsp; 1696 1697 while (ridx != le32toh(hv->hv_resp_write_idx)) { 1698 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx); 1699 1700 if (id == le16toh(rsp->rsp_id) && le16toh(rsp->rsp_seq) == seq) { 1701 *rspp = (struct txp_rsp_desc *)malloc( 1702 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1703 M_DEVBUF, M_NOWAIT); 1704 if ((*rspp) == NULL) 1705 return (-1); 1706 txp_rsp_fixup(sc, rsp, *rspp); 1707 return (0); 1708 } 1709 1710 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1711 printf("%s: response error: id 0x%x\n", 1712 TXP_DEVNAME(sc), le16toh(rsp->rsp_id)); 1713 txp_rsp_fixup(sc, rsp, NULL); 1714 ridx = le32toh(hv->hv_resp_read_idx); 1715 continue; 1716 } 1717 1718 switch (le16toh(rsp->rsp_id)) { 1719 case TXP_CMD_CYCLE_STATISTICS: 1720 case TXP_CMD_MEDIA_STATUS_READ: 1721 break; 1722 case TXP_CMD_HELLO_RESPONSE: 1723 printf("%s: hello\n", TXP_DEVNAME(sc)); 1724 break; 1725 default: 1726 printf("%s: unknown id(0x%x)\n", TXP_DEVNAME(sc), 1727 le16toh(rsp->rsp_id)); 1728 } 1729 1730 txp_rsp_fixup(sc, rsp, NULL); 1731 ridx = le32toh(hv->hv_resp_read_idx); 1732 hv->hv_resp_read_idx = le32toh(ridx); 1733 } 1734 1735 return (0); 1736 } 1737 1738 void 1739 txp_rsp_fixup(sc, rsp, dst) 1740 struct txp_softc *sc; 1741 struct txp_rsp_desc *rsp, *dst; 1742 { 1743 struct txp_rsp_desc *src = rsp; 1744 struct txp_hostvar *hv = sc->sc_hostvar; 1745 u_int32_t i, ridx; 1746 1747 ridx = le32toh(hv->hv_resp_read_idx); 1748 1749 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1750 if (dst != NULL) 1751 bcopy(src, dst++, sizeof(struct txp_rsp_desc)); 1752 ridx += sizeof(struct txp_rsp_desc); 1753 if (ridx == sc->sc_rspring.size) { 1754 src = sc->sc_rspring.base; 1755 ridx = 0; 1756 } else 1757 src++; 1758 sc->sc_rspring.lastwrite = ridx; 1759 hv->hv_resp_read_idx = htole32(ridx); 1760 } 1761 1762 hv->hv_resp_read_idx = htole32(ridx); 1763 } 1764 1765 int 1766 txp_cmd_desc_numfree(sc) 1767 struct txp_softc *sc; 1768 { 1769 struct txp_hostvar *hv = sc->sc_hostvar; 1770 struct txp_boot_record *br = sc->sc_boot; 1771 u_int32_t widx, ridx, nfree; 1772 1773 widx = sc->sc_cmdring.lastwrite; 1774 ridx = le32toh(hv->hv_cmd_read_idx); 1775 1776 if (widx == ridx) { 1777 /* Ring is completely free */ 1778 nfree = le32toh(br->br_cmd_siz) - sizeof(struct txp_cmd_desc); 1779 } else { 1780 if (widx > ridx) 1781 nfree = le32toh(br->br_cmd_siz) - 1782 (widx - ridx + sizeof(struct txp_cmd_desc)); 1783 else 1784 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1785 } 1786 1787 return (nfree / sizeof(struct txp_cmd_desc)); 1788 } 1789 1790 void 1791 txp_stop(sc) 1792 struct txp_softc *sc; 1793 { 1794 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1795 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1796 1797 if (callout_pending(&sc->sc_tick)) 1798 callout_stop(&sc->sc_tick); 1799 } 1800 1801 void 1802 txp_watchdog(ifp) 1803 struct ifnet *ifp; 1804 { 1805 } 1806 1807 int 1808 txp_ifmedia_upd(ifp) 1809 struct ifnet *ifp; 1810 { 1811 struct txp_softc *sc = ifp->if_softc; 1812 struct ifmedia *ifm = &sc->sc_ifmedia; 1813 u_int16_t new_xcvr; 1814 1815 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1816 return (EINVAL); 1817 1818 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1819 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1820 new_xcvr = TXP_XCVR_10_FDX; 1821 else 1822 new_xcvr = TXP_XCVR_10_HDX; 1823 } else if ((IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) || 1824 (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX)) { 1825 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1826 new_xcvr = TXP_XCVR_100_FDX; 1827 else 1828 new_xcvr = TXP_XCVR_100_HDX; 1829 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1830 new_xcvr = TXP_XCVR_AUTO; 1831 } else 1832 return (EINVAL); 1833 1834 /* nothing to do */ 1835 if (sc->sc_xcvr == new_xcvr) 1836 return (0); 1837 1838 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1839 NULL, NULL, NULL, 0); 1840 sc->sc_xcvr = new_xcvr; 1841 1842 return (0); 1843 } 1844 1845 void 1846 txp_ifmedia_sts(ifp, ifmr) 1847 struct ifnet *ifp; 1848 struct ifmediareq *ifmr; 1849 { 1850 struct txp_softc *sc = ifp->if_softc; 1851 struct ifmedia *ifm = &sc->sc_ifmedia; 1852 u_int16_t bmsr, bmcr, anlpar; 1853 1854 ifmr->ifm_status = IFM_AVALID; 1855 ifmr->ifm_active = IFM_ETHER; 1856 1857 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1858 &bmsr, NULL, NULL, 1)) 1859 goto bail; 1860 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1861 &bmsr, NULL, NULL, 1)) 1862 goto bail; 1863 1864 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1865 &bmcr, NULL, NULL, 1)) 1866 goto bail; 1867 1868 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1869 &anlpar, NULL, NULL, 1)) 1870 goto bail; 1871 1872 if (bmsr & BMSR_LINK) 1873 ifmr->ifm_status |= IFM_ACTIVE; 1874 1875 if (bmcr & BMCR_ISO) { 1876 ifmr->ifm_active |= IFM_NONE; 1877 ifmr->ifm_status = 0; 1878 return; 1879 } 1880 1881 if (bmcr & BMCR_LOOP) 1882 ifmr->ifm_active |= IFM_LOOP; 1883 1884 if (!(sc->sc_flags & TXP_FIBER) && (bmcr & BMCR_AUTOEN)) { 1885 if ((bmsr & BMSR_ACOMP) == 0) { 1886 ifmr->ifm_active |= IFM_NONE; 1887 return; 1888 } 1889 1890 if (anlpar & ANLPAR_T4) 1891 ifmr->ifm_active |= IFM_100_T4; 1892 else if (anlpar & ANLPAR_TX_FD) 1893 ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1894 else if (anlpar & ANLPAR_TX) 1895 ifmr->ifm_active |= IFM_100_TX; 1896 else if (anlpar & ANLPAR_10_FD) 1897 ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1898 else if (anlpar & ANLPAR_10) 1899 ifmr->ifm_active |= IFM_10_T; 1900 else 1901 ifmr->ifm_active |= IFM_NONE; 1902 } else 1903 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1904 return; 1905 1906 bail: 1907 ifmr->ifm_active |= IFM_NONE; 1908 ifmr->ifm_status &= ~IFM_AVALID; 1909 } 1910 1911 void 1912 txp_show_descriptor(d) 1913 void *d; 1914 { 1915 struct txp_cmd_desc *cmd = d; 1916 struct txp_rsp_desc *rsp = d; 1917 struct txp_tx_desc *txd = d; 1918 struct txp_frag_desc *frgd = d; 1919 1920 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1921 case CMD_FLAGS_TYPE_CMD: 1922 /* command descriptor */ 1923 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1924 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1925 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1926 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1927 break; 1928 case CMD_FLAGS_TYPE_RESP: 1929 /* response descriptor */ 1930 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1931 rsp->rsp_flags, rsp->rsp_numdesc, le16toh(rsp->rsp_id), 1932 le16toh(rsp->rsp_seq), le16toh(rsp->rsp_par1), 1933 le32toh(rsp->rsp_par2), le32toh(rsp->rsp_par3)); 1934 break; 1935 case CMD_FLAGS_TYPE_DATA: 1936 /* data header (assuming tx for now) */ 1937 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]", 1938 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1939 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1940 break; 1941 case CMD_FLAGS_TYPE_FRAG: 1942 /* fragment descriptor */ 1943 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]", 1944 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1945 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1946 break; 1947 default: 1948 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1949 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1950 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1951 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1952 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1953 break; 1954 } 1955 } 1956 1957 void 1958 txp_set_filter(sc) 1959 struct txp_softc *sc; 1960 { 1961 struct ethercom *ac = &sc->sc_arpcom; 1962 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1963 u_int32_t crc, carry, hashbit, hash[2]; 1964 u_int16_t filter; 1965 u_int8_t octet; 1966 int i, j, mcnt = 0; 1967 struct ether_multi *enm; 1968 struct ether_multistep step; 1969 1970 if (ifp->if_flags & IFF_PROMISC) { 1971 filter = TXP_RXFILT_PROMISC; 1972 goto setit; 1973 } 1974 1975 again: 1976 filter = TXP_RXFILT_DIRECT; 1977 1978 if (ifp->if_flags & IFF_BROADCAST) 1979 filter |= TXP_RXFILT_BROADCAST; 1980 1981 if (ifp->if_flags & IFF_ALLMULTI) 1982 filter |= TXP_RXFILT_ALLMULTI; 1983 else { 1984 hash[0] = hash[1] = 0; 1985 1986 ETHER_FIRST_MULTI(step, ac, enm); 1987 while (enm != NULL) { 1988 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1989 /* 1990 * We must listen to a range of multicast 1991 * addresses. For now, just accept all 1992 * multicasts, rather than trying to set only 1993 * those filter bits needed to match the range. 1994 * (At this time, the only use of address 1995 * ranges is for IP multicast routing, for 1996 * which the range is big enough to require 1997 * all bits set.) 1998 */ 1999 ifp->if_flags |= IFF_ALLMULTI; 2000 goto again; 2001 } 2002 2003 mcnt++; 2004 crc = 0xffffffff; 2005 2006 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2007 octet = enm->enm_addrlo[i]; 2008 for (j = 0; j < 8; j++) { 2009 carry = ((crc & 0x80000000) ? 1 : 0) ^ 2010 (octet & 1); 2011 crc <<= 1; 2012 octet >>= 1; 2013 if (carry) 2014 crc = (crc ^ TXP_POLYNOMIAL) | 2015 carry; 2016 } 2017 } 2018 hashbit = (u_int16_t)(crc & (64 - 1)); 2019 hash[hashbit / 32] |= (1 << hashbit % 32); 2020 ETHER_NEXT_MULTI(step, enm); 2021 } 2022 2023 if (mcnt > 0) { 2024 filter |= TXP_RXFILT_HASHMULTI; 2025 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 2026 2, hash[0], hash[1], NULL, NULL, NULL, 0); 2027 } 2028 } 2029 2030 setit: 2031 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 2032 NULL, NULL, NULL, 1); 2033 } 2034 2035 void 2036 txp_capabilities(sc) 2037 struct txp_softc *sc; 2038 { 2039 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 2040 struct txp_rsp_desc *rsp = NULL; 2041 struct txp_ext_desc *ext; 2042 2043 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 2044 goto out; 2045 2046 if (rsp->rsp_numdesc != 1) 2047 goto out; 2048 ext = (struct txp_ext_desc *)(rsp + 1); 2049 2050 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 2051 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 2052 2053 #if NVLAN > 0 2054 ifp->if_capabilities |= IFCAP_VLAN_MTU; 2055 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 2056 sc->sc_tx_capability |= OFFLOAD_VLAN; 2057 sc->sc_rx_capability |= OFFLOAD_VLAN; 2058 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 2059 } 2060 #endif 2061 2062 #if 0 2063 /* not ready yet */ 2064 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 2065 sc->sc_tx_capability |= OFFLOAD_IPSEC; 2066 sc->sc_rx_capability |= OFFLOAD_IPSEC; 2067 ifp->if_capabilities |= IFCAP_IPSEC; 2068 } 2069 #endif 2070 2071 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 2072 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 2073 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 2074 ifp->if_capabilities |= IFCAP_CSUM_IPv4; 2075 } 2076 2077 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 2078 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 2079 #ifdef TRY_TX_TCP_CSUM 2080 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 2081 ifp->if_capabilities |= IFCAP_CSUM_TCPv4; 2082 #endif 2083 } 2084 2085 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 2086 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 2087 #ifdef TRY_TX_UDP_CSUM 2088 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 2089 ifp->if_capabilities |= IFCAP_CSUM_UDPv4; 2090 #endif 2091 } 2092 2093 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 2094 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 2095 goto out; 2096 2097 out: 2098 if (rsp != NULL) 2099 free(rsp, M_DEVBUF); 2100 } 2101