1 /* $NetBSD: if_txp.c,v 1.33 2009/03/18 17:06:50 cegger Exp $ */ 2 3 /* 4 * Copyright (c) 2001 5 * Jason L. Wright <jason@thought.net>, Theo de Raadt, and 6 * Aaron Campbell <aaron@monkey.org>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR THE VOICES IN THEIR HEADS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Driver for 3c990 (Typhoon) Ethernet ASIC 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: if_txp.c,v 1.33 2009/03/18 17:06:50 cegger Exp $"); 36 37 #include "bpfilter.h" 38 #include "opt_inet.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/sockio.h> 43 #include <sys/mbuf.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/device.h> 48 #include <sys/callout.h> 49 50 #include <net/if.h> 51 #include <net/if_dl.h> 52 #include <net/if_types.h> 53 #include <net/if_ether.h> 54 #include <net/if_arp.h> 55 56 #ifdef INET 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/in_var.h> 60 #include <netinet/ip.h> 61 #include <netinet/if_inarp.h> 62 #endif 63 64 #include <net/if_media.h> 65 66 #if NBPFILTER > 0 67 #include <net/bpf.h> 68 #endif 69 70 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 71 #include <sys/bus.h> 72 73 #include <dev/mii/mii.h> 74 #include <dev/mii/miivar.h> 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/pcidevs.h> 78 79 #include <dev/pci/if_txpreg.h> 80 81 #include <dev/microcode/typhoon/3c990img.h> 82 83 /* 84 * These currently break the 3c990 firmware, hopefully will be resolved 85 * at some point. 86 */ 87 #undef TRY_TX_UDP_CSUM 88 #undef TRY_TX_TCP_CSUM 89 90 int txp_probe(device_t, cfdata_t, void *); 91 void txp_attach(device_t, device_t, void *); 92 int txp_intr(void *); 93 void txp_tick(void *); 94 void txp_shutdown(void *); 95 int txp_ioctl(struct ifnet *, u_long, void *); 96 void txp_start(struct ifnet *); 97 void txp_stop(struct txp_softc *); 98 void txp_init(struct txp_softc *); 99 void txp_watchdog(struct ifnet *); 100 101 int txp_chip_init(struct txp_softc *); 102 int txp_reset_adapter(struct txp_softc *); 103 int txp_download_fw(struct txp_softc *); 104 int txp_download_fw_wait(struct txp_softc *); 105 int txp_download_fw_section(struct txp_softc *, 106 const struct txp_fw_section_header *, int); 107 int txp_alloc_rings(struct txp_softc *); 108 void txp_dma_free(struct txp_softc *, struct txp_dma_alloc *); 109 int txp_dma_malloc(struct txp_softc *, bus_size_t, struct txp_dma_alloc *, int); 110 void txp_set_filter(struct txp_softc *); 111 112 int txp_cmd_desc_numfree(struct txp_softc *); 113 int txp_command(struct txp_softc *, u_int16_t, u_int16_t, u_int32_t, 114 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int); 115 int txp_command2(struct txp_softc *, u_int16_t, u_int16_t, 116 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t, 117 struct txp_rsp_desc **, int); 118 int txp_response(struct txp_softc *, u_int32_t, u_int16_t, u_int16_t, 119 struct txp_rsp_desc **); 120 void txp_rsp_fixup(struct txp_softc *, struct txp_rsp_desc *, 121 struct txp_rsp_desc *); 122 void txp_capabilities(struct txp_softc *); 123 124 void txp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 125 int txp_ifmedia_upd(struct ifnet *); 126 void txp_show_descriptor(void *); 127 void txp_tx_reclaim(struct txp_softc *, struct txp_tx_ring *, 128 struct txp_dma_alloc *); 129 void txp_rxbuf_reclaim(struct txp_softc *); 130 void txp_rx_reclaim(struct txp_softc *, struct txp_rx_ring *, 131 struct txp_dma_alloc *); 132 133 CFATTACH_DECL(txp, sizeof(struct txp_softc), txp_probe, txp_attach, 134 NULL, NULL); 135 136 const struct txp_pci_match { 137 int vid, did, flags; 138 } txp_devices[] = { 139 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990, 0 }, 140 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX95, 0 }, 141 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX97, 0 }, 142 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR95, TXP_SERVERVERSION }, 143 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR97, TXP_SERVERVERSION }, 144 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990B, TXP_USESUBSYSTEM }, 145 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BSVR, TXP_SERVERVERSION }, 146 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990FX, TXP_USESUBSYSTEM }, 147 }; 148 149 static const struct txp_pci_match *txp_pcilookup(pcireg_t); 150 151 static const struct { 152 u_int16_t mask, value; 153 int flags; 154 } txp_subsysinfo[] = { 155 {0xf000, 0x2000, TXP_SERVERVERSION}, 156 {0x0100, 0x0100, TXP_FIBER}, 157 #if 0 /* information from 3com header, unused */ 158 {0x0010, 0x0010, /* secured firmware */}, 159 {0x0003, 0x0000, /* variable DES */}, 160 {0x0003, 0x0001, /* single DES - "95" */}, 161 {0x0003, 0x0002, /* triple DES - "97" */}, 162 #endif 163 }; 164 165 static const struct txp_pci_match * 166 txp_pcilookup(pcireg_t id) 167 { 168 int i; 169 170 for (i = 0; i < __arraycount(txp_devices); i++) 171 if (PCI_VENDOR(id) == txp_devices[i].vid && 172 PCI_PRODUCT(id) == txp_devices[i].did) 173 return &txp_devices[i]; 174 return (0); 175 } 176 177 int 178 txp_probe(device_t parent, cfdata_t match, void *aux) 179 { 180 struct pci_attach_args *pa = aux; 181 182 if (txp_pcilookup(pa->pa_id)) 183 return (1); 184 return (0); 185 } 186 187 void 188 txp_attach(device_t parent, device_t self, void *aux) 189 { 190 struct txp_softc *sc = device_private(self); 191 struct pci_attach_args *pa = aux; 192 pci_chipset_tag_t pc = pa->pa_pc; 193 pci_intr_handle_t ih; 194 const char *intrstr = NULL; 195 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 196 u_int32_t command; 197 u_int16_t p1; 198 u_int32_t p2; 199 u_char enaddr[6]; 200 const struct txp_pci_match *match; 201 u_int16_t subsys; 202 int i, flags; 203 char devinfo[256]; 204 205 sc->sc_cold = 1; 206 207 match = txp_pcilookup(pa->pa_id); 208 flags = match->flags; 209 if (match->flags & TXP_USESUBSYSTEM) { 210 subsys = PCI_PRODUCT(pci_conf_read(pc, pa->pa_tag, 211 PCI_SUBSYS_ID_REG)); 212 for (i = 0; 213 i < sizeof(txp_subsysinfo)/sizeof(txp_subsysinfo[0]); 214 i++) 215 if ((subsys & txp_subsysinfo[i].mask) == 216 txp_subsysinfo[i].value) 217 flags |= txp_subsysinfo[i].flags; 218 } 219 sc->sc_flags = flags; 220 221 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 222 #define TXP_EXTRAINFO ((flags & (TXP_USESUBSYSTEM|TXP_SERVERVERSION)) == \ 223 (TXP_USESUBSYSTEM|TXP_SERVERVERSION) ? " (SVR)" : "") 224 printf(": %s%s\n%s", devinfo, TXP_EXTRAINFO, device_xname(&sc->sc_dev)); 225 226 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 227 228 if (!(command & PCI_COMMAND_MASTER_ENABLE)) { 229 printf(": failed to enable bus mastering\n"); 230 return; 231 } 232 233 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 234 printf(": failed to enable memory mapping\n"); 235 return; 236 } 237 if (pci_mapreg_map(pa, TXP_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 238 &sc->sc_bt, &sc->sc_bh, NULL, NULL)) { 239 printf(": can't map mem space %d\n", 0); 240 return; 241 } 242 243 sc->sc_dmat = pa->pa_dmat; 244 245 /* 246 * Allocate our interrupt. 247 */ 248 if (pci_intr_map(pa, &ih)) { 249 printf(": couldn't map interrupt\n"); 250 return; 251 } 252 253 intrstr = pci_intr_string(pc, ih); 254 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, txp_intr, sc); 255 if (sc->sc_ih == NULL) { 256 printf(": couldn't establish interrupt"); 257 if (intrstr != NULL) 258 printf(" at %s", intrstr); 259 printf("\n"); 260 return; 261 } 262 printf(": interrupting at %s\n", intrstr); 263 264 if (txp_chip_init(sc)) 265 goto cleanupintr; 266 267 if (txp_download_fw(sc)) 268 goto cleanupintr; 269 270 if (txp_alloc_rings(sc)) 271 goto cleanupintr; 272 273 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 274 NULL, NULL, NULL, 1)) 275 goto cleanupintr; 276 277 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 278 &p1, &p2, NULL, 1)) 279 goto cleanupintr; 280 281 txp_set_filter(sc); 282 283 p1 = htole16(p1); 284 enaddr[0] = ((u_int8_t *)&p1)[1]; 285 enaddr[1] = ((u_int8_t *)&p1)[0]; 286 p2 = htole32(p2); 287 enaddr[2] = ((u_int8_t *)&p2)[3]; 288 enaddr[3] = ((u_int8_t *)&p2)[2]; 289 enaddr[4] = ((u_int8_t *)&p2)[1]; 290 enaddr[5] = ((u_int8_t *)&p2)[0]; 291 292 printf("%s: Ethernet address %s\n", device_xname(&sc->sc_dev), 293 ether_sprintf(enaddr)); 294 sc->sc_cold = 0; 295 296 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 297 if (flags & TXP_FIBER) { 298 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX, 299 0, NULL); 300 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX|IFM_HDX, 301 0, NULL); 302 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX|IFM_FDX, 303 0, NULL); 304 } else { 305 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 306 0, NULL); 307 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 308 0, NULL); 309 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 310 0, NULL); 311 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 312 0, NULL); 313 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 314 0, NULL); 315 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 316 0, NULL); 317 } 318 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 319 320 sc->sc_xcvr = TXP_XCVR_AUTO; 321 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 322 NULL, NULL, NULL, 0); 323 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 324 325 ifp->if_softc = sc; 326 ifp->if_mtu = ETHERMTU; 327 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 328 ifp->if_ioctl = txp_ioctl; 329 ifp->if_start = txp_start; 330 ifp->if_watchdog = txp_watchdog; 331 ifp->if_baudrate = 10000000; 332 IFQ_SET_MAXLEN(&ifp->if_snd, TX_ENTRIES); 333 IFQ_SET_READY(&ifp->if_snd); 334 ifp->if_capabilities = 0; 335 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 336 337 txp_capabilities(sc); 338 339 callout_init(&sc->sc_tick, 0); 340 callout_setfunc(&sc->sc_tick, txp_tick, sc); 341 342 /* 343 * Attach us everywhere 344 */ 345 if_attach(ifp); 346 ether_ifattach(ifp, enaddr); 347 348 shutdownhook_establish(txp_shutdown, sc); 349 350 351 return; 352 353 cleanupintr: 354 pci_intr_disestablish(pc,sc->sc_ih); 355 356 return; 357 358 } 359 360 int 361 txp_chip_init(struct txp_softc *sc) 362 { 363 /* disable interrupts */ 364 WRITE_REG(sc, TXP_IER, 0); 365 WRITE_REG(sc, TXP_IMR, 366 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 367 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 368 TXP_INT_LATCH); 369 370 /* ack all interrupts */ 371 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 372 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 373 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 374 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 375 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 376 377 if (txp_reset_adapter(sc)) 378 return (-1); 379 380 /* disable interrupts */ 381 WRITE_REG(sc, TXP_IER, 0); 382 WRITE_REG(sc, TXP_IMR, 383 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 384 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 385 TXP_INT_LATCH); 386 387 /* ack all interrupts */ 388 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 389 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 390 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 391 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 392 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 393 394 return (0); 395 } 396 397 int 398 txp_reset_adapter(struct txp_softc *sc) 399 { 400 u_int32_t r; 401 int i; 402 403 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 404 DELAY(1000); 405 WRITE_REG(sc, TXP_SRR, 0); 406 407 /* Should wait max 6 seconds */ 408 for (i = 0; i < 6000; i++) { 409 r = READ_REG(sc, TXP_A2H_0); 410 if (r == STAT_WAITING_FOR_HOST_REQUEST) 411 break; 412 DELAY(1000); 413 } 414 415 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 416 printf("%s: reset hung\n", TXP_DEVNAME(sc)); 417 return (-1); 418 } 419 420 return (0); 421 } 422 423 int 424 txp_download_fw(struct txp_softc *sc) 425 { 426 const struct txp_fw_file_header *fileheader; 427 const struct txp_fw_section_header *secthead; 428 int sect; 429 u_int32_t r, i, ier, imr; 430 431 ier = READ_REG(sc, TXP_IER); 432 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 433 434 imr = READ_REG(sc, TXP_IMR); 435 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 436 437 for (i = 0; i < 10000; i++) { 438 r = READ_REG(sc, TXP_A2H_0); 439 if (r == STAT_WAITING_FOR_HOST_REQUEST) 440 break; 441 DELAY(50); 442 } 443 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 444 printf(": not waiting for host request\n"); 445 return (-1); 446 } 447 448 /* Ack the status */ 449 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 450 451 fileheader = (const struct txp_fw_file_header *)tc990image; 452 if (memcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) { 453 printf(": fw invalid magic\n"); 454 return (-1); 455 } 456 457 /* Tell boot firmware to get ready for image */ 458 WRITE_REG(sc, TXP_H2A_1, le32toh(fileheader->addr)); 459 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 460 461 if (txp_download_fw_wait(sc)) { 462 printf("%s: fw wait failed, initial\n", device_xname(&sc->sc_dev)); 463 return (-1); 464 } 465 466 secthead = (const struct txp_fw_section_header *) 467 (((const u_int8_t *)tc990image) + 468 sizeof(struct txp_fw_file_header)); 469 470 for (sect = 0; sect < le32toh(fileheader->nsections); sect++) { 471 if (txp_download_fw_section(sc, secthead, sect)) 472 return (-1); 473 secthead = (const struct txp_fw_section_header *) 474 (((const u_int8_t *)secthead) + le32toh(secthead->nbytes) + 475 sizeof(*secthead)); 476 } 477 478 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 479 480 for (i = 0; i < 10000; i++) { 481 r = READ_REG(sc, TXP_A2H_0); 482 if (r == STAT_WAITING_FOR_BOOT) 483 break; 484 DELAY(50); 485 } 486 if (r != STAT_WAITING_FOR_BOOT) { 487 printf(": not waiting for boot\n"); 488 return (-1); 489 } 490 491 WRITE_REG(sc, TXP_IER, ier); 492 WRITE_REG(sc, TXP_IMR, imr); 493 494 return (0); 495 } 496 497 int 498 txp_download_fw_wait(struct txp_softc *sc) 499 { 500 u_int32_t i, r; 501 502 for (i = 0; i < 10000; i++) { 503 r = READ_REG(sc, TXP_ISR); 504 if (r & TXP_INT_A2H_0) 505 break; 506 DELAY(50); 507 } 508 509 if (!(r & TXP_INT_A2H_0)) { 510 printf(": fw wait failed comm0\n"); 511 return (-1); 512 } 513 514 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 515 516 r = READ_REG(sc, TXP_A2H_0); 517 if (r != STAT_WAITING_FOR_SEGMENT) { 518 printf(": fw not waiting for segment\n"); 519 return (-1); 520 } 521 return (0); 522 } 523 524 int 525 txp_download_fw_section(struct txp_softc *sc, const struct txp_fw_section_header *sect, int sectnum) 526 { 527 struct txp_dma_alloc dma; 528 int rseg, err = 0; 529 struct mbuf m; 530 #ifdef INET 531 u_int16_t csum; 532 #endif 533 534 /* Skip zero length sections */ 535 if (sect->nbytes == 0) 536 return (0); 537 538 /* Make sure we aren't past the end of the image */ 539 rseg = ((const u_int8_t *)sect) - ((const u_int8_t *)tc990image); 540 if (rseg >= sizeof(tc990image)) { 541 printf(": fw invalid section address, section %d\n", sectnum); 542 return (-1); 543 } 544 545 /* Make sure this section doesn't go past the end */ 546 rseg += le32toh(sect->nbytes); 547 if (rseg >= sizeof(tc990image)) { 548 printf(": fw truncated section %d\n", sectnum); 549 return (-1); 550 } 551 552 /* map a buffer, copy segment to it, get physaddr */ 553 if (txp_dma_malloc(sc, le32toh(sect->nbytes), &dma, 0)) { 554 printf(": fw dma malloc failed, section %d\n", sectnum); 555 return (-1); 556 } 557 558 memcpy( dma.dma_vaddr, ((const u_int8_t *)sect) + sizeof(*sect), 559 le32toh(sect->nbytes)); 560 561 /* 562 * dummy up mbuf and verify section checksum 563 */ 564 m.m_type = MT_DATA; 565 m.m_next = m.m_nextpkt = NULL; 566 m.m_len = le32toh(sect->nbytes); 567 m.m_data = dma.dma_vaddr; 568 m.m_flags = 0; 569 #ifdef INET 570 csum = in_cksum(&m, le32toh(sect->nbytes)); 571 if (csum != sect->cksum) { 572 printf(": fw section %d, bad cksum (expected 0x%x got 0x%x)\n", 573 sectnum, sect->cksum, csum); 574 txp_dma_free(sc, &dma); 575 return -1; 576 } 577 #endif 578 579 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 580 dma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 581 582 WRITE_REG(sc, TXP_H2A_1, le32toh(sect->nbytes)); 583 WRITE_REG(sc, TXP_H2A_2, le32toh(sect->cksum)); 584 WRITE_REG(sc, TXP_H2A_3, le32toh(sect->addr)); 585 WRITE_REG(sc, TXP_H2A_4, dma.dma_paddr >> 32); 586 WRITE_REG(sc, TXP_H2A_5, dma.dma_paddr & 0xffffffff); 587 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 588 589 if (txp_download_fw_wait(sc)) { 590 printf("%s: fw wait failed, section %d\n", 591 device_xname(&sc->sc_dev), sectnum); 592 err = -1; 593 } 594 595 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 596 dma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 597 598 txp_dma_free(sc, &dma); 599 return (err); 600 } 601 602 int 603 txp_intr(void *vsc) 604 { 605 struct txp_softc *sc = vsc; 606 struct txp_hostvar *hv = sc->sc_hostvar; 607 u_int32_t isr; 608 int claimed = 0; 609 610 /* mask all interrupts */ 611 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 612 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 613 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 614 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 615 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 616 617 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 618 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 619 620 isr = READ_REG(sc, TXP_ISR); 621 while (isr) { 622 claimed = 1; 623 WRITE_REG(sc, TXP_ISR, isr); 624 625 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 626 txp_rx_reclaim(sc, &sc->sc_rxhir, &sc->sc_rxhiring_dma); 627 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 628 txp_rx_reclaim(sc, &sc->sc_rxlor, &sc->sc_rxloring_dma); 629 630 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 631 txp_rxbuf_reclaim(sc); 632 633 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 634 TXP_OFFSET2IDX(le32toh(*(sc->sc_txhir.r_off))))) 635 txp_tx_reclaim(sc, &sc->sc_txhir, &sc->sc_txhiring_dma); 636 637 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 638 TXP_OFFSET2IDX(le32toh(*(sc->sc_txlor.r_off))))) 639 txp_tx_reclaim(sc, &sc->sc_txlor, &sc->sc_txloring_dma); 640 641 isr = READ_REG(sc, TXP_ISR); 642 } 643 644 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 645 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 646 647 /* unmask all interrupts */ 648 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 649 650 txp_start(&sc->sc_arpcom.ec_if); 651 652 return (claimed); 653 } 654 655 void 656 txp_rx_reclaim(struct txp_softc *sc, struct txp_rx_ring *r, struct txp_dma_alloc *dma) 657 { 658 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 659 struct txp_rx_desc *rxd; 660 struct mbuf *m; 661 struct txp_swdesc *sd; 662 u_int32_t roff, woff; 663 int sumflags = 0; 664 int idx; 665 666 roff = le32toh(*r->r_roff); 667 woff = le32toh(*r->r_woff); 668 idx = roff / sizeof(struct txp_rx_desc); 669 rxd = r->r_desc + idx; 670 671 while (roff != woff) { 672 673 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 674 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 675 BUS_DMASYNC_POSTREAD); 676 677 if (rxd->rx_flags & RX_FLAGS_ERROR) { 678 printf("%s: error 0x%x\n", device_xname(&sc->sc_dev), 679 le32toh(rxd->rx_stat)); 680 ifp->if_ierrors++; 681 goto next; 682 } 683 684 /* retrieve stashed pointer */ 685 memcpy( &sd, __UNVOLATILE(&rxd->rx_vaddrlo), sizeof(sd)); 686 687 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 688 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 689 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 690 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 691 m = sd->sd_mbuf; 692 free(sd, M_DEVBUF); 693 m->m_pkthdr.len = m->m_len = le16toh(rxd->rx_len); 694 695 #ifdef __STRICT_ALIGNMENT 696 { 697 /* 698 * XXX Nice chip, except it won't accept "off by 2" 699 * buffers, so we're force to copy. Supposedly 700 * this will be fixed in a newer firmware rev 701 * and this will be temporary. 702 */ 703 struct mbuf *mnew; 704 705 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 706 if (mnew == NULL) { 707 m_freem(m); 708 goto next; 709 } 710 if (m->m_len > (MHLEN - 2)) { 711 MCLGET(mnew, M_DONTWAIT); 712 if (!(mnew->m_flags & M_EXT)) { 713 m_freem(mnew); 714 m_freem(m); 715 goto next; 716 } 717 } 718 mnew->m_pkthdr.rcvif = ifp; 719 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 720 mnew->m_data += 2; 721 memcpy( mnew->m_data, m->m_data, m->m_len); 722 m_freem(m); 723 m = mnew; 724 } 725 #endif 726 727 #if NBPFILTER > 0 728 /* 729 * Handle BPF listeners. Let the BPF user see the packet. 730 */ 731 if (ifp->if_bpf) 732 bpf_mtap(ifp->if_bpf, m); 733 #endif 734 735 if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMBAD)) 736 sumflags |= (M_CSUM_IPv4|M_CSUM_IPv4_BAD); 737 else if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMGOOD)) 738 sumflags |= M_CSUM_IPv4; 739 740 if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMBAD)) 741 sumflags |= (M_CSUM_TCPv4|M_CSUM_TCP_UDP_BAD); 742 else if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMGOOD)) 743 sumflags |= M_CSUM_TCPv4; 744 745 if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMBAD)) 746 sumflags |= (M_CSUM_UDPv4|M_CSUM_TCP_UDP_BAD); 747 else if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMGOOD)) 748 sumflags |= M_CSUM_UDPv4; 749 750 m->m_pkthdr.csum_flags = sumflags; 751 752 if (rxd->rx_stat & htole32(RX_STAT_VLAN)) { 753 VLAN_INPUT_TAG(ifp, m, htons(rxd->rx_vlan >> 16), 754 continue); 755 } 756 757 (*ifp->if_input)(ifp, m); 758 759 next: 760 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 761 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 762 BUS_DMASYNC_PREREAD); 763 764 roff += sizeof(struct txp_rx_desc); 765 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 766 idx = 0; 767 roff = 0; 768 rxd = r->r_desc; 769 } else { 770 idx++; 771 rxd++; 772 } 773 woff = le32toh(*r->r_woff); 774 } 775 776 *r->r_roff = htole32(woff); 777 } 778 779 void 780 txp_rxbuf_reclaim(struct txp_softc *sc) 781 { 782 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 783 struct txp_hostvar *hv = sc->sc_hostvar; 784 struct txp_rxbuf_desc *rbd; 785 struct txp_swdesc *sd; 786 u_int32_t i, end; 787 788 end = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_read_idx)); 789 i = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_write_idx)); 790 791 if (++i == RXBUF_ENTRIES) 792 i = 0; 793 794 rbd = sc->sc_rxbufs + i; 795 796 while (i != end) { 797 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 798 M_DEVBUF, M_NOWAIT); 799 if (sd == NULL) 800 break; 801 802 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 803 if (sd->sd_mbuf == NULL) 804 goto err_sd; 805 806 MCLGET(sd->sd_mbuf, M_DONTWAIT); 807 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 808 goto err_mbuf; 809 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 810 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 811 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 812 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) 813 goto err_mbuf; 814 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 815 BUS_DMA_NOWAIT)) { 816 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 817 goto err_mbuf; 818 } 819 820 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 821 i * sizeof(struct txp_rxbuf_desc), 822 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_POSTWRITE); 823 824 /* stash away pointer */ 825 memcpy( __UNVOLATILE(&rbd->rb_vaddrlo), &sd, sizeof(sd)); 826 827 rbd->rb_paddrlo = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 828 & 0xffffffff; 829 rbd->rb_paddrhi = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 830 >> 32; 831 832 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 833 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 834 835 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 836 i * sizeof(struct txp_rxbuf_desc), 837 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_PREWRITE); 838 839 hv->hv_rx_buf_write_idx = htole32(TXP_IDX2OFFSET(i)); 840 841 if (++i == RXBUF_ENTRIES) { 842 i = 0; 843 rbd = sc->sc_rxbufs; 844 } else 845 rbd++; 846 } 847 return; 848 849 err_mbuf: 850 m_freem(sd->sd_mbuf); 851 err_sd: 852 free(sd, M_DEVBUF); 853 } 854 855 /* 856 * Reclaim mbufs and entries from a transmit ring. 857 */ 858 void 859 txp_tx_reclaim(struct txp_softc *sc, struct txp_tx_ring *r, struct txp_dma_alloc *dma) 860 { 861 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 862 u_int32_t idx = TXP_OFFSET2IDX(le32toh(*(r->r_off))); 863 u_int32_t cons = r->r_cons, cnt = r->r_cnt; 864 struct txp_tx_desc *txd = r->r_desc + cons; 865 struct txp_swdesc *sd = sc->sc_txd + cons; 866 struct mbuf *m; 867 868 while (cons != idx) { 869 if (cnt == 0) 870 break; 871 872 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 873 cons * sizeof(struct txp_tx_desc), 874 sizeof(struct txp_tx_desc), 875 BUS_DMASYNC_POSTWRITE); 876 877 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 878 TX_FLAGS_TYPE_DATA) { 879 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 880 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 881 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 882 m = sd->sd_mbuf; 883 if (m != NULL) { 884 m_freem(m); 885 txd->tx_addrlo = 0; 886 txd->tx_addrhi = 0; 887 ifp->if_opackets++; 888 } 889 } 890 ifp->if_flags &= ~IFF_OACTIVE; 891 892 if (++cons == TX_ENTRIES) { 893 txd = r->r_desc; 894 cons = 0; 895 sd = sc->sc_txd; 896 } else { 897 txd++; 898 sd++; 899 } 900 901 cnt--; 902 } 903 904 r->r_cons = cons; 905 r->r_cnt = cnt; 906 if (cnt == 0) 907 ifp->if_timer = 0; 908 } 909 910 void 911 txp_shutdown(void *vsc) 912 { 913 struct txp_softc *sc = (struct txp_softc *)vsc; 914 915 /* mask all interrupts */ 916 WRITE_REG(sc, TXP_IMR, 917 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 918 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 919 TXP_INT_LATCH); 920 921 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 922 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 923 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 924 } 925 926 int 927 txp_alloc_rings(struct txp_softc *sc) 928 { 929 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 930 struct txp_boot_record *boot; 931 struct txp_swdesc *sd; 932 u_int32_t r; 933 int i, j, nb; 934 935 /* boot record */ 936 if (txp_dma_malloc(sc, sizeof(struct txp_boot_record), &sc->sc_boot_dma, 937 BUS_DMA_COHERENT)) { 938 printf(": can't allocate boot record\n"); 939 return (-1); 940 } 941 boot = (struct txp_boot_record *)sc->sc_boot_dma.dma_vaddr; 942 memset(boot, 0, sizeof(*boot)); 943 sc->sc_boot = boot; 944 945 /* host variables */ 946 if (txp_dma_malloc(sc, sizeof(struct txp_hostvar), &sc->sc_host_dma, 947 BUS_DMA_COHERENT)) { 948 printf(": can't allocate host ring\n"); 949 goto bail_boot; 950 } 951 memset(sc->sc_host_dma.dma_vaddr, 0, sizeof(struct txp_hostvar)); 952 boot->br_hostvar_lo = htole32(sc->sc_host_dma.dma_paddr & 0xffffffff); 953 boot->br_hostvar_hi = htole32(sc->sc_host_dma.dma_paddr >> 32); 954 sc->sc_hostvar = (struct txp_hostvar *)sc->sc_host_dma.dma_vaddr; 955 956 /* high priority tx ring */ 957 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 958 &sc->sc_txhiring_dma, BUS_DMA_COHERENT)) { 959 printf(": can't allocate high tx ring\n"); 960 goto bail_host; 961 } 962 memset(sc->sc_txhiring_dma.dma_vaddr, 0, sizeof(struct txp_tx_desc) * TX_ENTRIES); 963 boot->br_txhipri_lo = htole32(sc->sc_txhiring_dma.dma_paddr & 0xffffffff); 964 boot->br_txhipri_hi = htole32(sc->sc_txhiring_dma.dma_paddr >> 32); 965 boot->br_txhipri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 966 sc->sc_txhir.r_reg = TXP_H2A_1; 967 sc->sc_txhir.r_desc = (struct txp_tx_desc *)sc->sc_txhiring_dma.dma_vaddr; 968 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 969 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 970 for (i = 0; i < TX_ENTRIES; i++) { 971 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 972 TX_ENTRIES - 4, TXP_MAX_SEGLEN, 0, 973 BUS_DMA_NOWAIT, &sc->sc_txd[i].sd_map) != 0) { 974 for (j = 0; j < i; j++) { 975 bus_dmamap_destroy(sc->sc_dmat, 976 sc->sc_txd[j].sd_map); 977 sc->sc_txd[j].sd_map = NULL; 978 } 979 goto bail_txhiring; 980 } 981 } 982 983 /* low priority tx ring */ 984 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 985 &sc->sc_txloring_dma, BUS_DMA_COHERENT)) { 986 printf(": can't allocate low tx ring\n"); 987 goto bail_txhiring; 988 } 989 memset(sc->sc_txloring_dma.dma_vaddr, 0, sizeof(struct txp_tx_desc) * TX_ENTRIES); 990 boot->br_txlopri_lo = htole32(sc->sc_txloring_dma.dma_paddr & 0xffffffff); 991 boot->br_txlopri_hi = htole32(sc->sc_txloring_dma.dma_paddr >> 32); 992 boot->br_txlopri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 993 sc->sc_txlor.r_reg = TXP_H2A_3; 994 sc->sc_txlor.r_desc = (struct txp_tx_desc *)sc->sc_txloring_dma.dma_vaddr; 995 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 996 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 997 998 /* high priority rx ring */ 999 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1000 &sc->sc_rxhiring_dma, BUS_DMA_COHERENT)) { 1001 printf(": can't allocate high rx ring\n"); 1002 goto bail_txloring; 1003 } 1004 memset(sc->sc_rxhiring_dma.dma_vaddr, 0, sizeof(struct txp_rx_desc) * RX_ENTRIES); 1005 boot->br_rxhipri_lo = htole32(sc->sc_rxhiring_dma.dma_paddr & 0xffffffff); 1006 boot->br_rxhipri_hi = htole32(sc->sc_rxhiring_dma.dma_paddr >> 32); 1007 boot->br_rxhipri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1008 sc->sc_rxhir.r_desc = 1009 (struct txp_rx_desc *)sc->sc_rxhiring_dma.dma_vaddr; 1010 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 1011 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 1012 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxhiring_dma.dma_map, 1013 0, sc->sc_rxhiring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1014 1015 /* low priority ring */ 1016 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1017 &sc->sc_rxloring_dma, BUS_DMA_COHERENT)) { 1018 printf(": can't allocate low rx ring\n"); 1019 goto bail_rxhiring; 1020 } 1021 memset(sc->sc_rxloring_dma.dma_vaddr, 0, sizeof(struct txp_rx_desc) * RX_ENTRIES); 1022 boot->br_rxlopri_lo = htole32(sc->sc_rxloring_dma.dma_paddr & 0xffffffff); 1023 boot->br_rxlopri_hi = htole32(sc->sc_rxloring_dma.dma_paddr >> 32); 1024 boot->br_rxlopri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1025 sc->sc_rxlor.r_desc = 1026 (struct txp_rx_desc *)sc->sc_rxloring_dma.dma_vaddr; 1027 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 1028 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 1029 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxloring_dma.dma_map, 1030 0, sc->sc_rxloring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1031 1032 /* command ring */ 1033 if (txp_dma_malloc(sc, sizeof(struct txp_cmd_desc) * CMD_ENTRIES, 1034 &sc->sc_cmdring_dma, BUS_DMA_COHERENT)) { 1035 printf(": can't allocate command ring\n"); 1036 goto bail_rxloring; 1037 } 1038 memset(sc->sc_cmdring_dma.dma_vaddr, 0, sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 1039 boot->br_cmd_lo = htole32(sc->sc_cmdring_dma.dma_paddr & 0xffffffff); 1040 boot->br_cmd_hi = htole32(sc->sc_cmdring_dma.dma_paddr >> 32); 1041 boot->br_cmd_siz = htole32(CMD_ENTRIES * sizeof(struct txp_cmd_desc)); 1042 sc->sc_cmdring.base = (struct txp_cmd_desc *)sc->sc_cmdring_dma.dma_vaddr; 1043 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1044 sc->sc_cmdring.lastwrite = 0; 1045 1046 /* response ring */ 1047 if (txp_dma_malloc(sc, sizeof(struct txp_rsp_desc) * RSP_ENTRIES, 1048 &sc->sc_rspring_dma, BUS_DMA_COHERENT)) { 1049 printf(": can't allocate response ring\n"); 1050 goto bail_cmdring; 1051 } 1052 memset(sc->sc_rspring_dma.dma_vaddr, 0, sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 1053 boot->br_resp_lo = htole32(sc->sc_rspring_dma.dma_paddr & 0xffffffff); 1054 boot->br_resp_hi = htole32(sc->sc_rspring_dma.dma_paddr >> 32); 1055 boot->br_resp_siz = htole32(CMD_ENTRIES * sizeof(struct txp_rsp_desc)); 1056 sc->sc_rspring.base = (struct txp_rsp_desc *)sc->sc_rspring_dma.dma_vaddr; 1057 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 1058 sc->sc_rspring.lastwrite = 0; 1059 1060 /* receive buffer ring */ 1061 if (txp_dma_malloc(sc, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES, 1062 &sc->sc_rxbufring_dma, BUS_DMA_COHERENT)) { 1063 printf(": can't allocate rx buffer ring\n"); 1064 goto bail_rspring; 1065 } 1066 memset(sc->sc_rxbufring_dma.dma_vaddr, 0, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES); 1067 boot->br_rxbuf_lo = htole32(sc->sc_rxbufring_dma.dma_paddr & 0xffffffff); 1068 boot->br_rxbuf_hi = htole32(sc->sc_rxbufring_dma.dma_paddr >> 32); 1069 boot->br_rxbuf_siz = htole32(RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc)); 1070 sc->sc_rxbufs = (struct txp_rxbuf_desc *)sc->sc_rxbufring_dma.dma_vaddr; 1071 for (nb = 0; nb < RXBUF_ENTRIES; nb++) { 1072 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 1073 M_DEVBUF, M_NOWAIT); 1074 /* stash away pointer */ 1075 memcpy( __UNVOLATILE(&sc->sc_rxbufs[nb].rb_vaddrlo), &sd, sizeof(sd)); 1076 if (sd == NULL) 1077 break; 1078 1079 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 1080 if (sd->sd_mbuf == NULL) { 1081 goto bail_rxbufring; 1082 } 1083 1084 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1085 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1086 goto bail_rxbufring; 1087 } 1088 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1089 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 1090 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 1091 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) { 1092 goto bail_rxbufring; 1093 } 1094 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 1095 BUS_DMA_NOWAIT)) { 1096 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 1097 goto bail_rxbufring; 1098 } 1099 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1100 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1101 1102 1103 sc->sc_rxbufs[nb].rb_paddrlo = 1104 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) & 0xffffffff; 1105 sc->sc_rxbufs[nb].rb_paddrhi = 1106 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) >> 32; 1107 } 1108 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 1109 0, sc->sc_rxbufring_dma.dma_map->dm_mapsize, 1110 BUS_DMASYNC_PREWRITE); 1111 sc->sc_hostvar->hv_rx_buf_write_idx = htole32((RXBUF_ENTRIES - 1) * 1112 sizeof(struct txp_rxbuf_desc)); 1113 1114 /* zero dma */ 1115 if (txp_dma_malloc(sc, sizeof(u_int32_t), &sc->sc_zero_dma, 1116 BUS_DMA_COHERENT)) { 1117 printf(": can't allocate response ring\n"); 1118 goto bail_rxbufring; 1119 } 1120 memset(sc->sc_zero_dma.dma_vaddr, 0, sizeof(u_int32_t)); 1121 boot->br_zero_lo = htole32(sc->sc_zero_dma.dma_paddr & 0xffffffff); 1122 boot->br_zero_hi = htole32(sc->sc_zero_dma.dma_paddr >> 32); 1123 1124 /* See if it's waiting for boot, and try to boot it */ 1125 for (i = 0; i < 10000; i++) { 1126 r = READ_REG(sc, TXP_A2H_0); 1127 if (r == STAT_WAITING_FOR_BOOT) 1128 break; 1129 DELAY(50); 1130 } 1131 if (r != STAT_WAITING_FOR_BOOT) { 1132 printf(": not waiting for boot\n"); 1133 goto bail; 1134 } 1135 WRITE_REG(sc, TXP_H2A_2, sc->sc_boot_dma.dma_paddr >> 32); 1136 WRITE_REG(sc, TXP_H2A_1, sc->sc_boot_dma.dma_paddr & 0xffffffff); 1137 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1138 1139 /* See if it booted */ 1140 for (i = 0; i < 10000; i++) { 1141 r = READ_REG(sc, TXP_A2H_0); 1142 if (r == STAT_RUNNING) 1143 break; 1144 DELAY(50); 1145 } 1146 if (r != STAT_RUNNING) { 1147 printf(": fw not running\n"); 1148 goto bail; 1149 } 1150 1151 /* Clear TX and CMD ring write registers */ 1152 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1153 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1154 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1155 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1156 1157 return (0); 1158 1159 bail: 1160 txp_dma_free(sc, &sc->sc_zero_dma); 1161 bail_rxbufring: 1162 if (nb == RXBUF_ENTRIES) 1163 nb--; 1164 for (i = 0; i <= nb; i++) { 1165 memcpy( &sd, __UNVOLATILE(&sc->sc_rxbufs[i].rb_vaddrlo), 1166 sizeof(sd)); 1167 if (sd) 1168 free(sd, M_DEVBUF); 1169 } 1170 txp_dma_free(sc, &sc->sc_rxbufring_dma); 1171 bail_rspring: 1172 txp_dma_free(sc, &sc->sc_rspring_dma); 1173 bail_cmdring: 1174 txp_dma_free(sc, &sc->sc_cmdring_dma); 1175 bail_rxloring: 1176 txp_dma_free(sc, &sc->sc_rxloring_dma); 1177 bail_rxhiring: 1178 txp_dma_free(sc, &sc->sc_rxhiring_dma); 1179 bail_txloring: 1180 txp_dma_free(sc, &sc->sc_txloring_dma); 1181 bail_txhiring: 1182 txp_dma_free(sc, &sc->sc_txhiring_dma); 1183 bail_host: 1184 txp_dma_free(sc, &sc->sc_host_dma); 1185 bail_boot: 1186 txp_dma_free(sc, &sc->sc_boot_dma); 1187 return (-1); 1188 } 1189 1190 int 1191 txp_dma_malloc(struct txp_softc *sc, bus_size_t size, struct txp_dma_alloc *dma, int mapflags) 1192 { 1193 int r; 1194 1195 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 1196 &dma->dma_seg, 1, &dma->dma_nseg, 0)) != 0) 1197 goto fail_0; 1198 1199 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 1200 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 1201 goto fail_1; 1202 1203 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1204 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 1205 goto fail_2; 1206 1207 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 1208 size, NULL, BUS_DMA_NOWAIT)) != 0) 1209 goto fail_3; 1210 1211 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 1212 return (0); 1213 1214 fail_3: 1215 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1216 fail_2: 1217 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 1218 fail_1: 1219 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1220 fail_0: 1221 return (r); 1222 } 1223 1224 void 1225 txp_dma_free(struct txp_softc *sc, struct txp_dma_alloc *dma) 1226 { 1227 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 1228 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_map->dm_mapsize); 1229 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1230 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1231 } 1232 1233 int 1234 txp_ioctl(struct ifnet *ifp, u_long command, void *data) 1235 { 1236 struct txp_softc *sc = ifp->if_softc; 1237 struct ifreq *ifr = (struct ifreq *)data; 1238 struct ifaddr *ifa = (struct ifaddr *)data; 1239 int s, error = 0; 1240 1241 s = splnet(); 1242 1243 #if 0 1244 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, command, data)) > 0) { 1245 splx(s); 1246 return error; 1247 } 1248 #endif 1249 1250 switch(command) { 1251 case SIOCINITIFADDR: 1252 ifp->if_flags |= IFF_UP; 1253 txp_init(sc); 1254 switch (ifa->ifa_addr->sa_family) { 1255 #ifdef INET 1256 case AF_INET: 1257 arp_ifinit(ifp, ifa); 1258 break; 1259 #endif /* INET */ 1260 default: 1261 break; 1262 } 1263 break; 1264 case SIOCSIFFLAGS: 1265 if ((error = ifioctl_common(ifp, command, data)) != 0) 1266 break; 1267 if (ifp->if_flags & IFF_UP) { 1268 txp_init(sc); 1269 } else { 1270 if (ifp->if_flags & IFF_RUNNING) 1271 txp_stop(sc); 1272 } 1273 break; 1274 case SIOCADDMULTI: 1275 case SIOCDELMULTI: 1276 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1277 break; 1278 1279 error = 0; 1280 1281 if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1282 ; 1283 else if (ifp->if_flags & IFF_RUNNING) { 1284 /* 1285 * Multicast list has changed; set the hardware 1286 * filter accordingly. 1287 */ 1288 txp_set_filter(sc); 1289 } 1290 break; 1291 case SIOCGIFMEDIA: 1292 case SIOCSIFMEDIA: 1293 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command); 1294 break; 1295 default: 1296 error = ether_ioctl(ifp, command, data); 1297 break; 1298 } 1299 1300 splx(s); 1301 1302 return(error); 1303 } 1304 1305 void 1306 txp_init(struct txp_softc *sc) 1307 { 1308 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1309 int s; 1310 1311 txp_stop(sc); 1312 1313 s = splnet(); 1314 1315 txp_set_filter(sc); 1316 1317 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1318 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1319 1320 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1321 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1322 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1323 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1324 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1325 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1326 1327 ifp->if_flags |= IFF_RUNNING; 1328 ifp->if_flags &= ~IFF_OACTIVE; 1329 ifp->if_timer = 0; 1330 1331 if (!callout_pending(&sc->sc_tick)) 1332 callout_schedule(&sc->sc_tick, hz); 1333 1334 splx(s); 1335 } 1336 1337 void 1338 txp_tick(void *vsc) 1339 { 1340 struct txp_softc *sc = vsc; 1341 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1342 struct txp_rsp_desc *rsp = NULL; 1343 struct txp_ext_desc *ext; 1344 int s; 1345 1346 s = splnet(); 1347 txp_rxbuf_reclaim(sc); 1348 1349 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1350 &rsp, 1)) 1351 goto out; 1352 if (rsp->rsp_numdesc != 6) 1353 goto out; 1354 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1355 NULL, NULL, NULL, 1)) 1356 goto out; 1357 ext = (struct txp_ext_desc *)(rsp + 1); 1358 1359 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1360 ext[4].ext_1 + ext[4].ext_4; 1361 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1362 ext[2].ext_1; 1363 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1364 ext[1].ext_3; 1365 ifp->if_opackets += rsp->rsp_par2; 1366 ifp->if_ipackets += ext[2].ext_3; 1367 1368 out: 1369 if (rsp != NULL) 1370 free(rsp, M_DEVBUF); 1371 1372 splx(s); 1373 callout_schedule(&sc->sc_tick, hz); 1374 } 1375 1376 void 1377 txp_start(struct ifnet *ifp) 1378 { 1379 struct txp_softc *sc = ifp->if_softc; 1380 struct txp_tx_ring *r = &sc->sc_txhir; 1381 struct txp_tx_desc *txd; 1382 int txdidx; 1383 struct txp_frag_desc *fxd; 1384 struct mbuf *m, *mnew; 1385 struct txp_swdesc *sd; 1386 u_int32_t firstprod, firstcnt, prod, cnt, i; 1387 struct m_tag *mtag; 1388 1389 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1390 return; 1391 1392 prod = r->r_prod; 1393 cnt = r->r_cnt; 1394 1395 while (1) { 1396 IFQ_POLL(&ifp->if_snd, m); 1397 if (m == NULL) 1398 break; 1399 mnew = NULL; 1400 1401 firstprod = prod; 1402 firstcnt = cnt; 1403 1404 sd = sc->sc_txd + prod; 1405 sd->sd_mbuf = m; 1406 1407 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1408 BUS_DMA_NOWAIT)) { 1409 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1410 if (mnew == NULL) 1411 goto oactive1; 1412 if (m->m_pkthdr.len > MHLEN) { 1413 MCLGET(mnew, M_DONTWAIT); 1414 if ((mnew->m_flags & M_EXT) == 0) { 1415 m_freem(mnew); 1416 goto oactive1; 1417 } 1418 } 1419 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, void *)); 1420 mnew->m_pkthdr.len = mnew->m_len = m->m_pkthdr.len; 1421 IFQ_DEQUEUE(&ifp->if_snd, m); 1422 m_freem(m); 1423 m = mnew; 1424 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1425 BUS_DMA_NOWAIT)) 1426 goto oactive1; 1427 } 1428 1429 if ((TX_ENTRIES - cnt) < 4) 1430 goto oactive; 1431 1432 txd = r->r_desc + prod; 1433 txdidx = prod; 1434 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1435 txd->tx_numdesc = 0; 1436 txd->tx_addrlo = 0; 1437 txd->tx_addrhi = 0; 1438 txd->tx_totlen = m->m_pkthdr.len; 1439 txd->tx_pflags = 0; 1440 txd->tx_numdesc = sd->sd_map->dm_nsegs; 1441 1442 if (++prod == TX_ENTRIES) 1443 prod = 0; 1444 1445 if (++cnt >= (TX_ENTRIES - 4)) 1446 goto oactive; 1447 1448 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_arpcom, m))) 1449 txd->tx_pflags = TX_PFLAGS_VLAN | 1450 (htons(VLAN_TAG_VALUE(mtag)) << TX_PFLAGS_VLANTAG_S); 1451 1452 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 1453 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1454 #ifdef TRY_TX_TCP_CSUM 1455 if (m->m_pkthdr.csum_flags & M_CSUM_TCPv4) 1456 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1457 #endif 1458 #ifdef TRY_TX_UDP_CSUM 1459 if (m->m_pkthdr.csum_flags & M_CSUM_UDPv4) 1460 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1461 #endif 1462 1463 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1464 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1465 1466 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1467 for (i = 0; i < sd->sd_map->dm_nsegs; i++) { 1468 if (++cnt >= (TX_ENTRIES - 4)) { 1469 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 1470 0, sd->sd_map->dm_mapsize, 1471 BUS_DMASYNC_POSTWRITE); 1472 goto oactive; 1473 } 1474 1475 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG | 1476 FRAG_FLAGS_VALID; 1477 fxd->frag_rsvd1 = 0; 1478 fxd->frag_len = sd->sd_map->dm_segs[i].ds_len; 1479 fxd->frag_addrlo = 1480 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) & 1481 0xffffffff; 1482 fxd->frag_addrhi = 1483 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) >> 1484 32; 1485 fxd->frag_rsvd2 = 0; 1486 1487 bus_dmamap_sync(sc->sc_dmat, 1488 sc->sc_txhiring_dma.dma_map, 1489 prod * sizeof(struct txp_frag_desc), 1490 sizeof(struct txp_frag_desc), BUS_DMASYNC_PREWRITE); 1491 1492 if (++prod == TX_ENTRIES) { 1493 fxd = (struct txp_frag_desc *)r->r_desc; 1494 prod = 0; 1495 } else 1496 fxd++; 1497 1498 } 1499 1500 /* 1501 * if mnew isn't NULL, we already dequeued and copied 1502 * the packet. 1503 */ 1504 if (mnew == NULL) 1505 IFQ_DEQUEUE(&ifp->if_snd, m); 1506 1507 ifp->if_timer = 5; 1508 1509 #if NBPFILTER > 0 1510 if (ifp->if_bpf) 1511 bpf_mtap(ifp->if_bpf, m); 1512 #endif 1513 1514 txd->tx_flags |= TX_FLAGS_VALID; 1515 bus_dmamap_sync(sc->sc_dmat, sc->sc_txhiring_dma.dma_map, 1516 txdidx * sizeof(struct txp_tx_desc), 1517 sizeof(struct txp_tx_desc), BUS_DMASYNC_PREWRITE); 1518 1519 #if 0 1520 { 1521 struct mbuf *mx; 1522 int i; 1523 1524 printf("txd: flags 0x%x ndesc %d totlen %d pflags 0x%x\n", 1525 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1526 txd->tx_pflags); 1527 for (mx = m; mx != NULL; mx = mx->m_next) { 1528 for (i = 0; i < mx->m_len; i++) { 1529 printf(":%02x", 1530 (u_int8_t)m->m_data[i]); 1531 } 1532 } 1533 printf("\n"); 1534 } 1535 #endif 1536 1537 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1538 } 1539 1540 r->r_prod = prod; 1541 r->r_cnt = cnt; 1542 return; 1543 1544 oactive: 1545 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 1546 oactive1: 1547 ifp->if_flags |= IFF_OACTIVE; 1548 r->r_prod = firstprod; 1549 r->r_cnt = firstcnt; 1550 } 1551 1552 /* 1553 * Handle simple commands sent to the typhoon 1554 */ 1555 int 1556 txp_command(struct txp_softc *sc, u_int16_t id, u_int16_t in1, u_int32_t in2, u_int32_t in3, u_int16_t *out1, u_int32_t *out2, u_int32_t *out3, int wait) 1557 { 1558 struct txp_rsp_desc *rsp = NULL; 1559 1560 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1561 return (-1); 1562 1563 if (!wait) 1564 return (0); 1565 1566 if (out1 != NULL) 1567 *out1 = le16toh(rsp->rsp_par1); 1568 if (out2 != NULL) 1569 *out2 = le32toh(rsp->rsp_par2); 1570 if (out3 != NULL) 1571 *out3 = le32toh(rsp->rsp_par3); 1572 free(rsp, M_DEVBUF); 1573 return (0); 1574 } 1575 1576 int 1577 txp_command2(struct txp_softc *sc, u_int16_t id, u_int16_t in1, u_int32_t in2, u_int32_t in3, struct txp_ext_desc *in_extp, u_int8_t in_extn, struct txp_rsp_desc **rspp, int wait) 1578 { 1579 struct txp_hostvar *hv = sc->sc_hostvar; 1580 struct txp_cmd_desc *cmd; 1581 struct txp_ext_desc *ext; 1582 u_int32_t idx, i; 1583 u_int16_t seq; 1584 1585 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1586 printf("%s: no free cmd descriptors\n", TXP_DEVNAME(sc)); 1587 return (-1); 1588 } 1589 1590 idx = sc->sc_cmdring.lastwrite; 1591 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1592 memset(cmd, 0, sizeof(*cmd)); 1593 1594 cmd->cmd_numdesc = in_extn; 1595 seq = sc->sc_seq++; 1596 cmd->cmd_seq = htole16(seq); 1597 cmd->cmd_id = htole16(id); 1598 cmd->cmd_par1 = htole16(in1); 1599 cmd->cmd_par2 = htole32(in2); 1600 cmd->cmd_par3 = htole32(in3); 1601 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1602 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1603 1604 idx += sizeof(struct txp_cmd_desc); 1605 if (idx == sc->sc_cmdring.size) 1606 idx = 0; 1607 1608 for (i = 0; i < in_extn; i++) { 1609 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1610 memcpy( ext, in_extp, sizeof(struct txp_ext_desc)); 1611 in_extp++; 1612 idx += sizeof(struct txp_cmd_desc); 1613 if (idx == sc->sc_cmdring.size) 1614 idx = 0; 1615 } 1616 1617 sc->sc_cmdring.lastwrite = idx; 1618 1619 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1620 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1621 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1622 1623 if (!wait) 1624 return (0); 1625 1626 for (i = 0; i < 10000; i++) { 1627 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1628 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTREAD); 1629 idx = le32toh(hv->hv_resp_read_idx); 1630 if (idx != le32toh(hv->hv_resp_write_idx)) { 1631 *rspp = NULL; 1632 if (txp_response(sc, idx, id, seq, rspp)) 1633 return (-1); 1634 if (*rspp != NULL) 1635 break; 1636 } 1637 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1638 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1639 DELAY(50); 1640 } 1641 if (i == 1000 || (*rspp) == NULL) { 1642 printf("%s: 0x%x command failed\n", TXP_DEVNAME(sc), id); 1643 return (-1); 1644 } 1645 1646 return (0); 1647 } 1648 1649 int 1650 txp_response(struct txp_softc *sc, u_int32_t ridx, u_int16_t id, u_int16_t seq, struct txp_rsp_desc **rspp) 1651 { 1652 struct txp_hostvar *hv = sc->sc_hostvar; 1653 struct txp_rsp_desc *rsp; 1654 1655 while (ridx != le32toh(hv->hv_resp_write_idx)) { 1656 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx); 1657 1658 if (id == le16toh(rsp->rsp_id) && le16toh(rsp->rsp_seq) == seq) { 1659 *rspp = (struct txp_rsp_desc *)malloc( 1660 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1661 M_DEVBUF, M_NOWAIT); 1662 if ((*rspp) == NULL) 1663 return (-1); 1664 txp_rsp_fixup(sc, rsp, *rspp); 1665 return (0); 1666 } 1667 1668 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1669 printf("%s: response error: id 0x%x\n", 1670 TXP_DEVNAME(sc), le16toh(rsp->rsp_id)); 1671 txp_rsp_fixup(sc, rsp, NULL); 1672 ridx = le32toh(hv->hv_resp_read_idx); 1673 continue; 1674 } 1675 1676 switch (le16toh(rsp->rsp_id)) { 1677 case TXP_CMD_CYCLE_STATISTICS: 1678 case TXP_CMD_MEDIA_STATUS_READ: 1679 break; 1680 case TXP_CMD_HELLO_RESPONSE: 1681 printf("%s: hello\n", TXP_DEVNAME(sc)); 1682 break; 1683 default: 1684 printf("%s: unknown id(0x%x)\n", TXP_DEVNAME(sc), 1685 le16toh(rsp->rsp_id)); 1686 } 1687 1688 txp_rsp_fixup(sc, rsp, NULL); 1689 ridx = le32toh(hv->hv_resp_read_idx); 1690 hv->hv_resp_read_idx = le32toh(ridx); 1691 } 1692 1693 return (0); 1694 } 1695 1696 void 1697 txp_rsp_fixup(struct txp_softc *sc, struct txp_rsp_desc *rsp, struct txp_rsp_desc *dst) 1698 { 1699 struct txp_rsp_desc *src = rsp; 1700 struct txp_hostvar *hv = sc->sc_hostvar; 1701 u_int32_t i, ridx; 1702 1703 ridx = le32toh(hv->hv_resp_read_idx); 1704 1705 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1706 if (dst != NULL) 1707 memcpy( dst++, src, sizeof(struct txp_rsp_desc)); 1708 ridx += sizeof(struct txp_rsp_desc); 1709 if (ridx == sc->sc_rspring.size) { 1710 src = sc->sc_rspring.base; 1711 ridx = 0; 1712 } else 1713 src++; 1714 sc->sc_rspring.lastwrite = ridx; 1715 hv->hv_resp_read_idx = htole32(ridx); 1716 } 1717 1718 hv->hv_resp_read_idx = htole32(ridx); 1719 } 1720 1721 int 1722 txp_cmd_desc_numfree(struct txp_softc *sc) 1723 { 1724 struct txp_hostvar *hv = sc->sc_hostvar; 1725 struct txp_boot_record *br = sc->sc_boot; 1726 u_int32_t widx, ridx, nfree; 1727 1728 widx = sc->sc_cmdring.lastwrite; 1729 ridx = le32toh(hv->hv_cmd_read_idx); 1730 1731 if (widx == ridx) { 1732 /* Ring is completely free */ 1733 nfree = le32toh(br->br_cmd_siz) - sizeof(struct txp_cmd_desc); 1734 } else { 1735 if (widx > ridx) 1736 nfree = le32toh(br->br_cmd_siz) - 1737 (widx - ridx + sizeof(struct txp_cmd_desc)); 1738 else 1739 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1740 } 1741 1742 return (nfree / sizeof(struct txp_cmd_desc)); 1743 } 1744 1745 void 1746 txp_stop(struct txp_softc *sc) 1747 { 1748 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1749 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1750 1751 if (callout_pending(&sc->sc_tick)) 1752 callout_stop(&sc->sc_tick); 1753 } 1754 1755 void 1756 txp_watchdog(struct ifnet *ifp) 1757 { 1758 } 1759 1760 int 1761 txp_ifmedia_upd(struct ifnet *ifp) 1762 { 1763 struct txp_softc *sc = ifp->if_softc; 1764 struct ifmedia *ifm = &sc->sc_ifmedia; 1765 u_int16_t new_xcvr; 1766 1767 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1768 return (EINVAL); 1769 1770 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1771 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1772 new_xcvr = TXP_XCVR_10_FDX; 1773 else 1774 new_xcvr = TXP_XCVR_10_HDX; 1775 } else if ((IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) || 1776 (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX)) { 1777 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1778 new_xcvr = TXP_XCVR_100_FDX; 1779 else 1780 new_xcvr = TXP_XCVR_100_HDX; 1781 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1782 new_xcvr = TXP_XCVR_AUTO; 1783 } else 1784 return (EINVAL); 1785 1786 /* nothing to do */ 1787 if (sc->sc_xcvr == new_xcvr) 1788 return (0); 1789 1790 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1791 NULL, NULL, NULL, 0); 1792 sc->sc_xcvr = new_xcvr; 1793 1794 return (0); 1795 } 1796 1797 void 1798 txp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1799 { 1800 struct txp_softc *sc = ifp->if_softc; 1801 struct ifmedia *ifm = &sc->sc_ifmedia; 1802 u_int16_t bmsr, bmcr, anlpar; 1803 1804 ifmr->ifm_status = IFM_AVALID; 1805 ifmr->ifm_active = IFM_ETHER; 1806 1807 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1808 &bmsr, NULL, NULL, 1)) 1809 goto bail; 1810 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1811 &bmsr, NULL, NULL, 1)) 1812 goto bail; 1813 1814 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1815 &bmcr, NULL, NULL, 1)) 1816 goto bail; 1817 1818 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1819 &anlpar, NULL, NULL, 1)) 1820 goto bail; 1821 1822 if (bmsr & BMSR_LINK) 1823 ifmr->ifm_status |= IFM_ACTIVE; 1824 1825 if (bmcr & BMCR_ISO) { 1826 ifmr->ifm_active |= IFM_NONE; 1827 ifmr->ifm_status = 0; 1828 return; 1829 } 1830 1831 if (bmcr & BMCR_LOOP) 1832 ifmr->ifm_active |= IFM_LOOP; 1833 1834 if (!(sc->sc_flags & TXP_FIBER) && (bmcr & BMCR_AUTOEN)) { 1835 if ((bmsr & BMSR_ACOMP) == 0) { 1836 ifmr->ifm_active |= IFM_NONE; 1837 return; 1838 } 1839 1840 if (anlpar & ANLPAR_TX_FD) 1841 ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1842 else if (anlpar & ANLPAR_T4) 1843 ifmr->ifm_active |= IFM_100_T4; 1844 else if (anlpar & ANLPAR_TX) 1845 ifmr->ifm_active |= IFM_100_TX; 1846 else if (anlpar & ANLPAR_10_FD) 1847 ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1848 else if (anlpar & ANLPAR_10) 1849 ifmr->ifm_active |= IFM_10_T; 1850 else 1851 ifmr->ifm_active |= IFM_NONE; 1852 } else 1853 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1854 return; 1855 1856 bail: 1857 ifmr->ifm_active |= IFM_NONE; 1858 ifmr->ifm_status &= ~IFM_AVALID; 1859 } 1860 1861 void 1862 txp_show_descriptor(void *d) 1863 { 1864 struct txp_cmd_desc *cmd = d; 1865 struct txp_rsp_desc *rsp = d; 1866 struct txp_tx_desc *txd = d; 1867 struct txp_frag_desc *frgd = d; 1868 1869 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1870 case CMD_FLAGS_TYPE_CMD: 1871 /* command descriptor */ 1872 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1873 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1874 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1875 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1876 break; 1877 case CMD_FLAGS_TYPE_RESP: 1878 /* response descriptor */ 1879 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1880 rsp->rsp_flags, rsp->rsp_numdesc, le16toh(rsp->rsp_id), 1881 le16toh(rsp->rsp_seq), le16toh(rsp->rsp_par1), 1882 le32toh(rsp->rsp_par2), le32toh(rsp->rsp_par3)); 1883 break; 1884 case CMD_FLAGS_TYPE_DATA: 1885 /* data header (assuming tx for now) */ 1886 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]", 1887 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1888 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1889 break; 1890 case CMD_FLAGS_TYPE_FRAG: 1891 /* fragment descriptor */ 1892 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]", 1893 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1894 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1895 break; 1896 default: 1897 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1898 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1899 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1900 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1901 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1902 break; 1903 } 1904 } 1905 1906 void 1907 txp_set_filter(struct txp_softc *sc) 1908 { 1909 struct ethercom *ac = &sc->sc_arpcom; 1910 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1911 u_int32_t crc, carry, hashbit, hash[2]; 1912 u_int16_t filter; 1913 u_int8_t octet; 1914 int i, j, mcnt = 0; 1915 struct ether_multi *enm; 1916 struct ether_multistep step; 1917 1918 if (ifp->if_flags & IFF_PROMISC) { 1919 filter = TXP_RXFILT_PROMISC; 1920 goto setit; 1921 } 1922 1923 again: 1924 filter = TXP_RXFILT_DIRECT; 1925 1926 if (ifp->if_flags & IFF_BROADCAST) 1927 filter |= TXP_RXFILT_BROADCAST; 1928 1929 if (ifp->if_flags & IFF_ALLMULTI) 1930 filter |= TXP_RXFILT_ALLMULTI; 1931 else { 1932 hash[0] = hash[1] = 0; 1933 1934 ETHER_FIRST_MULTI(step, ac, enm); 1935 while (enm != NULL) { 1936 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1937 /* 1938 * We must listen to a range of multicast 1939 * addresses. For now, just accept all 1940 * multicasts, rather than trying to set only 1941 * those filter bits needed to match the range. 1942 * (At this time, the only use of address 1943 * ranges is for IP multicast routing, for 1944 * which the range is big enough to require 1945 * all bits set.) 1946 */ 1947 ifp->if_flags |= IFF_ALLMULTI; 1948 goto again; 1949 } 1950 1951 mcnt++; 1952 crc = 0xffffffff; 1953 1954 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1955 octet = enm->enm_addrlo[i]; 1956 for (j = 0; j < 8; j++) { 1957 carry = ((crc & 0x80000000) ? 1 : 0) ^ 1958 (octet & 1); 1959 crc <<= 1; 1960 octet >>= 1; 1961 if (carry) 1962 crc = (crc ^ TXP_POLYNOMIAL) | 1963 carry; 1964 } 1965 } 1966 hashbit = (u_int16_t)(crc & (64 - 1)); 1967 hash[hashbit / 32] |= (1 << hashbit % 32); 1968 ETHER_NEXT_MULTI(step, enm); 1969 } 1970 1971 if (mcnt > 0) { 1972 filter |= TXP_RXFILT_HASHMULTI; 1973 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 1974 2, hash[0], hash[1], NULL, NULL, NULL, 0); 1975 } 1976 } 1977 1978 setit: 1979 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 1980 NULL, NULL, NULL, 1); 1981 } 1982 1983 void 1984 txp_capabilities(struct txp_softc *sc) 1985 { 1986 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1987 struct txp_rsp_desc *rsp = NULL; 1988 struct txp_ext_desc *ext; 1989 1990 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 1991 goto out; 1992 1993 if (rsp->rsp_numdesc != 1) 1994 goto out; 1995 ext = (struct txp_ext_desc *)(rsp + 1); 1996 1997 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 1998 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 1999 2000 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_MTU; 2001 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 2002 sc->sc_tx_capability |= OFFLOAD_VLAN; 2003 sc->sc_rx_capability |= OFFLOAD_VLAN; 2004 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 2005 } 2006 2007 #if 0 2008 /* not ready yet */ 2009 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 2010 sc->sc_tx_capability |= OFFLOAD_IPSEC; 2011 sc->sc_rx_capability |= OFFLOAD_IPSEC; 2012 ifp->if_capabilities |= IFCAP_IPSEC; 2013 } 2014 #endif 2015 2016 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 2017 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 2018 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 2019 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 2020 } 2021 2022 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 2023 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 2024 #ifdef TRY_TX_TCP_CSUM 2025 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 2026 ifp->if_capabilities |= 2027 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 2028 #endif 2029 } 2030 2031 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 2032 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 2033 #ifdef TRY_TX_UDP_CSUM 2034 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 2035 ifp->if_capabilities |= 2036 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2037 #endif 2038 } 2039 2040 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 2041 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 2042 goto out; 2043 2044 out: 2045 if (rsp != NULL) 2046 free(rsp, M_DEVBUF); 2047 } 2048