1 /* $NetBSD: if_txp.c,v 1.10 2005/02/27 00:27:33 perry Exp $ */ 2 3 /* 4 * Copyright (c) 2001 5 * Jason L. Wright <jason@thought.net>, Theo de Raadt, and 6 * Aaron Campbell <aaron@monkey.org>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR THE VOICES IN THEIR HEADS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Driver for 3c990 (Typhoon) Ethernet ASIC 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: if_txp.c,v 1.10 2005/02/27 00:27:33 perry Exp $"); 36 37 #include "bpfilter.h" 38 #include "opt_inet.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/sockio.h> 43 #include <sys/mbuf.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/device.h> 48 #include <sys/callout.h> 49 50 #include <net/if.h> 51 #include <net/if_dl.h> 52 #include <net/if_types.h> 53 #include <net/if_ether.h> 54 #include <net/if_arp.h> 55 56 #ifdef INET 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/in_var.h> 60 #include <netinet/ip.h> 61 #include <netinet/if_inarp.h> 62 #endif 63 64 #include <net/if_media.h> 65 66 #if NBPFILTER > 0 67 #include <net/bpf.h> 68 #endif 69 70 #include <uvm/uvm_extern.h> /* for vtophys */ 71 #include <machine/bus.h> 72 73 #include <dev/mii/mii.h> 74 #include <dev/mii/miivar.h> 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/pcidevs.h> 78 79 #include <dev/pci/if_txpreg.h> 80 81 #include <dev/microcode/typhoon/3c990img.h> 82 83 /* 84 * These currently break the 3c990 firmware, hopefully will be resolved 85 * at some point. 86 */ 87 #undef TRY_TX_UDP_CSUM 88 #undef TRY_TX_TCP_CSUM 89 90 int txp_probe(struct device *, struct cfdata *, void *); 91 void txp_attach(struct device *, struct device *, void *); 92 int txp_intr(void *); 93 void txp_tick(void *); 94 void txp_shutdown(void *); 95 int txp_ioctl(struct ifnet *, u_long, caddr_t); 96 void txp_start(struct ifnet *); 97 void txp_stop(struct txp_softc *); 98 void txp_init(struct txp_softc *); 99 void txp_watchdog(struct ifnet *); 100 101 int txp_chip_init(struct txp_softc *); 102 int txp_reset_adapter(struct txp_softc *); 103 int txp_download_fw(struct txp_softc *); 104 int txp_download_fw_wait(struct txp_softc *); 105 int txp_download_fw_section(struct txp_softc *, 106 struct txp_fw_section_header *, int); 107 int txp_alloc_rings(struct txp_softc *); 108 void txp_dma_free(struct txp_softc *, struct txp_dma_alloc *); 109 int txp_dma_malloc(struct txp_softc *, bus_size_t, struct txp_dma_alloc *, int); 110 void txp_set_filter(struct txp_softc *); 111 112 int txp_cmd_desc_numfree(struct txp_softc *); 113 int txp_command(struct txp_softc *, u_int16_t, u_int16_t, u_int32_t, 114 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int); 115 int txp_command2(struct txp_softc *, u_int16_t, u_int16_t, 116 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t, 117 struct txp_rsp_desc **, int); 118 int txp_response(struct txp_softc *, u_int32_t, u_int16_t, u_int16_t, 119 struct txp_rsp_desc **); 120 void txp_rsp_fixup(struct txp_softc *, struct txp_rsp_desc *, 121 struct txp_rsp_desc *); 122 void txp_capabilities(struct txp_softc *); 123 124 void txp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 125 int txp_ifmedia_upd(struct ifnet *); 126 void txp_show_descriptor(void *); 127 void txp_tx_reclaim(struct txp_softc *, struct txp_tx_ring *, 128 struct txp_dma_alloc *); 129 void txp_rxbuf_reclaim(struct txp_softc *); 130 void txp_rx_reclaim(struct txp_softc *, struct txp_rx_ring *, 131 struct txp_dma_alloc *); 132 133 CFATTACH_DECL(txp, sizeof(struct txp_softc), txp_probe, txp_attach, 134 NULL, NULL); 135 136 const struct txp_pci_match { 137 int vid, did, flags; 138 } txp_devices[] = { 139 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990, 0 }, 140 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX95, 0 }, 141 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX97, 0 }, 142 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR95, TXP_SERVERVERSION }, 143 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR97, TXP_SERVERVERSION }, 144 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990B, TXP_USESUBSYSTEM }, 145 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BSVR, TXP_SERVERVERSION }, 146 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990FX, TXP_USESUBSYSTEM }, 147 }; 148 149 static const struct txp_pci_match *txp_pcilookup(pcireg_t); 150 151 static const struct { 152 u_int16_t mask, value; 153 int flags; 154 } txp_subsysinfo[] = { 155 {0xf000, 0x2000, TXP_SERVERVERSION}, 156 {0x0100, 0x0100, TXP_FIBER}, 157 #if 0 /* information from 3com header, unused */ 158 {0x0010, 0x0010, /* secured firmware */}, 159 {0x0003, 0x0000, /* variable DES */}, 160 {0x0003, 0x0001, /* single DES - "95" */}, 161 {0x0003, 0x0002, /* triple DES - "97" */}, 162 #endif 163 }; 164 165 static const struct txp_pci_match * 166 txp_pcilookup(id) 167 pcireg_t id; 168 { 169 int i; 170 171 for (i = 0; i < sizeof(txp_devices) / sizeof(txp_devices[0]); i++) 172 if ((PCI_VENDOR(id) == txp_devices[i].vid) && 173 (PCI_PRODUCT(id) == txp_devices[i].did)) 174 return (&txp_devices[i]); 175 return (0); 176 } 177 178 int 179 txp_probe(parent, match, aux) 180 struct device *parent; 181 struct cfdata *match; 182 void *aux; 183 { 184 struct pci_attach_args *pa = aux; 185 186 if (txp_pcilookup(pa->pa_id)) 187 return (1); 188 return (0); 189 } 190 191 void 192 txp_attach(parent, self, aux) 193 struct device *parent, *self; 194 void *aux; 195 { 196 struct txp_softc *sc = (struct txp_softc *)self; 197 struct pci_attach_args *pa = aux; 198 pci_chipset_tag_t pc = pa->pa_pc; 199 pci_intr_handle_t ih; 200 const char *intrstr = NULL; 201 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 202 u_int32_t command; 203 u_int16_t p1; 204 u_int32_t p2; 205 u_char enaddr[6]; 206 const struct txp_pci_match *pcimatch; 207 u_int16_t subsys; 208 int i, flags; 209 char devinfo[256]; 210 211 sc->sc_cold = 1; 212 213 pcimatch = txp_pcilookup(pa->pa_id); 214 flags = pcimatch->flags; 215 if (pcimatch->flags & TXP_USESUBSYSTEM) { 216 subsys = PCI_PRODUCT(pci_conf_read(pc, pa->pa_tag, 217 PCI_SUBSYS_ID_REG)); 218 for (i = 0; 219 i < sizeof(txp_subsysinfo)/sizeof(txp_subsysinfo[0]); 220 i++) 221 if ((subsys & txp_subsysinfo[i].mask) == 222 txp_subsysinfo[i].value) 223 flags |= txp_subsysinfo[i].flags; 224 } 225 sc->sc_flags = flags; 226 227 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 228 #define TXP_EXTRAINFO ((flags & (TXP_USESUBSYSTEM|TXP_SERVERVERSION)) == \ 229 (TXP_USESUBSYSTEM|TXP_SERVERVERSION) ? " (SVR)" : "") 230 printf(": %s%s\n%s", devinfo, TXP_EXTRAINFO, sc->sc_dev.dv_xname); 231 232 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 233 234 if (!(command & PCI_COMMAND_MASTER_ENABLE)) { 235 printf(": failed to enable bus mastering\n"); 236 return; 237 } 238 239 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 240 printf(": failed to enable memory mapping\n"); 241 return; 242 } 243 if (pci_mapreg_map(pa, TXP_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 244 &sc->sc_bt, &sc->sc_bh, NULL, NULL)) { 245 printf(": can't map mem space %d\n", 0); 246 return; 247 } 248 249 sc->sc_dmat = pa->pa_dmat; 250 251 /* 252 * Allocate our interrupt. 253 */ 254 if (pci_intr_map(pa, &ih)) { 255 printf(": couldn't map interrupt\n"); 256 return; 257 } 258 259 intrstr = pci_intr_string(pc, ih); 260 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, txp_intr, sc); 261 if (sc->sc_ih == NULL) { 262 printf(": couldn't establish interrupt"); 263 if (intrstr != NULL) 264 printf(" at %s", intrstr); 265 printf("\n"); 266 return; 267 } 268 printf(": interrupting at %s\n", intrstr); 269 270 if (txp_chip_init(sc)) 271 goto cleanupintr; 272 273 if (txp_download_fw(sc)) 274 goto cleanupintr; 275 276 if (txp_alloc_rings(sc)) 277 goto cleanupintr; 278 279 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 280 NULL, NULL, NULL, 1)) 281 goto cleanupintr; 282 283 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 284 &p1, &p2, NULL, 1)) 285 goto cleanupintr; 286 287 txp_set_filter(sc); 288 289 p1 = htole16(p1); 290 enaddr[0] = ((u_int8_t *)&p1)[1]; 291 enaddr[1] = ((u_int8_t *)&p1)[0]; 292 p2 = htole32(p2); 293 enaddr[2] = ((u_int8_t *)&p2)[3]; 294 enaddr[3] = ((u_int8_t *)&p2)[2]; 295 enaddr[4] = ((u_int8_t *)&p2)[1]; 296 enaddr[5] = ((u_int8_t *)&p2)[0]; 297 298 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 299 ether_sprintf(enaddr)); 300 sc->sc_cold = 0; 301 302 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 303 if (flags & TXP_FIBER) { 304 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX, 305 0, NULL); 306 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX|IFM_HDX, 307 0, NULL); 308 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX|IFM_FDX, 309 0, NULL); 310 } else { 311 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 312 0, NULL); 313 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 314 0, NULL); 315 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 316 0, NULL); 317 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 318 0, NULL); 319 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 320 0, NULL); 321 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 322 0, NULL); 323 } 324 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 325 326 sc->sc_xcvr = TXP_XCVR_AUTO; 327 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 328 NULL, NULL, NULL, 0); 329 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 330 331 ifp->if_softc = sc; 332 ifp->if_mtu = ETHERMTU; 333 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 334 ifp->if_ioctl = txp_ioctl; 335 ifp->if_start = txp_start; 336 ifp->if_watchdog = txp_watchdog; 337 ifp->if_baudrate = 10000000; 338 IFQ_SET_MAXLEN(&ifp->if_snd, TX_ENTRIES); 339 IFQ_SET_READY(&ifp->if_snd); 340 ifp->if_capabilities = 0; 341 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 342 343 txp_capabilities(sc); 344 345 callout_init(&sc->sc_tick); 346 callout_setfunc(&sc->sc_tick, txp_tick, sc); 347 348 /* 349 * Attach us everywhere 350 */ 351 if_attach(ifp); 352 ether_ifattach(ifp, enaddr); 353 354 shutdownhook_establish(txp_shutdown, sc); 355 356 357 return; 358 359 cleanupintr: 360 pci_intr_disestablish(pc,sc->sc_ih); 361 362 return; 363 364 } 365 366 int 367 txp_chip_init(sc) 368 struct txp_softc *sc; 369 { 370 /* disable interrupts */ 371 WRITE_REG(sc, TXP_IER, 0); 372 WRITE_REG(sc, TXP_IMR, 373 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 374 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 375 TXP_INT_LATCH); 376 377 /* ack all interrupts */ 378 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 379 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 380 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 381 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 382 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 383 384 if (txp_reset_adapter(sc)) 385 return (-1); 386 387 /* disable interrupts */ 388 WRITE_REG(sc, TXP_IER, 0); 389 WRITE_REG(sc, TXP_IMR, 390 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 391 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 392 TXP_INT_LATCH); 393 394 /* ack all interrupts */ 395 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 396 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 397 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 398 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 399 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 400 401 return (0); 402 } 403 404 int 405 txp_reset_adapter(sc) 406 struct txp_softc *sc; 407 { 408 u_int32_t r; 409 int i; 410 411 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 412 DELAY(1000); 413 WRITE_REG(sc, TXP_SRR, 0); 414 415 /* Should wait max 6 seconds */ 416 for (i = 0; i < 6000; i++) { 417 r = READ_REG(sc, TXP_A2H_0); 418 if (r == STAT_WAITING_FOR_HOST_REQUEST) 419 break; 420 DELAY(1000); 421 } 422 423 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 424 printf("%s: reset hung\n", TXP_DEVNAME(sc)); 425 return (-1); 426 } 427 428 return (0); 429 } 430 431 int 432 txp_download_fw(sc) 433 struct txp_softc *sc; 434 { 435 struct txp_fw_file_header *fileheader; 436 struct txp_fw_section_header *secthead; 437 int sect; 438 u_int32_t r, i, ier, imr; 439 440 ier = READ_REG(sc, TXP_IER); 441 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 442 443 imr = READ_REG(sc, TXP_IMR); 444 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 445 446 for (i = 0; i < 10000; i++) { 447 r = READ_REG(sc, TXP_A2H_0); 448 if (r == STAT_WAITING_FOR_HOST_REQUEST) 449 break; 450 DELAY(50); 451 } 452 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 453 printf(": not waiting for host request\n"); 454 return (-1); 455 } 456 457 /* Ack the status */ 458 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 459 460 fileheader = (struct txp_fw_file_header *)tc990image; 461 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) { 462 printf(": fw invalid magic\n"); 463 return (-1); 464 } 465 466 /* Tell boot firmware to get ready for image */ 467 WRITE_REG(sc, TXP_H2A_1, le32toh(fileheader->addr)); 468 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 469 470 if (txp_download_fw_wait(sc)) { 471 printf("%s: fw wait failed, initial\n", sc->sc_dev.dv_xname); 472 return (-1); 473 } 474 475 secthead = (struct txp_fw_section_header *)(((u_int8_t *)tc990image) + 476 sizeof(struct txp_fw_file_header)); 477 478 for (sect = 0; sect < le32toh(fileheader->nsections); sect++) { 479 if (txp_download_fw_section(sc, secthead, sect)) 480 return (-1); 481 secthead = (struct txp_fw_section_header *) 482 (((u_int8_t *)secthead) + le32toh(secthead->nbytes) + 483 sizeof(*secthead)); 484 } 485 486 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 487 488 for (i = 0; i < 10000; i++) { 489 r = READ_REG(sc, TXP_A2H_0); 490 if (r == STAT_WAITING_FOR_BOOT) 491 break; 492 DELAY(50); 493 } 494 if (r != STAT_WAITING_FOR_BOOT) { 495 printf(": not waiting for boot\n"); 496 return (-1); 497 } 498 499 WRITE_REG(sc, TXP_IER, ier); 500 WRITE_REG(sc, TXP_IMR, imr); 501 502 return (0); 503 } 504 505 int 506 txp_download_fw_wait(sc) 507 struct txp_softc *sc; 508 { 509 u_int32_t i, r; 510 511 for (i = 0; i < 10000; i++) { 512 r = READ_REG(sc, TXP_ISR); 513 if (r & TXP_INT_A2H_0) 514 break; 515 DELAY(50); 516 } 517 518 if (!(r & TXP_INT_A2H_0)) { 519 printf(": fw wait failed comm0\n"); 520 return (-1); 521 } 522 523 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 524 525 r = READ_REG(sc, TXP_A2H_0); 526 if (r != STAT_WAITING_FOR_SEGMENT) { 527 printf(": fw not waiting for segment\n"); 528 return (-1); 529 } 530 return (0); 531 } 532 533 int 534 txp_download_fw_section(sc, sect, sectnum) 535 struct txp_softc *sc; 536 struct txp_fw_section_header *sect; 537 int sectnum; 538 { 539 struct txp_dma_alloc dma; 540 int rseg, err = 0; 541 struct mbuf m; 542 u_int16_t csum; 543 544 /* Skip zero length sections */ 545 if (sect->nbytes == 0) 546 return (0); 547 548 /* Make sure we aren't past the end of the image */ 549 rseg = ((u_int8_t *)sect) - ((u_int8_t *)tc990image); 550 if (rseg >= sizeof(tc990image)) { 551 printf(": fw invalid section address, section %d\n", sectnum); 552 return (-1); 553 } 554 555 /* Make sure this section doesn't go past the end */ 556 rseg += le32toh(sect->nbytes); 557 if (rseg >= sizeof(tc990image)) { 558 printf(": fw truncated section %d\n", sectnum); 559 return (-1); 560 } 561 562 /* map a buffer, copy segment to it, get physaddr */ 563 if (txp_dma_malloc(sc, le32toh(sect->nbytes), &dma, 0)) { 564 printf(": fw dma malloc failed, section %d\n", sectnum); 565 return (-1); 566 } 567 568 bcopy(((u_int8_t *)sect) + sizeof(*sect), dma.dma_vaddr, 569 le32toh(sect->nbytes)); 570 571 /* 572 * dummy up mbuf and verify section checksum 573 */ 574 m.m_type = MT_DATA; 575 m.m_next = m.m_nextpkt = NULL; 576 m.m_len = le32toh(sect->nbytes); 577 m.m_data = dma.dma_vaddr; 578 m.m_flags = 0; 579 csum = in_cksum(&m, le32toh(sect->nbytes)); 580 if (csum != sect->cksum) { 581 printf(": fw section %d, bad cksum (expected 0x%x got 0x%x)\n", 582 sectnum, sect->cksum, csum); 583 err = -1; 584 goto bail; 585 } 586 587 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 588 dma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 589 590 WRITE_REG(sc, TXP_H2A_1, le32toh(sect->nbytes)); 591 WRITE_REG(sc, TXP_H2A_2, le32toh(sect->cksum)); 592 WRITE_REG(sc, TXP_H2A_3, le32toh(sect->addr)); 593 WRITE_REG(sc, TXP_H2A_4, dma.dma_paddr >> 32); 594 WRITE_REG(sc, TXP_H2A_5, dma.dma_paddr & 0xffffffff); 595 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 596 597 if (txp_download_fw_wait(sc)) { 598 printf("%s: fw wait failed, section %d\n", 599 sc->sc_dev.dv_xname, sectnum); 600 err = -1; 601 } 602 603 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 604 dma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 605 606 bail: 607 txp_dma_free(sc, &dma); 608 609 return (err); 610 } 611 612 int 613 txp_intr(vsc) 614 void *vsc; 615 { 616 struct txp_softc *sc = vsc; 617 struct txp_hostvar *hv = sc->sc_hostvar; 618 u_int32_t isr; 619 int claimed = 0; 620 621 /* mask all interrupts */ 622 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 623 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 624 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 625 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 626 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 627 628 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 629 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 630 631 isr = READ_REG(sc, TXP_ISR); 632 while (isr) { 633 claimed = 1; 634 WRITE_REG(sc, TXP_ISR, isr); 635 636 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 637 txp_rx_reclaim(sc, &sc->sc_rxhir, &sc->sc_rxhiring_dma); 638 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 639 txp_rx_reclaim(sc, &sc->sc_rxlor, &sc->sc_rxloring_dma); 640 641 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 642 txp_rxbuf_reclaim(sc); 643 644 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 645 TXP_OFFSET2IDX(le32toh(*(sc->sc_txhir.r_off))))) 646 txp_tx_reclaim(sc, &sc->sc_txhir, &sc->sc_txhiring_dma); 647 648 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 649 TXP_OFFSET2IDX(le32toh(*(sc->sc_txlor.r_off))))) 650 txp_tx_reclaim(sc, &sc->sc_txlor, &sc->sc_txloring_dma); 651 652 isr = READ_REG(sc, TXP_ISR); 653 } 654 655 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 656 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 657 658 /* unmask all interrupts */ 659 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 660 661 txp_start(&sc->sc_arpcom.ec_if); 662 663 return (claimed); 664 } 665 666 void 667 txp_rx_reclaim(sc, r, dma) 668 struct txp_softc *sc; 669 struct txp_rx_ring *r; 670 struct txp_dma_alloc *dma; 671 { 672 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 673 struct txp_rx_desc *rxd; 674 struct mbuf *m; 675 struct txp_swdesc *sd; 676 u_int32_t roff, woff; 677 int sumflags = 0; 678 int idx; 679 680 roff = le32toh(*r->r_roff); 681 woff = le32toh(*r->r_woff); 682 idx = roff / sizeof(struct txp_rx_desc); 683 rxd = r->r_desc + idx; 684 685 while (roff != woff) { 686 687 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 688 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 689 BUS_DMASYNC_POSTREAD); 690 691 if (rxd->rx_flags & RX_FLAGS_ERROR) { 692 printf("%s: error 0x%x\n", sc->sc_dev.dv_xname, 693 le32toh(rxd->rx_stat)); 694 ifp->if_ierrors++; 695 goto next; 696 } 697 698 /* retrieve stashed pointer */ 699 bcopy((u_long *)&rxd->rx_vaddrlo, &sd, sizeof(sd)); 700 701 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 702 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 703 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 704 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 705 m = sd->sd_mbuf; 706 free(sd, M_DEVBUF); 707 m->m_pkthdr.len = m->m_len = le16toh(rxd->rx_len); 708 709 #ifdef __STRICT_ALIGNMENT 710 { 711 /* 712 * XXX Nice chip, except it won't accept "off by 2" 713 * buffers, so we're force to copy. Supposedly 714 * this will be fixed in a newer firmware rev 715 * and this will be temporary. 716 */ 717 struct mbuf *mnew; 718 719 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 720 if (mnew == NULL) { 721 m_freem(m); 722 goto next; 723 } 724 if (m->m_len > (MHLEN - 2)) { 725 MCLGET(mnew, M_DONTWAIT); 726 if (!(mnew->m_flags & M_EXT)) { 727 m_freem(mnew); 728 m_freem(m); 729 goto next; 730 } 731 } 732 mnew->m_pkthdr.rcvif = ifp; 733 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 734 mnew->m_data += 2; 735 bcopy(m->m_data, mnew->m_data, m->m_len); 736 m_freem(m); 737 m = mnew; 738 } 739 #endif 740 741 #if NBPFILTER > 0 742 /* 743 * Handle BPF listeners. Let the BPF user see the packet. 744 */ 745 if (ifp->if_bpf) 746 bpf_mtap(ifp->if_bpf, m); 747 #endif 748 749 if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMBAD)) 750 sumflags |= (M_CSUM_IPv4|M_CSUM_IPv4_BAD); 751 else if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMGOOD)) 752 sumflags |= M_CSUM_IPv4; 753 754 if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMBAD)) 755 sumflags |= (M_CSUM_TCPv4|M_CSUM_TCP_UDP_BAD); 756 else if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMGOOD)) 757 sumflags |= M_CSUM_TCPv4; 758 759 if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMBAD)) 760 sumflags |= (M_CSUM_UDPv4|M_CSUM_TCP_UDP_BAD); 761 else if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMGOOD)) 762 sumflags |= M_CSUM_UDPv4; 763 764 m->m_pkthdr.csum_flags = sumflags; 765 766 if (rxd->rx_stat & htole32(RX_STAT_VLAN)) { 767 VLAN_INPUT_TAG(ifp, m, htons(rxd->rx_vlan >> 16), 768 continue); 769 } 770 771 (*ifp->if_input)(ifp, m); 772 773 next: 774 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 775 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 776 BUS_DMASYNC_PREREAD); 777 778 roff += sizeof(struct txp_rx_desc); 779 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 780 idx = 0; 781 roff = 0; 782 rxd = r->r_desc; 783 } else { 784 idx++; 785 rxd++; 786 } 787 woff = le32toh(*r->r_woff); 788 } 789 790 *r->r_roff = htole32(woff); 791 } 792 793 void 794 txp_rxbuf_reclaim(sc) 795 struct txp_softc *sc; 796 { 797 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 798 struct txp_hostvar *hv = sc->sc_hostvar; 799 struct txp_rxbuf_desc *rbd; 800 struct txp_swdesc *sd; 801 u_int32_t i, end; 802 803 end = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_read_idx)); 804 i = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_write_idx)); 805 806 if (++i == RXBUF_ENTRIES) 807 i = 0; 808 809 rbd = sc->sc_rxbufs + i; 810 811 while (i != end) { 812 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 813 M_DEVBUF, M_NOWAIT); 814 if (sd == NULL) 815 break; 816 817 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 818 if (sd->sd_mbuf == NULL) 819 goto err_sd; 820 821 MCLGET(sd->sd_mbuf, M_DONTWAIT); 822 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 823 goto err_mbuf; 824 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 825 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 826 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 827 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) 828 goto err_mbuf; 829 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 830 BUS_DMA_NOWAIT)) { 831 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 832 goto err_mbuf; 833 } 834 835 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 836 i * sizeof(struct txp_rxbuf_desc), 837 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_POSTWRITE); 838 839 /* stash away pointer */ 840 bcopy(&sd, (u_long *)&rbd->rb_vaddrlo, sizeof(sd)); 841 842 rbd->rb_paddrlo = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 843 & 0xffffffff; 844 rbd->rb_paddrhi = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 845 >> 32; 846 847 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 848 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 849 850 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 851 i * sizeof(struct txp_rxbuf_desc), 852 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_PREWRITE); 853 854 hv->hv_rx_buf_write_idx = htole32(TXP_IDX2OFFSET(i)); 855 856 if (++i == RXBUF_ENTRIES) { 857 i = 0; 858 rbd = sc->sc_rxbufs; 859 } else 860 rbd++; 861 } 862 return; 863 864 err_mbuf: 865 m_freem(sd->sd_mbuf); 866 err_sd: 867 free(sd, M_DEVBUF); 868 } 869 870 /* 871 * Reclaim mbufs and entries from a transmit ring. 872 */ 873 void 874 txp_tx_reclaim(sc, r, dma) 875 struct txp_softc *sc; 876 struct txp_tx_ring *r; 877 struct txp_dma_alloc *dma; 878 { 879 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 880 u_int32_t idx = TXP_OFFSET2IDX(le32toh(*(r->r_off))); 881 u_int32_t cons = r->r_cons, cnt = r->r_cnt; 882 struct txp_tx_desc *txd = r->r_desc + cons; 883 struct txp_swdesc *sd = sc->sc_txd + cons; 884 struct mbuf *m; 885 886 while (cons != idx) { 887 if (cnt == 0) 888 break; 889 890 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 891 cons * sizeof(struct txp_tx_desc), 892 sizeof(struct txp_tx_desc), 893 BUS_DMASYNC_POSTWRITE); 894 895 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 896 TX_FLAGS_TYPE_DATA) { 897 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 898 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 899 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 900 m = sd->sd_mbuf; 901 if (m != NULL) { 902 m_freem(m); 903 txd->tx_addrlo = 0; 904 txd->tx_addrhi = 0; 905 ifp->if_opackets++; 906 } 907 } 908 ifp->if_flags &= ~IFF_OACTIVE; 909 910 if (++cons == TX_ENTRIES) { 911 txd = r->r_desc; 912 cons = 0; 913 sd = sc->sc_txd; 914 } else { 915 txd++; 916 sd++; 917 } 918 919 cnt--; 920 } 921 922 r->r_cons = cons; 923 r->r_cnt = cnt; 924 if (cnt == 0) 925 ifp->if_timer = 0; 926 } 927 928 void 929 txp_shutdown(vsc) 930 void *vsc; 931 { 932 struct txp_softc *sc = (struct txp_softc *)vsc; 933 934 /* mask all interrupts */ 935 WRITE_REG(sc, TXP_IMR, 936 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 937 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 938 TXP_INT_LATCH); 939 940 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 941 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 942 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 943 } 944 945 int 946 txp_alloc_rings(sc) 947 struct txp_softc *sc; 948 { 949 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 950 struct txp_boot_record *boot; 951 struct txp_swdesc *sd; 952 u_int32_t r; 953 int i, j; 954 955 /* boot record */ 956 if (txp_dma_malloc(sc, sizeof(struct txp_boot_record), &sc->sc_boot_dma, 957 BUS_DMA_COHERENT)) { 958 printf(": can't allocate boot record\n"); 959 return (-1); 960 } 961 boot = (struct txp_boot_record *)sc->sc_boot_dma.dma_vaddr; 962 bzero(boot, sizeof(*boot)); 963 sc->sc_boot = boot; 964 965 /* host variables */ 966 if (txp_dma_malloc(sc, sizeof(struct txp_hostvar), &sc->sc_host_dma, 967 BUS_DMA_COHERENT)) { 968 printf(": can't allocate host ring\n"); 969 goto bail_boot; 970 } 971 bzero(sc->sc_host_dma.dma_vaddr, sizeof(struct txp_hostvar)); 972 boot->br_hostvar_lo = htole32(sc->sc_host_dma.dma_paddr & 0xffffffff); 973 boot->br_hostvar_hi = htole32(sc->sc_host_dma.dma_paddr >> 32); 974 sc->sc_hostvar = (struct txp_hostvar *)sc->sc_host_dma.dma_vaddr; 975 976 /* high priority tx ring */ 977 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 978 &sc->sc_txhiring_dma, BUS_DMA_COHERENT)) { 979 printf(": can't allocate high tx ring\n"); 980 goto bail_host; 981 } 982 bzero(sc->sc_txhiring_dma.dma_vaddr, sizeof(struct txp_tx_desc) * TX_ENTRIES); 983 boot->br_txhipri_lo = htole32(sc->sc_txhiring_dma.dma_paddr & 0xffffffff); 984 boot->br_txhipri_hi = htole32(sc->sc_txhiring_dma.dma_paddr >> 32); 985 boot->br_txhipri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 986 sc->sc_txhir.r_reg = TXP_H2A_1; 987 sc->sc_txhir.r_desc = (struct txp_tx_desc *)sc->sc_txhiring_dma.dma_vaddr; 988 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 989 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 990 for (i = 0; i < TX_ENTRIES; i++) { 991 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 992 TX_ENTRIES - 4, TXP_MAX_SEGLEN, 0, 993 BUS_DMA_NOWAIT, &sc->sc_txd[i].sd_map) != 0) { 994 for (j = 0; j < i; j++) { 995 bus_dmamap_destroy(sc->sc_dmat, 996 sc->sc_txd[j].sd_map); 997 sc->sc_txd[j].sd_map = NULL; 998 } 999 goto bail_txhiring; 1000 } 1001 } 1002 1003 /* low priority tx ring */ 1004 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 1005 &sc->sc_txloring_dma, BUS_DMA_COHERENT)) { 1006 printf(": can't allocate low tx ring\n"); 1007 goto bail_txhiring; 1008 } 1009 bzero(sc->sc_txloring_dma.dma_vaddr, sizeof(struct txp_tx_desc) * TX_ENTRIES); 1010 boot->br_txlopri_lo = htole32(sc->sc_txloring_dma.dma_paddr & 0xffffffff); 1011 boot->br_txlopri_hi = htole32(sc->sc_txloring_dma.dma_paddr >> 32); 1012 boot->br_txlopri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 1013 sc->sc_txlor.r_reg = TXP_H2A_3; 1014 sc->sc_txlor.r_desc = (struct txp_tx_desc *)sc->sc_txloring_dma.dma_vaddr; 1015 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 1016 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 1017 1018 /* high priority rx ring */ 1019 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1020 &sc->sc_rxhiring_dma, BUS_DMA_COHERENT)) { 1021 printf(": can't allocate high rx ring\n"); 1022 goto bail_txloring; 1023 } 1024 bzero(sc->sc_rxhiring_dma.dma_vaddr, sizeof(struct txp_rx_desc) * RX_ENTRIES); 1025 boot->br_rxhipri_lo = htole32(sc->sc_rxhiring_dma.dma_paddr & 0xffffffff); 1026 boot->br_rxhipri_hi = htole32(sc->sc_rxhiring_dma.dma_paddr >> 32); 1027 boot->br_rxhipri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1028 sc->sc_rxhir.r_desc = 1029 (struct txp_rx_desc *)sc->sc_rxhiring_dma.dma_vaddr; 1030 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 1031 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 1032 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxhiring_dma.dma_map, 1033 0, sc->sc_rxhiring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1034 1035 /* low priority ring */ 1036 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1037 &sc->sc_rxloring_dma, BUS_DMA_COHERENT)) { 1038 printf(": can't allocate low rx ring\n"); 1039 goto bail_rxhiring; 1040 } 1041 bzero(sc->sc_rxloring_dma.dma_vaddr, sizeof(struct txp_rx_desc) * RX_ENTRIES); 1042 boot->br_rxlopri_lo = htole32(sc->sc_rxloring_dma.dma_paddr & 0xffffffff); 1043 boot->br_rxlopri_hi = htole32(sc->sc_rxloring_dma.dma_paddr >> 32); 1044 boot->br_rxlopri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1045 sc->sc_rxlor.r_desc = 1046 (struct txp_rx_desc *)sc->sc_rxloring_dma.dma_vaddr; 1047 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 1048 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 1049 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxloring_dma.dma_map, 1050 0, sc->sc_rxloring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1051 1052 /* command ring */ 1053 if (txp_dma_malloc(sc, sizeof(struct txp_cmd_desc) * CMD_ENTRIES, 1054 &sc->sc_cmdring_dma, BUS_DMA_COHERENT)) { 1055 printf(": can't allocate command ring\n"); 1056 goto bail_rxloring; 1057 } 1058 bzero(sc->sc_cmdring_dma.dma_vaddr, sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 1059 boot->br_cmd_lo = htole32(sc->sc_cmdring_dma.dma_paddr & 0xffffffff); 1060 boot->br_cmd_hi = htole32(sc->sc_cmdring_dma.dma_paddr >> 32); 1061 boot->br_cmd_siz = htole32(CMD_ENTRIES * sizeof(struct txp_cmd_desc)); 1062 sc->sc_cmdring.base = (struct txp_cmd_desc *)sc->sc_cmdring_dma.dma_vaddr; 1063 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1064 sc->sc_cmdring.lastwrite = 0; 1065 1066 /* response ring */ 1067 if (txp_dma_malloc(sc, sizeof(struct txp_rsp_desc) * RSP_ENTRIES, 1068 &sc->sc_rspring_dma, BUS_DMA_COHERENT)) { 1069 printf(": can't allocate response ring\n"); 1070 goto bail_cmdring; 1071 } 1072 bzero(sc->sc_rspring_dma.dma_vaddr, sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 1073 boot->br_resp_lo = htole32(sc->sc_rspring_dma.dma_paddr & 0xffffffff); 1074 boot->br_resp_hi = htole32(sc->sc_rspring_dma.dma_paddr >> 32); 1075 boot->br_resp_siz = htole32(CMD_ENTRIES * sizeof(struct txp_rsp_desc)); 1076 sc->sc_rspring.base = (struct txp_rsp_desc *)sc->sc_rspring_dma.dma_vaddr; 1077 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 1078 sc->sc_rspring.lastwrite = 0; 1079 1080 /* receive buffer ring */ 1081 if (txp_dma_malloc(sc, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES, 1082 &sc->sc_rxbufring_dma, BUS_DMA_COHERENT)) { 1083 printf(": can't allocate rx buffer ring\n"); 1084 goto bail_rspring; 1085 } 1086 bzero(sc->sc_rxbufring_dma.dma_vaddr, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES); 1087 boot->br_rxbuf_lo = htole32(sc->sc_rxbufring_dma.dma_paddr & 0xffffffff); 1088 boot->br_rxbuf_hi = htole32(sc->sc_rxbufring_dma.dma_paddr >> 32); 1089 boot->br_rxbuf_siz = htole32(RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc)); 1090 sc->sc_rxbufs = (struct txp_rxbuf_desc *)sc->sc_rxbufring_dma.dma_vaddr; 1091 for (i = 0; i < RXBUF_ENTRIES; i++) { 1092 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 1093 M_DEVBUF, M_NOWAIT); 1094 if (sd == NULL) 1095 break; 1096 1097 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 1098 if (sd->sd_mbuf == NULL) { 1099 goto bail_rxbufring; 1100 } 1101 1102 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1103 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1104 goto bail_rxbufring; 1105 } 1106 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1107 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 1108 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 1109 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) { 1110 goto bail_rxbufring; 1111 } 1112 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 1113 BUS_DMA_NOWAIT)) { 1114 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 1115 goto bail_rxbufring; 1116 } 1117 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1118 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1119 1120 /* stash away pointer */ 1121 bcopy(&sd, (u_long *)&sc->sc_rxbufs[i].rb_vaddrlo, sizeof(sd)); 1122 1123 sc->sc_rxbufs[i].rb_paddrlo = 1124 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) & 0xffffffff; 1125 sc->sc_rxbufs[i].rb_paddrhi = 1126 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) >> 32; 1127 } 1128 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 1129 0, sc->sc_rxbufring_dma.dma_map->dm_mapsize, 1130 BUS_DMASYNC_PREWRITE); 1131 sc->sc_hostvar->hv_rx_buf_write_idx = htole32((RXBUF_ENTRIES - 1) * 1132 sizeof(struct txp_rxbuf_desc)); 1133 1134 /* zero dma */ 1135 if (txp_dma_malloc(sc, sizeof(u_int32_t), &sc->sc_zero_dma, 1136 BUS_DMA_COHERENT)) { 1137 printf(": can't allocate response ring\n"); 1138 goto bail_rxbufring; 1139 } 1140 bzero(sc->sc_zero_dma.dma_vaddr, sizeof(u_int32_t)); 1141 boot->br_zero_lo = htole32(sc->sc_zero_dma.dma_paddr & 0xffffffff); 1142 boot->br_zero_hi = htole32(sc->sc_zero_dma.dma_paddr >> 32); 1143 1144 /* See if it's waiting for boot, and try to boot it */ 1145 for (i = 0; i < 10000; i++) { 1146 r = READ_REG(sc, TXP_A2H_0); 1147 if (r == STAT_WAITING_FOR_BOOT) 1148 break; 1149 DELAY(50); 1150 } 1151 if (r != STAT_WAITING_FOR_BOOT) { 1152 printf(": not waiting for boot\n"); 1153 goto bail; 1154 } 1155 WRITE_REG(sc, TXP_H2A_2, sc->sc_boot_dma.dma_paddr >> 32); 1156 WRITE_REG(sc, TXP_H2A_1, sc->sc_boot_dma.dma_paddr & 0xffffffff); 1157 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1158 1159 /* See if it booted */ 1160 for (i = 0; i < 10000; i++) { 1161 r = READ_REG(sc, TXP_A2H_0); 1162 if (r == STAT_RUNNING) 1163 break; 1164 DELAY(50); 1165 } 1166 if (r != STAT_RUNNING) { 1167 printf(": fw not running\n"); 1168 goto bail; 1169 } 1170 1171 /* Clear TX and CMD ring write registers */ 1172 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1173 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1174 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1175 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1176 1177 return (0); 1178 1179 bail: 1180 txp_dma_free(sc, &sc->sc_zero_dma); 1181 bail_rxbufring: 1182 txp_dma_free(sc, &sc->sc_rxbufring_dma); 1183 bail_rspring: 1184 txp_dma_free(sc, &sc->sc_rspring_dma); 1185 bail_cmdring: 1186 txp_dma_free(sc, &sc->sc_cmdring_dma); 1187 bail_rxloring: 1188 txp_dma_free(sc, &sc->sc_rxloring_dma); 1189 bail_rxhiring: 1190 txp_dma_free(sc, &sc->sc_rxhiring_dma); 1191 bail_txloring: 1192 txp_dma_free(sc, &sc->sc_txloring_dma); 1193 bail_txhiring: 1194 txp_dma_free(sc, &sc->sc_txhiring_dma); 1195 bail_host: 1196 txp_dma_free(sc, &sc->sc_host_dma); 1197 bail_boot: 1198 txp_dma_free(sc, &sc->sc_boot_dma); 1199 return (-1); 1200 } 1201 1202 int 1203 txp_dma_malloc(sc, size, dma, mapflags) 1204 struct txp_softc *sc; 1205 bus_size_t size; 1206 struct txp_dma_alloc *dma; 1207 int mapflags; 1208 { 1209 int r; 1210 1211 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 1212 &dma->dma_seg, 1, &dma->dma_nseg, 0)) != 0) 1213 goto fail_0; 1214 1215 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 1216 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 1217 goto fail_1; 1218 1219 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1220 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 1221 goto fail_2; 1222 1223 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 1224 size, NULL, BUS_DMA_NOWAIT)) != 0) 1225 goto fail_3; 1226 1227 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 1228 return (0); 1229 1230 fail_3: 1231 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1232 fail_2: 1233 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 1234 fail_1: 1235 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1236 fail_0: 1237 return (r); 1238 } 1239 1240 void 1241 txp_dma_free(sc, dma) 1242 struct txp_softc *sc; 1243 struct txp_dma_alloc *dma; 1244 { 1245 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 1246 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_map->dm_mapsize); 1247 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1248 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1249 } 1250 1251 int 1252 txp_ioctl(ifp, command, data) 1253 struct ifnet *ifp; 1254 u_long command; 1255 caddr_t data; 1256 { 1257 struct txp_softc *sc = ifp->if_softc; 1258 struct ifreq *ifr = (struct ifreq *)data; 1259 struct ifaddr *ifa = (struct ifaddr *)data; 1260 int s, error = 0; 1261 1262 s = splnet(); 1263 1264 #if 0 1265 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, command, data)) > 0) { 1266 splx(s); 1267 return error; 1268 } 1269 #endif 1270 1271 switch(command) { 1272 case SIOCSIFADDR: 1273 ifp->if_flags |= IFF_UP; 1274 switch (ifa->ifa_addr->sa_family) { 1275 #ifdef INET 1276 case AF_INET: 1277 txp_init(sc); 1278 arp_ifinit(ifp, ifa); 1279 break; 1280 #endif /* INET */ 1281 default: 1282 txp_init(sc); 1283 break; 1284 } 1285 break; 1286 case SIOCSIFFLAGS: 1287 if (ifp->if_flags & IFF_UP) { 1288 txp_init(sc); 1289 } else { 1290 if (ifp->if_flags & IFF_RUNNING) 1291 txp_stop(sc); 1292 } 1293 break; 1294 case SIOCADDMULTI: 1295 case SIOCDELMULTI: 1296 error = (command == SIOCADDMULTI) ? 1297 ether_addmulti(ifr, &sc->sc_arpcom) : 1298 ether_delmulti(ifr, &sc->sc_arpcom); 1299 1300 if (error == ENETRESET) { 1301 /* 1302 * Multicast list has changed; set the hardware 1303 * filter accordingly. 1304 */ 1305 if (ifp->if_flags & IFF_RUNNING) 1306 txp_set_filter(sc); 1307 error = 0; 1308 } 1309 break; 1310 case SIOCGIFMEDIA: 1311 case SIOCSIFMEDIA: 1312 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command); 1313 break; 1314 default: 1315 error = EINVAL; 1316 break; 1317 } 1318 1319 splx(s); 1320 1321 return(error); 1322 } 1323 1324 void 1325 txp_init(sc) 1326 struct txp_softc *sc; 1327 { 1328 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1329 int s; 1330 1331 txp_stop(sc); 1332 1333 s = splnet(); 1334 1335 txp_set_filter(sc); 1336 1337 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1338 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1339 1340 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1341 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1342 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1343 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1344 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1345 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1346 1347 ifp->if_flags |= IFF_RUNNING; 1348 ifp->if_flags &= ~IFF_OACTIVE; 1349 ifp->if_timer = 0; 1350 1351 if (!callout_pending(&sc->sc_tick)) 1352 callout_schedule(&sc->sc_tick, hz); 1353 1354 splx(s); 1355 } 1356 1357 void 1358 txp_tick(vsc) 1359 void *vsc; 1360 { 1361 struct txp_softc *sc = vsc; 1362 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1363 struct txp_rsp_desc *rsp = NULL; 1364 struct txp_ext_desc *ext; 1365 int s; 1366 1367 s = splnet(); 1368 txp_rxbuf_reclaim(sc); 1369 1370 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1371 &rsp, 1)) 1372 goto out; 1373 if (rsp->rsp_numdesc != 6) 1374 goto out; 1375 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1376 NULL, NULL, NULL, 1)) 1377 goto out; 1378 ext = (struct txp_ext_desc *)(rsp + 1); 1379 1380 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1381 ext[4].ext_1 + ext[4].ext_4; 1382 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1383 ext[2].ext_1; 1384 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1385 ext[1].ext_3; 1386 ifp->if_opackets += rsp->rsp_par2; 1387 ifp->if_ipackets += ext[2].ext_3; 1388 1389 out: 1390 if (rsp != NULL) 1391 free(rsp, M_DEVBUF); 1392 1393 splx(s); 1394 callout_schedule(&sc->sc_tick, hz); 1395 } 1396 1397 void 1398 txp_start(ifp) 1399 struct ifnet *ifp; 1400 { 1401 struct txp_softc *sc = ifp->if_softc; 1402 struct txp_tx_ring *r = &sc->sc_txhir; 1403 struct txp_tx_desc *txd; 1404 int txdidx; 1405 struct txp_frag_desc *fxd; 1406 struct mbuf *m, *mnew; 1407 struct txp_swdesc *sd; 1408 u_int32_t firstprod, firstcnt, prod, cnt, i; 1409 struct m_tag *mtag; 1410 1411 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1412 return; 1413 1414 prod = r->r_prod; 1415 cnt = r->r_cnt; 1416 1417 while (1) { 1418 IFQ_POLL(&ifp->if_snd, m); 1419 if (m == NULL) 1420 break; 1421 mnew = NULL; 1422 1423 firstprod = prod; 1424 firstcnt = cnt; 1425 1426 sd = sc->sc_txd + prod; 1427 sd->sd_mbuf = m; 1428 1429 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1430 BUS_DMA_NOWAIT)) { 1431 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1432 if (mnew == NULL) 1433 goto oactive1; 1434 if (m->m_pkthdr.len > MHLEN) { 1435 MCLGET(mnew, M_DONTWAIT); 1436 if ((mnew->m_flags & M_EXT) == 0) { 1437 m_freem(mnew); 1438 goto oactive1; 1439 } 1440 } 1441 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, caddr_t)); 1442 mnew->m_pkthdr.len = mnew->m_len = m->m_pkthdr.len; 1443 IFQ_DEQUEUE(&ifp->if_snd, m); 1444 m_freem(m); 1445 m = mnew; 1446 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1447 BUS_DMA_NOWAIT)) 1448 goto oactive1; 1449 } 1450 1451 if ((TX_ENTRIES - cnt) < 4) 1452 goto oactive; 1453 1454 txd = r->r_desc + prod; 1455 txdidx = prod; 1456 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1457 txd->tx_numdesc = 0; 1458 txd->tx_addrlo = 0; 1459 txd->tx_addrhi = 0; 1460 txd->tx_totlen = m->m_pkthdr.len; 1461 txd->tx_pflags = 0; 1462 txd->tx_numdesc = sd->sd_map->dm_nsegs; 1463 1464 if (++prod == TX_ENTRIES) 1465 prod = 0; 1466 1467 if (++cnt >= (TX_ENTRIES - 4)) 1468 goto oactive; 1469 1470 if ((mtag = VLAN_OUTPUT_TAG(sc->sc_ethercom, m))) 1471 txd->tx_pflags = TX_PFLAGS_VLAN | 1472 (htons(VLAN_TAG_VALUE(mtag)) << TX_PFLAGS_VLANTAG_S); 1473 1474 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 1475 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1476 #ifdef TRY_TX_TCP_CSUM 1477 if (m->m_pkthdr.csum_flags & M_CSUM_TCPv4) 1478 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1479 #endif 1480 #ifdef TRY_TX_UDP_CSUM 1481 if (m->m_pkthdr.csum_flags & M_CSUM_UDPv4) 1482 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1483 #endif 1484 1485 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1486 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1487 1488 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1489 for (i = 0; i < sd->sd_map->dm_nsegs; i++) { 1490 if (++cnt >= (TX_ENTRIES - 4)) { 1491 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 1492 0, sd->sd_map->dm_mapsize, 1493 BUS_DMASYNC_POSTWRITE); 1494 goto oactive; 1495 } 1496 1497 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG | 1498 FRAG_FLAGS_VALID; 1499 fxd->frag_rsvd1 = 0; 1500 fxd->frag_len = sd->sd_map->dm_segs[i].ds_len; 1501 fxd->frag_addrlo = 1502 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) & 1503 0xffffffff; 1504 fxd->frag_addrhi = 1505 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) >> 1506 32; 1507 fxd->frag_rsvd2 = 0; 1508 1509 bus_dmamap_sync(sc->sc_dmat, 1510 sc->sc_txhiring_dma.dma_map, 1511 prod * sizeof(struct txp_frag_desc), 1512 sizeof(struct txp_frag_desc), BUS_DMASYNC_PREWRITE); 1513 1514 if (++prod == TX_ENTRIES) { 1515 fxd = (struct txp_frag_desc *)r->r_desc; 1516 prod = 0; 1517 } else 1518 fxd++; 1519 1520 } 1521 1522 /* 1523 * if mnew isn't NULL, we already dequeued and copied 1524 * the packet. 1525 */ 1526 if (mnew == NULL) 1527 IFQ_DEQUEUE(&ifp->if_snd, m); 1528 1529 ifp->if_timer = 5; 1530 1531 #if NBPFILTER > 0 1532 if (ifp->if_bpf) 1533 bpf_mtap(ifp->if_bpf, m); 1534 #endif 1535 1536 txd->tx_flags |= TX_FLAGS_VALID; 1537 bus_dmamap_sync(sc->sc_dmat, sc->sc_txhiring_dma.dma_map, 1538 txdidx * sizeof(struct txp_tx_desc), 1539 sizeof(struct txp_tx_desc), BUS_DMASYNC_PREWRITE); 1540 1541 #if 0 1542 { 1543 struct mbuf *mx; 1544 int i; 1545 1546 printf("txd: flags 0x%x ndesc %d totlen %d pflags 0x%x\n", 1547 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1548 txd->tx_pflags); 1549 for (mx = m; mx != NULL; mx = mx->m_next) { 1550 for (i = 0; i < mx->m_len; i++) { 1551 printf(":%02x", 1552 (u_int8_t)m->m_data[i]); 1553 } 1554 } 1555 printf("\n"); 1556 } 1557 #endif 1558 1559 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1560 } 1561 1562 r->r_prod = prod; 1563 r->r_cnt = cnt; 1564 return; 1565 1566 oactive: 1567 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 1568 oactive1: 1569 ifp->if_flags |= IFF_OACTIVE; 1570 r->r_prod = firstprod; 1571 r->r_cnt = firstcnt; 1572 } 1573 1574 /* 1575 * Handle simple commands sent to the typhoon 1576 */ 1577 int 1578 txp_command(sc, id, in1, in2, in3, out1, out2, out3, wait) 1579 struct txp_softc *sc; 1580 u_int16_t id, in1, *out1; 1581 u_int32_t in2, in3, *out2, *out3; 1582 int wait; 1583 { 1584 struct txp_rsp_desc *rsp = NULL; 1585 1586 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1587 return (-1); 1588 1589 if (!wait) 1590 return (0); 1591 1592 if (out1 != NULL) 1593 *out1 = le16toh(rsp->rsp_par1); 1594 if (out2 != NULL) 1595 *out2 = le32toh(rsp->rsp_par2); 1596 if (out3 != NULL) 1597 *out3 = le32toh(rsp->rsp_par3); 1598 free(rsp, M_DEVBUF); 1599 return (0); 1600 } 1601 1602 int 1603 txp_command2(sc, id, in1, in2, in3, in_extp, in_extn, rspp, wait) 1604 struct txp_softc *sc; 1605 u_int16_t id, in1; 1606 u_int32_t in2, in3; 1607 struct txp_ext_desc *in_extp; 1608 u_int8_t in_extn; 1609 struct txp_rsp_desc **rspp; 1610 int wait; 1611 { 1612 struct txp_hostvar *hv = sc->sc_hostvar; 1613 struct txp_cmd_desc *cmd; 1614 struct txp_ext_desc *ext; 1615 u_int32_t idx, i; 1616 u_int16_t seq; 1617 1618 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1619 printf("%s: no free cmd descriptors\n", TXP_DEVNAME(sc)); 1620 return (-1); 1621 } 1622 1623 idx = sc->sc_cmdring.lastwrite; 1624 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1625 bzero(cmd, sizeof(*cmd)); 1626 1627 cmd->cmd_numdesc = in_extn; 1628 seq = sc->sc_seq++; 1629 cmd->cmd_seq = htole16(seq); 1630 cmd->cmd_id = htole16(id); 1631 cmd->cmd_par1 = htole16(in1); 1632 cmd->cmd_par2 = htole32(in2); 1633 cmd->cmd_par3 = htole32(in3); 1634 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1635 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1636 1637 idx += sizeof(struct txp_cmd_desc); 1638 if (idx == sc->sc_cmdring.size) 1639 idx = 0; 1640 1641 for (i = 0; i < in_extn; i++) { 1642 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1643 bcopy(in_extp, ext, sizeof(struct txp_ext_desc)); 1644 in_extp++; 1645 idx += sizeof(struct txp_cmd_desc); 1646 if (idx == sc->sc_cmdring.size) 1647 idx = 0; 1648 } 1649 1650 sc->sc_cmdring.lastwrite = idx; 1651 1652 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1653 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1654 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1655 1656 if (!wait) 1657 return (0); 1658 1659 for (i = 0; i < 10000; i++) { 1660 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1661 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTREAD); 1662 idx = le32toh(hv->hv_resp_read_idx); 1663 if (idx != le32toh(hv->hv_resp_write_idx)) { 1664 *rspp = NULL; 1665 if (txp_response(sc, idx, id, seq, rspp)) 1666 return (-1); 1667 if (*rspp != NULL) 1668 break; 1669 } 1670 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1671 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1672 DELAY(50); 1673 } 1674 if (i == 1000 || (*rspp) == NULL) { 1675 printf("%s: 0x%x command failed\n", TXP_DEVNAME(sc), id); 1676 return (-1); 1677 } 1678 1679 return (0); 1680 } 1681 1682 int 1683 txp_response(sc, ridx, id, seq, rspp) 1684 struct txp_softc *sc; 1685 u_int32_t ridx; 1686 u_int16_t id; 1687 u_int16_t seq; 1688 struct txp_rsp_desc **rspp; 1689 { 1690 struct txp_hostvar *hv = sc->sc_hostvar; 1691 struct txp_rsp_desc *rsp; 1692 1693 while (ridx != le32toh(hv->hv_resp_write_idx)) { 1694 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx); 1695 1696 if (id == le16toh(rsp->rsp_id) && le16toh(rsp->rsp_seq) == seq) { 1697 *rspp = (struct txp_rsp_desc *)malloc( 1698 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1699 M_DEVBUF, M_NOWAIT); 1700 if ((*rspp) == NULL) 1701 return (-1); 1702 txp_rsp_fixup(sc, rsp, *rspp); 1703 return (0); 1704 } 1705 1706 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1707 printf("%s: response error: id 0x%x\n", 1708 TXP_DEVNAME(sc), le16toh(rsp->rsp_id)); 1709 txp_rsp_fixup(sc, rsp, NULL); 1710 ridx = le32toh(hv->hv_resp_read_idx); 1711 continue; 1712 } 1713 1714 switch (le16toh(rsp->rsp_id)) { 1715 case TXP_CMD_CYCLE_STATISTICS: 1716 case TXP_CMD_MEDIA_STATUS_READ: 1717 break; 1718 case TXP_CMD_HELLO_RESPONSE: 1719 printf("%s: hello\n", TXP_DEVNAME(sc)); 1720 break; 1721 default: 1722 printf("%s: unknown id(0x%x)\n", TXP_DEVNAME(sc), 1723 le16toh(rsp->rsp_id)); 1724 } 1725 1726 txp_rsp_fixup(sc, rsp, NULL); 1727 ridx = le32toh(hv->hv_resp_read_idx); 1728 hv->hv_resp_read_idx = le32toh(ridx); 1729 } 1730 1731 return (0); 1732 } 1733 1734 void 1735 txp_rsp_fixup(sc, rsp, dst) 1736 struct txp_softc *sc; 1737 struct txp_rsp_desc *rsp, *dst; 1738 { 1739 struct txp_rsp_desc *src = rsp; 1740 struct txp_hostvar *hv = sc->sc_hostvar; 1741 u_int32_t i, ridx; 1742 1743 ridx = le32toh(hv->hv_resp_read_idx); 1744 1745 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1746 if (dst != NULL) 1747 bcopy(src, dst++, sizeof(struct txp_rsp_desc)); 1748 ridx += sizeof(struct txp_rsp_desc); 1749 if (ridx == sc->sc_rspring.size) { 1750 src = sc->sc_rspring.base; 1751 ridx = 0; 1752 } else 1753 src++; 1754 sc->sc_rspring.lastwrite = ridx; 1755 hv->hv_resp_read_idx = htole32(ridx); 1756 } 1757 1758 hv->hv_resp_read_idx = htole32(ridx); 1759 } 1760 1761 int 1762 txp_cmd_desc_numfree(sc) 1763 struct txp_softc *sc; 1764 { 1765 struct txp_hostvar *hv = sc->sc_hostvar; 1766 struct txp_boot_record *br = sc->sc_boot; 1767 u_int32_t widx, ridx, nfree; 1768 1769 widx = sc->sc_cmdring.lastwrite; 1770 ridx = le32toh(hv->hv_cmd_read_idx); 1771 1772 if (widx == ridx) { 1773 /* Ring is completely free */ 1774 nfree = le32toh(br->br_cmd_siz) - sizeof(struct txp_cmd_desc); 1775 } else { 1776 if (widx > ridx) 1777 nfree = le32toh(br->br_cmd_siz) - 1778 (widx - ridx + sizeof(struct txp_cmd_desc)); 1779 else 1780 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1781 } 1782 1783 return (nfree / sizeof(struct txp_cmd_desc)); 1784 } 1785 1786 void 1787 txp_stop(sc) 1788 struct txp_softc *sc; 1789 { 1790 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1791 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1792 1793 if (callout_pending(&sc->sc_tick)) 1794 callout_stop(&sc->sc_tick); 1795 } 1796 1797 void 1798 txp_watchdog(ifp) 1799 struct ifnet *ifp; 1800 { 1801 } 1802 1803 int 1804 txp_ifmedia_upd(ifp) 1805 struct ifnet *ifp; 1806 { 1807 struct txp_softc *sc = ifp->if_softc; 1808 struct ifmedia *ifm = &sc->sc_ifmedia; 1809 u_int16_t new_xcvr; 1810 1811 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1812 return (EINVAL); 1813 1814 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1815 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1816 new_xcvr = TXP_XCVR_10_FDX; 1817 else 1818 new_xcvr = TXP_XCVR_10_HDX; 1819 } else if ((IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) || 1820 (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX)) { 1821 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1822 new_xcvr = TXP_XCVR_100_FDX; 1823 else 1824 new_xcvr = TXP_XCVR_100_HDX; 1825 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1826 new_xcvr = TXP_XCVR_AUTO; 1827 } else 1828 return (EINVAL); 1829 1830 /* nothing to do */ 1831 if (sc->sc_xcvr == new_xcvr) 1832 return (0); 1833 1834 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1835 NULL, NULL, NULL, 0); 1836 sc->sc_xcvr = new_xcvr; 1837 1838 return (0); 1839 } 1840 1841 void 1842 txp_ifmedia_sts(ifp, ifmr) 1843 struct ifnet *ifp; 1844 struct ifmediareq *ifmr; 1845 { 1846 struct txp_softc *sc = ifp->if_softc; 1847 struct ifmedia *ifm = &sc->sc_ifmedia; 1848 u_int16_t bmsr, bmcr, anlpar; 1849 1850 ifmr->ifm_status = IFM_AVALID; 1851 ifmr->ifm_active = IFM_ETHER; 1852 1853 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1854 &bmsr, NULL, NULL, 1)) 1855 goto bail; 1856 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1857 &bmsr, NULL, NULL, 1)) 1858 goto bail; 1859 1860 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1861 &bmcr, NULL, NULL, 1)) 1862 goto bail; 1863 1864 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1865 &anlpar, NULL, NULL, 1)) 1866 goto bail; 1867 1868 if (bmsr & BMSR_LINK) 1869 ifmr->ifm_status |= IFM_ACTIVE; 1870 1871 if (bmcr & BMCR_ISO) { 1872 ifmr->ifm_active |= IFM_NONE; 1873 ifmr->ifm_status = 0; 1874 return; 1875 } 1876 1877 if (bmcr & BMCR_LOOP) 1878 ifmr->ifm_active |= IFM_LOOP; 1879 1880 if (!(sc->sc_flags & TXP_FIBER) && (bmcr & BMCR_AUTOEN)) { 1881 if ((bmsr & BMSR_ACOMP) == 0) { 1882 ifmr->ifm_active |= IFM_NONE; 1883 return; 1884 } 1885 1886 if (anlpar & ANLPAR_T4) 1887 ifmr->ifm_active |= IFM_100_T4; 1888 else if (anlpar & ANLPAR_TX_FD) 1889 ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1890 else if (anlpar & ANLPAR_TX) 1891 ifmr->ifm_active |= IFM_100_TX; 1892 else if (anlpar & ANLPAR_10_FD) 1893 ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1894 else if (anlpar & ANLPAR_10) 1895 ifmr->ifm_active |= IFM_10_T; 1896 else 1897 ifmr->ifm_active |= IFM_NONE; 1898 } else 1899 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1900 return; 1901 1902 bail: 1903 ifmr->ifm_active |= IFM_NONE; 1904 ifmr->ifm_status &= ~IFM_AVALID; 1905 } 1906 1907 void 1908 txp_show_descriptor(d) 1909 void *d; 1910 { 1911 struct txp_cmd_desc *cmd = d; 1912 struct txp_rsp_desc *rsp = d; 1913 struct txp_tx_desc *txd = d; 1914 struct txp_frag_desc *frgd = d; 1915 1916 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1917 case CMD_FLAGS_TYPE_CMD: 1918 /* command descriptor */ 1919 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1920 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1921 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1922 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1923 break; 1924 case CMD_FLAGS_TYPE_RESP: 1925 /* response descriptor */ 1926 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1927 rsp->rsp_flags, rsp->rsp_numdesc, le16toh(rsp->rsp_id), 1928 le16toh(rsp->rsp_seq), le16toh(rsp->rsp_par1), 1929 le32toh(rsp->rsp_par2), le32toh(rsp->rsp_par3)); 1930 break; 1931 case CMD_FLAGS_TYPE_DATA: 1932 /* data header (assuming tx for now) */ 1933 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]", 1934 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1935 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1936 break; 1937 case CMD_FLAGS_TYPE_FRAG: 1938 /* fragment descriptor */ 1939 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]", 1940 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1941 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1942 break; 1943 default: 1944 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1945 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1946 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1947 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1948 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1949 break; 1950 } 1951 } 1952 1953 void 1954 txp_set_filter(sc) 1955 struct txp_softc *sc; 1956 { 1957 struct ethercom *ac = &sc->sc_arpcom; 1958 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1959 u_int32_t crc, carry, hashbit, hash[2]; 1960 u_int16_t filter; 1961 u_int8_t octet; 1962 int i, j, mcnt = 0; 1963 struct ether_multi *enm; 1964 struct ether_multistep step; 1965 1966 if (ifp->if_flags & IFF_PROMISC) { 1967 filter = TXP_RXFILT_PROMISC; 1968 goto setit; 1969 } 1970 1971 again: 1972 filter = TXP_RXFILT_DIRECT; 1973 1974 if (ifp->if_flags & IFF_BROADCAST) 1975 filter |= TXP_RXFILT_BROADCAST; 1976 1977 if (ifp->if_flags & IFF_ALLMULTI) 1978 filter |= TXP_RXFILT_ALLMULTI; 1979 else { 1980 hash[0] = hash[1] = 0; 1981 1982 ETHER_FIRST_MULTI(step, ac, enm); 1983 while (enm != NULL) { 1984 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1985 /* 1986 * We must listen to a range of multicast 1987 * addresses. For now, just accept all 1988 * multicasts, rather than trying to set only 1989 * those filter bits needed to match the range. 1990 * (At this time, the only use of address 1991 * ranges is for IP multicast routing, for 1992 * which the range is big enough to require 1993 * all bits set.) 1994 */ 1995 ifp->if_flags |= IFF_ALLMULTI; 1996 goto again; 1997 } 1998 1999 mcnt++; 2000 crc = 0xffffffff; 2001 2002 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2003 octet = enm->enm_addrlo[i]; 2004 for (j = 0; j < 8; j++) { 2005 carry = ((crc & 0x80000000) ? 1 : 0) ^ 2006 (octet & 1); 2007 crc <<= 1; 2008 octet >>= 1; 2009 if (carry) 2010 crc = (crc ^ TXP_POLYNOMIAL) | 2011 carry; 2012 } 2013 } 2014 hashbit = (u_int16_t)(crc & (64 - 1)); 2015 hash[hashbit / 32] |= (1 << hashbit % 32); 2016 ETHER_NEXT_MULTI(step, enm); 2017 } 2018 2019 if (mcnt > 0) { 2020 filter |= TXP_RXFILT_HASHMULTI; 2021 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 2022 2, hash[0], hash[1], NULL, NULL, NULL, 0); 2023 } 2024 } 2025 2026 setit: 2027 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 2028 NULL, NULL, NULL, 1); 2029 } 2030 2031 void 2032 txp_capabilities(sc) 2033 struct txp_softc *sc; 2034 { 2035 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 2036 struct txp_rsp_desc *rsp = NULL; 2037 struct txp_ext_desc *ext; 2038 2039 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 2040 goto out; 2041 2042 if (rsp->rsp_numdesc != 1) 2043 goto out; 2044 ext = (struct txp_ext_desc *)(rsp + 1); 2045 2046 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 2047 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 2048 2049 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_MTU; 2050 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 2051 sc->sc_tx_capability |= OFFLOAD_VLAN; 2052 sc->sc_rx_capability |= OFFLOAD_VLAN; 2053 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 2054 } 2055 2056 #if 0 2057 /* not ready yet */ 2058 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 2059 sc->sc_tx_capability |= OFFLOAD_IPSEC; 2060 sc->sc_rx_capability |= OFFLOAD_IPSEC; 2061 ifp->if_capabilities |= IFCAP_IPSEC; 2062 } 2063 #endif 2064 2065 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 2066 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 2067 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 2068 ifp->if_capabilities |= IFCAP_CSUM_IPv4; 2069 } 2070 2071 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 2072 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 2073 #ifdef TRY_TX_TCP_CSUM 2074 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 2075 ifp->if_capabilities |= IFCAP_CSUM_TCPv4; 2076 #endif 2077 } 2078 2079 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 2080 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 2081 #ifdef TRY_TX_UDP_CSUM 2082 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 2083 ifp->if_capabilities |= IFCAP_CSUM_UDPv4; 2084 #endif 2085 } 2086 2087 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 2088 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 2089 goto out; 2090 2091 out: 2092 if (rsp != NULL) 2093 free(rsp, M_DEVBUF); 2094 } 2095