1 /* $NetBSD: if_txp.c,v 1.15 2006/04/14 18:45:53 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2001 5 * Jason L. Wright <jason@thought.net>, Theo de Raadt, and 6 * Aaron Campbell <aaron@monkey.org>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR THE VOICES IN THEIR HEADS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * Driver for 3c990 (Typhoon) Ethernet ASIC 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: if_txp.c,v 1.15 2006/04/14 18:45:53 christos Exp $"); 36 37 #include "bpfilter.h" 38 #include "opt_inet.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/sockio.h> 43 #include <sys/mbuf.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/device.h> 48 #include <sys/callout.h> 49 50 #include <net/if.h> 51 #include <net/if_dl.h> 52 #include <net/if_types.h> 53 #include <net/if_ether.h> 54 #include <net/if_arp.h> 55 56 #ifdef INET 57 #include <netinet/in.h> 58 #include <netinet/in_systm.h> 59 #include <netinet/in_var.h> 60 #include <netinet/ip.h> 61 #include <netinet/if_inarp.h> 62 #endif 63 64 #include <net/if_media.h> 65 66 #if NBPFILTER > 0 67 #include <net/bpf.h> 68 #endif 69 70 #include <uvm/uvm_extern.h> /* for vtophys */ 71 #include <machine/bus.h> 72 73 #include <dev/mii/mii.h> 74 #include <dev/mii/miivar.h> 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/pcidevs.h> 78 79 #include <dev/pci/if_txpreg.h> 80 81 #include <dev/microcode/typhoon/3c990img.h> 82 83 /* 84 * These currently break the 3c990 firmware, hopefully will be resolved 85 * at some point. 86 */ 87 #undef TRY_TX_UDP_CSUM 88 #undef TRY_TX_TCP_CSUM 89 90 int txp_probe(struct device *, struct cfdata *, void *); 91 void txp_attach(struct device *, struct device *, void *); 92 int txp_intr(void *); 93 void txp_tick(void *); 94 void txp_shutdown(void *); 95 int txp_ioctl(struct ifnet *, u_long, caddr_t); 96 void txp_start(struct ifnet *); 97 void txp_stop(struct txp_softc *); 98 void txp_init(struct txp_softc *); 99 void txp_watchdog(struct ifnet *); 100 101 int txp_chip_init(struct txp_softc *); 102 int txp_reset_adapter(struct txp_softc *); 103 int txp_download_fw(struct txp_softc *); 104 int txp_download_fw_wait(struct txp_softc *); 105 int txp_download_fw_section(struct txp_softc *, 106 const struct txp_fw_section_header *, int); 107 int txp_alloc_rings(struct txp_softc *); 108 void txp_dma_free(struct txp_softc *, struct txp_dma_alloc *); 109 int txp_dma_malloc(struct txp_softc *, bus_size_t, struct txp_dma_alloc *, int); 110 void txp_set_filter(struct txp_softc *); 111 112 int txp_cmd_desc_numfree(struct txp_softc *); 113 int txp_command(struct txp_softc *, u_int16_t, u_int16_t, u_int32_t, 114 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int); 115 int txp_command2(struct txp_softc *, u_int16_t, u_int16_t, 116 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t, 117 struct txp_rsp_desc **, int); 118 int txp_response(struct txp_softc *, u_int32_t, u_int16_t, u_int16_t, 119 struct txp_rsp_desc **); 120 void txp_rsp_fixup(struct txp_softc *, struct txp_rsp_desc *, 121 struct txp_rsp_desc *); 122 void txp_capabilities(struct txp_softc *); 123 124 void txp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 125 int txp_ifmedia_upd(struct ifnet *); 126 void txp_show_descriptor(void *); 127 void txp_tx_reclaim(struct txp_softc *, struct txp_tx_ring *, 128 struct txp_dma_alloc *); 129 void txp_rxbuf_reclaim(struct txp_softc *); 130 void txp_rx_reclaim(struct txp_softc *, struct txp_rx_ring *, 131 struct txp_dma_alloc *); 132 133 CFATTACH_DECL(txp, sizeof(struct txp_softc), txp_probe, txp_attach, 134 NULL, NULL); 135 136 const struct txp_pci_match { 137 int vid, did, flags; 138 } txp_devices[] = { 139 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990, 0 }, 140 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX95, 0 }, 141 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX97, 0 }, 142 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR95, TXP_SERVERVERSION }, 143 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR97, TXP_SERVERVERSION }, 144 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990B, TXP_USESUBSYSTEM }, 145 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BSVR, TXP_SERVERVERSION }, 146 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990FX, TXP_USESUBSYSTEM }, 147 }; 148 149 static const struct txp_pci_match *txp_pcilookup(pcireg_t); 150 151 static const struct { 152 u_int16_t mask, value; 153 int flags; 154 } txp_subsysinfo[] = { 155 {0xf000, 0x2000, TXP_SERVERVERSION}, 156 {0x0100, 0x0100, TXP_FIBER}, 157 #if 0 /* information from 3com header, unused */ 158 {0x0010, 0x0010, /* secured firmware */}, 159 {0x0003, 0x0000, /* variable DES */}, 160 {0x0003, 0x0001, /* single DES - "95" */}, 161 {0x0003, 0x0002, /* triple DES - "97" */}, 162 #endif 163 }; 164 165 static const struct txp_pci_match * 166 txp_pcilookup(id) 167 pcireg_t id; 168 { 169 int i; 170 171 for (i = 0; i < sizeof(txp_devices) / sizeof(txp_devices[0]); i++) 172 if ((PCI_VENDOR(id) == txp_devices[i].vid) && 173 (PCI_PRODUCT(id) == txp_devices[i].did)) 174 return (&txp_devices[i]); 175 return (0); 176 } 177 178 int 179 txp_probe(parent, match, aux) 180 struct device *parent; 181 struct cfdata *match; 182 void *aux; 183 { 184 struct pci_attach_args *pa = aux; 185 186 if (txp_pcilookup(pa->pa_id)) 187 return (1); 188 return (0); 189 } 190 191 void 192 txp_attach(parent, self, aux) 193 struct device *parent, *self; 194 void *aux; 195 { 196 struct txp_softc *sc = (struct txp_softc *)self; 197 struct pci_attach_args *pa = aux; 198 pci_chipset_tag_t pc = pa->pa_pc; 199 pci_intr_handle_t ih; 200 const char *intrstr = NULL; 201 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 202 u_int32_t command; 203 u_int16_t p1; 204 u_int32_t p2; 205 u_char enaddr[6]; 206 const struct txp_pci_match *pcimatch; 207 u_int16_t subsys; 208 int i, flags; 209 char devinfo[256]; 210 211 sc->sc_cold = 1; 212 213 pcimatch = txp_pcilookup(pa->pa_id); 214 flags = pcimatch->flags; 215 if (pcimatch->flags & TXP_USESUBSYSTEM) { 216 subsys = PCI_PRODUCT(pci_conf_read(pc, pa->pa_tag, 217 PCI_SUBSYS_ID_REG)); 218 for (i = 0; 219 i < sizeof(txp_subsysinfo)/sizeof(txp_subsysinfo[0]); 220 i++) 221 if ((subsys & txp_subsysinfo[i].mask) == 222 txp_subsysinfo[i].value) 223 flags |= txp_subsysinfo[i].flags; 224 } 225 sc->sc_flags = flags; 226 227 pci_devinfo(pa->pa_id, 0, 0, devinfo, sizeof(devinfo)); 228 #define TXP_EXTRAINFO ((flags & (TXP_USESUBSYSTEM|TXP_SERVERVERSION)) == \ 229 (TXP_USESUBSYSTEM|TXP_SERVERVERSION) ? " (SVR)" : "") 230 printf(": %s%s\n%s", devinfo, TXP_EXTRAINFO, sc->sc_dev.dv_xname); 231 232 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 233 234 if (!(command & PCI_COMMAND_MASTER_ENABLE)) { 235 printf(": failed to enable bus mastering\n"); 236 return; 237 } 238 239 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 240 printf(": failed to enable memory mapping\n"); 241 return; 242 } 243 if (pci_mapreg_map(pa, TXP_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 244 &sc->sc_bt, &sc->sc_bh, NULL, NULL)) { 245 printf(": can't map mem space %d\n", 0); 246 return; 247 } 248 249 sc->sc_dmat = pa->pa_dmat; 250 251 /* 252 * Allocate our interrupt. 253 */ 254 if (pci_intr_map(pa, &ih)) { 255 printf(": couldn't map interrupt\n"); 256 return; 257 } 258 259 intrstr = pci_intr_string(pc, ih); 260 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, txp_intr, sc); 261 if (sc->sc_ih == NULL) { 262 printf(": couldn't establish interrupt"); 263 if (intrstr != NULL) 264 printf(" at %s", intrstr); 265 printf("\n"); 266 return; 267 } 268 printf(": interrupting at %s\n", intrstr); 269 270 if (txp_chip_init(sc)) 271 goto cleanupintr; 272 273 if (txp_download_fw(sc)) 274 goto cleanupintr; 275 276 if (txp_alloc_rings(sc)) 277 goto cleanupintr; 278 279 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 280 NULL, NULL, NULL, 1)) 281 goto cleanupintr; 282 283 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 284 &p1, &p2, NULL, 1)) 285 goto cleanupintr; 286 287 txp_set_filter(sc); 288 289 p1 = htole16(p1); 290 enaddr[0] = ((u_int8_t *)&p1)[1]; 291 enaddr[1] = ((u_int8_t *)&p1)[0]; 292 p2 = htole32(p2); 293 enaddr[2] = ((u_int8_t *)&p2)[3]; 294 enaddr[3] = ((u_int8_t *)&p2)[2]; 295 enaddr[4] = ((u_int8_t *)&p2)[1]; 296 enaddr[5] = ((u_int8_t *)&p2)[0]; 297 298 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 299 ether_sprintf(enaddr)); 300 sc->sc_cold = 0; 301 302 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 303 if (flags & TXP_FIBER) { 304 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX, 305 0, NULL); 306 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX|IFM_HDX, 307 0, NULL); 308 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_FX|IFM_FDX, 309 0, NULL); 310 } else { 311 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 312 0, NULL); 313 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 314 0, NULL); 315 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 316 0, NULL); 317 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 318 0, NULL); 319 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 320 0, NULL); 321 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 322 0, NULL); 323 } 324 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 325 326 sc->sc_xcvr = TXP_XCVR_AUTO; 327 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 328 NULL, NULL, NULL, 0); 329 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 330 331 ifp->if_softc = sc; 332 ifp->if_mtu = ETHERMTU; 333 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 334 ifp->if_ioctl = txp_ioctl; 335 ifp->if_start = txp_start; 336 ifp->if_watchdog = txp_watchdog; 337 ifp->if_baudrate = 10000000; 338 IFQ_SET_MAXLEN(&ifp->if_snd, TX_ENTRIES); 339 IFQ_SET_READY(&ifp->if_snd); 340 ifp->if_capabilities = 0; 341 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 342 343 txp_capabilities(sc); 344 345 callout_init(&sc->sc_tick); 346 callout_setfunc(&sc->sc_tick, txp_tick, sc); 347 348 /* 349 * Attach us everywhere 350 */ 351 if_attach(ifp); 352 ether_ifattach(ifp, enaddr); 353 354 shutdownhook_establish(txp_shutdown, sc); 355 356 357 return; 358 359 cleanupintr: 360 pci_intr_disestablish(pc,sc->sc_ih); 361 362 return; 363 364 } 365 366 int 367 txp_chip_init(sc) 368 struct txp_softc *sc; 369 { 370 /* disable interrupts */ 371 WRITE_REG(sc, TXP_IER, 0); 372 WRITE_REG(sc, TXP_IMR, 373 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 374 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 375 TXP_INT_LATCH); 376 377 /* ack all interrupts */ 378 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 379 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 380 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 381 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 382 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 383 384 if (txp_reset_adapter(sc)) 385 return (-1); 386 387 /* disable interrupts */ 388 WRITE_REG(sc, TXP_IER, 0); 389 WRITE_REG(sc, TXP_IMR, 390 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 391 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 392 TXP_INT_LATCH); 393 394 /* ack all interrupts */ 395 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 396 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 397 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 398 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 399 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 400 401 return (0); 402 } 403 404 int 405 txp_reset_adapter(sc) 406 struct txp_softc *sc; 407 { 408 u_int32_t r; 409 int i; 410 411 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 412 DELAY(1000); 413 WRITE_REG(sc, TXP_SRR, 0); 414 415 /* Should wait max 6 seconds */ 416 for (i = 0; i < 6000; i++) { 417 r = READ_REG(sc, TXP_A2H_0); 418 if (r == STAT_WAITING_FOR_HOST_REQUEST) 419 break; 420 DELAY(1000); 421 } 422 423 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 424 printf("%s: reset hung\n", TXP_DEVNAME(sc)); 425 return (-1); 426 } 427 428 return (0); 429 } 430 431 int 432 txp_download_fw(sc) 433 struct txp_softc *sc; 434 { 435 const struct txp_fw_file_header *fileheader; 436 const struct txp_fw_section_header *secthead; 437 int sect; 438 u_int32_t r, i, ier, imr; 439 440 ier = READ_REG(sc, TXP_IER); 441 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 442 443 imr = READ_REG(sc, TXP_IMR); 444 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 445 446 for (i = 0; i < 10000; i++) { 447 r = READ_REG(sc, TXP_A2H_0); 448 if (r == STAT_WAITING_FOR_HOST_REQUEST) 449 break; 450 DELAY(50); 451 } 452 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 453 printf(": not waiting for host request\n"); 454 return (-1); 455 } 456 457 /* Ack the status */ 458 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 459 460 fileheader = (const struct txp_fw_file_header *)tc990image; 461 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) { 462 printf(": fw invalid magic\n"); 463 return (-1); 464 } 465 466 /* Tell boot firmware to get ready for image */ 467 WRITE_REG(sc, TXP_H2A_1, le32toh(fileheader->addr)); 468 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 469 470 if (txp_download_fw_wait(sc)) { 471 printf("%s: fw wait failed, initial\n", sc->sc_dev.dv_xname); 472 return (-1); 473 } 474 475 secthead = (const struct txp_fw_section_header *) 476 (((const u_int8_t *)tc990image) + 477 sizeof(struct txp_fw_file_header)); 478 479 for (sect = 0; sect < le32toh(fileheader->nsections); sect++) { 480 if (txp_download_fw_section(sc, secthead, sect)) 481 return (-1); 482 secthead = (const struct txp_fw_section_header *) 483 (((const u_int8_t *)secthead) + le32toh(secthead->nbytes) + 484 sizeof(*secthead)); 485 } 486 487 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 488 489 for (i = 0; i < 10000; i++) { 490 r = READ_REG(sc, TXP_A2H_0); 491 if (r == STAT_WAITING_FOR_BOOT) 492 break; 493 DELAY(50); 494 } 495 if (r != STAT_WAITING_FOR_BOOT) { 496 printf(": not waiting for boot\n"); 497 return (-1); 498 } 499 500 WRITE_REG(sc, TXP_IER, ier); 501 WRITE_REG(sc, TXP_IMR, imr); 502 503 return (0); 504 } 505 506 int 507 txp_download_fw_wait(sc) 508 struct txp_softc *sc; 509 { 510 u_int32_t i, r; 511 512 for (i = 0; i < 10000; i++) { 513 r = READ_REG(sc, TXP_ISR); 514 if (r & TXP_INT_A2H_0) 515 break; 516 DELAY(50); 517 } 518 519 if (!(r & TXP_INT_A2H_0)) { 520 printf(": fw wait failed comm0\n"); 521 return (-1); 522 } 523 524 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 525 526 r = READ_REG(sc, TXP_A2H_0); 527 if (r != STAT_WAITING_FOR_SEGMENT) { 528 printf(": fw not waiting for segment\n"); 529 return (-1); 530 } 531 return (0); 532 } 533 534 int 535 txp_download_fw_section(sc, sect, sectnum) 536 struct txp_softc *sc; 537 const struct txp_fw_section_header *sect; 538 int sectnum; 539 { 540 struct txp_dma_alloc dma; 541 int rseg, err = 0; 542 struct mbuf m; 543 #ifdef INET 544 u_int16_t csum; 545 #endif 546 547 /* Skip zero length sections */ 548 if (sect->nbytes == 0) 549 return (0); 550 551 /* Make sure we aren't past the end of the image */ 552 rseg = ((const u_int8_t *)sect) - ((const u_int8_t *)tc990image); 553 if (rseg >= sizeof(tc990image)) { 554 printf(": fw invalid section address, section %d\n", sectnum); 555 return (-1); 556 } 557 558 /* Make sure this section doesn't go past the end */ 559 rseg += le32toh(sect->nbytes); 560 if (rseg >= sizeof(tc990image)) { 561 printf(": fw truncated section %d\n", sectnum); 562 return (-1); 563 } 564 565 /* map a buffer, copy segment to it, get physaddr */ 566 if (txp_dma_malloc(sc, le32toh(sect->nbytes), &dma, 0)) { 567 printf(": fw dma malloc failed, section %d\n", sectnum); 568 return (-1); 569 } 570 571 bcopy(((const u_int8_t *)sect) + sizeof(*sect), dma.dma_vaddr, 572 le32toh(sect->nbytes)); 573 574 /* 575 * dummy up mbuf and verify section checksum 576 */ 577 m.m_type = MT_DATA; 578 m.m_next = m.m_nextpkt = NULL; 579 m.m_len = le32toh(sect->nbytes); 580 m.m_data = dma.dma_vaddr; 581 m.m_flags = 0; 582 #ifdef INET 583 csum = in_cksum(&m, le32toh(sect->nbytes)); 584 if (csum != sect->cksum) { 585 printf(": fw section %d, bad cksum (expected 0x%x got 0x%x)\n", 586 sectnum, sect->cksum, csum); 587 txp_dma_free(sc, &dma); 588 return -1; 589 } 590 #endif 591 592 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 593 dma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 594 595 WRITE_REG(sc, TXP_H2A_1, le32toh(sect->nbytes)); 596 WRITE_REG(sc, TXP_H2A_2, le32toh(sect->cksum)); 597 WRITE_REG(sc, TXP_H2A_3, le32toh(sect->addr)); 598 WRITE_REG(sc, TXP_H2A_4, dma.dma_paddr >> 32); 599 WRITE_REG(sc, TXP_H2A_5, dma.dma_paddr & 0xffffffff); 600 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 601 602 if (txp_download_fw_wait(sc)) { 603 printf("%s: fw wait failed, section %d\n", 604 sc->sc_dev.dv_xname, sectnum); 605 err = -1; 606 } 607 608 bus_dmamap_sync(sc->sc_dmat, dma.dma_map, 0, 609 dma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 610 611 txp_dma_free(sc, &dma); 612 return (err); 613 } 614 615 int 616 txp_intr(vsc) 617 void *vsc; 618 { 619 struct txp_softc *sc = vsc; 620 struct txp_hostvar *hv = sc->sc_hostvar; 621 u_int32_t isr; 622 int claimed = 0; 623 624 /* mask all interrupts */ 625 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 626 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 627 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 628 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 629 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 630 631 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 632 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 633 634 isr = READ_REG(sc, TXP_ISR); 635 while (isr) { 636 claimed = 1; 637 WRITE_REG(sc, TXP_ISR, isr); 638 639 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 640 txp_rx_reclaim(sc, &sc->sc_rxhir, &sc->sc_rxhiring_dma); 641 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 642 txp_rx_reclaim(sc, &sc->sc_rxlor, &sc->sc_rxloring_dma); 643 644 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 645 txp_rxbuf_reclaim(sc); 646 647 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 648 TXP_OFFSET2IDX(le32toh(*(sc->sc_txhir.r_off))))) 649 txp_tx_reclaim(sc, &sc->sc_txhir, &sc->sc_txhiring_dma); 650 651 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 652 TXP_OFFSET2IDX(le32toh(*(sc->sc_txlor.r_off))))) 653 txp_tx_reclaim(sc, &sc->sc_txlor, &sc->sc_txloring_dma); 654 655 isr = READ_REG(sc, TXP_ISR); 656 } 657 658 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 659 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTWRITE|BUS_DMASYNC_POSTREAD); 660 661 /* unmask all interrupts */ 662 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 663 664 txp_start(&sc->sc_arpcom.ec_if); 665 666 return (claimed); 667 } 668 669 void 670 txp_rx_reclaim(sc, r, dma) 671 struct txp_softc *sc; 672 struct txp_rx_ring *r; 673 struct txp_dma_alloc *dma; 674 { 675 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 676 struct txp_rx_desc *rxd; 677 struct mbuf *m; 678 struct txp_swdesc *sd; 679 u_int32_t roff, woff; 680 int sumflags = 0; 681 int idx; 682 683 roff = le32toh(*r->r_roff); 684 woff = le32toh(*r->r_woff); 685 idx = roff / sizeof(struct txp_rx_desc); 686 rxd = r->r_desc + idx; 687 688 while (roff != woff) { 689 690 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 691 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 692 BUS_DMASYNC_POSTREAD); 693 694 if (rxd->rx_flags & RX_FLAGS_ERROR) { 695 printf("%s: error 0x%x\n", sc->sc_dev.dv_xname, 696 le32toh(rxd->rx_stat)); 697 ifp->if_ierrors++; 698 goto next; 699 } 700 701 /* retrieve stashed pointer */ 702 bcopy(__UNVOLATILE(&rxd->rx_vaddrlo), &sd, sizeof(sd)); 703 704 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 705 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTREAD); 706 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 707 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 708 m = sd->sd_mbuf; 709 free(sd, M_DEVBUF); 710 m->m_pkthdr.len = m->m_len = le16toh(rxd->rx_len); 711 712 #ifdef __STRICT_ALIGNMENT 713 { 714 /* 715 * XXX Nice chip, except it won't accept "off by 2" 716 * buffers, so we're force to copy. Supposedly 717 * this will be fixed in a newer firmware rev 718 * and this will be temporary. 719 */ 720 struct mbuf *mnew; 721 722 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 723 if (mnew == NULL) { 724 m_freem(m); 725 goto next; 726 } 727 if (m->m_len > (MHLEN - 2)) { 728 MCLGET(mnew, M_DONTWAIT); 729 if (!(mnew->m_flags & M_EXT)) { 730 m_freem(mnew); 731 m_freem(m); 732 goto next; 733 } 734 } 735 mnew->m_pkthdr.rcvif = ifp; 736 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 737 mnew->m_data += 2; 738 bcopy(m->m_data, mnew->m_data, m->m_len); 739 m_freem(m); 740 m = mnew; 741 } 742 #endif 743 744 #if NBPFILTER > 0 745 /* 746 * Handle BPF listeners. Let the BPF user see the packet. 747 */ 748 if (ifp->if_bpf) 749 bpf_mtap(ifp->if_bpf, m); 750 #endif 751 752 if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMBAD)) 753 sumflags |= (M_CSUM_IPv4|M_CSUM_IPv4_BAD); 754 else if (rxd->rx_stat & htole32(RX_STAT_IPCKSUMGOOD)) 755 sumflags |= M_CSUM_IPv4; 756 757 if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMBAD)) 758 sumflags |= (M_CSUM_TCPv4|M_CSUM_TCP_UDP_BAD); 759 else if (rxd->rx_stat & htole32(RX_STAT_TCPCKSUMGOOD)) 760 sumflags |= M_CSUM_TCPv4; 761 762 if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMBAD)) 763 sumflags |= (M_CSUM_UDPv4|M_CSUM_TCP_UDP_BAD); 764 else if (rxd->rx_stat & htole32(RX_STAT_UDPCKSUMGOOD)) 765 sumflags |= M_CSUM_UDPv4; 766 767 m->m_pkthdr.csum_flags = sumflags; 768 769 if (rxd->rx_stat & htole32(RX_STAT_VLAN)) { 770 VLAN_INPUT_TAG(ifp, m, htons(rxd->rx_vlan >> 16), 771 continue); 772 } 773 774 (*ifp->if_input)(ifp, m); 775 776 next: 777 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 778 idx * sizeof(struct txp_rx_desc), sizeof(struct txp_rx_desc), 779 BUS_DMASYNC_PREREAD); 780 781 roff += sizeof(struct txp_rx_desc); 782 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 783 idx = 0; 784 roff = 0; 785 rxd = r->r_desc; 786 } else { 787 idx++; 788 rxd++; 789 } 790 woff = le32toh(*r->r_woff); 791 } 792 793 *r->r_roff = htole32(woff); 794 } 795 796 void 797 txp_rxbuf_reclaim(sc) 798 struct txp_softc *sc; 799 { 800 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 801 struct txp_hostvar *hv = sc->sc_hostvar; 802 struct txp_rxbuf_desc *rbd; 803 struct txp_swdesc *sd; 804 u_int32_t i, end; 805 806 end = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_read_idx)); 807 i = TXP_OFFSET2IDX(le32toh(hv->hv_rx_buf_write_idx)); 808 809 if (++i == RXBUF_ENTRIES) 810 i = 0; 811 812 rbd = sc->sc_rxbufs + i; 813 814 while (i != end) { 815 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 816 M_DEVBUF, M_NOWAIT); 817 if (sd == NULL) 818 break; 819 820 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 821 if (sd->sd_mbuf == NULL) 822 goto err_sd; 823 824 MCLGET(sd->sd_mbuf, M_DONTWAIT); 825 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 826 goto err_mbuf; 827 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 828 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 829 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 830 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) 831 goto err_mbuf; 832 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 833 BUS_DMA_NOWAIT)) { 834 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 835 goto err_mbuf; 836 } 837 838 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 839 i * sizeof(struct txp_rxbuf_desc), 840 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_POSTWRITE); 841 842 /* stash away pointer */ 843 bcopy(&sd, __UNVOLATILE(&rbd->rb_vaddrlo), sizeof(sd)); 844 845 rbd->rb_paddrlo = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 846 & 0xffffffff; 847 rbd->rb_paddrhi = ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) 848 >> 32; 849 850 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 851 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 852 853 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 854 i * sizeof(struct txp_rxbuf_desc), 855 sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_PREWRITE); 856 857 hv->hv_rx_buf_write_idx = htole32(TXP_IDX2OFFSET(i)); 858 859 if (++i == RXBUF_ENTRIES) { 860 i = 0; 861 rbd = sc->sc_rxbufs; 862 } else 863 rbd++; 864 } 865 return; 866 867 err_mbuf: 868 m_freem(sd->sd_mbuf); 869 err_sd: 870 free(sd, M_DEVBUF); 871 } 872 873 /* 874 * Reclaim mbufs and entries from a transmit ring. 875 */ 876 void 877 txp_tx_reclaim(sc, r, dma) 878 struct txp_softc *sc; 879 struct txp_tx_ring *r; 880 struct txp_dma_alloc *dma; 881 { 882 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 883 u_int32_t idx = TXP_OFFSET2IDX(le32toh(*(r->r_off))); 884 u_int32_t cons = r->r_cons, cnt = r->r_cnt; 885 struct txp_tx_desc *txd = r->r_desc + cons; 886 struct txp_swdesc *sd = sc->sc_txd + cons; 887 struct mbuf *m; 888 889 while (cons != idx) { 890 if (cnt == 0) 891 break; 892 893 bus_dmamap_sync(sc->sc_dmat, dma->dma_map, 894 cons * sizeof(struct txp_tx_desc), 895 sizeof(struct txp_tx_desc), 896 BUS_DMASYNC_POSTWRITE); 897 898 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 899 TX_FLAGS_TYPE_DATA) { 900 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 901 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 902 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 903 m = sd->sd_mbuf; 904 if (m != NULL) { 905 m_freem(m); 906 txd->tx_addrlo = 0; 907 txd->tx_addrhi = 0; 908 ifp->if_opackets++; 909 } 910 } 911 ifp->if_flags &= ~IFF_OACTIVE; 912 913 if (++cons == TX_ENTRIES) { 914 txd = r->r_desc; 915 cons = 0; 916 sd = sc->sc_txd; 917 } else { 918 txd++; 919 sd++; 920 } 921 922 cnt--; 923 } 924 925 r->r_cons = cons; 926 r->r_cnt = cnt; 927 if (cnt == 0) 928 ifp->if_timer = 0; 929 } 930 931 void 932 txp_shutdown(vsc) 933 void *vsc; 934 { 935 struct txp_softc *sc = (struct txp_softc *)vsc; 936 937 /* mask all interrupts */ 938 WRITE_REG(sc, TXP_IMR, 939 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 940 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 941 TXP_INT_LATCH); 942 943 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 944 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 945 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 946 } 947 948 int 949 txp_alloc_rings(sc) 950 struct txp_softc *sc; 951 { 952 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 953 struct txp_boot_record *boot; 954 struct txp_swdesc *sd; 955 u_int32_t r; 956 int i, j, nb; 957 958 /* boot record */ 959 if (txp_dma_malloc(sc, sizeof(struct txp_boot_record), &sc->sc_boot_dma, 960 BUS_DMA_COHERENT)) { 961 printf(": can't allocate boot record\n"); 962 return (-1); 963 } 964 boot = (struct txp_boot_record *)sc->sc_boot_dma.dma_vaddr; 965 bzero(boot, sizeof(*boot)); 966 sc->sc_boot = boot; 967 968 /* host variables */ 969 if (txp_dma_malloc(sc, sizeof(struct txp_hostvar), &sc->sc_host_dma, 970 BUS_DMA_COHERENT)) { 971 printf(": can't allocate host ring\n"); 972 goto bail_boot; 973 } 974 bzero(sc->sc_host_dma.dma_vaddr, sizeof(struct txp_hostvar)); 975 boot->br_hostvar_lo = htole32(sc->sc_host_dma.dma_paddr & 0xffffffff); 976 boot->br_hostvar_hi = htole32(sc->sc_host_dma.dma_paddr >> 32); 977 sc->sc_hostvar = (struct txp_hostvar *)sc->sc_host_dma.dma_vaddr; 978 979 /* high priority tx ring */ 980 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 981 &sc->sc_txhiring_dma, BUS_DMA_COHERENT)) { 982 printf(": can't allocate high tx ring\n"); 983 goto bail_host; 984 } 985 bzero(sc->sc_txhiring_dma.dma_vaddr, sizeof(struct txp_tx_desc) * TX_ENTRIES); 986 boot->br_txhipri_lo = htole32(sc->sc_txhiring_dma.dma_paddr & 0xffffffff); 987 boot->br_txhipri_hi = htole32(sc->sc_txhiring_dma.dma_paddr >> 32); 988 boot->br_txhipri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 989 sc->sc_txhir.r_reg = TXP_H2A_1; 990 sc->sc_txhir.r_desc = (struct txp_tx_desc *)sc->sc_txhiring_dma.dma_vaddr; 991 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 992 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 993 for (i = 0; i < TX_ENTRIES; i++) { 994 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 995 TX_ENTRIES - 4, TXP_MAX_SEGLEN, 0, 996 BUS_DMA_NOWAIT, &sc->sc_txd[i].sd_map) != 0) { 997 for (j = 0; j < i; j++) { 998 bus_dmamap_destroy(sc->sc_dmat, 999 sc->sc_txd[j].sd_map); 1000 sc->sc_txd[j].sd_map = NULL; 1001 } 1002 goto bail_txhiring; 1003 } 1004 } 1005 1006 /* low priority tx ring */ 1007 if (txp_dma_malloc(sc, sizeof(struct txp_tx_desc) * TX_ENTRIES, 1008 &sc->sc_txloring_dma, BUS_DMA_COHERENT)) { 1009 printf(": can't allocate low tx ring\n"); 1010 goto bail_txhiring; 1011 } 1012 bzero(sc->sc_txloring_dma.dma_vaddr, sizeof(struct txp_tx_desc) * TX_ENTRIES); 1013 boot->br_txlopri_lo = htole32(sc->sc_txloring_dma.dma_paddr & 0xffffffff); 1014 boot->br_txlopri_hi = htole32(sc->sc_txloring_dma.dma_paddr >> 32); 1015 boot->br_txlopri_siz = htole32(TX_ENTRIES * sizeof(struct txp_tx_desc)); 1016 sc->sc_txlor.r_reg = TXP_H2A_3; 1017 sc->sc_txlor.r_desc = (struct txp_tx_desc *)sc->sc_txloring_dma.dma_vaddr; 1018 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 1019 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 1020 1021 /* high priority rx ring */ 1022 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1023 &sc->sc_rxhiring_dma, BUS_DMA_COHERENT)) { 1024 printf(": can't allocate high rx ring\n"); 1025 goto bail_txloring; 1026 } 1027 bzero(sc->sc_rxhiring_dma.dma_vaddr, sizeof(struct txp_rx_desc) * RX_ENTRIES); 1028 boot->br_rxhipri_lo = htole32(sc->sc_rxhiring_dma.dma_paddr & 0xffffffff); 1029 boot->br_rxhipri_hi = htole32(sc->sc_rxhiring_dma.dma_paddr >> 32); 1030 boot->br_rxhipri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1031 sc->sc_rxhir.r_desc = 1032 (struct txp_rx_desc *)sc->sc_rxhiring_dma.dma_vaddr; 1033 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 1034 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 1035 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxhiring_dma.dma_map, 1036 0, sc->sc_rxhiring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1037 1038 /* low priority ring */ 1039 if (txp_dma_malloc(sc, sizeof(struct txp_rx_desc) * RX_ENTRIES, 1040 &sc->sc_rxloring_dma, BUS_DMA_COHERENT)) { 1041 printf(": can't allocate low rx ring\n"); 1042 goto bail_rxhiring; 1043 } 1044 bzero(sc->sc_rxloring_dma.dma_vaddr, sizeof(struct txp_rx_desc) * RX_ENTRIES); 1045 boot->br_rxlopri_lo = htole32(sc->sc_rxloring_dma.dma_paddr & 0xffffffff); 1046 boot->br_rxlopri_hi = htole32(sc->sc_rxloring_dma.dma_paddr >> 32); 1047 boot->br_rxlopri_siz = htole32(RX_ENTRIES * sizeof(struct txp_rx_desc)); 1048 sc->sc_rxlor.r_desc = 1049 (struct txp_rx_desc *)sc->sc_rxloring_dma.dma_vaddr; 1050 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 1051 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 1052 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxloring_dma.dma_map, 1053 0, sc->sc_rxloring_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1054 1055 /* command ring */ 1056 if (txp_dma_malloc(sc, sizeof(struct txp_cmd_desc) * CMD_ENTRIES, 1057 &sc->sc_cmdring_dma, BUS_DMA_COHERENT)) { 1058 printf(": can't allocate command ring\n"); 1059 goto bail_rxloring; 1060 } 1061 bzero(sc->sc_cmdring_dma.dma_vaddr, sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 1062 boot->br_cmd_lo = htole32(sc->sc_cmdring_dma.dma_paddr & 0xffffffff); 1063 boot->br_cmd_hi = htole32(sc->sc_cmdring_dma.dma_paddr >> 32); 1064 boot->br_cmd_siz = htole32(CMD_ENTRIES * sizeof(struct txp_cmd_desc)); 1065 sc->sc_cmdring.base = (struct txp_cmd_desc *)sc->sc_cmdring_dma.dma_vaddr; 1066 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1067 sc->sc_cmdring.lastwrite = 0; 1068 1069 /* response ring */ 1070 if (txp_dma_malloc(sc, sizeof(struct txp_rsp_desc) * RSP_ENTRIES, 1071 &sc->sc_rspring_dma, BUS_DMA_COHERENT)) { 1072 printf(": can't allocate response ring\n"); 1073 goto bail_cmdring; 1074 } 1075 bzero(sc->sc_rspring_dma.dma_vaddr, sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 1076 boot->br_resp_lo = htole32(sc->sc_rspring_dma.dma_paddr & 0xffffffff); 1077 boot->br_resp_hi = htole32(sc->sc_rspring_dma.dma_paddr >> 32); 1078 boot->br_resp_siz = htole32(CMD_ENTRIES * sizeof(struct txp_rsp_desc)); 1079 sc->sc_rspring.base = (struct txp_rsp_desc *)sc->sc_rspring_dma.dma_vaddr; 1080 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 1081 sc->sc_rspring.lastwrite = 0; 1082 1083 /* receive buffer ring */ 1084 if (txp_dma_malloc(sc, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES, 1085 &sc->sc_rxbufring_dma, BUS_DMA_COHERENT)) { 1086 printf(": can't allocate rx buffer ring\n"); 1087 goto bail_rspring; 1088 } 1089 bzero(sc->sc_rxbufring_dma.dma_vaddr, sizeof(struct txp_rxbuf_desc) * RXBUF_ENTRIES); 1090 boot->br_rxbuf_lo = htole32(sc->sc_rxbufring_dma.dma_paddr & 0xffffffff); 1091 boot->br_rxbuf_hi = htole32(sc->sc_rxbufring_dma.dma_paddr >> 32); 1092 boot->br_rxbuf_siz = htole32(RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc)); 1093 sc->sc_rxbufs = (struct txp_rxbuf_desc *)sc->sc_rxbufring_dma.dma_vaddr; 1094 for (nb = 0; nb < RXBUF_ENTRIES; nb++) { 1095 sd = (struct txp_swdesc *)malloc(sizeof(struct txp_swdesc), 1096 M_DEVBUF, M_NOWAIT); 1097 /* stash away pointer */ 1098 bcopy(&sd, __UNVOLATILE(&sc->sc_rxbufs[nb].rb_vaddrlo), sizeof(sd)); 1099 if (sd == NULL) 1100 break; 1101 1102 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 1103 if (sd->sd_mbuf == NULL) { 1104 goto bail_rxbufring; 1105 } 1106 1107 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1108 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1109 goto bail_rxbufring; 1110 } 1111 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1112 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 1113 if (bus_dmamap_create(sc->sc_dmat, TXP_MAX_PKTLEN, 1, 1114 TXP_MAX_PKTLEN, 0, BUS_DMA_NOWAIT, &sd->sd_map)) { 1115 goto bail_rxbufring; 1116 } 1117 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, sd->sd_mbuf, 1118 BUS_DMA_NOWAIT)) { 1119 bus_dmamap_destroy(sc->sc_dmat, sd->sd_map); 1120 goto bail_rxbufring; 1121 } 1122 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1123 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREREAD); 1124 1125 1126 sc->sc_rxbufs[nb].rb_paddrlo = 1127 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) & 0xffffffff; 1128 sc->sc_rxbufs[nb].rb_paddrhi = 1129 ((u_int64_t)sd->sd_map->dm_segs[0].ds_addr) >> 32; 1130 } 1131 bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, 1132 0, sc->sc_rxbufring_dma.dma_map->dm_mapsize, 1133 BUS_DMASYNC_PREWRITE); 1134 sc->sc_hostvar->hv_rx_buf_write_idx = htole32((RXBUF_ENTRIES - 1) * 1135 sizeof(struct txp_rxbuf_desc)); 1136 1137 /* zero dma */ 1138 if (txp_dma_malloc(sc, sizeof(u_int32_t), &sc->sc_zero_dma, 1139 BUS_DMA_COHERENT)) { 1140 printf(": can't allocate response ring\n"); 1141 goto bail_rxbufring; 1142 } 1143 bzero(sc->sc_zero_dma.dma_vaddr, sizeof(u_int32_t)); 1144 boot->br_zero_lo = htole32(sc->sc_zero_dma.dma_paddr & 0xffffffff); 1145 boot->br_zero_hi = htole32(sc->sc_zero_dma.dma_paddr >> 32); 1146 1147 /* See if it's waiting for boot, and try to boot it */ 1148 for (i = 0; i < 10000; i++) { 1149 r = READ_REG(sc, TXP_A2H_0); 1150 if (r == STAT_WAITING_FOR_BOOT) 1151 break; 1152 DELAY(50); 1153 } 1154 if (r != STAT_WAITING_FOR_BOOT) { 1155 printf(": not waiting for boot\n"); 1156 goto bail; 1157 } 1158 WRITE_REG(sc, TXP_H2A_2, sc->sc_boot_dma.dma_paddr >> 32); 1159 WRITE_REG(sc, TXP_H2A_1, sc->sc_boot_dma.dma_paddr & 0xffffffff); 1160 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1161 1162 /* See if it booted */ 1163 for (i = 0; i < 10000; i++) { 1164 r = READ_REG(sc, TXP_A2H_0); 1165 if (r == STAT_RUNNING) 1166 break; 1167 DELAY(50); 1168 } 1169 if (r != STAT_RUNNING) { 1170 printf(": fw not running\n"); 1171 goto bail; 1172 } 1173 1174 /* Clear TX and CMD ring write registers */ 1175 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1176 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1177 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1178 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1179 1180 return (0); 1181 1182 bail: 1183 txp_dma_free(sc, &sc->sc_zero_dma); 1184 bail_rxbufring: 1185 if (nb == RXBUF_ENTRIES) 1186 nb--; 1187 for (i = 0; i <= nb; i++) { 1188 bcopy(__UNVOLATILE(&sc->sc_rxbufs[i].rb_vaddrlo), &sd, 1189 sizeof(sd)); 1190 if (sd) 1191 free(sd, M_DEVBUF); 1192 } 1193 txp_dma_free(sc, &sc->sc_rxbufring_dma); 1194 bail_rspring: 1195 txp_dma_free(sc, &sc->sc_rspring_dma); 1196 bail_cmdring: 1197 txp_dma_free(sc, &sc->sc_cmdring_dma); 1198 bail_rxloring: 1199 txp_dma_free(sc, &sc->sc_rxloring_dma); 1200 bail_rxhiring: 1201 txp_dma_free(sc, &sc->sc_rxhiring_dma); 1202 bail_txloring: 1203 txp_dma_free(sc, &sc->sc_txloring_dma); 1204 bail_txhiring: 1205 txp_dma_free(sc, &sc->sc_txhiring_dma); 1206 bail_host: 1207 txp_dma_free(sc, &sc->sc_host_dma); 1208 bail_boot: 1209 txp_dma_free(sc, &sc->sc_boot_dma); 1210 return (-1); 1211 } 1212 1213 int 1214 txp_dma_malloc(sc, size, dma, mapflags) 1215 struct txp_softc *sc; 1216 bus_size_t size; 1217 struct txp_dma_alloc *dma; 1218 int mapflags; 1219 { 1220 int r; 1221 1222 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, 1223 &dma->dma_seg, 1, &dma->dma_nseg, 0)) != 0) 1224 goto fail_0; 1225 1226 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg, 1227 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0) 1228 goto fail_1; 1229 1230 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, 1231 BUS_DMA_NOWAIT, &dma->dma_map)) != 0) 1232 goto fail_2; 1233 1234 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr, 1235 size, NULL, BUS_DMA_NOWAIT)) != 0) 1236 goto fail_3; 1237 1238 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr; 1239 return (0); 1240 1241 fail_3: 1242 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1243 fail_2: 1244 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size); 1245 fail_1: 1246 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1247 fail_0: 1248 return (r); 1249 } 1250 1251 void 1252 txp_dma_free(sc, dma) 1253 struct txp_softc *sc; 1254 struct txp_dma_alloc *dma; 1255 { 1256 bus_dmamap_unload(sc->sc_dmat, dma->dma_map); 1257 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_map->dm_mapsize); 1258 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg); 1259 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map); 1260 } 1261 1262 int 1263 txp_ioctl(ifp, command, data) 1264 struct ifnet *ifp; 1265 u_long command; 1266 caddr_t data; 1267 { 1268 struct txp_softc *sc = ifp->if_softc; 1269 struct ifreq *ifr = (struct ifreq *)data; 1270 struct ifaddr *ifa = (struct ifaddr *)data; 1271 int s, error = 0; 1272 1273 s = splnet(); 1274 1275 #if 0 1276 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, command, data)) > 0) { 1277 splx(s); 1278 return error; 1279 } 1280 #endif 1281 1282 switch(command) { 1283 case SIOCSIFADDR: 1284 ifp->if_flags |= IFF_UP; 1285 switch (ifa->ifa_addr->sa_family) { 1286 #ifdef INET 1287 case AF_INET: 1288 txp_init(sc); 1289 arp_ifinit(ifp, ifa); 1290 break; 1291 #endif /* INET */ 1292 default: 1293 txp_init(sc); 1294 break; 1295 } 1296 break; 1297 case SIOCSIFFLAGS: 1298 if (ifp->if_flags & IFF_UP) { 1299 txp_init(sc); 1300 } else { 1301 if (ifp->if_flags & IFF_RUNNING) 1302 txp_stop(sc); 1303 } 1304 break; 1305 case SIOCADDMULTI: 1306 case SIOCDELMULTI: 1307 error = (command == SIOCADDMULTI) ? 1308 ether_addmulti(ifr, &sc->sc_arpcom) : 1309 ether_delmulti(ifr, &sc->sc_arpcom); 1310 1311 if (error == ENETRESET) { 1312 /* 1313 * Multicast list has changed; set the hardware 1314 * filter accordingly. 1315 */ 1316 if (ifp->if_flags & IFF_RUNNING) 1317 txp_set_filter(sc); 1318 error = 0; 1319 } 1320 break; 1321 case SIOCGIFMEDIA: 1322 case SIOCSIFMEDIA: 1323 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command); 1324 break; 1325 default: 1326 error = EINVAL; 1327 break; 1328 } 1329 1330 splx(s); 1331 1332 return(error); 1333 } 1334 1335 void 1336 txp_init(sc) 1337 struct txp_softc *sc; 1338 { 1339 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1340 int s; 1341 1342 txp_stop(sc); 1343 1344 s = splnet(); 1345 1346 txp_set_filter(sc); 1347 1348 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1349 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1350 1351 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1352 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1353 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1354 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1355 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1356 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1357 1358 ifp->if_flags |= IFF_RUNNING; 1359 ifp->if_flags &= ~IFF_OACTIVE; 1360 ifp->if_timer = 0; 1361 1362 if (!callout_pending(&sc->sc_tick)) 1363 callout_schedule(&sc->sc_tick, hz); 1364 1365 splx(s); 1366 } 1367 1368 void 1369 txp_tick(vsc) 1370 void *vsc; 1371 { 1372 struct txp_softc *sc = vsc; 1373 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1374 struct txp_rsp_desc *rsp = NULL; 1375 struct txp_ext_desc *ext; 1376 int s; 1377 1378 s = splnet(); 1379 txp_rxbuf_reclaim(sc); 1380 1381 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1382 &rsp, 1)) 1383 goto out; 1384 if (rsp->rsp_numdesc != 6) 1385 goto out; 1386 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1387 NULL, NULL, NULL, 1)) 1388 goto out; 1389 ext = (struct txp_ext_desc *)(rsp + 1); 1390 1391 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1392 ext[4].ext_1 + ext[4].ext_4; 1393 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1394 ext[2].ext_1; 1395 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1396 ext[1].ext_3; 1397 ifp->if_opackets += rsp->rsp_par2; 1398 ifp->if_ipackets += ext[2].ext_3; 1399 1400 out: 1401 if (rsp != NULL) 1402 free(rsp, M_DEVBUF); 1403 1404 splx(s); 1405 callout_schedule(&sc->sc_tick, hz); 1406 } 1407 1408 void 1409 txp_start(ifp) 1410 struct ifnet *ifp; 1411 { 1412 struct txp_softc *sc = ifp->if_softc; 1413 struct txp_tx_ring *r = &sc->sc_txhir; 1414 struct txp_tx_desc *txd; 1415 int txdidx; 1416 struct txp_frag_desc *fxd; 1417 struct mbuf *m, *mnew; 1418 struct txp_swdesc *sd; 1419 u_int32_t firstprod, firstcnt, prod, cnt, i; 1420 struct m_tag *mtag; 1421 1422 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1423 return; 1424 1425 prod = r->r_prod; 1426 cnt = r->r_cnt; 1427 1428 while (1) { 1429 IFQ_POLL(&ifp->if_snd, m); 1430 if (m == NULL) 1431 break; 1432 mnew = NULL; 1433 1434 firstprod = prod; 1435 firstcnt = cnt; 1436 1437 sd = sc->sc_txd + prod; 1438 sd->sd_mbuf = m; 1439 1440 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1441 BUS_DMA_NOWAIT)) { 1442 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1443 if (mnew == NULL) 1444 goto oactive1; 1445 if (m->m_pkthdr.len > MHLEN) { 1446 MCLGET(mnew, M_DONTWAIT); 1447 if ((mnew->m_flags & M_EXT) == 0) { 1448 m_freem(mnew); 1449 goto oactive1; 1450 } 1451 } 1452 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, caddr_t)); 1453 mnew->m_pkthdr.len = mnew->m_len = m->m_pkthdr.len; 1454 IFQ_DEQUEUE(&ifp->if_snd, m); 1455 m_freem(m); 1456 m = mnew; 1457 if (bus_dmamap_load_mbuf(sc->sc_dmat, sd->sd_map, m, 1458 BUS_DMA_NOWAIT)) 1459 goto oactive1; 1460 } 1461 1462 if ((TX_ENTRIES - cnt) < 4) 1463 goto oactive; 1464 1465 txd = r->r_desc + prod; 1466 txdidx = prod; 1467 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1468 txd->tx_numdesc = 0; 1469 txd->tx_addrlo = 0; 1470 txd->tx_addrhi = 0; 1471 txd->tx_totlen = m->m_pkthdr.len; 1472 txd->tx_pflags = 0; 1473 txd->tx_numdesc = sd->sd_map->dm_nsegs; 1474 1475 if (++prod == TX_ENTRIES) 1476 prod = 0; 1477 1478 if (++cnt >= (TX_ENTRIES - 4)) 1479 goto oactive; 1480 1481 if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_arpcom, m))) 1482 txd->tx_pflags = TX_PFLAGS_VLAN | 1483 (htons(VLAN_TAG_VALUE(mtag)) << TX_PFLAGS_VLANTAG_S); 1484 1485 if (m->m_pkthdr.csum_flags & M_CSUM_IPv4) 1486 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1487 #ifdef TRY_TX_TCP_CSUM 1488 if (m->m_pkthdr.csum_flags & M_CSUM_TCPv4) 1489 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1490 #endif 1491 #ifdef TRY_TX_UDP_CSUM 1492 if (m->m_pkthdr.csum_flags & M_CSUM_UDPv4) 1493 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1494 #endif 1495 1496 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 0, 1497 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1498 1499 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1500 for (i = 0; i < sd->sd_map->dm_nsegs; i++) { 1501 if (++cnt >= (TX_ENTRIES - 4)) { 1502 bus_dmamap_sync(sc->sc_dmat, sd->sd_map, 1503 0, sd->sd_map->dm_mapsize, 1504 BUS_DMASYNC_POSTWRITE); 1505 goto oactive; 1506 } 1507 1508 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG | 1509 FRAG_FLAGS_VALID; 1510 fxd->frag_rsvd1 = 0; 1511 fxd->frag_len = sd->sd_map->dm_segs[i].ds_len; 1512 fxd->frag_addrlo = 1513 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) & 1514 0xffffffff; 1515 fxd->frag_addrhi = 1516 ((u_int64_t)sd->sd_map->dm_segs[i].ds_addr) >> 1517 32; 1518 fxd->frag_rsvd2 = 0; 1519 1520 bus_dmamap_sync(sc->sc_dmat, 1521 sc->sc_txhiring_dma.dma_map, 1522 prod * sizeof(struct txp_frag_desc), 1523 sizeof(struct txp_frag_desc), BUS_DMASYNC_PREWRITE); 1524 1525 if (++prod == TX_ENTRIES) { 1526 fxd = (struct txp_frag_desc *)r->r_desc; 1527 prod = 0; 1528 } else 1529 fxd++; 1530 1531 } 1532 1533 /* 1534 * if mnew isn't NULL, we already dequeued and copied 1535 * the packet. 1536 */ 1537 if (mnew == NULL) 1538 IFQ_DEQUEUE(&ifp->if_snd, m); 1539 1540 ifp->if_timer = 5; 1541 1542 #if NBPFILTER > 0 1543 if (ifp->if_bpf) 1544 bpf_mtap(ifp->if_bpf, m); 1545 #endif 1546 1547 txd->tx_flags |= TX_FLAGS_VALID; 1548 bus_dmamap_sync(sc->sc_dmat, sc->sc_txhiring_dma.dma_map, 1549 txdidx * sizeof(struct txp_tx_desc), 1550 sizeof(struct txp_tx_desc), BUS_DMASYNC_PREWRITE); 1551 1552 #if 0 1553 { 1554 struct mbuf *mx; 1555 int i; 1556 1557 printf("txd: flags 0x%x ndesc %d totlen %d pflags 0x%x\n", 1558 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1559 txd->tx_pflags); 1560 for (mx = m; mx != NULL; mx = mx->m_next) { 1561 for (i = 0; i < mx->m_len; i++) { 1562 printf(":%02x", 1563 (u_int8_t)m->m_data[i]); 1564 } 1565 } 1566 printf("\n"); 1567 } 1568 #endif 1569 1570 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1571 } 1572 1573 r->r_prod = prod; 1574 r->r_cnt = cnt; 1575 return; 1576 1577 oactive: 1578 bus_dmamap_unload(sc->sc_dmat, sd->sd_map); 1579 oactive1: 1580 ifp->if_flags |= IFF_OACTIVE; 1581 r->r_prod = firstprod; 1582 r->r_cnt = firstcnt; 1583 } 1584 1585 /* 1586 * Handle simple commands sent to the typhoon 1587 */ 1588 int 1589 txp_command(sc, id, in1, in2, in3, out1, out2, out3, wait) 1590 struct txp_softc *sc; 1591 u_int16_t id, in1, *out1; 1592 u_int32_t in2, in3, *out2, *out3; 1593 int wait; 1594 { 1595 struct txp_rsp_desc *rsp = NULL; 1596 1597 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1598 return (-1); 1599 1600 if (!wait) 1601 return (0); 1602 1603 if (out1 != NULL) 1604 *out1 = le16toh(rsp->rsp_par1); 1605 if (out2 != NULL) 1606 *out2 = le32toh(rsp->rsp_par2); 1607 if (out3 != NULL) 1608 *out3 = le32toh(rsp->rsp_par3); 1609 free(rsp, M_DEVBUF); 1610 return (0); 1611 } 1612 1613 int 1614 txp_command2(sc, id, in1, in2, in3, in_extp, in_extn, rspp, wait) 1615 struct txp_softc *sc; 1616 u_int16_t id, in1; 1617 u_int32_t in2, in3; 1618 struct txp_ext_desc *in_extp; 1619 u_int8_t in_extn; 1620 struct txp_rsp_desc **rspp; 1621 int wait; 1622 { 1623 struct txp_hostvar *hv = sc->sc_hostvar; 1624 struct txp_cmd_desc *cmd; 1625 struct txp_ext_desc *ext; 1626 u_int32_t idx, i; 1627 u_int16_t seq; 1628 1629 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1630 printf("%s: no free cmd descriptors\n", TXP_DEVNAME(sc)); 1631 return (-1); 1632 } 1633 1634 idx = sc->sc_cmdring.lastwrite; 1635 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1636 bzero(cmd, sizeof(*cmd)); 1637 1638 cmd->cmd_numdesc = in_extn; 1639 seq = sc->sc_seq++; 1640 cmd->cmd_seq = htole16(seq); 1641 cmd->cmd_id = htole16(id); 1642 cmd->cmd_par1 = htole16(in1); 1643 cmd->cmd_par2 = htole32(in2); 1644 cmd->cmd_par3 = htole32(in3); 1645 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1646 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1647 1648 idx += sizeof(struct txp_cmd_desc); 1649 if (idx == sc->sc_cmdring.size) 1650 idx = 0; 1651 1652 for (i = 0; i < in_extn; i++) { 1653 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1654 bcopy(in_extp, ext, sizeof(struct txp_ext_desc)); 1655 in_extp++; 1656 idx += sizeof(struct txp_cmd_desc); 1657 if (idx == sc->sc_cmdring.size) 1658 idx = 0; 1659 } 1660 1661 sc->sc_cmdring.lastwrite = idx; 1662 1663 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1664 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1665 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1666 1667 if (!wait) 1668 return (0); 1669 1670 for (i = 0; i < 10000; i++) { 1671 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1672 sizeof(struct txp_hostvar), BUS_DMASYNC_POSTREAD); 1673 idx = le32toh(hv->hv_resp_read_idx); 1674 if (idx != le32toh(hv->hv_resp_write_idx)) { 1675 *rspp = NULL; 1676 if (txp_response(sc, idx, id, seq, rspp)) 1677 return (-1); 1678 if (*rspp != NULL) 1679 break; 1680 } 1681 bus_dmamap_sync(sc->sc_dmat, sc->sc_host_dma.dma_map, 0, 1682 sizeof(struct txp_hostvar), BUS_DMASYNC_PREREAD); 1683 DELAY(50); 1684 } 1685 if (i == 1000 || (*rspp) == NULL) { 1686 printf("%s: 0x%x command failed\n", TXP_DEVNAME(sc), id); 1687 return (-1); 1688 } 1689 1690 return (0); 1691 } 1692 1693 int 1694 txp_response(sc, ridx, id, seq, rspp) 1695 struct txp_softc *sc; 1696 u_int32_t ridx; 1697 u_int16_t id; 1698 u_int16_t seq; 1699 struct txp_rsp_desc **rspp; 1700 { 1701 struct txp_hostvar *hv = sc->sc_hostvar; 1702 struct txp_rsp_desc *rsp; 1703 1704 while (ridx != le32toh(hv->hv_resp_write_idx)) { 1705 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx); 1706 1707 if (id == le16toh(rsp->rsp_id) && le16toh(rsp->rsp_seq) == seq) { 1708 *rspp = (struct txp_rsp_desc *)malloc( 1709 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1710 M_DEVBUF, M_NOWAIT); 1711 if ((*rspp) == NULL) 1712 return (-1); 1713 txp_rsp_fixup(sc, rsp, *rspp); 1714 return (0); 1715 } 1716 1717 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1718 printf("%s: response error: id 0x%x\n", 1719 TXP_DEVNAME(sc), le16toh(rsp->rsp_id)); 1720 txp_rsp_fixup(sc, rsp, NULL); 1721 ridx = le32toh(hv->hv_resp_read_idx); 1722 continue; 1723 } 1724 1725 switch (le16toh(rsp->rsp_id)) { 1726 case TXP_CMD_CYCLE_STATISTICS: 1727 case TXP_CMD_MEDIA_STATUS_READ: 1728 break; 1729 case TXP_CMD_HELLO_RESPONSE: 1730 printf("%s: hello\n", TXP_DEVNAME(sc)); 1731 break; 1732 default: 1733 printf("%s: unknown id(0x%x)\n", TXP_DEVNAME(sc), 1734 le16toh(rsp->rsp_id)); 1735 } 1736 1737 txp_rsp_fixup(sc, rsp, NULL); 1738 ridx = le32toh(hv->hv_resp_read_idx); 1739 hv->hv_resp_read_idx = le32toh(ridx); 1740 } 1741 1742 return (0); 1743 } 1744 1745 void 1746 txp_rsp_fixup(sc, rsp, dst) 1747 struct txp_softc *sc; 1748 struct txp_rsp_desc *rsp, *dst; 1749 { 1750 struct txp_rsp_desc *src = rsp; 1751 struct txp_hostvar *hv = sc->sc_hostvar; 1752 u_int32_t i, ridx; 1753 1754 ridx = le32toh(hv->hv_resp_read_idx); 1755 1756 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1757 if (dst != NULL) 1758 bcopy(src, dst++, sizeof(struct txp_rsp_desc)); 1759 ridx += sizeof(struct txp_rsp_desc); 1760 if (ridx == sc->sc_rspring.size) { 1761 src = sc->sc_rspring.base; 1762 ridx = 0; 1763 } else 1764 src++; 1765 sc->sc_rspring.lastwrite = ridx; 1766 hv->hv_resp_read_idx = htole32(ridx); 1767 } 1768 1769 hv->hv_resp_read_idx = htole32(ridx); 1770 } 1771 1772 int 1773 txp_cmd_desc_numfree(sc) 1774 struct txp_softc *sc; 1775 { 1776 struct txp_hostvar *hv = sc->sc_hostvar; 1777 struct txp_boot_record *br = sc->sc_boot; 1778 u_int32_t widx, ridx, nfree; 1779 1780 widx = sc->sc_cmdring.lastwrite; 1781 ridx = le32toh(hv->hv_cmd_read_idx); 1782 1783 if (widx == ridx) { 1784 /* Ring is completely free */ 1785 nfree = le32toh(br->br_cmd_siz) - sizeof(struct txp_cmd_desc); 1786 } else { 1787 if (widx > ridx) 1788 nfree = le32toh(br->br_cmd_siz) - 1789 (widx - ridx + sizeof(struct txp_cmd_desc)); 1790 else 1791 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1792 } 1793 1794 return (nfree / sizeof(struct txp_cmd_desc)); 1795 } 1796 1797 void 1798 txp_stop(sc) 1799 struct txp_softc *sc; 1800 { 1801 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1802 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1803 1804 if (callout_pending(&sc->sc_tick)) 1805 callout_stop(&sc->sc_tick); 1806 } 1807 1808 void 1809 txp_watchdog(ifp) 1810 struct ifnet *ifp; 1811 { 1812 } 1813 1814 int 1815 txp_ifmedia_upd(ifp) 1816 struct ifnet *ifp; 1817 { 1818 struct txp_softc *sc = ifp->if_softc; 1819 struct ifmedia *ifm = &sc->sc_ifmedia; 1820 u_int16_t new_xcvr; 1821 1822 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1823 return (EINVAL); 1824 1825 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1826 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1827 new_xcvr = TXP_XCVR_10_FDX; 1828 else 1829 new_xcvr = TXP_XCVR_10_HDX; 1830 } else if ((IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) || 1831 (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX)) { 1832 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1833 new_xcvr = TXP_XCVR_100_FDX; 1834 else 1835 new_xcvr = TXP_XCVR_100_HDX; 1836 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1837 new_xcvr = TXP_XCVR_AUTO; 1838 } else 1839 return (EINVAL); 1840 1841 /* nothing to do */ 1842 if (sc->sc_xcvr == new_xcvr) 1843 return (0); 1844 1845 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1846 NULL, NULL, NULL, 0); 1847 sc->sc_xcvr = new_xcvr; 1848 1849 return (0); 1850 } 1851 1852 void 1853 txp_ifmedia_sts(ifp, ifmr) 1854 struct ifnet *ifp; 1855 struct ifmediareq *ifmr; 1856 { 1857 struct txp_softc *sc = ifp->if_softc; 1858 struct ifmedia *ifm = &sc->sc_ifmedia; 1859 u_int16_t bmsr, bmcr, anlpar; 1860 1861 ifmr->ifm_status = IFM_AVALID; 1862 ifmr->ifm_active = IFM_ETHER; 1863 1864 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1865 &bmsr, NULL, NULL, 1)) 1866 goto bail; 1867 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1868 &bmsr, NULL, NULL, 1)) 1869 goto bail; 1870 1871 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1872 &bmcr, NULL, NULL, 1)) 1873 goto bail; 1874 1875 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1876 &anlpar, NULL, NULL, 1)) 1877 goto bail; 1878 1879 if (bmsr & BMSR_LINK) 1880 ifmr->ifm_status |= IFM_ACTIVE; 1881 1882 if (bmcr & BMCR_ISO) { 1883 ifmr->ifm_active |= IFM_NONE; 1884 ifmr->ifm_status = 0; 1885 return; 1886 } 1887 1888 if (bmcr & BMCR_LOOP) 1889 ifmr->ifm_active |= IFM_LOOP; 1890 1891 if (!(sc->sc_flags & TXP_FIBER) && (bmcr & BMCR_AUTOEN)) { 1892 if ((bmsr & BMSR_ACOMP) == 0) { 1893 ifmr->ifm_active |= IFM_NONE; 1894 return; 1895 } 1896 1897 if (anlpar & ANLPAR_T4) 1898 ifmr->ifm_active |= IFM_100_T4; 1899 else if (anlpar & ANLPAR_TX_FD) 1900 ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1901 else if (anlpar & ANLPAR_TX) 1902 ifmr->ifm_active |= IFM_100_TX; 1903 else if (anlpar & ANLPAR_10_FD) 1904 ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1905 else if (anlpar & ANLPAR_10) 1906 ifmr->ifm_active |= IFM_10_T; 1907 else 1908 ifmr->ifm_active |= IFM_NONE; 1909 } else 1910 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1911 return; 1912 1913 bail: 1914 ifmr->ifm_active |= IFM_NONE; 1915 ifmr->ifm_status &= ~IFM_AVALID; 1916 } 1917 1918 void 1919 txp_show_descriptor(d) 1920 void *d; 1921 { 1922 struct txp_cmd_desc *cmd = d; 1923 struct txp_rsp_desc *rsp = d; 1924 struct txp_tx_desc *txd = d; 1925 struct txp_frag_desc *frgd = d; 1926 1927 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1928 case CMD_FLAGS_TYPE_CMD: 1929 /* command descriptor */ 1930 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1931 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1932 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1933 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1934 break; 1935 case CMD_FLAGS_TYPE_RESP: 1936 /* response descriptor */ 1937 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1938 rsp->rsp_flags, rsp->rsp_numdesc, le16toh(rsp->rsp_id), 1939 le16toh(rsp->rsp_seq), le16toh(rsp->rsp_par1), 1940 le32toh(rsp->rsp_par2), le32toh(rsp->rsp_par3)); 1941 break; 1942 case CMD_FLAGS_TYPE_DATA: 1943 /* data header (assuming tx for now) */ 1944 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]", 1945 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1946 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1947 break; 1948 case CMD_FLAGS_TYPE_FRAG: 1949 /* fragment descriptor */ 1950 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]", 1951 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1952 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1953 break; 1954 default: 1955 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1956 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1957 cmd->cmd_flags, cmd->cmd_numdesc, le16toh(cmd->cmd_id), 1958 le16toh(cmd->cmd_seq), le16toh(cmd->cmd_par1), 1959 le32toh(cmd->cmd_par2), le32toh(cmd->cmd_par3)); 1960 break; 1961 } 1962 } 1963 1964 void 1965 txp_set_filter(sc) 1966 struct txp_softc *sc; 1967 { 1968 struct ethercom *ac = &sc->sc_arpcom; 1969 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 1970 u_int32_t crc, carry, hashbit, hash[2]; 1971 u_int16_t filter; 1972 u_int8_t octet; 1973 int i, j, mcnt = 0; 1974 struct ether_multi *enm; 1975 struct ether_multistep step; 1976 1977 if (ifp->if_flags & IFF_PROMISC) { 1978 filter = TXP_RXFILT_PROMISC; 1979 goto setit; 1980 } 1981 1982 again: 1983 filter = TXP_RXFILT_DIRECT; 1984 1985 if (ifp->if_flags & IFF_BROADCAST) 1986 filter |= TXP_RXFILT_BROADCAST; 1987 1988 if (ifp->if_flags & IFF_ALLMULTI) 1989 filter |= TXP_RXFILT_ALLMULTI; 1990 else { 1991 hash[0] = hash[1] = 0; 1992 1993 ETHER_FIRST_MULTI(step, ac, enm); 1994 while (enm != NULL) { 1995 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1996 /* 1997 * We must listen to a range of multicast 1998 * addresses. For now, just accept all 1999 * multicasts, rather than trying to set only 2000 * those filter bits needed to match the range. 2001 * (At this time, the only use of address 2002 * ranges is for IP multicast routing, for 2003 * which the range is big enough to require 2004 * all bits set.) 2005 */ 2006 ifp->if_flags |= IFF_ALLMULTI; 2007 goto again; 2008 } 2009 2010 mcnt++; 2011 crc = 0xffffffff; 2012 2013 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2014 octet = enm->enm_addrlo[i]; 2015 for (j = 0; j < 8; j++) { 2016 carry = ((crc & 0x80000000) ? 1 : 0) ^ 2017 (octet & 1); 2018 crc <<= 1; 2019 octet >>= 1; 2020 if (carry) 2021 crc = (crc ^ TXP_POLYNOMIAL) | 2022 carry; 2023 } 2024 } 2025 hashbit = (u_int16_t)(crc & (64 - 1)); 2026 hash[hashbit / 32] |= (1 << hashbit % 32); 2027 ETHER_NEXT_MULTI(step, enm); 2028 } 2029 2030 if (mcnt > 0) { 2031 filter |= TXP_RXFILT_HASHMULTI; 2032 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 2033 2, hash[0], hash[1], NULL, NULL, NULL, 0); 2034 } 2035 } 2036 2037 setit: 2038 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 2039 NULL, NULL, NULL, 1); 2040 } 2041 2042 void 2043 txp_capabilities(sc) 2044 struct txp_softc *sc; 2045 { 2046 struct ifnet *ifp = &sc->sc_arpcom.ec_if; 2047 struct txp_rsp_desc *rsp = NULL; 2048 struct txp_ext_desc *ext; 2049 2050 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 2051 goto out; 2052 2053 if (rsp->rsp_numdesc != 1) 2054 goto out; 2055 ext = (struct txp_ext_desc *)(rsp + 1); 2056 2057 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 2058 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 2059 2060 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_MTU; 2061 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 2062 sc->sc_tx_capability |= OFFLOAD_VLAN; 2063 sc->sc_rx_capability |= OFFLOAD_VLAN; 2064 sc->sc_arpcom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 2065 } 2066 2067 #if 0 2068 /* not ready yet */ 2069 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 2070 sc->sc_tx_capability |= OFFLOAD_IPSEC; 2071 sc->sc_rx_capability |= OFFLOAD_IPSEC; 2072 ifp->if_capabilities |= IFCAP_IPSEC; 2073 } 2074 #endif 2075 2076 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 2077 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 2078 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 2079 ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx; 2080 } 2081 2082 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 2083 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 2084 #ifdef TRY_TX_TCP_CSUM 2085 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 2086 ifp->if_capabilities |= 2087 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 2088 #endif 2089 } 2090 2091 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 2092 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 2093 #ifdef TRY_TX_UDP_CSUM 2094 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 2095 ifp->if_capabilities |= 2096 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 2097 #endif 2098 } 2099 2100 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 2101 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 2102 goto out; 2103 2104 out: 2105 if (rsp != NULL) 2106 free(rsp, M_DEVBUF); 2107 } 2108