1 /* $NetBSD: if_tl.c,v 1.39 2000/12/28 22:59:13 sommerfeld Exp $ */ 2 3 /* XXX ALTQ XXX */ 4 5 /* 6 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Manuel Bouyer. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Texas Instruments ThunderLAN ethernet controller 36 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A) 37 * available from www.ti.com 38 */ 39 40 #undef TLDEBUG 41 #define TL_PRIV_STATS 42 #undef TLDEBUG_RX 43 #undef TLDEBUG_TX 44 #undef TLDEBUG_ADDR 45 46 #include "opt_inet.h" 47 #include "opt_ns.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/mbuf.h> 52 #include <sys/protosw.h> 53 #include <sys/socket.h> 54 #include <sys/ioctl.h> 55 #include <sys/errno.h> 56 #include <sys/malloc.h> 57 #include <sys/kernel.h> 58 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 59 #include <sys/device.h> 60 61 #include <net/if.h> 62 #if defined(SIOCSIFMEDIA) 63 #include <net/if_media.h> 64 #endif 65 #include <net/if_types.h> 66 #include <net/if_dl.h> 67 #include <net/route.h> 68 #include <net/netisr.h> 69 70 #include "bpfilter.h" 71 #if NBPFILTER > 0 72 #include <net/bpf.h> 73 #include <net/bpfdesc.h> 74 #endif 75 76 #ifdef INET 77 #include <netinet/in.h> 78 #include <netinet/in_systm.h> 79 #include <netinet/in_var.h> 80 #include <netinet/ip.h> 81 #endif 82 83 #ifdef NS 84 #include <netns/ns.h> 85 #include <netns/ns_if.h> 86 #endif 87 88 #if defined(__NetBSD__) 89 #include <net/if_ether.h> 90 #include <uvm/uvm_extern.h> 91 #if defined(INET) 92 #include <netinet/if_inarp.h> 93 #endif 94 95 #include <machine/bus.h> 96 #include <machine/intr.h> 97 98 #include <dev/pci/pcireg.h> 99 #include <dev/pci/pcivar.h> 100 #include <dev/pci/pcidevs.h> 101 102 #include <dev/i2c/i2c_bus.h> 103 #include <dev/i2c/i2c_eeprom.h> 104 105 #include <dev/mii/mii.h> 106 #include <dev/mii/miivar.h> 107 108 #include <dev/mii/tlphyvar.h> 109 110 #include <dev/pci/if_tlregs.h> 111 #include <dev/pci/if_tlvar.h> 112 #endif /* __NetBSD__ */ 113 114 #if defined(__NetBSD__) && defined(__alpha__) 115 /* XXX XXX NEED REAL DMA MAPPING SUPPORT XXX XXX */ 116 #undef vtophys 117 #define vtophys(va) alpha_XXX_dmamap((vaddr_t)(va)) 118 #endif 119 120 /* number of transmit/receive buffers */ 121 #ifndef TL_NBUF 122 #define TL_NBUF 10 123 #endif 124 125 /* number of seconds the link can be idle */ 126 #ifndef TL_IDLETIME 127 #define TL_IDLETIME 10 128 #endif 129 130 static int tl_pci_match __P((struct device *, struct cfdata *, void *)); 131 static void tl_pci_attach __P((struct device *, struct device *, void *)); 132 static int tl_intr __P((void *)); 133 134 static int tl_ifioctl __P((struct ifnet *, ioctl_cmd_t, caddr_t)); 135 static int tl_mediachange __P((struct ifnet *)); 136 static void tl_mediastatus __P((struct ifnet *, struct ifmediareq *)); 137 static void tl_ifwatchdog __P((struct ifnet *)); 138 static void tl_shutdown __P((void*)); 139 140 static void tl_ifstart __P((struct ifnet *)); 141 static void tl_reset __P((tl_softc_t*)); 142 static int tl_init __P((tl_softc_t*)); 143 static void tl_restart __P((void *)); 144 static int tl_add_RxBuff __P((struct Rx_list*, struct mbuf*)); 145 static void tl_read_stats __P((tl_softc_t*)); 146 static void tl_ticks __P((void*)); 147 static int tl_multicast_hash __P((u_int8_t*)); 148 static void tl_addr_filter __P((tl_softc_t*)); 149 150 static u_int32_t tl_intreg_read __P((tl_softc_t*, u_int32_t)); 151 static void tl_intreg_write __P((tl_softc_t*, u_int32_t, u_int32_t)); 152 static u_int8_t tl_intreg_read_byte __P((tl_softc_t*, u_int32_t)); 153 static void tl_intreg_write_byte __P((tl_softc_t*, u_int32_t, u_int8_t)); 154 155 void tl_mii_sync __P((struct tl_softc *)); 156 void tl_mii_sendbits __P((struct tl_softc *, u_int32_t, int)); 157 158 159 #if defined(TLDEBUG_RX) 160 static void ether_printheader __P((struct ether_header*)); 161 #endif 162 163 int tl_mii_read __P((struct device *, int, int)); 164 void tl_mii_write __P((struct device *, int, int, int)); 165 166 void tl_statchg __P((struct device *)); 167 168 void tl_i2c_set __P((void*, u_int8_t)); 169 void tl_i2c_clr __P((void*, u_int8_t)); 170 int tl_i2c_read __P((void*, u_int8_t)); 171 172 static __inline void netsio_clr __P((tl_softc_t*, u_int8_t)); 173 static __inline void netsio_set __P((tl_softc_t*, u_int8_t)); 174 static __inline u_int8_t netsio_read __P((tl_softc_t*, u_int8_t)); 175 static __inline void netsio_clr(sc, bits) 176 tl_softc_t* sc; 177 u_int8_t bits; 178 { 179 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 180 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits)); 181 } 182 static __inline void netsio_set(sc, bits) 183 tl_softc_t* sc; 184 u_int8_t bits; 185 { 186 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 187 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits); 188 } 189 static __inline u_int8_t netsio_read(sc, bits) 190 tl_softc_t* sc; 191 u_int8_t bits; 192 { 193 return (tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits); 194 } 195 196 struct cfattach tl_ca = { 197 sizeof(tl_softc_t), tl_pci_match, tl_pci_attach 198 }; 199 200 const struct tl_product_desc tl_compaq_products[] = { 201 { PCI_PRODUCT_COMPAQ_N100TX, TLPHY_MEDIA_NO_10_T, 202 "Compaq Netelligent 10/100 TX" }, 203 { PCI_PRODUCT_COMPAQ_N10T, TLPHY_MEDIA_10_5, 204 "Compaq Netelligent 10 T" }, 205 { PCI_PRODUCT_COMPAQ_IntNF3P, TLPHY_MEDIA_10_2, 206 "Compaq Integrated NetFlex 3/P" }, 207 { PCI_PRODUCT_COMPAQ_IntPL100TX, TLPHY_MEDIA_10_2|TLPHY_MEDIA_NO_10_T, 208 "Compaq ProLiant Integrated Netelligent 10/100 TX" }, 209 { PCI_PRODUCT_COMPAQ_DPNet100TX, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 210 "Compaq Dual Port Netelligent 10/100 TX" }, 211 { PCI_PRODUCT_COMPAQ_DP4000, TLPHY_MEDIA_10_5, 212 "Compaq Deskpro 4000 5233MMX" }, 213 { PCI_PRODUCT_COMPAQ_NF3P_BNC, TLPHY_MEDIA_10_2, 214 "Compaq NetFlex 3/P w/ BNC" }, 215 { PCI_PRODUCT_COMPAQ_NF3P, TLPHY_MEDIA_10_5, 216 "Compaq NetFlex 3/P" }, 217 { 0, 0, NULL }, 218 }; 219 220 const struct tl_product_desc tl_ti_products[] = { 221 /* 222 * Built-in Ethernet on the TI TravelMate 5000 223 * docking station; better product description? 224 */ 225 { PCI_PRODUCT_TI_TLAN, 0, 226 "Texas Instruments ThunderLAN" }, 227 { 0, 0, NULL }, 228 }; 229 230 struct tl_vendor_desc { 231 u_int32_t tv_vendor; 232 const struct tl_product_desc *tv_products; 233 }; 234 235 const struct tl_vendor_desc tl_vendors[] = { 236 { PCI_VENDOR_COMPAQ, tl_compaq_products }, 237 { PCI_VENDOR_TI, tl_ti_products }, 238 { 0, NULL }, 239 }; 240 241 const struct tl_product_desc *tl_lookup_product __P((u_int32_t)); 242 243 const struct tl_product_desc * 244 tl_lookup_product(id) 245 u_int32_t id; 246 { 247 const struct tl_product_desc *tp; 248 const struct tl_vendor_desc *tv; 249 250 for (tv = tl_vendors; tv->tv_products != NULL; tv++) 251 if (PCI_VENDOR(id) == tv->tv_vendor) 252 break; 253 254 if ((tp = tv->tv_products) == NULL) 255 return (NULL); 256 257 for (; tp->tp_desc != NULL; tp++) 258 if (PCI_PRODUCT(id) == tp->tp_product) 259 break; 260 261 if (tp->tp_desc == NULL) 262 return (NULL); 263 264 return (tp); 265 } 266 267 static char *nullbuf = NULL; 268 269 static int 270 tl_pci_match(parent, match, aux) 271 struct device *parent; 272 struct cfdata *match; 273 void *aux; 274 { 275 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 276 277 if (tl_lookup_product(pa->pa_id) != NULL) 278 return (1); 279 280 return (0); 281 } 282 283 static void 284 tl_pci_attach(parent, self, aux) 285 struct device * parent; 286 struct device * self; 287 void * aux; 288 { 289 tl_softc_t *sc = (tl_softc_t *)self; 290 struct pci_attach_args * const pa = (struct pci_attach_args *) aux; 291 const struct tl_product_desc *tp; 292 struct ifnet * const ifp = &sc->tl_if; 293 bus_space_tag_t iot, memt; 294 bus_space_handle_t ioh, memh; 295 pci_intr_handle_t intrhandle; 296 const char *intrstr; 297 int i, tmp, ioh_valid, memh_valid; 298 int reg_io, reg_mem; 299 pcireg_t reg10, reg14; 300 pcireg_t csr; 301 302 printf("\n"); 303 304 callout_init(&sc->tl_tick_ch); 305 callout_init(&sc->tl_restart_ch); 306 307 tp = tl_lookup_product(pa->pa_id); 308 if (tp == NULL) 309 panic("tl_pci_attach: impossible"); 310 sc->tl_product = tp; 311 312 /* 313 * Map the card space. Fisrt we have to find the I/O and MEM 314 * registers. I/O is supposed to be at 0x10, MEM at 0x14, 315 * but some boards (Compaq Netflex 3/P PCI) seem to have it reversed. 316 * The ThunderLAN manual is not consistent about this either (there 317 * are both cases in code examples). 318 */ 319 reg10 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x10); 320 reg14 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x14); 321 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_IO) 322 reg_io = 0x10; 323 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_IO) 324 reg_io = 0x14; 325 else 326 reg_io = 0; 327 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_MEM) 328 reg_mem = 0x10; 329 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_MEM) 330 reg_mem = 0x14; 331 else 332 reg_mem = 0; 333 334 if (reg_io != 0) 335 ioh_valid = (pci_mapreg_map(pa, reg_io, PCI_MAPREG_TYPE_IO, 336 0, &iot, &ioh, NULL, NULL) == 0); 337 else 338 ioh_valid = 0; 339 if (reg_mem != 0) 340 memh_valid = (pci_mapreg_map(pa, PCI_CBMA, 341 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 342 0, &memt, &memh, NULL, NULL) == 0); 343 else 344 memh_valid = 0; 345 346 if (ioh_valid) { 347 sc->tl_bustag = iot; 348 sc->tl_bushandle = ioh; 349 } else if (memh_valid) { 350 sc->tl_bustag = memt; 351 sc->tl_bushandle = memh; 352 } else { 353 printf("%s: unable to map device registers\n", 354 sc->sc_dev.dv_xname); 355 return; 356 } 357 358 /* Enable the device. */ 359 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 360 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 361 csr | PCI_COMMAND_MASTER_ENABLE); 362 363 printf("%s: %s\n", sc->sc_dev.dv_xname, tp->tp_desc); 364 365 tl_reset(sc); 366 367 /* fill in the i2c struct */ 368 sc->i2cbus.adapter_softc = sc; 369 sc->i2cbus.set_bit = tl_i2c_set; 370 sc->i2cbus.clr_bit = tl_i2c_clr; 371 sc->i2cbus.read_bit = tl_i2c_read; 372 373 #ifdef TLDEBUG 374 printf("default values of INTreg: 0x%x\n", 375 tl_intreg_read(sc, TL_INT_Defaults)); 376 #endif 377 378 /* read mac addr */ 379 for (i=0; i<ETHER_ADDR_LEN; i++) { 380 tmp = i2c_eeprom_read(&sc->i2cbus, 0x83 + i); 381 if (tmp < 0) { 382 printf("%s: error reading Ethernet adress\n", 383 sc->sc_dev.dv_xname); 384 return; 385 } else { 386 sc->tl_enaddr[i] = tmp; 387 } 388 } 389 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 390 ether_sprintf(sc->tl_enaddr)); 391 392 /* Map and establish interrupts */ 393 if (pci_intr_map(pa, &intrhandle)) { 394 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 395 return; 396 } 397 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 398 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 399 tl_intr, sc); 400 if (sc->tl_ih == NULL) { 401 printf("%s: couldn't establish interrupt", 402 sc->sc_dev.dv_xname); 403 if (intrstr != NULL) 404 printf(" at %s", intrstr); 405 printf("\n"); 406 return; 407 } 408 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 409 410 /* 411 * Add shutdown hook so that DMA is disabled prior to reboot. Not 412 * doing do could allow DMA to corrupt kernel memory during the 413 * reboot before the driver initializes. 414 */ 415 (void) shutdownhook_establish(tl_shutdown, sc); 416 417 /* 418 * Initialize our media structures and probe the MII. 419 * 420 * Note that we don't care about the media instance. We 421 * are expecting to have multiple PHYs on the 10/100 cards, 422 * and on those cards we exclude the internal PHY from providing 423 * 10baseT. By ignoring the instance, it allows us to not have 424 * to specify it on the command line when switching media. 425 */ 426 sc->tl_mii.mii_ifp = ifp; 427 sc->tl_mii.mii_readreg = tl_mii_read; 428 sc->tl_mii.mii_writereg = tl_mii_write; 429 sc->tl_mii.mii_statchg = tl_statchg; 430 ifmedia_init(&sc->tl_mii.mii_media, IFM_IMASK, tl_mediachange, 431 tl_mediastatus); 432 mii_attach(self, &sc->tl_mii, 0xffffffff, MII_PHY_ANY, 433 MII_OFFSET_ANY, 0); 434 if (LIST_FIRST(&sc->tl_mii.mii_phys) == NULL) { 435 ifmedia_add(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 436 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE); 437 } else 438 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_AUTO); 439 440 bcopy(sc->sc_dev.dv_xname, sc->tl_if.if_xname, IFNAMSIZ); 441 sc->tl_if.if_softc = sc; 442 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 443 ifp->if_ioctl = tl_ifioctl; 444 ifp->if_start = tl_ifstart; 445 ifp->if_watchdog = tl_ifwatchdog; 446 ifp->if_timer = 0; 447 if_attach(ifp); 448 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr); 449 } 450 451 static void 452 tl_reset(sc) 453 tl_softc_t *sc; 454 { 455 int i; 456 457 /* read stats */ 458 if (sc->tl_if.if_flags & IFF_RUNNING) { 459 callout_stop(&sc->tl_tick_ch); 460 tl_read_stats(sc); 461 } 462 /* Reset adapter */ 463 TL_HR_WRITE(sc, TL_HOST_CMD, 464 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst); 465 DELAY(100000); 466 /* Disable interrupts */ 467 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 468 /* setup aregs & hash */ 469 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 470 tl_intreg_write(sc, i, 0); 471 #ifdef TLDEBUG_ADDR 472 printf("Areg & hash registers: \n"); 473 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 474 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 475 #endif 476 /* Setup NetConfig */ 477 tl_intreg_write(sc, TL_INT_NetConfig, 478 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN); 479 /* Bsize: accept default */ 480 /* TX commit in Acommit: accept default */ 481 /* Load Ld_tmr and Ld_thr */ 482 /* Ld_tmr = 3 */ 483 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr); 484 /* Ld_thr = 0 */ 485 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr); 486 /* Unreset MII */ 487 netsio_set(sc, TL_NETSIO_NMRST); 488 DELAY(100000); 489 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 490 sc->tl_flags = 0; 491 sc->opkt = 0; 492 sc->stats_exesscoll = 0; 493 } 494 495 static void tl_shutdown(v) 496 void *v; 497 { 498 tl_softc_t *sc = v; 499 struct Tx_list *Tx; 500 int i; 501 502 if ((sc->tl_if.if_flags & IFF_RUNNING) == 0) 503 return; 504 /* disable interrupts */ 505 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 506 /* stop TX and RX channels */ 507 TL_HR_WRITE(sc, TL_HOST_CMD, 508 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes); 509 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP); 510 DELAY(100000); 511 512 /* stop statistics reading loop, read stats */ 513 callout_stop(&sc->tl_tick_ch); 514 tl_read_stats(sc); 515 516 /* Down the MII. */ 517 mii_down(&sc->tl_mii); 518 519 /* deallocate memory allocations */ 520 for (i=0; i< TL_NBUF; i++) { 521 if (sc->Rx_list[i].m) 522 m_freem(sc->Rx_list[i].m); 523 sc->Rx_list[i].m = NULL; 524 } 525 free(sc->Rx_list, M_DEVBUF); 526 sc->Rx_list = NULL; 527 while ((Tx = sc->active_Tx) != NULL) { 528 Tx->hw_list.stat = 0; 529 m_freem(Tx->m); 530 sc->active_Tx = Tx->next; 531 Tx->next = sc->Free_Tx; 532 sc->Free_Tx = Tx; 533 } 534 sc->last_Tx = NULL; 535 free(sc->Tx_list, M_DEVBUF); 536 sc->Tx_list = NULL; 537 sc->tl_if.if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 538 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 539 sc->tl_flags = 0; 540 } 541 542 static void tl_restart(v) 543 void *v; 544 { 545 tl_init(v); 546 } 547 548 static int tl_init(sc) 549 tl_softc_t *sc; 550 { 551 struct ifnet *ifp = &sc->tl_if; 552 int i, s; 553 554 s = splnet(); 555 /* cancel any pending IO */ 556 tl_shutdown(sc); 557 tl_reset(sc); 558 if ((sc->tl_if.if_flags & IFF_UP) == 0) { 559 splx(s); 560 return 0; 561 } 562 /* Set various register to reasonable value */ 563 /* setup NetCmd in promisc mode if needed */ 564 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0; 565 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 566 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i); 567 /* Max receive size : MCLBYTES */ 568 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff); 569 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH, 570 (MCLBYTES >> 8) & 0xff); 571 572 /* init MAC addr */ 573 for (i = 0; i < ETHER_ADDR_LEN; i++) 574 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]); 575 /* add multicast filters */ 576 tl_addr_filter(sc); 577 #ifdef TLDEBUG_ADDR 578 printf("Wrote Mac addr, Areg & hash registers are now: \n"); 579 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 580 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 581 #endif 582 583 /* Pre-allocate receivers mbuf, make the lists */ 584 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF, 585 M_NOWAIT); 586 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF, 587 M_NOWAIT); 588 if (sc->Rx_list == NULL || sc->Tx_list == NULL) { 589 printf("%s: out of memory for lists\n", sc->sc_dev.dv_xname); 590 sc->tl_if.if_flags &= ~IFF_UP; 591 splx(s); 592 return ENOMEM; 593 } 594 for (i=0; i< TL_NBUF; i++) { 595 if (tl_add_RxBuff(&sc->Rx_list[i], NULL) == 0) { 596 printf("%s: out of mbuf for receive list\n", 597 sc->sc_dev.dv_xname); 598 sc->tl_if.if_flags &= ~IFF_UP; 599 splx(s); 600 return ENOMEM; 601 } 602 if (i > 0) { /* chain the list */ 603 sc->Rx_list[i-1].next = &sc->Rx_list[i]; 604 sc->Rx_list[i-1].hw_list.fwd = 605 vtophys((vaddr_t)&sc->Rx_list[i].hw_list); 606 #ifdef DIAGNOSTIC 607 if (sc->Rx_list[i-1].hw_list.fwd & 0x7) 608 printf("%s: physical addr 0x%x of list not " 609 "properly aligned\n", 610 sc->sc_dev.dv_xname, 611 sc->Rx_list[i-1].hw_list.fwd); 612 #endif 613 sc->Tx_list[i-1].next = &sc->Tx_list[i]; 614 } 615 } 616 sc->Rx_list[TL_NBUF-1].next = NULL; 617 sc->Rx_list[TL_NBUF-1].hw_list.fwd = 0; 618 sc->Tx_list[TL_NBUF-1].next = NULL; 619 620 sc->active_Rx = &sc->Rx_list[0]; 621 sc->last_Rx = &sc->Rx_list[TL_NBUF-1]; 622 sc->active_Tx = sc->last_Tx = NULL; 623 sc->Free_Tx = &sc->Tx_list[0]; 624 625 if (nullbuf == NULL) 626 nullbuf = malloc(ETHER_MIN_TX, M_DEVBUF, M_NOWAIT); 627 if (nullbuf == NULL) { 628 printf("%s: can't allocate space for pad buffer\n", 629 sc->sc_dev.dv_xname); 630 sc->tl_if.if_flags &= ~IFF_UP; 631 splx(s); 632 return ENOMEM; 633 } 634 bzero(nullbuf, ETHER_MIN_TX); 635 636 /* set media */ 637 mii_mediachg(&sc->tl_mii); 638 639 /* start ticks calls */ 640 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 641 /* write adress of Rx list and enable interrupts */ 642 TL_HR_WRITE(sc, TL_HOST_CH_PARM, vtophys((vaddr_t)&sc->Rx_list[0].hw_list)); 643 TL_HR_WRITE(sc, TL_HOST_CMD, 644 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn); 645 sc->tl_if.if_flags |= IFF_RUNNING; 646 sc->tl_if.if_flags &= ~IFF_OACTIVE; 647 return 0; 648 } 649 650 651 static u_int32_t 652 tl_intreg_read(sc, reg) 653 tl_softc_t *sc; 654 u_int32_t reg; 655 { 656 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 657 return TL_HR_READ(sc, TL_HOST_DIO_DATA); 658 } 659 660 static u_int8_t 661 tl_intreg_read_byte(sc, reg) 662 tl_softc_t *sc; 663 u_int32_t reg; 664 { 665 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 666 (reg & (~0x07)) & TL_HOST_DIOADR_MASK); 667 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07)); 668 } 669 670 static void 671 tl_intreg_write(sc, reg, val) 672 tl_softc_t *sc; 673 u_int32_t reg; 674 u_int32_t val; 675 { 676 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 677 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val); 678 } 679 680 static void 681 tl_intreg_write_byte(sc, reg, val) 682 tl_softc_t *sc; 683 u_int32_t reg; 684 u_int8_t val; 685 { 686 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 687 (reg & (~0x03)) & TL_HOST_DIOADR_MASK); 688 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val); 689 } 690 691 void 692 tl_mii_sync(sc) 693 struct tl_softc *sc; 694 { 695 int i; 696 697 netsio_clr(sc, TL_NETSIO_MTXEN); 698 for (i = 0; i < 32; i++) { 699 netsio_clr(sc, TL_NETSIO_MCLK); 700 netsio_set(sc, TL_NETSIO_MCLK); 701 } 702 } 703 704 void 705 tl_mii_sendbits(sc, data, nbits) 706 struct tl_softc *sc; 707 u_int32_t data; 708 int nbits; 709 { 710 int i; 711 712 netsio_set(sc, TL_NETSIO_MTXEN); 713 for (i = 1 << (nbits - 1); i; i = i >> 1) { 714 netsio_clr(sc, TL_NETSIO_MCLK); 715 netsio_read(sc, TL_NETSIO_MCLK); 716 if (data & i) 717 netsio_set(sc, TL_NETSIO_MDATA); 718 else 719 netsio_clr(sc, TL_NETSIO_MDATA); 720 netsio_set(sc, TL_NETSIO_MCLK); 721 netsio_read(sc, TL_NETSIO_MCLK); 722 } 723 } 724 725 int 726 tl_mii_read(self, phy, reg) 727 struct device *self; 728 int phy, reg; 729 { 730 struct tl_softc *sc = (struct tl_softc *)self; 731 int val = 0, i, err; 732 733 /* 734 * Read the PHY register by manually driving the MII control lines. 735 */ 736 737 tl_mii_sync(sc); 738 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 739 tl_mii_sendbits(sc, MII_COMMAND_READ, 2); 740 tl_mii_sendbits(sc, phy, 5); 741 tl_mii_sendbits(sc, reg, 5); 742 743 netsio_clr(sc, TL_NETSIO_MTXEN); 744 netsio_clr(sc, TL_NETSIO_MCLK); 745 netsio_set(sc, TL_NETSIO_MCLK); 746 netsio_clr(sc, TL_NETSIO_MCLK); 747 748 err = netsio_read(sc, TL_NETSIO_MDATA); 749 netsio_set(sc, TL_NETSIO_MCLK); 750 751 /* Even if an error occurs, must still clock out the cycle. */ 752 for (i = 0; i < 16; i++) { 753 val <<= 1; 754 netsio_clr(sc, TL_NETSIO_MCLK); 755 if (err == 0 && netsio_read(sc, TL_NETSIO_MDATA)) 756 val |= 1; 757 netsio_set(sc, TL_NETSIO_MCLK); 758 } 759 netsio_clr(sc, TL_NETSIO_MCLK); 760 netsio_set(sc, TL_NETSIO_MCLK); 761 762 return (err ? 0 : val); 763 } 764 765 void 766 tl_mii_write(self, phy, reg, val) 767 struct device *self; 768 int phy, reg, val; 769 { 770 struct tl_softc *sc = (struct tl_softc *)self; 771 772 /* 773 * Write the PHY register by manually driving the MII control lines. 774 */ 775 776 tl_mii_sync(sc); 777 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 778 tl_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 779 tl_mii_sendbits(sc, phy, 5); 780 tl_mii_sendbits(sc, reg, 5); 781 tl_mii_sendbits(sc, MII_COMMAND_ACK, 2); 782 tl_mii_sendbits(sc, val, 16); 783 784 netsio_clr(sc, TL_NETSIO_MCLK); 785 netsio_set(sc, TL_NETSIO_MCLK); 786 } 787 788 void 789 tl_statchg(self) 790 struct device *self; 791 { 792 tl_softc_t *sc = (struct tl_softc *)self; 793 u_int32_t reg; 794 795 #ifdef TLDEBUG 796 printf("tl_statchg, media %x\n", sc->tl_ifmedia.ifm_media); 797 #endif 798 799 /* 800 * We must keep the ThunderLAN and the PHY in sync as 801 * to the status of full-duplex! 802 */ 803 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 804 if (sc->tl_mii.mii_media_active & IFM_FDX) 805 reg |= TL_NETCOMMAND_DUPLEX; 806 else 807 reg &= ~TL_NETCOMMAND_DUPLEX; 808 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 809 } 810 811 void tl_i2c_set(v, bit) 812 void *v; 813 u_int8_t bit; 814 { 815 tl_softc_t *sc = v; 816 817 switch (bit) { 818 case I2C_DATA: 819 netsio_set(sc, TL_NETSIO_EDATA); 820 break; 821 case I2C_CLOCK: 822 netsio_set(sc, TL_NETSIO_ECLOCK); 823 break; 824 case I2C_TXEN: 825 netsio_set(sc, TL_NETSIO_ETXEN); 826 break; 827 default: 828 printf("tl_i2c_set: unknown bit %d\n", bit); 829 } 830 return; 831 } 832 833 void tl_i2c_clr(v, bit) 834 void *v; 835 u_int8_t bit; 836 { 837 tl_softc_t *sc = v; 838 839 switch (bit) { 840 case I2C_DATA: 841 netsio_clr(sc, TL_NETSIO_EDATA); 842 break; 843 case I2C_CLOCK: 844 netsio_clr(sc, TL_NETSIO_ECLOCK); 845 break; 846 case I2C_TXEN: 847 netsio_clr(sc, TL_NETSIO_ETXEN); 848 break; 849 default: 850 printf("tl_i2c_clr: unknown bit %d\n", bit); 851 } 852 return; 853 } 854 855 int tl_i2c_read(v, bit) 856 void *v; 857 u_int8_t bit; 858 { 859 tl_softc_t *sc = v; 860 861 switch (bit) { 862 case I2C_DATA: 863 return netsio_read(sc, TL_NETSIO_EDATA); 864 break; 865 case I2C_CLOCK: 866 return netsio_read(sc, TL_NETSIO_ECLOCK); 867 break; 868 case I2C_TXEN: 869 return netsio_read(sc, TL_NETSIO_ETXEN); 870 break; 871 default: 872 printf("tl_i2c_read: unknown bit %d\n", bit); 873 return -1; 874 } 875 } 876 877 static int 878 tl_intr(v) 879 void *v; 880 { 881 tl_softc_t *sc = v; 882 struct ifnet *ifp = &sc->tl_if; 883 struct Rx_list *Rx; 884 struct Tx_list *Tx; 885 struct mbuf *m; 886 u_int32_t int_type, int_reg; 887 int ack = 0; 888 int size; 889 890 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR); 891 int_type = int_reg & TL_INTR_MASK; 892 if (int_type == 0) 893 return 0; 894 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX) 895 printf("%s: interrupt type %x, intr_reg %x\n", sc->sc_dev.dv_xname, 896 int_type, int_reg); 897 #endif 898 /* disable interrupts */ 899 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 900 switch(int_type & TL_INTR_MASK) { 901 case TL_INTR_RxEOF: 902 while(sc->active_Rx->hw_list.stat & TL_RX_CSTAT_CPLT) { 903 /* dequeue and requeue at end of list */ 904 ack++; 905 Rx = sc->active_Rx; 906 sc->active_Rx = Rx->next; 907 m = Rx->m; 908 size = Rx->hw_list.stat >> 16; 909 #ifdef TLDEBUG_RX 910 printf("tl_intr: RX list complete, Rx %p, size=%d\n", 911 Rx, size); 912 #endif 913 if (tl_add_RxBuff(Rx, m ) == 0) { 914 /* 915 * No new mbuf, reuse the same. This means 916 * that this packet 917 * is lost 918 */ 919 m = NULL; 920 #ifdef TL_PRIV_STATS 921 sc->ierr_nomem++; 922 #endif 923 #ifdef TLDEBUG 924 printf("%s: out of mbuf, lost input packet\n", 925 sc->sc_dev.dv_xname); 926 #endif 927 } 928 Rx->next = NULL; 929 Rx->hw_list.fwd = 0; 930 sc->last_Rx->hw_list.fwd = vtophys((vaddr_t)&Rx->hw_list); 931 #ifdef DIAGNOSTIC 932 if (sc->last_Rx->hw_list.fwd & 0x7) 933 printf("%s: physical addr 0x%x of list not " 934 "properly aligned\n", 935 sc->sc_dev.dv_xname, 936 sc->last_Rx->hw_list.fwd); 937 #endif 938 sc->last_Rx->next = Rx; 939 sc->last_Rx = Rx; 940 941 /* deliver packet */ 942 if (m) { 943 if (size < sizeof(struct ether_header)) { 944 m_freem(m); 945 continue; 946 } 947 m->m_pkthdr.rcvif = ifp; 948 m->m_pkthdr.len = m->m_len = size; 949 #ifdef TLDEBUG_RX 950 { struct ether_header *eh = 951 mtod(m, struct ether_header *); 952 printf("tl_intr: Rx packet:\n"); 953 ether_printheader(eh); } 954 #endif 955 #if NBPFILTER > 0 956 if (ifp->if_bpf) 957 bpf_mtap(ifp->if_bpf, m); 958 #endif /* NBPFILTER > 0 */ 959 (*ifp->if_input)(ifp, m); 960 } 961 } 962 #ifdef TLDEBUG_RX 963 printf("TL_INTR_RxEOF: ack %d\n", ack); 964 #else 965 if (ack == 0) { 966 printf("%s: EOF intr without anything to read !\n", 967 sc->sc_dev.dv_xname); 968 tl_reset(sc); 969 /* shedule reinit of the board */ 970 callout_reset(&sc->tl_restart_ch, 1, tl_restart, sc); 971 return(1); 972 } 973 #endif 974 break; 975 case TL_INTR_RxEOC: 976 ack++; 977 #ifdef TLDEBUG_RX 978 printf("TL_INTR_RxEOC: ack %d\n", ack); 979 #endif 980 #ifdef DIAGNOSTIC 981 if (sc->active_Rx->hw_list.stat & TL_RX_CSTAT_CPLT) { 982 printf("%s: Rx EOC interrupt and active Rx list not " 983 "cleared\n", sc->sc_dev.dv_xname); 984 return 0; 985 } else 986 #endif 987 { 988 /* 989 * write adress of Rx list and send Rx GO command, ack 990 * interrupt and enable interrupts in one command 991 */ 992 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 993 vtophys((vaddr_t)&sc->active_Rx->hw_list)); 994 TL_HR_WRITE(sc, TL_HOST_CMD, 995 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type | 996 HOST_CMD_ACK | HOST_CMD_IntOn); 997 return 1; 998 } 999 case TL_INTR_TxEOF: 1000 case TL_INTR_TxEOC: 1001 while ((Tx = sc->active_Tx) != NULL) { 1002 if((Tx->hw_list.stat & TL_TX_CSTAT_CPLT) == 0) 1003 break; 1004 ack++; 1005 #ifdef TLDEBUG_TX 1006 printf("TL_INTR_TxEOC: list 0x%xp done\n", 1007 vtophys((vaddr_t)&Tx->hw_list)); 1008 #endif 1009 Tx->hw_list.stat = 0; 1010 m_freem(Tx->m); 1011 Tx->m = NULL; 1012 sc->active_Tx = Tx->next; 1013 if (sc->active_Tx == NULL) 1014 sc->last_Tx = NULL; 1015 Tx->next = sc->Free_Tx; 1016 sc->Free_Tx = Tx; 1017 } 1018 /* if this was an EOC, ACK immediatly */ 1019 if (int_type == TL_INTR_TxEOC) { 1020 #ifdef TLDEBUG_TX 1021 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n", 1022 ack); 1023 #endif 1024 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type | 1025 HOST_CMD_ACK | HOST_CMD_IntOn); 1026 if ( sc->active_Tx != NULL) { 1027 /* needs a Tx go command */ 1028 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 1029 vtophys((vaddr_t)&sc->active_Tx->hw_list)); 1030 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1031 } 1032 sc->tl_if.if_timer = 0; 1033 if (sc->tl_if.if_snd.ifq_head != NULL) 1034 tl_ifstart(&sc->tl_if); 1035 return 1; 1036 } 1037 #ifdef TLDEBUG 1038 else { 1039 printf("TL_INTR_TxEOF: ack %d\n", ack); 1040 } 1041 #endif 1042 sc->tl_if.if_timer = 0; 1043 if (sc->tl_if.if_snd.ifq_head != NULL) 1044 tl_ifstart(&sc->tl_if); 1045 break; 1046 case TL_INTR_Stat: 1047 ack++; 1048 #ifdef TLDEBUG 1049 printf("TL_INTR_Stat: ack %d\n", ack); 1050 #endif 1051 tl_read_stats(sc); 1052 break; 1053 case TL_INTR_Adc: 1054 if (int_reg & TL_INTVec_MASK) { 1055 /* adapter check conditions */ 1056 printf("%s: check condition, intvect=0x%x, " 1057 "ch_param=0x%x\n", sc->sc_dev.dv_xname, 1058 int_reg & TL_INTVec_MASK, 1059 TL_HR_READ(sc, TL_HOST_CH_PARM)); 1060 tl_reset(sc); 1061 /* shedule reinit of the board */ 1062 callout_reset(&sc->tl_restart_ch, 1, tl_restart, sc); 1063 return(1); 1064 } else { 1065 u_int8_t netstat; 1066 /* Network status */ 1067 netstat = 1068 tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts); 1069 printf("%s: network status, NetSts=%x\n", 1070 sc->sc_dev.dv_xname, netstat); 1071 /* Ack interrupts */ 1072 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts, 1073 netstat); 1074 ack++; 1075 } 1076 break; 1077 default: 1078 printf("%s: unhandled interrupt code %x!\n", 1079 sc->sc_dev.dv_xname, int_type); 1080 ack++; 1081 } 1082 1083 if (ack) { 1084 /* Ack the interrupt and enable interrupts */ 1085 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK | 1086 HOST_CMD_IntOn); 1087 return 1; 1088 } 1089 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */ 1090 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn); 1091 return 0; 1092 } 1093 1094 static int 1095 tl_ifioctl(ifp, cmd, data) 1096 struct ifnet *ifp; 1097 ioctl_cmd_t cmd; 1098 caddr_t data; 1099 { 1100 struct tl_softc *sc = ifp->if_softc; 1101 struct ifreq *ifr = (struct ifreq *)data; 1102 int s, error; 1103 1104 s = splnet(); 1105 switch(cmd) { 1106 case SIOCSIFADDR: { 1107 struct ifaddr *ifa = (struct ifaddr *)data; 1108 sc->tl_if.if_flags |= IFF_UP; 1109 if ((error = tl_init(sc)) != NULL) { 1110 sc->tl_if.if_flags &= ~IFF_UP; 1111 break; 1112 } 1113 switch (ifa->ifa_addr->sa_family) { 1114 #ifdef INET 1115 case AF_INET: 1116 arp_ifinit(ifp, ifa); 1117 break; 1118 #endif 1119 #ifdef NS 1120 case AF_NS: { 1121 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1122 1123 if (ns_nullhost(*ina)) 1124 ina->x_host = 1125 *(union ns_host*) LLADDR(ifp->if_sadl); 1126 else 1127 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1128 ifp->if_addrlen); 1129 break; 1130 } 1131 #endif 1132 default: 1133 break; 1134 } 1135 break; 1136 } 1137 case SIOCSIFFLAGS: 1138 { 1139 u_int8_t reg; 1140 /* 1141 * If interface is marked up and not running, then start it. 1142 * If it is marked down and running, stop it. 1143 */ 1144 if (ifp->if_flags & IFF_UP) { 1145 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1146 error = tl_init(sc); 1147 /* all flags have been handled by init */ 1148 break; 1149 } 1150 error = 0; 1151 reg = tl_intreg_read_byte(sc, 1152 TL_INT_NET + TL_INT_NetCmd); 1153 if (ifp->if_flags & IFF_PROMISC) 1154 reg |= TL_NETCOMMAND_CAF; 1155 else 1156 reg &= ~TL_NETCOMMAND_CAF; 1157 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 1158 reg); 1159 #ifdef TL_PRIV_STATS 1160 if (ifp->if_flags & IFF_LINK0) { 1161 ifp->if_flags &= ~IFF_LINK0; 1162 printf("%s errors statistics\n", 1163 sc->sc_dev.dv_xname); 1164 printf(" %4d RX buffer overrun\n", 1165 sc->ierr_overr); 1166 printf(" %4d RX code error\n", 1167 sc->ierr_code); 1168 printf(" %4d RX crc error\n", 1169 sc->ierr_crc); 1170 printf(" %4d RX out of memory\n", 1171 sc->ierr_nomem); 1172 printf(" %4d TX buffer underrun\n", 1173 sc->oerr_underr); 1174 printf(" %4d TX deffered frames\n", 1175 sc->oerr_deffered); 1176 printf(" %4d TX single collisions\n", 1177 sc->oerr_coll); 1178 printf(" %4d TX multi collisions\n", 1179 sc->oerr_multicoll); 1180 printf(" %4d TX exessive collisions\n", 1181 sc->oerr_exesscoll); 1182 printf(" %4d TX late collisions\n", 1183 sc->oerr_latecoll); 1184 printf(" %4d TX carrier loss\n", 1185 sc->oerr_carrloss); 1186 printf(" %4d TX mbuf copy\n", 1187 sc->oerr_mcopy); 1188 } 1189 #endif 1190 } else { 1191 if (ifp->if_flags & IFF_RUNNING) 1192 tl_shutdown(sc); 1193 error = 0; 1194 } 1195 break; 1196 } 1197 case SIOCADDMULTI: 1198 case SIOCDELMULTI: 1199 /* 1200 * Update multicast listeners 1201 */ 1202 if (cmd == SIOCADDMULTI) 1203 error = ether_addmulti(ifr, &sc->tl_ec); 1204 else 1205 error = ether_delmulti(ifr, &sc->tl_ec); 1206 if (error == ENETRESET) { 1207 tl_addr_filter(sc); 1208 error = 0; 1209 } 1210 break; 1211 case SIOCSIFMEDIA: 1212 case SIOCGIFMEDIA: 1213 error = ifmedia_ioctl(ifp, ifr, &sc->tl_mii.mii_media, cmd); 1214 break; 1215 default: 1216 error = EINVAL; 1217 } 1218 splx(s); 1219 return error; 1220 } 1221 1222 static void 1223 tl_ifstart(ifp) 1224 struct ifnet *ifp; 1225 { 1226 tl_softc_t *sc = ifp->if_softc; 1227 struct mbuf *m, *mb_head; 1228 struct Tx_list *Tx; 1229 int segment, size; 1230 1231 txloop: 1232 /* If we don't have more space ... */ 1233 if (sc->Free_Tx == NULL) { 1234 #ifdef TLDEBUG 1235 printf("tl_ifstart: No free TX list\n"); 1236 #endif 1237 return; 1238 } 1239 /* Grab a paquet for output */ 1240 IF_DEQUEUE(&ifp->if_snd, mb_head); 1241 if (mb_head == NULL) { 1242 #ifdef TLDEBUG_TX 1243 printf("tl_ifstart: nothing to send\n"); 1244 #endif 1245 return; 1246 } 1247 Tx = sc->Free_Tx; 1248 sc->Free_Tx = Tx->next; 1249 /* 1250 * Go through each of the mbufs in the chain and initialize 1251 * the transmit list descriptors with the physical address 1252 * and size of the mbuf. 1253 */ 1254 tbdinit: 1255 bzero(Tx, sizeof(struct Tx_list)); 1256 Tx->m = mb_head; 1257 size = 0; 1258 for (m = mb_head, segment = 0; m != NULL ; m = m->m_next) { 1259 if (m->m_len != 0) { 1260 if (segment == TL_NSEG) 1261 break; 1262 size += m->m_len; 1263 Tx->hw_list.seg[segment].data_addr = 1264 vtophys(mtod(m, vaddr_t)); 1265 Tx->hw_list.seg[segment].data_count = m->m_len; 1266 segment++; 1267 } 1268 } 1269 if (m != NULL || (size < ETHER_MIN_TX && segment == TL_NSEG)) { 1270 /* 1271 * We ran out of segments, or we will. We have to recopy this 1272 * mbuf chain first. 1273 */ 1274 struct mbuf *mn; 1275 #ifdef TLDEBUG_TX 1276 printf("tl_ifstart: need to copy mbuf\n"); 1277 #endif 1278 #ifdef TL_PRIV_STATS 1279 sc->oerr_mcopy++; 1280 #endif 1281 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1282 if (mn == NULL) { 1283 m_freem(mb_head); 1284 goto bad; 1285 } 1286 if (mb_head->m_pkthdr.len > MHLEN) { 1287 MCLGET(mn, M_DONTWAIT); 1288 if ((mn->m_flags & M_EXT) == 0) { 1289 m_freem(mn); 1290 m_freem(mb_head); 1291 goto bad; 1292 } 1293 } 1294 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1295 mtod(mn, caddr_t)); 1296 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1297 m_freem(mb_head); 1298 mb_head = mn; 1299 goto tbdinit; 1300 } 1301 /* We are at end of mbuf chain. check the size and 1302 * see if it needs to be extended 1303 */ 1304 if (size < ETHER_MIN_TX) { 1305 #ifdef DIAGNOSTIC 1306 if (segment >= TL_NSEG) { 1307 panic("tl_ifstart: to much segmets (%d)\n", segment); 1308 } 1309 #endif 1310 /* 1311 * add the nullbuf in the seg 1312 */ 1313 Tx->hw_list.seg[segment].data_count = 1314 ETHER_MIN_TX - size; 1315 Tx->hw_list.seg[segment].data_addr = 1316 vtophys((vaddr_t)nullbuf); 1317 size = ETHER_MIN_TX; 1318 segment++; 1319 } 1320 /* The list is done, finish the list init */ 1321 Tx->hw_list.seg[segment-1].data_count |= 1322 TL_LAST_SEG; 1323 Tx->hw_list.stat = (size << 16) | 0x3000; 1324 #ifdef TLDEBUG_TX 1325 printf("%s: sending, Tx : stat = 0x%x\n", sc->sc_dev.dv_xname, 1326 Tx->hw_list.stat); 1327 #if 0 1328 for(segment = 0; segment < TL_NSEG; segment++) { 1329 printf(" seg %d addr 0x%x len 0x%x\n", 1330 segment, 1331 Tx->hw_list.seg[segment].data_addr, 1332 Tx->hw_list.seg[segment].data_count); 1333 } 1334 #endif 1335 #endif 1336 sc->opkt++; 1337 if (sc->active_Tx == NULL) { 1338 sc->active_Tx = sc->last_Tx = Tx; 1339 #ifdef TLDEBUG_TX 1340 printf("%s: Tx GO, addr=0x%x\n", sc->sc_dev.dv_xname, 1341 vtophys((vaddr_t)&Tx->hw_list)); 1342 #endif 1343 TL_HR_WRITE(sc, TL_HOST_CH_PARM, vtophys((vaddr_t)&Tx->hw_list)); 1344 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1345 } else { 1346 #ifdef TLDEBUG_TX 1347 printf("%s: Tx addr=0x%x queued\n", sc->sc_dev.dv_xname, 1348 vtophys((vaddr_t)&Tx->hw_list)); 1349 #endif 1350 sc->last_Tx->hw_list.fwd = vtophys((vaddr_t)&Tx->hw_list); 1351 sc->last_Tx->next = Tx; 1352 sc->last_Tx = Tx; 1353 #ifdef DIAGNOSTIC 1354 if (sc->last_Tx->hw_list.fwd & 0x7) 1355 printf("%s: physical addr 0x%x of list not properly " 1356 "aligned\n", 1357 sc->sc_dev.dv_xname, sc->last_Rx->hw_list.fwd); 1358 #endif 1359 } 1360 #if NBPFILTER > 0 1361 /* Pass packet to bpf if there is a listener */ 1362 if (ifp->if_bpf) 1363 bpf_mtap(ifp->if_bpf, mb_head); 1364 #endif 1365 /* 1366 * Set a 5 second timer just in case we don't hear from the card again. 1367 */ 1368 ifp->if_timer = 5; 1369 goto txloop; 1370 bad: 1371 #ifdef TLDEBUG 1372 printf("tl_ifstart: Out of mbuf, Tx pkt lost\n"); 1373 #endif 1374 Tx->next = sc->Free_Tx; 1375 sc->Free_Tx = Tx; 1376 return; 1377 } 1378 1379 static void 1380 tl_ifwatchdog(ifp) 1381 struct ifnet *ifp; 1382 { 1383 tl_softc_t *sc = ifp->if_softc; 1384 1385 if ((ifp->if_flags & IFF_RUNNING) == 0) 1386 return; 1387 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1388 ifp->if_oerrors++; 1389 tl_init(sc); 1390 } 1391 1392 static int 1393 tl_mediachange(ifp) 1394 struct ifnet *ifp; 1395 { 1396 1397 if (ifp->if_flags & IFF_UP) 1398 tl_init(ifp->if_softc); 1399 return (0); 1400 } 1401 1402 static void 1403 tl_mediastatus(ifp, ifmr) 1404 struct ifnet *ifp; 1405 struct ifmediareq *ifmr; 1406 { 1407 tl_softc_t *sc = ifp->if_softc; 1408 1409 mii_pollstat(&sc->tl_mii); 1410 ifmr->ifm_active = sc->tl_mii.mii_media_active; 1411 ifmr->ifm_status = sc->tl_mii.mii_media_status; 1412 } 1413 1414 static int tl_add_RxBuff(Rx, oldm) 1415 struct Rx_list *Rx; 1416 struct mbuf *oldm; 1417 { 1418 struct mbuf *m; 1419 1420 MGETHDR(m, M_DONTWAIT, MT_DATA); 1421 if (m != NULL) { 1422 MCLGET(m, M_DONTWAIT); 1423 if ((m->m_flags & M_EXT) == 0) { 1424 m_freem(m); 1425 if (oldm == NULL) 1426 return 0; 1427 m = oldm; 1428 m->m_data = m->m_ext.ext_buf; 1429 } 1430 } else { 1431 if (oldm == NULL) 1432 return 0; 1433 m = oldm; 1434 m->m_data = m->m_ext.ext_buf; 1435 } 1436 /* 1437 * Move the data pointer up so that the incoming data packet 1438 * will be 32-bit aligned. 1439 */ 1440 m->m_data += 2; 1441 1442 /* (re)init the Rx_list struct */ 1443 1444 Rx->m = m; 1445 Rx->hw_list.stat = ((MCLBYTES -2) << 16) | 0x3000; 1446 Rx->hw_list.seg.data_count = (MCLBYTES -2); 1447 Rx->hw_list.seg.data_addr = vtophys((vaddr_t)m->m_data); 1448 return (m != oldm); 1449 } 1450 1451 static void tl_ticks(v) 1452 void *v; 1453 { 1454 tl_softc_t *sc = v; 1455 1456 tl_read_stats(sc); 1457 1458 /* Tick the MII. */ 1459 mii_tick(&sc->tl_mii); 1460 1461 if (sc->opkt > 0) { 1462 if (sc->oerr_exesscoll > sc->opkt / 100) { 1463 /* exess collisions */ 1464 if (sc->tl_flags & TL_IFACT) /* only print once */ 1465 printf("%s: no carrier\n", 1466 sc->sc_dev.dv_xname); 1467 sc->tl_flags &= ~TL_IFACT; 1468 } else 1469 sc->tl_flags |= TL_IFACT; 1470 sc->oerr_exesscoll = sc->opkt = 0; 1471 sc->tl_lasttx = 0; 1472 } else { 1473 sc->tl_lasttx++; 1474 if (sc->tl_lasttx >= TL_IDLETIME) { 1475 /* 1476 * No TX activity in the last TL_IDLETIME seconds. 1477 * sends a LLC Class1 TEST pkt 1478 */ 1479 struct mbuf *m; 1480 int s; 1481 MGETHDR(m, M_DONTWAIT, MT_DATA); 1482 if (m != NULL) { 1483 #ifdef TLDEBUG 1484 printf("tl_ticks: sending LLC test pkt\n"); 1485 #endif 1486 bcopy(sc->tl_enaddr, 1487 mtod(m, struct ether_header *)->ether_dhost, 1488 6); 1489 bcopy(sc->tl_enaddr, 1490 mtod(m, struct ether_header *)->ether_shost, 1491 6); 1492 mtod(m, struct ether_header *)->ether_type = 1493 htons(3); 1494 mtod(m, unsigned char *)[14] = 0; 1495 mtod(m, unsigned char *)[15] = 0; 1496 mtod(m, unsigned char *)[16] = 0xE3; 1497 /* LLC Class1 TEST (no poll) */ 1498 m->m_len = m->m_pkthdr.len = 1499 sizeof(struct ether_header) + 3; 1500 s = splnet(); 1501 IF_PREPEND(&sc->tl_if.if_snd, m); 1502 tl_ifstart(&sc->tl_if); 1503 splx(s); 1504 } 1505 } 1506 } 1507 1508 /* read statistics every seconds */ 1509 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 1510 } 1511 1512 static void 1513 tl_read_stats(sc) 1514 tl_softc_t *sc; 1515 { 1516 u_int32_t reg; 1517 int ierr_overr; 1518 int ierr_code; 1519 int ierr_crc; 1520 int oerr_underr; 1521 int oerr_deffered; 1522 int oerr_coll; 1523 int oerr_multicoll; 1524 int oerr_exesscoll; 1525 int oerr_latecoll; 1526 int oerr_carrloss; 1527 struct ifnet *ifp = &sc->tl_if; 1528 1529 reg = tl_intreg_read(sc, TL_INT_STATS_TX); 1530 ifp->if_opackets += reg & 0x00ffffff; 1531 oerr_underr = reg >> 24; 1532 1533 reg = tl_intreg_read(sc, TL_INT_STATS_RX); 1534 ifp->if_ipackets += reg & 0x00ffffff; 1535 ierr_overr = reg >> 24; 1536 1537 reg = tl_intreg_read(sc, TL_INT_STATS_FERR); 1538 ierr_crc = (reg & TL_FERR_CRC) >> 16; 1539 ierr_code = (reg & TL_FERR_CODE) >> 24; 1540 oerr_deffered = (reg & TL_FERR_DEF); 1541 1542 reg = tl_intreg_read(sc, TL_INT_STATS_COLL); 1543 oerr_multicoll = (reg & TL_COL_MULTI); 1544 oerr_coll = (reg & TL_COL_SINGLE) >> 16; 1545 1546 reg = tl_intreg_read(sc, TL_INT_LERR); 1547 oerr_exesscoll = (reg & TL_LERR_ECOLL); 1548 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8; 1549 oerr_carrloss = (reg & TL_LERR_CL) >> 16; 1550 1551 1552 sc->stats_exesscoll += oerr_exesscoll; 1553 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll + 1554 oerr_carrloss; 1555 ifp->if_collisions += oerr_coll + oerr_multicoll; 1556 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc; 1557 1558 if (ierr_overr) 1559 printf("%s: receiver ring buffer overrun\n", 1560 sc->sc_dev.dv_xname); 1561 if (oerr_underr) 1562 printf("%s: transmit buffer underrun\n", 1563 sc->sc_dev.dv_xname); 1564 #ifdef TL_PRIV_STATS 1565 sc->ierr_overr += ierr_overr; 1566 sc->ierr_code += ierr_code; 1567 sc->ierr_crc += ierr_crc; 1568 sc->oerr_underr += oerr_underr; 1569 sc->oerr_deffered += oerr_deffered; 1570 sc->oerr_coll += oerr_coll; 1571 sc->oerr_multicoll += oerr_multicoll; 1572 sc->oerr_exesscoll += oerr_exesscoll; 1573 sc->oerr_latecoll += oerr_latecoll; 1574 sc->oerr_carrloss += oerr_carrloss; 1575 #endif 1576 } 1577 1578 static void tl_addr_filter(sc) 1579 tl_softc_t *sc; 1580 { 1581 struct ether_multistep step; 1582 struct ether_multi *enm; 1583 u_int32_t hash[2] = {0, 0}; 1584 int i; 1585 1586 sc->tl_if.if_flags &= ~IFF_ALLMULTI; 1587 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm); 1588 while (enm != NULL) { 1589 #ifdef TLDEBUG 1590 printf("tl_addr_filter: addrs %s %s\n", 1591 ether_sprintf(enm->enm_addrlo), 1592 ether_sprintf(enm->enm_addrhi)); 1593 #endif 1594 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1595 i = tl_multicast_hash(enm->enm_addrlo); 1596 hash[i/32] |= 1 << (i%32); 1597 } else { 1598 hash[0] = hash[1] = 0xffffffff; 1599 sc->tl_if.if_flags |= IFF_ALLMULTI; 1600 break; 1601 } 1602 ETHER_NEXT_MULTI(step, enm); 1603 } 1604 #ifdef TLDEBUG 1605 printf("tl_addr_filer: hash1 %x has2 %x\n", hash[0], hash[1]); 1606 #endif 1607 tl_intreg_write(sc, TL_INT_HASH1, hash[0]); 1608 tl_intreg_write(sc, TL_INT_HASH2, hash[1]); 1609 } 1610 1611 static int tl_multicast_hash(a) 1612 u_int8_t *a; 1613 { 1614 int hash; 1615 1616 #define DA(addr,bit) (addr[5 - (bit/8)] & (1 << bit%8)) 1617 #define xor8(a,b,c,d,e,f,g,h) (((a != 0) + (b != 0) + (c != 0) + (d != 0) + (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1618 1619 hash = xor8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1620 DA(a,36), DA(a,42)); 1621 hash |= xor8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1622 DA(a,37), DA(a,43)) << 1; 1623 hash |= xor8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1624 DA(a,38), DA(a,44)) << 2; 1625 hash |= xor8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1626 DA(a,39), DA(a,45)) << 3; 1627 hash |= xor8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1628 DA(a,40), DA(a,46)) << 4; 1629 hash |= xor8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1630 DA(a,41), DA(a,47)) << 5; 1631 1632 return hash; 1633 } 1634 1635 #if defined(TLDEBUG_RX) 1636 void 1637 ether_printheader(eh) 1638 struct ether_header *eh; 1639 { 1640 u_char *c = (char*)eh; 1641 int i; 1642 for (i=0; i<sizeof(struct ether_header); i++) 1643 printf("%x ", (u_int)c[i]); 1644 printf("\n"); 1645 } 1646 #endif 1647