1 /* $NetBSD: if_tl.c,v 1.46 2001/09/20 10:04:10 bouyer Exp $ */ 2 3 /* XXX ALTQ XXX */ 4 5 /* 6 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Manuel Bouyer. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Texas Instruments ThunderLAN ethernet controller 36 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A) 37 * available from www.ti.com 38 */ 39 40 #undef TLDEBUG 41 #define TL_PRIV_STATS 42 #undef TLDEBUG_RX 43 #undef TLDEBUG_TX 44 #undef TLDEBUG_ADDR 45 46 #include "opt_inet.h" 47 #include "opt_ns.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/mbuf.h> 52 #include <sys/protosw.h> 53 #include <sys/socket.h> 54 #include <sys/ioctl.h> 55 #include <sys/errno.h> 56 #include <sys/malloc.h> 57 #include <sys/kernel.h> 58 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 59 #include <sys/device.h> 60 61 #include <net/if.h> 62 #if defined(SIOCSIFMEDIA) 63 #include <net/if_media.h> 64 #endif 65 #include <net/if_types.h> 66 #include <net/if_dl.h> 67 #include <net/route.h> 68 #include <net/netisr.h> 69 70 #include "bpfilter.h" 71 #if NBPFILTER > 0 72 #include <net/bpf.h> 73 #include <net/bpfdesc.h> 74 #endif 75 76 #ifdef INET 77 #include <netinet/in.h> 78 #include <netinet/in_systm.h> 79 #include <netinet/in_var.h> 80 #include <netinet/ip.h> 81 #endif 82 83 #ifdef NS 84 #include <netns/ns.h> 85 #include <netns/ns_if.h> 86 #endif 87 88 #if defined(__NetBSD__) 89 #include <net/if_ether.h> 90 #include <uvm/uvm_extern.h> 91 #if defined(INET) 92 #include <netinet/if_inarp.h> 93 #endif 94 95 #include <machine/bus.h> 96 #include <machine/intr.h> 97 98 #include <dev/pci/pcireg.h> 99 #include <dev/pci/pcivar.h> 100 #include <dev/pci/pcidevs.h> 101 102 #include <dev/i2c/i2c_bus.h> 103 #include <dev/i2c/i2c_eeprom.h> 104 105 #include <dev/mii/mii.h> 106 #include <dev/mii/miivar.h> 107 108 #include <dev/mii/tlphyvar.h> 109 110 #include <dev/pci/if_tlregs.h> 111 #include <dev/pci/if_tlvar.h> 112 #endif /* __NetBSD__ */ 113 114 /* number of transmit/receive buffers */ 115 #ifndef TL_NBUF 116 #define TL_NBUF 10 117 #endif 118 119 static int tl_pci_match __P((struct device *, struct cfdata *, void *)); 120 static void tl_pci_attach __P((struct device *, struct device *, void *)); 121 static int tl_intr __P((void *)); 122 123 static int tl_ifioctl __P((struct ifnet *, ioctl_cmd_t, caddr_t)); 124 static int tl_mediachange __P((struct ifnet *)); 125 static void tl_mediastatus __P((struct ifnet *, struct ifmediareq *)); 126 static void tl_ifwatchdog __P((struct ifnet *)); 127 static void tl_shutdown __P((void*)); 128 129 static void tl_ifstart __P((struct ifnet *)); 130 static void tl_reset __P((tl_softc_t*)); 131 static int tl_init __P((struct ifnet *)); 132 static void tl_stop __P((struct ifnet *, int)); 133 static void tl_restart __P((void *)); 134 static int tl_add_RxBuff __P((tl_softc_t*, struct Rx_list*, struct mbuf*)); 135 static void tl_read_stats __P((tl_softc_t*)); 136 static void tl_ticks __P((void*)); 137 static int tl_multicast_hash __P((u_int8_t*)); 138 static void tl_addr_filter __P((tl_softc_t*)); 139 140 static u_int32_t tl_intreg_read __P((tl_softc_t*, u_int32_t)); 141 static void tl_intreg_write __P((tl_softc_t*, u_int32_t, u_int32_t)); 142 static u_int8_t tl_intreg_read_byte __P((tl_softc_t*, u_int32_t)); 143 static void tl_intreg_write_byte __P((tl_softc_t*, u_int32_t, u_int8_t)); 144 145 void tl_mii_sync __P((struct tl_softc *)); 146 void tl_mii_sendbits __P((struct tl_softc *, u_int32_t, int)); 147 148 149 #if defined(TLDEBUG_RX) 150 static void ether_printheader __P((struct ether_header*)); 151 #endif 152 153 int tl_mii_read __P((struct device *, int, int)); 154 void tl_mii_write __P((struct device *, int, int, int)); 155 156 void tl_statchg __P((struct device *)); 157 158 void tl_i2c_set __P((void*, u_int8_t)); 159 void tl_i2c_clr __P((void*, u_int8_t)); 160 int tl_i2c_read __P((void*, u_int8_t)); 161 162 static __inline void netsio_clr __P((tl_softc_t*, u_int8_t)); 163 static __inline void netsio_set __P((tl_softc_t*, u_int8_t)); 164 static __inline u_int8_t netsio_read __P((tl_softc_t*, u_int8_t)); 165 static __inline void netsio_clr(sc, bits) 166 tl_softc_t* sc; 167 u_int8_t bits; 168 { 169 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 170 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits)); 171 } 172 static __inline void netsio_set(sc, bits) 173 tl_softc_t* sc; 174 u_int8_t bits; 175 { 176 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 177 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits); 178 } 179 static __inline u_int8_t netsio_read(sc, bits) 180 tl_softc_t* sc; 181 u_int8_t bits; 182 { 183 return (tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits); 184 } 185 186 struct cfattach tl_ca = { 187 sizeof(tl_softc_t), tl_pci_match, tl_pci_attach 188 }; 189 190 const struct tl_product_desc tl_compaq_products[] = { 191 { PCI_PRODUCT_COMPAQ_N100TX, TLPHY_MEDIA_NO_10_T, 192 "Compaq Netelligent 10/100 TX" }, 193 { PCI_PRODUCT_COMPAQ_N10T, TLPHY_MEDIA_10_5, 194 "Compaq Netelligent 10 T" }, 195 { PCI_PRODUCT_COMPAQ_IntNF3P, TLPHY_MEDIA_10_2, 196 "Compaq Integrated NetFlex 3/P" }, 197 { PCI_PRODUCT_COMPAQ_IntPL100TX, TLPHY_MEDIA_10_2|TLPHY_MEDIA_NO_10_T, 198 "Compaq ProLiant Integrated Netelligent 10/100 TX" }, 199 { PCI_PRODUCT_COMPAQ_DPNet100TX, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 200 "Compaq Dual Port Netelligent 10/100 TX" }, 201 { PCI_PRODUCT_COMPAQ_DP4000, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 202 "Compaq Deskpro 4000 5233MMX" }, 203 { PCI_PRODUCT_COMPAQ_NF3P_BNC, TLPHY_MEDIA_10_2, 204 "Compaq NetFlex 3/P w/ BNC" }, 205 { PCI_PRODUCT_COMPAQ_NF3P, TLPHY_MEDIA_10_5, 206 "Compaq NetFlex 3/P" }, 207 { 0, 0, NULL }, 208 }; 209 210 const struct tl_product_desc tl_ti_products[] = { 211 /* 212 * Built-in Ethernet on the TI TravelMate 5000 213 * docking station; better product description? 214 */ 215 { PCI_PRODUCT_TI_TLAN, 0, 216 "Texas Instruments ThunderLAN" }, 217 { 0, 0, NULL }, 218 }; 219 220 struct tl_vendor_desc { 221 u_int32_t tv_vendor; 222 const struct tl_product_desc *tv_products; 223 }; 224 225 const struct tl_vendor_desc tl_vendors[] = { 226 { PCI_VENDOR_COMPAQ, tl_compaq_products }, 227 { PCI_VENDOR_TI, tl_ti_products }, 228 { 0, NULL }, 229 }; 230 231 const struct tl_product_desc *tl_lookup_product __P((u_int32_t)); 232 233 const struct tl_product_desc * 234 tl_lookup_product(id) 235 u_int32_t id; 236 { 237 const struct tl_product_desc *tp; 238 const struct tl_vendor_desc *tv; 239 240 for (tv = tl_vendors; tv->tv_products != NULL; tv++) 241 if (PCI_VENDOR(id) == tv->tv_vendor) 242 break; 243 244 if ((tp = tv->tv_products) == NULL) 245 return (NULL); 246 247 for (; tp->tp_desc != NULL; tp++) 248 if (PCI_PRODUCT(id) == tp->tp_product) 249 break; 250 251 if (tp->tp_desc == NULL) 252 return (NULL); 253 254 return (tp); 255 } 256 257 static int 258 tl_pci_match(parent, match, aux) 259 struct device *parent; 260 struct cfdata *match; 261 void *aux; 262 { 263 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 264 265 if (tl_lookup_product(pa->pa_id) != NULL) 266 return (1); 267 268 return (0); 269 } 270 271 static void 272 tl_pci_attach(parent, self, aux) 273 struct device * parent; 274 struct device * self; 275 void * aux; 276 { 277 tl_softc_t *sc = (tl_softc_t *)self; 278 struct pci_attach_args * const pa = (struct pci_attach_args *) aux; 279 const struct tl_product_desc *tp; 280 struct ifnet * const ifp = &sc->tl_if; 281 bus_space_tag_t iot, memt; 282 bus_space_handle_t ioh, memh; 283 pci_intr_handle_t intrhandle; 284 const char *intrstr; 285 int i, tmp, ioh_valid, memh_valid; 286 int reg_io, reg_mem; 287 pcireg_t reg10, reg14; 288 pcireg_t csr; 289 290 printf("\n"); 291 292 callout_init(&sc->tl_tick_ch); 293 callout_init(&sc->tl_restart_ch); 294 295 tp = tl_lookup_product(pa->pa_id); 296 if (tp == NULL) 297 panic("tl_pci_attach: impossible"); 298 sc->tl_product = tp; 299 300 /* 301 * Map the card space. Fisrt we have to find the I/O and MEM 302 * registers. I/O is supposed to be at 0x10, MEM at 0x14, 303 * but some boards (Compaq Netflex 3/P PCI) seem to have it reversed. 304 * The ThunderLAN manual is not consistent about this either (there 305 * are both cases in code examples). 306 */ 307 reg10 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x10); 308 reg14 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x14); 309 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_IO) 310 reg_io = 0x10; 311 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_IO) 312 reg_io = 0x14; 313 else 314 reg_io = 0; 315 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_MEM) 316 reg_mem = 0x10; 317 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_MEM) 318 reg_mem = 0x14; 319 else 320 reg_mem = 0; 321 322 if (reg_io != 0) 323 ioh_valid = (pci_mapreg_map(pa, reg_io, PCI_MAPREG_TYPE_IO, 324 0, &iot, &ioh, NULL, NULL) == 0); 325 else 326 ioh_valid = 0; 327 if (reg_mem != 0) 328 memh_valid = (pci_mapreg_map(pa, PCI_CBMA, 329 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 330 0, &memt, &memh, NULL, NULL) == 0); 331 else 332 memh_valid = 0; 333 334 if (ioh_valid) { 335 sc->tl_bustag = iot; 336 sc->tl_bushandle = ioh; 337 } else if (memh_valid) { 338 sc->tl_bustag = memt; 339 sc->tl_bushandle = memh; 340 } else { 341 printf("%s: unable to map device registers\n", 342 sc->sc_dev.dv_xname); 343 return; 344 } 345 sc->tl_dmatag = pa->pa_dmat; 346 347 /* Enable the device. */ 348 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 349 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 350 csr | PCI_COMMAND_MASTER_ENABLE); 351 352 printf("%s: %s\n", sc->sc_dev.dv_xname, tp->tp_desc); 353 354 tl_reset(sc); 355 356 /* fill in the i2c struct */ 357 sc->i2cbus.adapter_softc = sc; 358 sc->i2cbus.set_bit = tl_i2c_set; 359 sc->i2cbus.clr_bit = tl_i2c_clr; 360 sc->i2cbus.read_bit = tl_i2c_read; 361 362 #ifdef TLDEBUG 363 printf("default values of INTreg: 0x%x\n", 364 tl_intreg_read(sc, TL_INT_Defaults)); 365 #endif 366 367 /* read mac addr */ 368 for (i=0; i<ETHER_ADDR_LEN; i++) { 369 tmp = i2c_eeprom_read(&sc->i2cbus, 0x83 + i); 370 if (tmp < 0) { 371 printf("%s: error reading Ethernet adress\n", 372 sc->sc_dev.dv_xname); 373 return; 374 } else { 375 sc->tl_enaddr[i] = tmp; 376 } 377 } 378 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 379 ether_sprintf(sc->tl_enaddr)); 380 381 /* Map and establish interrupts */ 382 if (pci_intr_map(pa, &intrhandle)) { 383 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 384 return; 385 } 386 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 387 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 388 tl_intr, sc); 389 if (sc->tl_ih == NULL) { 390 printf("%s: couldn't establish interrupt", 391 sc->sc_dev.dv_xname); 392 if (intrstr != NULL) 393 printf(" at %s", intrstr); 394 printf("\n"); 395 return; 396 } 397 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 398 399 /* init these pointers, so that tl_shutdown won't try to read them */ 400 sc->Rx_list = NULL; 401 sc->Tx_list = NULL; 402 403 /* allocate DMA-safe memory for control structs */ 404 if (bus_dmamem_alloc(sc->tl_dmatag, 405 PAGE_SIZE, 0, PAGE_SIZE, 406 &sc->ctrl_segs, 1, &sc->ctrl_nsegs, BUS_DMA_NOWAIT) != 0 || 407 bus_dmamem_map(sc->tl_dmatag, &sc->ctrl_segs, 408 sc->ctrl_nsegs, PAGE_SIZE, (caddr_t*)&sc->ctrl, 409 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0) { 410 printf("%s: can't allocate DMA memory for lists\n", 411 sc->sc_dev.dv_xname); 412 return; 413 } 414 /* 415 * Add shutdown hook so that DMA is disabled prior to reboot. Not 416 * doing do could allow DMA to corrupt kernel memory during the 417 * reboot before the driver initializes. 418 */ 419 (void) shutdownhook_establish(tl_shutdown, ifp); 420 421 /* 422 * Initialize our media structures and probe the MII. 423 * 424 * Note that we don't care about the media instance. We 425 * are expecting to have multiple PHYs on the 10/100 cards, 426 * and on those cards we exclude the internal PHY from providing 427 * 10baseT. By ignoring the instance, it allows us to not have 428 * to specify it on the command line when switching media. 429 */ 430 sc->tl_mii.mii_ifp = ifp; 431 sc->tl_mii.mii_readreg = tl_mii_read; 432 sc->tl_mii.mii_writereg = tl_mii_write; 433 sc->tl_mii.mii_statchg = tl_statchg; 434 ifmedia_init(&sc->tl_mii.mii_media, IFM_IMASK, tl_mediachange, 435 tl_mediastatus); 436 mii_attach(self, &sc->tl_mii, 0xffffffff, MII_PHY_ANY, 437 MII_OFFSET_ANY, 0); 438 if (LIST_FIRST(&sc->tl_mii.mii_phys) == NULL) { 439 ifmedia_add(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 440 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE); 441 } else 442 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_AUTO); 443 444 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 445 sc->tl_if.if_softc = sc; 446 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 447 ifp->if_ioctl = tl_ifioctl; 448 ifp->if_start = tl_ifstart; 449 ifp->if_watchdog = tl_ifwatchdog; 450 ifp->if_init = tl_init; 451 ifp->if_stop = tl_stop; 452 ifp->if_timer = 0; 453 if_attach(ifp); 454 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr); 455 } 456 457 static void 458 tl_reset(sc) 459 tl_softc_t *sc; 460 { 461 int i; 462 463 /* read stats */ 464 if (sc->tl_if.if_flags & IFF_RUNNING) { 465 callout_stop(&sc->tl_tick_ch); 466 tl_read_stats(sc); 467 } 468 /* Reset adapter */ 469 TL_HR_WRITE(sc, TL_HOST_CMD, 470 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst); 471 DELAY(100000); 472 /* Disable interrupts */ 473 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 474 /* setup aregs & hash */ 475 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 476 tl_intreg_write(sc, i, 0); 477 #ifdef TLDEBUG_ADDR 478 printf("Areg & hash registers: \n"); 479 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 480 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 481 #endif 482 /* Setup NetConfig */ 483 tl_intreg_write(sc, TL_INT_NetConfig, 484 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN); 485 /* Bsize: accept default */ 486 /* TX commit in Acommit: accept default */ 487 /* Load Ld_tmr and Ld_thr */ 488 /* Ld_tmr = 3 */ 489 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr); 490 /* Ld_thr = 0 */ 491 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr); 492 /* Unreset MII */ 493 netsio_set(sc, TL_NETSIO_NMRST); 494 DELAY(100000); 495 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 496 } 497 498 static void tl_shutdown(v) 499 void *v; 500 { 501 tl_stop(v, 1); 502 } 503 504 static void tl_stop(ifp, disable) 505 struct ifnet *ifp; 506 int disable; 507 { 508 tl_softc_t *sc = ifp->if_softc; 509 struct Tx_list *Tx; 510 int i; 511 512 if ((ifp->if_flags & IFF_RUNNING) == 0) 513 return; 514 /* disable interrupts */ 515 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 516 /* stop TX and RX channels */ 517 TL_HR_WRITE(sc, TL_HOST_CMD, 518 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes); 519 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP); 520 DELAY(100000); 521 522 /* stop statistics reading loop, read stats */ 523 callout_stop(&sc->tl_tick_ch); 524 tl_read_stats(sc); 525 526 /* Down the MII. */ 527 mii_down(&sc->tl_mii); 528 529 /* deallocate memory allocations */ 530 if (sc->Rx_list) { 531 for (i=0; i< TL_NBUF; i++) { 532 if (sc->Rx_list[i].m) { 533 bus_dmamap_unload(sc->tl_dmatag, 534 sc->Rx_list[i].m_dmamap); 535 m_freem(sc->Rx_list[i].m); 536 } 537 bus_dmamap_destroy(sc->tl_dmatag, 538 sc->Rx_list[i].m_dmamap); 539 sc->Rx_list[i].m = NULL; 540 } 541 free(sc->Rx_list, M_DEVBUF); 542 sc->Rx_list = NULL; 543 bus_dmamap_unload(sc->tl_dmatag, sc->Rx_dmamap); 544 bus_dmamap_destroy(sc->tl_dmatag, sc->Rx_dmamap); 545 sc->hw_Rx_list = NULL; 546 while ((Tx = sc->active_Tx) != NULL) { 547 Tx->hw_list->stat = 0; 548 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 549 bus_dmamap_destroy(sc->tl_dmatag, Tx->m_dmamap); 550 m_freem(Tx->m); 551 sc->active_Tx = Tx->next; 552 Tx->next = sc->Free_Tx; 553 sc->Free_Tx = Tx; 554 } 555 sc->last_Tx = NULL; 556 free(sc->Tx_list, M_DEVBUF); 557 sc->Tx_list = NULL; 558 bus_dmamap_unload(sc->tl_dmatag, sc->Tx_dmamap); 559 bus_dmamap_destroy(sc->tl_dmatag, sc->Tx_dmamap); 560 sc->hw_Tx_list = NULL; 561 } 562 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 563 ifp->if_timer = 0; 564 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 565 } 566 567 static void tl_restart(v) 568 void *v; 569 { 570 tl_init(v); 571 } 572 573 static int tl_init(ifp) 574 struct ifnet *ifp; 575 { 576 tl_softc_t *sc = ifp->if_softc; 577 int i, s, error; 578 char *errstring; 579 char *nullbuf; 580 581 s = splnet(); 582 /* cancel any pending IO */ 583 tl_stop(ifp, 1); 584 tl_reset(sc); 585 if ((sc->tl_if.if_flags & IFF_UP) == 0) { 586 splx(s); 587 return 0; 588 } 589 /* Set various register to reasonable value */ 590 /* setup NetCmd in promisc mode if needed */ 591 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0; 592 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 593 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i); 594 /* Max receive size : MCLBYTES */ 595 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff); 596 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH, 597 (MCLBYTES >> 8) & 0xff); 598 599 /* init MAC addr */ 600 for (i = 0; i < ETHER_ADDR_LEN; i++) 601 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]); 602 /* add multicast filters */ 603 tl_addr_filter(sc); 604 #ifdef TLDEBUG_ADDR 605 printf("Wrote Mac addr, Areg & hash registers are now: \n"); 606 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 607 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 608 #endif 609 610 /* Pre-allocate receivers mbuf, make the lists */ 611 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF, 612 M_NOWAIT); 613 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF, 614 M_NOWAIT); 615 if (sc->Rx_list == NULL || sc->Tx_list == NULL) { 616 errstring = "out of memory for lists"; 617 error = ENOMEM; 618 goto bad; 619 } 620 memset(sc->Rx_list, 0, sizeof(struct Rx_list) * TL_NBUF); 621 memset(sc->Tx_list, 0, sizeof(struct Tx_list) * TL_NBUF); 622 error = bus_dmamap_create(sc->tl_dmatag, 623 sizeof(struct tl_Rx_list) * TL_NBUF, 1, 624 sizeof(struct tl_Rx_list) * TL_NBUF, 0, BUS_DMA_WAITOK, 625 &sc->Rx_dmamap); 626 if (error == 0) 627 error = bus_dmamap_create(sc->tl_dmatag, 628 sizeof(struct tl_Tx_list) * TL_NBUF, 1, 629 sizeof(struct tl_Tx_list) * TL_NBUF, 0, BUS_DMA_WAITOK, 630 &sc->Tx_dmamap); 631 if (error == 0) 632 error = bus_dmamap_create(sc->tl_dmatag, ETHER_MIN_TX, 1, 633 ETHER_MIN_TX, 0, BUS_DMA_WAITOK, 634 &sc->null_dmamap); 635 if (error) { 636 errstring = "can't allocate DMA maps for lists"; 637 goto bad; 638 } 639 memset(sc->ctrl, 0, PAGE_SIZE); 640 sc->hw_Rx_list = (void *)sc->ctrl; 641 sc->hw_Tx_list = 642 (void *)(sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF); 643 nullbuf = sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF + 644 sizeof(struct tl_Tx_list) * TL_NBUF; 645 error = bus_dmamap_load(sc->tl_dmatag, sc->Rx_dmamap, 646 sc->hw_Rx_list, sizeof(struct tl_Rx_list) * TL_NBUF, NULL, 647 BUS_DMA_WAITOK); 648 if (error == 0) 649 error = bus_dmamap_load(sc->tl_dmatag, sc->Tx_dmamap, 650 sc->hw_Tx_list, sizeof(struct tl_Tx_list) * TL_NBUF, NULL, 651 BUS_DMA_WAITOK); 652 if (error == 0) 653 error = bus_dmamap_load(sc->tl_dmatag, sc->null_dmamap, 654 nullbuf, ETHER_MIN_TX, NULL, BUS_DMA_WAITOK); 655 if (error) { 656 errstring = "can't DMA map DMA memory for lists"; 657 goto bad; 658 } 659 for (i=0; i< TL_NBUF; i++) { 660 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 661 1, MCLBYTES, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 662 &sc->Rx_list[i].m_dmamap); 663 if (error == 0) { 664 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 665 TL_NSEG, MCLBYTES, 0, 666 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 667 &sc->Tx_list[i].m_dmamap); 668 } 669 if (error) { 670 errstring = "can't allocate DMA maps for mbufs"; 671 goto bad; 672 } 673 sc->Rx_list[i].hw_list = &sc->hw_Rx_list[i]; 674 sc->Rx_list[i].hw_listaddr = sc->Rx_dmamap->dm_segs[0].ds_addr 675 + sizeof(struct tl_Rx_list) * i; 676 sc->Tx_list[i].hw_list = &sc->hw_Tx_list[i]; 677 sc->Tx_list[i].hw_listaddr = sc->Tx_dmamap->dm_segs[0].ds_addr 678 + sizeof(struct tl_Tx_list) * i; 679 if (tl_add_RxBuff(sc, &sc->Rx_list[i], NULL) == 0) { 680 errstring = "out of mbuf for receive list"; 681 error = ENOMEM; 682 goto bad; 683 } 684 if (i > 0) { /* chain the list */ 685 sc->Rx_list[i-1].next = &sc->Rx_list[i]; 686 sc->hw_Rx_list[i-1].fwd = 687 htole32(sc->Rx_list[i].hw_listaddr); 688 sc->Tx_list[i-1].next = &sc->Tx_list[i]; 689 } 690 } 691 sc->hw_Rx_list[TL_NBUF-1].fwd = 0; 692 sc->Rx_list[TL_NBUF-1].next = NULL; 693 sc->hw_Tx_list[TL_NBUF-1].fwd = 0; 694 sc->Tx_list[TL_NBUF-1].next = NULL; 695 696 sc->active_Rx = &sc->Rx_list[0]; 697 sc->last_Rx = &sc->Rx_list[TL_NBUF-1]; 698 sc->active_Tx = sc->last_Tx = NULL; 699 sc->Free_Tx = &sc->Tx_list[0]; 700 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 701 sizeof(struct tl_Rx_list) * TL_NBUF, 702 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 703 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 704 sizeof(struct tl_Tx_list) * TL_NBUF, 705 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 706 bus_dmamap_sync(sc->tl_dmatag, sc->null_dmamap, 0, ETHER_MIN_TX, 707 BUS_DMASYNC_PREWRITE); 708 709 /* set media */ 710 mii_mediachg(&sc->tl_mii); 711 712 /* start ticks calls */ 713 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 714 /* write adress of Rx list and enable interrupts */ 715 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->Rx_list[0].hw_listaddr); 716 TL_HR_WRITE(sc, TL_HOST_CMD, 717 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn); 718 sc->tl_if.if_flags |= IFF_RUNNING; 719 sc->tl_if.if_flags &= ~IFF_OACTIVE; 720 return 0; 721 bad: 722 printf("%s: %s\n", sc->sc_dev.dv_xname, errstring); 723 splx(s); 724 return error; 725 } 726 727 728 static u_int32_t 729 tl_intreg_read(sc, reg) 730 tl_softc_t *sc; 731 u_int32_t reg; 732 { 733 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 734 return TL_HR_READ(sc, TL_HOST_DIO_DATA); 735 } 736 737 static u_int8_t 738 tl_intreg_read_byte(sc, reg) 739 tl_softc_t *sc; 740 u_int32_t reg; 741 { 742 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 743 (reg & (~0x07)) & TL_HOST_DIOADR_MASK); 744 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07)); 745 } 746 747 static void 748 tl_intreg_write(sc, reg, val) 749 tl_softc_t *sc; 750 u_int32_t reg; 751 u_int32_t val; 752 { 753 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 754 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val); 755 } 756 757 static void 758 tl_intreg_write_byte(sc, reg, val) 759 tl_softc_t *sc; 760 u_int32_t reg; 761 u_int8_t val; 762 { 763 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 764 (reg & (~0x03)) & TL_HOST_DIOADR_MASK); 765 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val); 766 } 767 768 void 769 tl_mii_sync(sc) 770 struct tl_softc *sc; 771 { 772 int i; 773 774 netsio_clr(sc, TL_NETSIO_MTXEN); 775 for (i = 0; i < 32; i++) { 776 netsio_clr(sc, TL_NETSIO_MCLK); 777 netsio_set(sc, TL_NETSIO_MCLK); 778 } 779 } 780 781 void 782 tl_mii_sendbits(sc, data, nbits) 783 struct tl_softc *sc; 784 u_int32_t data; 785 int nbits; 786 { 787 int i; 788 789 netsio_set(sc, TL_NETSIO_MTXEN); 790 for (i = 1 << (nbits - 1); i; i = i >> 1) { 791 netsio_clr(sc, TL_NETSIO_MCLK); 792 netsio_read(sc, TL_NETSIO_MCLK); 793 if (data & i) 794 netsio_set(sc, TL_NETSIO_MDATA); 795 else 796 netsio_clr(sc, TL_NETSIO_MDATA); 797 netsio_set(sc, TL_NETSIO_MCLK); 798 netsio_read(sc, TL_NETSIO_MCLK); 799 } 800 } 801 802 int 803 tl_mii_read(self, phy, reg) 804 struct device *self; 805 int phy, reg; 806 { 807 struct tl_softc *sc = (struct tl_softc *)self; 808 int val = 0, i, err; 809 810 /* 811 * Read the PHY register by manually driving the MII control lines. 812 */ 813 814 tl_mii_sync(sc); 815 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 816 tl_mii_sendbits(sc, MII_COMMAND_READ, 2); 817 tl_mii_sendbits(sc, phy, 5); 818 tl_mii_sendbits(sc, reg, 5); 819 820 netsio_clr(sc, TL_NETSIO_MTXEN); 821 netsio_clr(sc, TL_NETSIO_MCLK); 822 netsio_set(sc, TL_NETSIO_MCLK); 823 netsio_clr(sc, TL_NETSIO_MCLK); 824 825 err = netsio_read(sc, TL_NETSIO_MDATA); 826 netsio_set(sc, TL_NETSIO_MCLK); 827 828 /* Even if an error occurs, must still clock out the cycle. */ 829 for (i = 0; i < 16; i++) { 830 val <<= 1; 831 netsio_clr(sc, TL_NETSIO_MCLK); 832 if (err == 0 && netsio_read(sc, TL_NETSIO_MDATA)) 833 val |= 1; 834 netsio_set(sc, TL_NETSIO_MCLK); 835 } 836 netsio_clr(sc, TL_NETSIO_MCLK); 837 netsio_set(sc, TL_NETSIO_MCLK); 838 839 return (err ? 0 : val); 840 } 841 842 void 843 tl_mii_write(self, phy, reg, val) 844 struct device *self; 845 int phy, reg, val; 846 { 847 struct tl_softc *sc = (struct tl_softc *)self; 848 849 /* 850 * Write the PHY register by manually driving the MII control lines. 851 */ 852 853 tl_mii_sync(sc); 854 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 855 tl_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 856 tl_mii_sendbits(sc, phy, 5); 857 tl_mii_sendbits(sc, reg, 5); 858 tl_mii_sendbits(sc, MII_COMMAND_ACK, 2); 859 tl_mii_sendbits(sc, val, 16); 860 861 netsio_clr(sc, TL_NETSIO_MCLK); 862 netsio_set(sc, TL_NETSIO_MCLK); 863 } 864 865 void 866 tl_statchg(self) 867 struct device *self; 868 { 869 tl_softc_t *sc = (struct tl_softc *)self; 870 u_int32_t reg; 871 872 #ifdef TLDEBUG 873 printf("tl_statchg, media %x\n", sc->tl_ifmedia.ifm_media); 874 #endif 875 876 /* 877 * We must keep the ThunderLAN and the PHY in sync as 878 * to the status of full-duplex! 879 */ 880 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 881 if (sc->tl_mii.mii_media_active & IFM_FDX) 882 reg |= TL_NETCOMMAND_DUPLEX; 883 else 884 reg &= ~TL_NETCOMMAND_DUPLEX; 885 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 886 } 887 888 void tl_i2c_set(v, bit) 889 void *v; 890 u_int8_t bit; 891 { 892 tl_softc_t *sc = v; 893 894 switch (bit) { 895 case I2C_DATA: 896 netsio_set(sc, TL_NETSIO_EDATA); 897 break; 898 case I2C_CLOCK: 899 netsio_set(sc, TL_NETSIO_ECLOCK); 900 break; 901 case I2C_TXEN: 902 netsio_set(sc, TL_NETSIO_ETXEN); 903 break; 904 default: 905 printf("tl_i2c_set: unknown bit %d\n", bit); 906 } 907 return; 908 } 909 910 void tl_i2c_clr(v, bit) 911 void *v; 912 u_int8_t bit; 913 { 914 tl_softc_t *sc = v; 915 916 switch (bit) { 917 case I2C_DATA: 918 netsio_clr(sc, TL_NETSIO_EDATA); 919 break; 920 case I2C_CLOCK: 921 netsio_clr(sc, TL_NETSIO_ECLOCK); 922 break; 923 case I2C_TXEN: 924 netsio_clr(sc, TL_NETSIO_ETXEN); 925 break; 926 default: 927 printf("tl_i2c_clr: unknown bit %d\n", bit); 928 } 929 return; 930 } 931 932 int tl_i2c_read(v, bit) 933 void *v; 934 u_int8_t bit; 935 { 936 tl_softc_t *sc = v; 937 938 switch (bit) { 939 case I2C_DATA: 940 return netsio_read(sc, TL_NETSIO_EDATA); 941 break; 942 case I2C_CLOCK: 943 return netsio_read(sc, TL_NETSIO_ECLOCK); 944 break; 945 case I2C_TXEN: 946 return netsio_read(sc, TL_NETSIO_ETXEN); 947 break; 948 default: 949 printf("tl_i2c_read: unknown bit %d\n", bit); 950 return -1; 951 } 952 } 953 954 static int 955 tl_intr(v) 956 void *v; 957 { 958 tl_softc_t *sc = v; 959 struct ifnet *ifp = &sc->tl_if; 960 struct Rx_list *Rx; 961 struct Tx_list *Tx; 962 struct mbuf *m; 963 u_int32_t int_type, int_reg; 964 int ack = 0; 965 int size; 966 967 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR); 968 int_type = int_reg & TL_INTR_MASK; 969 if (int_type == 0) 970 return 0; 971 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX) 972 printf("%s: interrupt type %x, intr_reg %x\n", sc->sc_dev.dv_xname, 973 int_type, int_reg); 974 #endif 975 /* disable interrupts */ 976 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 977 switch(int_type & TL_INTR_MASK) { 978 case TL_INTR_RxEOF: 979 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 980 sizeof(struct tl_Rx_list) * TL_NBUF, 981 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 982 while(le32toh(sc->active_Rx->hw_list->stat) & 983 TL_RX_CSTAT_CPLT) { 984 /* dequeue and requeue at end of list */ 985 ack++; 986 Rx = sc->active_Rx; 987 sc->active_Rx = Rx->next; 988 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 989 MCLBYTES, BUS_DMASYNC_POSTREAD); 990 bus_dmamap_unload(sc->tl_dmatag, Rx->m_dmamap); 991 m = Rx->m; 992 size = le32toh(Rx->hw_list->stat) >> 16; 993 #ifdef TLDEBUG_RX 994 printf("tl_intr: RX list complete, Rx %p, size=%d\n", 995 Rx, size); 996 #endif 997 if (tl_add_RxBuff(sc, Rx, m ) == 0) { 998 /* 999 * No new mbuf, reuse the same. This means 1000 * that this packet 1001 * is lost 1002 */ 1003 m = NULL; 1004 #ifdef TL_PRIV_STATS 1005 sc->ierr_nomem++; 1006 #endif 1007 #ifdef TLDEBUG 1008 printf("%s: out of mbuf, lost input packet\n", 1009 sc->sc_dev.dv_xname); 1010 #endif 1011 } 1012 Rx->next = NULL; 1013 Rx->hw_list->fwd = 0; 1014 sc->last_Rx->hw_list->fwd = htole32(Rx->hw_listaddr); 1015 sc->last_Rx->next = Rx; 1016 sc->last_Rx = Rx; 1017 1018 /* deliver packet */ 1019 if (m) { 1020 if (size < sizeof(struct ether_header)) { 1021 m_freem(m); 1022 continue; 1023 } 1024 m->m_pkthdr.rcvif = ifp; 1025 m->m_pkthdr.len = m->m_len = size; 1026 #ifdef TLDEBUG_RX 1027 { struct ether_header *eh = 1028 mtod(m, struct ether_header *); 1029 printf("tl_intr: Rx packet:\n"); 1030 ether_printheader(eh); } 1031 #endif 1032 #if NBPFILTER > 0 1033 if (ifp->if_bpf) 1034 bpf_mtap(ifp->if_bpf, m); 1035 #endif /* NBPFILTER > 0 */ 1036 (*ifp->if_input)(ifp, m); 1037 } 1038 } 1039 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1040 sizeof(struct tl_Rx_list) * TL_NBUF, 1041 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1042 #ifdef TLDEBUG_RX 1043 printf("TL_INTR_RxEOF: ack %d\n", ack); 1044 #else 1045 if (ack == 0) { 1046 printf("%s: EOF intr without anything to read !\n", 1047 sc->sc_dev.dv_xname); 1048 tl_reset(sc); 1049 /* shedule reinit of the board */ 1050 callout_reset(&sc->tl_restart_ch, 1, tl_restart, sc); 1051 return(1); 1052 } 1053 #endif 1054 break; 1055 case TL_INTR_RxEOC: 1056 ack++; 1057 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1058 sizeof(struct tl_Rx_list) * TL_NBUF, 1059 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1060 #ifdef TLDEBUG_RX 1061 printf("TL_INTR_RxEOC: ack %d\n", ack); 1062 #endif 1063 #ifdef DIAGNOSTIC 1064 if (le32toh(sc->active_Rx->hw_list->stat) & TL_RX_CSTAT_CPLT) { 1065 printf("%s: Rx EOC interrupt and active Tx list not " 1066 "cleared\n", sc->sc_dev.dv_xname); 1067 return 0; 1068 } else 1069 #endif 1070 { 1071 /* 1072 * write adress of Rx list and send Rx GO command, ack 1073 * interrupt and enable interrupts in one command 1074 */ 1075 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->active_Rx->hw_listaddr); 1076 TL_HR_WRITE(sc, TL_HOST_CMD, 1077 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type | 1078 HOST_CMD_ACK | HOST_CMD_IntOn); 1079 return 1; 1080 } 1081 case TL_INTR_TxEOF: 1082 case TL_INTR_TxEOC: 1083 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1084 sizeof(struct tl_Tx_list) * TL_NBUF, 1085 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1086 while ((Tx = sc->active_Tx) != NULL) { 1087 if((le32toh(Tx->hw_list->stat) & TL_TX_CSTAT_CPLT) == 0) 1088 break; 1089 ack++; 1090 #ifdef TLDEBUG_TX 1091 printf("TL_INTR_TxEOC: list 0x%x done\n", 1092 (int)Tx->hw_listaddr); 1093 #endif 1094 Tx->hw_list->stat = 0; 1095 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, 1096 MCLBYTES, BUS_DMASYNC_POSTWRITE); 1097 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1098 m_freem(Tx->m); 1099 Tx->m = NULL; 1100 sc->active_Tx = Tx->next; 1101 if (sc->active_Tx == NULL) 1102 sc->last_Tx = NULL; 1103 Tx->next = sc->Free_Tx; 1104 sc->Free_Tx = Tx; 1105 } 1106 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1107 sizeof(struct tl_Tx_list) * TL_NBUF, 1108 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1109 /* if this was an EOC, ACK immediatly */ 1110 if (ack) 1111 sc->tl_if.if_flags &= ~IFF_OACTIVE; 1112 if (int_type == TL_INTR_TxEOC) { 1113 #ifdef TLDEBUG_TX 1114 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n", 1115 ack); 1116 #endif 1117 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type | 1118 HOST_CMD_ACK | HOST_CMD_IntOn); 1119 if ( sc->active_Tx != NULL) { 1120 /* needs a Tx go command */ 1121 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 1122 sc->active_Tx->hw_listaddr); 1123 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1124 } 1125 sc->tl_if.if_timer = 0; 1126 if (sc->tl_if.if_snd.ifq_head != NULL) 1127 tl_ifstart(&sc->tl_if); 1128 return 1; 1129 } 1130 #ifdef TLDEBUG 1131 else { 1132 printf("TL_INTR_TxEOF: ack %d\n", ack); 1133 } 1134 #endif 1135 sc->tl_if.if_timer = 0; 1136 if (sc->tl_if.if_snd.ifq_head != NULL) 1137 tl_ifstart(&sc->tl_if); 1138 break; 1139 case TL_INTR_Stat: 1140 ack++; 1141 #ifdef TLDEBUG 1142 printf("TL_INTR_Stat: ack %d\n", ack); 1143 #endif 1144 tl_read_stats(sc); 1145 break; 1146 case TL_INTR_Adc: 1147 if (int_reg & TL_INTVec_MASK) { 1148 /* adapter check conditions */ 1149 printf("%s: check condition, intvect=0x%x, " 1150 "ch_param=0x%x\n", sc->sc_dev.dv_xname, 1151 int_reg & TL_INTVec_MASK, 1152 TL_HR_READ(sc, TL_HOST_CH_PARM)); 1153 tl_reset(sc); 1154 /* shedule reinit of the board */ 1155 callout_reset(&sc->tl_restart_ch, 1, tl_restart, sc); 1156 return(1); 1157 } else { 1158 u_int8_t netstat; 1159 /* Network status */ 1160 netstat = 1161 tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts); 1162 printf("%s: network status, NetSts=%x\n", 1163 sc->sc_dev.dv_xname, netstat); 1164 /* Ack interrupts */ 1165 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts, 1166 netstat); 1167 ack++; 1168 } 1169 break; 1170 default: 1171 printf("%s: unhandled interrupt code %x!\n", 1172 sc->sc_dev.dv_xname, int_type); 1173 ack++; 1174 } 1175 1176 if (ack) { 1177 /* Ack the interrupt and enable interrupts */ 1178 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK | 1179 HOST_CMD_IntOn); 1180 return 1; 1181 } 1182 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */ 1183 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn); 1184 return 0; 1185 } 1186 1187 static int 1188 tl_ifioctl(ifp, cmd, data) 1189 struct ifnet *ifp; 1190 ioctl_cmd_t cmd; 1191 caddr_t data; 1192 { 1193 struct tl_softc *sc = ifp->if_softc; 1194 struct ifreq *ifr = (struct ifreq *)data; 1195 int s, error; 1196 1197 s = splnet(); 1198 switch(cmd) { 1199 case SIOCSIFMEDIA: 1200 case SIOCGIFMEDIA: 1201 error = ifmedia_ioctl(ifp, ifr, &sc->tl_mii.mii_media, cmd); 1202 break; 1203 default: 1204 error = ether_ioctl(ifp, cmd, data); 1205 if (error == ENETRESET) { 1206 tl_addr_filter(sc); 1207 error = 0; 1208 } 1209 } 1210 splx(s); 1211 return error; 1212 } 1213 1214 static void 1215 tl_ifstart(ifp) 1216 struct ifnet *ifp; 1217 { 1218 tl_softc_t *sc = ifp->if_softc; 1219 struct mbuf *mb_head; 1220 struct Tx_list *Tx; 1221 int segment, size; 1222 int again, error; 1223 1224 if ((sc->tl_if.if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1225 return; 1226 txloop: 1227 /* If we don't have more space ... */ 1228 if (sc->Free_Tx == NULL) { 1229 #ifdef TLDEBUG 1230 printf("tl_ifstart: No free TX list\n"); 1231 #endif 1232 sc->tl_if.if_flags |= IFF_OACTIVE; 1233 return; 1234 } 1235 /* Grab a paquet for output */ 1236 IF_DEQUEUE(&ifp->if_snd, mb_head); 1237 if (mb_head == NULL) { 1238 #ifdef TLDEBUG_TX 1239 printf("tl_ifstart: nothing to send\n"); 1240 #endif 1241 return; 1242 } 1243 Tx = sc->Free_Tx; 1244 sc->Free_Tx = Tx->next; 1245 Tx->next = NULL; 1246 again = 0; 1247 /* 1248 * Go through each of the mbufs in the chain and initialize 1249 * the transmit list descriptors with the physical address 1250 * and size of the mbuf. 1251 */ 1252 tbdinit: 1253 memset(Tx->hw_list, 0, sizeof(struct tl_Tx_list)); 1254 Tx->m = mb_head; 1255 size = mb_head->m_pkthdr.len; 1256 if ((error = bus_dmamap_load_mbuf(sc->tl_dmatag, Tx->m_dmamap, mb_head, 1257 BUS_DMA_NOWAIT)) || (size < ETHER_MIN_TX && 1258 Tx->m_dmamap->dm_nsegs == TL_NSEG)) { 1259 struct mbuf *mn; 1260 /* 1261 * We ran out of segments, or we will. We have to recopy this 1262 * mbuf chain first. 1263 */ 1264 if (error == 0) 1265 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1266 if (again) { 1267 /* already copyed, can't do much more */ 1268 m_freem(mb_head); 1269 goto bad; 1270 } 1271 again = 1; 1272 #ifdef TLDEBUG_TX 1273 printf("tl_ifstart: need to copy mbuf\n"); 1274 #endif 1275 #ifdef TL_PRIV_STATS 1276 sc->oerr_mcopy++; 1277 #endif 1278 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1279 if (mn == NULL) { 1280 m_freem(mb_head); 1281 goto bad; 1282 } 1283 if (mb_head->m_pkthdr.len > MHLEN) { 1284 MCLGET(mn, M_DONTWAIT); 1285 if ((mn->m_flags & M_EXT) == 0) { 1286 m_freem(mn); 1287 m_freem(mb_head); 1288 goto bad; 1289 } 1290 } 1291 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1292 mtod(mn, caddr_t)); 1293 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1294 m_freem(mb_head); 1295 mb_head = mn; 1296 goto tbdinit; 1297 } 1298 for (segment = 0; segment < Tx->m_dmamap->dm_nsegs; segment++) { 1299 Tx->hw_list->seg[segment].data_addr = 1300 htole32(Tx->m_dmamap->dm_segs[segment].ds_addr); 1301 Tx->hw_list->seg[segment].data_count = 1302 htole32(Tx->m_dmamap->dm_segs[segment].ds_len); 1303 } 1304 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, size, 1305 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1306 /* We are at end of mbuf chain. check the size and 1307 * see if it needs to be extended 1308 */ 1309 if (size < ETHER_MIN_TX) { 1310 #ifdef DIAGNOSTIC 1311 if (segment >= TL_NSEG) { 1312 panic("tl_ifstart: to much segmets (%d)\n", segment); 1313 } 1314 #endif 1315 /* 1316 * add the nullbuf in the seg 1317 */ 1318 Tx->hw_list->seg[segment].data_count = 1319 htole32(ETHER_MIN_TX - size); 1320 Tx->hw_list->seg[segment].data_addr = 1321 htole32(sc->null_dmamap->dm_segs[0].ds_addr); 1322 size = ETHER_MIN_TX; 1323 segment++; 1324 } 1325 /* The list is done, finish the list init */ 1326 Tx->hw_list->seg[segment-1].data_count |= 1327 htole32(TL_LAST_SEG); 1328 Tx->hw_list->stat = htole32((size << 16) | 0x3000); 1329 #ifdef TLDEBUG_TX 1330 printf("%s: sending, Tx : stat = 0x%x\n", sc->sc_dev.dv_xname, 1331 le32toh(Tx->hw_list->stat)); 1332 #if 0 1333 for(segment = 0; segment < TL_NSEG; segment++) { 1334 printf(" seg %d addr 0x%x len 0x%x\n", 1335 segment, 1336 le32toh(Tx->hw_list->seg[segment].data_addr), 1337 le32toh(Tx->hw_list->seg[segment].data_count)); 1338 } 1339 #endif 1340 #endif 1341 if (sc->active_Tx == NULL) { 1342 sc->active_Tx = sc->last_Tx = Tx; 1343 #ifdef TLDEBUG_TX 1344 printf("%s: Tx GO, addr=0x%ux\n", sc->sc_dev.dv_xname, 1345 (int)Tx->hw_listaddr); 1346 #endif 1347 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1348 sizeof(struct tl_Tx_list) * TL_NBUF, 1349 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1350 TL_HR_WRITE(sc, TL_HOST_CH_PARM, Tx->hw_listaddr); 1351 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1352 } else { 1353 #ifdef TLDEBUG_TX 1354 printf("%s: Tx addr=0x%ux queued\n", sc->sc_dev.dv_xname, 1355 (int)Tx->hw_listaddr); 1356 #endif 1357 sc->last_Tx->hw_list->fwd = htole32(Tx->hw_listaddr); 1358 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1359 sizeof(struct tl_Tx_list) * TL_NBUF, 1360 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1361 sc->last_Tx->next = Tx; 1362 sc->last_Tx = Tx; 1363 #ifdef DIAGNOSTIC 1364 if (sc->last_Tx->hw_list->fwd & 0x7) 1365 printf("%s: physical addr 0x%x of list not properly " 1366 "aligned\n", 1367 sc->sc_dev.dv_xname, sc->last_Rx->hw_list->fwd); 1368 #endif 1369 } 1370 #if NBPFILTER > 0 1371 /* Pass packet to bpf if there is a listener */ 1372 if (ifp->if_bpf) 1373 bpf_mtap(ifp->if_bpf, mb_head); 1374 #endif 1375 /* 1376 * Set a 5 second timer just in case we don't hear from the card again. 1377 */ 1378 ifp->if_timer = 5; 1379 goto txloop; 1380 bad: 1381 #ifdef TLDEBUG 1382 printf("tl_ifstart: Out of mbuf, Tx pkt lost\n"); 1383 #endif 1384 Tx->next = sc->Free_Tx; 1385 sc->Free_Tx = Tx; 1386 return; 1387 } 1388 1389 static void 1390 tl_ifwatchdog(ifp) 1391 struct ifnet *ifp; 1392 { 1393 tl_softc_t *sc = ifp->if_softc; 1394 1395 if ((ifp->if_flags & IFF_RUNNING) == 0) 1396 return; 1397 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1398 ifp->if_oerrors++; 1399 tl_init(ifp); 1400 } 1401 1402 static int 1403 tl_mediachange(ifp) 1404 struct ifnet *ifp; 1405 { 1406 1407 if (ifp->if_flags & IFF_UP) 1408 tl_init(ifp->if_softc); 1409 return (0); 1410 } 1411 1412 static void 1413 tl_mediastatus(ifp, ifmr) 1414 struct ifnet *ifp; 1415 struct ifmediareq *ifmr; 1416 { 1417 tl_softc_t *sc = ifp->if_softc; 1418 1419 mii_pollstat(&sc->tl_mii); 1420 ifmr->ifm_active = sc->tl_mii.mii_media_active; 1421 ifmr->ifm_status = sc->tl_mii.mii_media_status; 1422 } 1423 1424 static int tl_add_RxBuff(sc, Rx, oldm) 1425 tl_softc_t *sc; 1426 struct Rx_list *Rx; 1427 struct mbuf *oldm; 1428 { 1429 struct mbuf *m; 1430 int error; 1431 1432 MGETHDR(m, M_DONTWAIT, MT_DATA); 1433 if (m != NULL) { 1434 MCLGET(m, M_DONTWAIT); 1435 if ((m->m_flags & M_EXT) == 0) { 1436 m_freem(m); 1437 if (oldm == NULL) 1438 return 0; 1439 m = oldm; 1440 m->m_data = m->m_ext.ext_buf; 1441 } 1442 } else { 1443 if (oldm == NULL) 1444 return 0; 1445 m = oldm; 1446 m->m_data = m->m_ext.ext_buf; 1447 } 1448 1449 /* (re)init the Rx_list struct */ 1450 1451 Rx->m = m; 1452 if ((error = bus_dmamap_load(sc->tl_dmatag, Rx->m_dmamap, 1453 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1454 printf("%s: bus_dmamap_load() failed (error %d) for " 1455 "tl_add_RxBuff\n", sc->sc_dev.dv_xname, error); 1456 printf("size %d (%d)\n", m->m_pkthdr.len, MCLBYTES); 1457 m_freem(m); 1458 Rx->m = NULL; 1459 return 0; 1460 } 1461 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 1462 MCLBYTES, BUS_DMASYNC_PREREAD); 1463 /* 1464 * Move the data pointer up so that the incoming data packet 1465 * will be 32-bit aligned. 1466 */ 1467 m->m_data += 2; 1468 1469 Rx->hw_list->stat = 1470 htole32(((Rx->m_dmamap->dm_segs[0].ds_len -2) << 16) | 0x3000); 1471 Rx->hw_list->seg.data_count = 1472 htole32(Rx->m_dmamap->dm_segs[0].ds_len -2); 1473 Rx->hw_list->seg.data_addr = 1474 htole32(Rx->m_dmamap->dm_segs[0].ds_addr + 2); 1475 return (m != oldm); 1476 } 1477 1478 static void tl_ticks(v) 1479 void *v; 1480 { 1481 tl_softc_t *sc = v; 1482 1483 tl_read_stats(sc); 1484 1485 /* Tick the MII. */ 1486 mii_tick(&sc->tl_mii); 1487 1488 /* read statistics every seconds */ 1489 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 1490 } 1491 1492 static void 1493 tl_read_stats(sc) 1494 tl_softc_t *sc; 1495 { 1496 u_int32_t reg; 1497 int ierr_overr; 1498 int ierr_code; 1499 int ierr_crc; 1500 int oerr_underr; 1501 int oerr_deffered; 1502 int oerr_coll; 1503 int oerr_multicoll; 1504 int oerr_exesscoll; 1505 int oerr_latecoll; 1506 int oerr_carrloss; 1507 struct ifnet *ifp = &sc->tl_if; 1508 1509 reg = tl_intreg_read(sc, TL_INT_STATS_TX); 1510 ifp->if_opackets += reg & 0x00ffffff; 1511 oerr_underr = reg >> 24; 1512 1513 reg = tl_intreg_read(sc, TL_INT_STATS_RX); 1514 ifp->if_ipackets += reg & 0x00ffffff; 1515 ierr_overr = reg >> 24; 1516 1517 reg = tl_intreg_read(sc, TL_INT_STATS_FERR); 1518 ierr_crc = (reg & TL_FERR_CRC) >> 16; 1519 ierr_code = (reg & TL_FERR_CODE) >> 24; 1520 oerr_deffered = (reg & TL_FERR_DEF); 1521 1522 reg = tl_intreg_read(sc, TL_INT_STATS_COLL); 1523 oerr_multicoll = (reg & TL_COL_MULTI); 1524 oerr_coll = (reg & TL_COL_SINGLE) >> 16; 1525 1526 reg = tl_intreg_read(sc, TL_INT_LERR); 1527 oerr_exesscoll = (reg & TL_LERR_ECOLL); 1528 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8; 1529 oerr_carrloss = (reg & TL_LERR_CL) >> 16; 1530 1531 1532 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll + 1533 oerr_carrloss; 1534 ifp->if_collisions += oerr_coll + oerr_multicoll; 1535 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc; 1536 1537 if (ierr_overr) 1538 printf("%s: receiver ring buffer overrun\n", 1539 sc->sc_dev.dv_xname); 1540 if (oerr_underr) 1541 printf("%s: transmit buffer underrun\n", 1542 sc->sc_dev.dv_xname); 1543 #ifdef TL_PRIV_STATS 1544 sc->ierr_overr += ierr_overr; 1545 sc->ierr_code += ierr_code; 1546 sc->ierr_crc += ierr_crc; 1547 sc->oerr_underr += oerr_underr; 1548 sc->oerr_deffered += oerr_deffered; 1549 sc->oerr_coll += oerr_coll; 1550 sc->oerr_multicoll += oerr_multicoll; 1551 sc->oerr_exesscoll += oerr_exesscoll; 1552 sc->oerr_latecoll += oerr_latecoll; 1553 sc->oerr_carrloss += oerr_carrloss; 1554 #endif 1555 } 1556 1557 static void tl_addr_filter(sc) 1558 tl_softc_t *sc; 1559 { 1560 struct ether_multistep step; 1561 struct ether_multi *enm; 1562 u_int32_t hash[2] = {0, 0}; 1563 int i; 1564 1565 sc->tl_if.if_flags &= ~IFF_ALLMULTI; 1566 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm); 1567 while (enm != NULL) { 1568 #ifdef TLDEBUG 1569 printf("tl_addr_filter: addrs %s %s\n", 1570 ether_sprintf(enm->enm_addrlo), 1571 ether_sprintf(enm->enm_addrhi)); 1572 #endif 1573 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1574 i = tl_multicast_hash(enm->enm_addrlo); 1575 hash[i/32] |= 1 << (i%32); 1576 } else { 1577 hash[0] = hash[1] = 0xffffffff; 1578 sc->tl_if.if_flags |= IFF_ALLMULTI; 1579 break; 1580 } 1581 ETHER_NEXT_MULTI(step, enm); 1582 } 1583 #ifdef TLDEBUG 1584 printf("tl_addr_filer: hash1 %x has2 %x\n", hash[0], hash[1]); 1585 #endif 1586 tl_intreg_write(sc, TL_INT_HASH1, hash[0]); 1587 tl_intreg_write(sc, TL_INT_HASH2, hash[1]); 1588 } 1589 1590 static int tl_multicast_hash(a) 1591 u_int8_t *a; 1592 { 1593 int hash; 1594 1595 #define DA(addr,bit) (addr[5 - (bit/8)] & (1 << bit%8)) 1596 #define xor8(a,b,c,d,e,f,g,h) (((a != 0) + (b != 0) + (c != 0) + (d != 0) + (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1597 1598 hash = xor8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1599 DA(a,36), DA(a,42)); 1600 hash |= xor8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1601 DA(a,37), DA(a,43)) << 1; 1602 hash |= xor8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1603 DA(a,38), DA(a,44)) << 2; 1604 hash |= xor8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1605 DA(a,39), DA(a,45)) << 3; 1606 hash |= xor8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1607 DA(a,40), DA(a,46)) << 4; 1608 hash |= xor8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1609 DA(a,41), DA(a,47)) << 5; 1610 1611 return hash; 1612 } 1613 1614 #if defined(TLDEBUG_RX) 1615 void 1616 ether_printheader(eh) 1617 struct ether_header *eh; 1618 { 1619 u_char *c = (char*)eh; 1620 int i; 1621 for (i=0; i<sizeof(struct ether_header); i++) 1622 printf("%x ", (u_int)c[i]); 1623 printf("\n"); 1624 } 1625 #endif 1626