1 /* $NetBSD: if_tl.c,v 1.32 2000/03/23 07:01:39 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Texas Instruments ThunderLAN ethernet controller 34 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A) 35 * available from www.ti.com 36 */ 37 38 #undef TLDEBUG 39 #define TL_PRIV_STATS 40 #undef TLDEBUG_RX 41 #undef TLDEBUG_TX 42 #undef TLDEBUG_ADDR 43 44 #include "opt_inet.h" 45 #include "opt_ns.h" 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/mbuf.h> 50 #include <sys/protosw.h> 51 #include <sys/socket.h> 52 #include <sys/ioctl.h> 53 #include <sys/errno.h> 54 #include <sys/malloc.h> 55 #include <sys/kernel.h> 56 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 57 #include <sys/device.h> 58 59 #include <net/if.h> 60 #if defined(SIOCSIFMEDIA) 61 #include <net/if_media.h> 62 #endif 63 #include <net/if_types.h> 64 #include <net/if_dl.h> 65 #include <net/route.h> 66 #include <net/netisr.h> 67 68 #include "bpfilter.h" 69 #if NBPFILTER > 0 70 #include <net/bpf.h> 71 #include <net/bpfdesc.h> 72 #endif 73 74 #ifdef INET 75 #include <netinet/in.h> 76 #include <netinet/in_systm.h> 77 #include <netinet/in_var.h> 78 #include <netinet/ip.h> 79 #endif 80 81 #ifdef NS 82 #include <netns/ns.h> 83 #include <netns/ns_if.h> 84 #endif 85 86 #include <vm/vm.h> 87 #include <vm/vm_param.h> 88 #include <vm/vm_kern.h> 89 90 #if defined(__NetBSD__) 91 #include <net/if_ether.h> 92 #if defined(INET) 93 #include <netinet/if_inarp.h> 94 #endif 95 96 #include <machine/bus.h> 97 #include <machine/intr.h> 98 99 #include <dev/pci/pcireg.h> 100 #include <dev/pci/pcivar.h> 101 #include <dev/pci/pcidevs.h> 102 103 #include <dev/i2c/i2c_bus.h> 104 #include <dev/i2c/i2c_eeprom.h> 105 106 #include <dev/mii/mii.h> 107 #include <dev/mii/miivar.h> 108 109 #include <dev/mii/tlphyvar.h> 110 111 #include <dev/pci/if_tlregs.h> 112 #include <dev/pci/if_tlvar.h> 113 #endif /* __NetBSD__ */ 114 115 #if defined(__NetBSD__) && defined(__alpha__) 116 /* XXX XXX NEED REAL DMA MAPPING SUPPORT XXX XXX */ 117 #undef vtophys 118 #define vtophys(va) alpha_XXX_dmamap((vaddr_t)(va)) 119 #endif 120 121 /* number of transmit/receive buffers */ 122 #ifndef TL_NBUF 123 #define TL_NBUF 10 124 #endif 125 126 /* number of seconds the link can be idle */ 127 #ifndef TL_IDLETIME 128 #define TL_IDLETIME 10 129 #endif 130 131 static int tl_pci_match __P((struct device *, struct cfdata *, void *)); 132 static void tl_pci_attach __P((struct device *, struct device *, void *)); 133 static int tl_intr __P((void *)); 134 135 static int tl_ifioctl __P((struct ifnet *, ioctl_cmd_t, caddr_t)); 136 static int tl_mediachange __P((struct ifnet *)); 137 static void tl_mediastatus __P((struct ifnet *, struct ifmediareq *)); 138 static void tl_ifwatchdog __P((struct ifnet *)); 139 static void tl_shutdown __P((void*)); 140 141 static void tl_ifstart __P((struct ifnet *)); 142 static void tl_reset __P((tl_softc_t*)); 143 static int tl_init __P((tl_softc_t*)); 144 static void tl_restart __P((void *)); 145 static int tl_add_RxBuff __P((struct Rx_list*, struct mbuf*)); 146 static void tl_read_stats __P((tl_softc_t*)); 147 static void tl_ticks __P((void*)); 148 static int tl_multicast_hash __P((u_int8_t*)); 149 static void tl_addr_filter __P((tl_softc_t*)); 150 151 static u_int32_t tl_intreg_read __P((tl_softc_t*, u_int32_t)); 152 static void tl_intreg_write __P((tl_softc_t*, u_int32_t, u_int32_t)); 153 static u_int8_t tl_intreg_read_byte __P((tl_softc_t*, u_int32_t)); 154 static void tl_intreg_write_byte __P((tl_softc_t*, u_int32_t, u_int8_t)); 155 156 void tl_mii_sync __P((struct tl_softc *)); 157 void tl_mii_sendbits __P((struct tl_softc *, u_int32_t, int)); 158 159 160 #if defined(TLDEBUG_RX) 161 static void ether_printheader __P((struct ether_header*)); 162 #endif 163 164 int tl_mii_read __P((struct device *, int, int)); 165 void tl_mii_write __P((struct device *, int, int, int)); 166 167 void tl_statchg __P((struct device *)); 168 169 void tl_i2c_set __P((void*, u_int8_t)); 170 void tl_i2c_clr __P((void*, u_int8_t)); 171 int tl_i2c_read __P((void*, u_int8_t)); 172 173 static __inline void netsio_clr __P((tl_softc_t*, u_int8_t)); 174 static __inline void netsio_set __P((tl_softc_t*, u_int8_t)); 175 static __inline u_int8_t netsio_read __P((tl_softc_t*, u_int8_t)); 176 static __inline void netsio_clr(sc, bits) 177 tl_softc_t* sc; 178 u_int8_t bits; 179 { 180 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 181 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits)); 182 } 183 static __inline void netsio_set(sc, bits) 184 tl_softc_t* sc; 185 u_int8_t bits; 186 { 187 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 188 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits); 189 } 190 static __inline u_int8_t netsio_read(sc, bits) 191 tl_softc_t* sc; 192 u_int8_t bits; 193 { 194 return (tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits); 195 } 196 197 struct cfattach tl_ca = { 198 sizeof(tl_softc_t), tl_pci_match, tl_pci_attach 199 }; 200 201 const struct tl_product_desc tl_compaq_products[] = { 202 { PCI_PRODUCT_COMPAQ_N100TX, TLPHY_MEDIA_NO_10_T, 203 "Compaq Netelligent 10/100 TX" }, 204 { PCI_PRODUCT_COMPAQ_N10T, TLPHY_MEDIA_10_5, 205 "Compaq Netelligent 10 T" }, 206 { PCI_PRODUCT_COMPAQ_IntNF3P, TLPHY_MEDIA_10_2, 207 "Compaq Integrated NetFlex 3/P" }, 208 { PCI_PRODUCT_COMPAQ_IntPL100TX, TLPHY_MEDIA_10_2|TLPHY_MEDIA_NO_10_T, 209 "Compaq ProLiant Integrated Netelligent 10/100 TX" }, 210 { PCI_PRODUCT_COMPAQ_DPNet100TX, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 211 "Compaq Dual Port Netelligent 10/100 TX" }, 212 { PCI_PRODUCT_COMPAQ_DP4000, TLPHY_MEDIA_10_5, 213 "Compaq Deskpro 4000 5233MMX" }, 214 { PCI_PRODUCT_COMPAQ_NF3P_BNC, TLPHY_MEDIA_10_2, 215 "Compaq NetFlex 3/P w/ BNC" }, 216 { PCI_PRODUCT_COMPAQ_NF3P, TLPHY_MEDIA_10_5, 217 "Compaq NetFlex 3/P" }, 218 { 0, 0, NULL }, 219 }; 220 221 const struct tl_product_desc tl_ti_products[] = { 222 /* 223 * Built-in Ethernet on the TI TravelMate 5000 224 * docking station; better product description? 225 */ 226 { PCI_PRODUCT_TI_TLAN, 0, 227 "Texas Instruments ThunderLAN" }, 228 { 0, 0, NULL }, 229 }; 230 231 struct tl_vendor_desc { 232 u_int32_t tv_vendor; 233 const struct tl_product_desc *tv_products; 234 }; 235 236 const struct tl_vendor_desc tl_vendors[] = { 237 { PCI_VENDOR_COMPAQ, tl_compaq_products }, 238 { PCI_VENDOR_TI, tl_ti_products }, 239 { 0, NULL }, 240 }; 241 242 const struct tl_product_desc *tl_lookup_product __P((u_int32_t)); 243 244 const struct tl_product_desc * 245 tl_lookup_product(id) 246 u_int32_t id; 247 { 248 const struct tl_product_desc *tp; 249 const struct tl_vendor_desc *tv; 250 251 for (tv = tl_vendors; tv->tv_products != NULL; tv++) 252 if (PCI_VENDOR(id) == tv->tv_vendor) 253 break; 254 255 if ((tp = tv->tv_products) == NULL) 256 return (NULL); 257 258 for (; tp->tp_desc != NULL; tp++) 259 if (PCI_PRODUCT(id) == tp->tp_product) 260 break; 261 262 if (tp->tp_desc == NULL) 263 return (NULL); 264 265 return (tp); 266 } 267 268 static char *nullbuf = NULL; 269 270 static int 271 tl_pci_match(parent, match, aux) 272 struct device *parent; 273 struct cfdata *match; 274 void *aux; 275 { 276 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 277 278 if (tl_lookup_product(pa->pa_id) != NULL) 279 return (1); 280 281 return (0); 282 } 283 284 static void 285 tl_pci_attach(parent, self, aux) 286 struct device * parent; 287 struct device * self; 288 void * aux; 289 { 290 tl_softc_t *sc = (tl_softc_t *)self; 291 struct pci_attach_args * const pa = (struct pci_attach_args *) aux; 292 const struct tl_product_desc *tp; 293 struct ifnet * const ifp = &sc->tl_if; 294 bus_space_tag_t iot, memt; 295 bus_space_handle_t ioh, memh; 296 pci_intr_handle_t intrhandle; 297 const char *intrstr; 298 int i, tmp, ioh_valid, memh_valid; 299 int reg_io, reg_mem; 300 pcireg_t reg10, reg14; 301 pcireg_t csr; 302 303 printf("\n"); 304 305 callout_init(&sc->tl_tick_ch); 306 callout_init(&sc->tl_restart_ch); 307 308 tp = tl_lookup_product(pa->pa_id); 309 if (tp == NULL) 310 panic("tl_pci_attach: impossible"); 311 sc->tl_product = tp; 312 313 /* 314 * Map the card space. Fisrt we have to find the I/O and MEM 315 * registers. I/O is supposed to be at 0x10, MEM at 0x14, 316 * but some boards (Compaq Netflex 3/P PCI) seem to have it reversed. 317 * The ThunderLAN manual is not consistent about this either (there 318 * are both cases in code examples). 319 */ 320 reg10 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x10); 321 reg14 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x14); 322 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_IO) 323 reg_io = 0x10; 324 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_IO) 325 reg_io = 0x14; 326 else 327 reg_io = 0; 328 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_MEM) 329 reg_mem = 0x10; 330 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_MEM) 331 reg_mem = 0x14; 332 else 333 reg_mem = 0; 334 335 if (reg_io != 0) 336 ioh_valid = (pci_mapreg_map(pa, reg_io, PCI_MAPREG_TYPE_IO, 337 0, &iot, &ioh, NULL, NULL) == 0); 338 else 339 ioh_valid = 0; 340 if (reg_mem != 0) 341 memh_valid = (pci_mapreg_map(pa, PCI_CBMA, 342 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 343 0, &memt, &memh, NULL, NULL) == 0); 344 else 345 memh_valid = 0; 346 347 if (ioh_valid) { 348 sc->tl_bustag = iot; 349 sc->tl_bushandle = ioh; 350 } else if (memh_valid) { 351 sc->tl_bustag = memt; 352 sc->tl_bushandle = memh; 353 } else { 354 printf("%s: unable to map device registers\n", 355 sc->sc_dev.dv_xname); 356 return; 357 } 358 359 /* Enable the device. */ 360 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 361 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 362 csr | PCI_COMMAND_MASTER_ENABLE); 363 364 printf("%s: %s\n", sc->sc_dev.dv_xname, tp->tp_desc); 365 366 tl_reset(sc); 367 368 /* fill in the i2c struct */ 369 sc->i2cbus.adapter_softc = sc; 370 sc->i2cbus.set_bit = tl_i2c_set; 371 sc->i2cbus.clr_bit = tl_i2c_clr; 372 sc->i2cbus.read_bit = tl_i2c_read; 373 374 #ifdef TLDEBUG 375 printf("default values of INTreg: 0x%x\n", 376 tl_intreg_read(sc, TL_INT_Defaults)); 377 #endif 378 379 /* read mac addr */ 380 for (i=0; i<ETHER_ADDR_LEN; i++) { 381 tmp = i2c_eeprom_read(&sc->i2cbus, 0x83 + i); 382 if (tmp < 0) { 383 printf("%s: error reading Ethernet adress\n", 384 sc->sc_dev.dv_xname); 385 return; 386 } else { 387 sc->tl_enaddr[i] = tmp; 388 } 389 } 390 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 391 ether_sprintf(sc->tl_enaddr)); 392 393 /* Map and establish interrupts */ 394 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 395 pa->pa_intrline, &intrhandle)) { 396 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 397 return; 398 } 399 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 400 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 401 tl_intr, sc); 402 if (sc->tl_ih == NULL) { 403 printf("%s: couldn't establish interrupt", 404 sc->sc_dev.dv_xname); 405 if (intrstr != NULL) 406 printf(" at %s", intrstr); 407 printf("\n"); 408 return; 409 } 410 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 411 412 /* 413 * Add shutdown hook so that DMA is disabled prior to reboot. Not 414 * doing do could allow DMA to corrupt kernel memory during the 415 * reboot before the driver initializes. 416 */ 417 (void) shutdownhook_establish(tl_shutdown, sc); 418 419 /* 420 * Initialize our media structures and probe the MII. 421 * 422 * Note that we don't care about the media instance. We 423 * are expecting to have multiple PHYs on the 10/100 cards, 424 * and on those cards we exclude the internal PHY from providing 425 * 10baseT. By ignoring the instance, it allows us to not have 426 * to specify it on the command line when switching media. 427 */ 428 sc->tl_mii.mii_ifp = ifp; 429 sc->tl_mii.mii_readreg = tl_mii_read; 430 sc->tl_mii.mii_writereg = tl_mii_write; 431 sc->tl_mii.mii_statchg = tl_statchg; 432 ifmedia_init(&sc->tl_mii.mii_media, IFM_IMASK, tl_mediachange, 433 tl_mediastatus); 434 mii_attach(self, &sc->tl_mii, 0xffffffff, MII_PHY_ANY, 435 MII_OFFSET_ANY, 0); 436 if (LIST_FIRST(&sc->tl_mii.mii_phys) == NULL) { 437 ifmedia_add(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 438 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE); 439 } else 440 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_AUTO); 441 442 bcopy(sc->sc_dev.dv_xname, sc->tl_if.if_xname, IFNAMSIZ); 443 sc->tl_if.if_softc = sc; 444 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 445 ifp->if_ioctl = tl_ifioctl; 446 ifp->if_start = tl_ifstart; 447 ifp->if_watchdog = tl_ifwatchdog; 448 ifp->if_timer = 0; 449 if_attach(ifp); 450 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr); 451 #if NBPFILTER > 0 452 bpfattach(&sc->tl_bpf, &sc->tl_if, DLT_EN10MB, 453 sizeof(struct ether_header)); 454 #endif 455 } 456 457 static void 458 tl_reset(sc) 459 tl_softc_t *sc; 460 { 461 int i; 462 463 /* read stats */ 464 if (sc->tl_if.if_flags & IFF_RUNNING) { 465 callout_stop(&sc->tl_tick_ch); 466 tl_read_stats(sc); 467 } 468 /* Reset adapter */ 469 TL_HR_WRITE(sc, TL_HOST_CMD, 470 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst); 471 DELAY(100000); 472 /* Disable interrupts */ 473 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 474 /* setup aregs & hash */ 475 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 476 tl_intreg_write(sc, i, 0); 477 #ifdef TLDEBUG_ADDR 478 printf("Areg & hash registers: \n"); 479 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 480 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 481 #endif 482 /* Setup NetConfig */ 483 tl_intreg_write(sc, TL_INT_NetConfig, 484 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN); 485 /* Bsize: accept default */ 486 /* TX commit in Acommit: accept default */ 487 /* Load Ld_tmr and Ld_thr */ 488 /* Ld_tmr = 3 */ 489 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr); 490 /* Ld_thr = 0 */ 491 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr); 492 /* Unreset MII */ 493 netsio_set(sc, TL_NETSIO_NMRST); 494 DELAY(100000); 495 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 496 sc->tl_flags = 0; 497 sc->opkt = 0; 498 sc->stats_exesscoll = 0; 499 } 500 501 static void tl_shutdown(v) 502 void *v; 503 { 504 tl_softc_t *sc = v; 505 struct Tx_list *Tx; 506 int i; 507 508 if ((sc->tl_if.if_flags & IFF_RUNNING) == 0) 509 return; 510 /* disable interrupts */ 511 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 512 /* stop TX and RX channels */ 513 TL_HR_WRITE(sc, TL_HOST_CMD, 514 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes); 515 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP); 516 DELAY(100000); 517 518 /* stop statistics reading loop, read stats */ 519 callout_stop(&sc->tl_tick_ch); 520 tl_read_stats(sc); 521 522 /* Down the MII. */ 523 mii_down(&sc->tl_mii); 524 525 /* deallocate memory allocations */ 526 for (i=0; i< TL_NBUF; i++) { 527 if (sc->Rx_list[i].m) 528 m_freem(sc->Rx_list[i].m); 529 sc->Rx_list[i].m = NULL; 530 } 531 free(sc->Rx_list, M_DEVBUF); 532 sc->Rx_list = NULL; 533 while ((Tx = sc->active_Tx) != NULL) { 534 Tx->hw_list.stat = 0; 535 m_freem(Tx->m); 536 sc->active_Tx = Tx->next; 537 Tx->next = sc->Free_Tx; 538 sc->Free_Tx = Tx; 539 } 540 sc->last_Tx = NULL; 541 free(sc->Tx_list, M_DEVBUF); 542 sc->Tx_list = NULL; 543 sc->tl_if.if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 544 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 545 sc->tl_flags = 0; 546 } 547 548 static void tl_restart(v) 549 void *v; 550 { 551 tl_init(v); 552 } 553 554 static int tl_init(sc) 555 tl_softc_t *sc; 556 { 557 struct ifnet *ifp = &sc->tl_if; 558 int i, s; 559 560 s = splnet(); 561 /* cancel any pending IO */ 562 tl_shutdown(sc); 563 tl_reset(sc); 564 if ((sc->tl_if.if_flags & IFF_UP) == 0) { 565 splx(s); 566 return 0; 567 } 568 /* Set various register to reasonable value */ 569 /* setup NetCmd in promisc mode if needed */ 570 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0; 571 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 572 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i); 573 /* Max receive size : MCLBYTES */ 574 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff); 575 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH, 576 (MCLBYTES >> 8) & 0xff); 577 578 /* init MAC addr */ 579 for (i = 0; i < ETHER_ADDR_LEN; i++) 580 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]); 581 /* add multicast filters */ 582 tl_addr_filter(sc); 583 #ifdef TLDEBUG_ADDR 584 printf("Wrote Mac addr, Areg & hash registers are now: \n"); 585 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 586 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 587 #endif 588 589 /* Pre-allocate receivers mbuf, make the lists */ 590 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF, 591 M_NOWAIT); 592 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF, 593 M_NOWAIT); 594 if (sc->Rx_list == NULL || sc->Tx_list == NULL) { 595 printf("%s: out of memory for lists\n", sc->sc_dev.dv_xname); 596 sc->tl_if.if_flags &= ~IFF_UP; 597 splx(s); 598 return ENOMEM; 599 } 600 for (i=0; i< TL_NBUF; i++) { 601 if (tl_add_RxBuff(&sc->Rx_list[i], NULL) == 0) { 602 printf("%s: out of mbuf for receive list\n", 603 sc->sc_dev.dv_xname); 604 sc->tl_if.if_flags &= ~IFF_UP; 605 splx(s); 606 return ENOMEM; 607 } 608 if (i > 0) { /* chain the list */ 609 sc->Rx_list[i-1].next = &sc->Rx_list[i]; 610 sc->Rx_list[i-1].hw_list.fwd = 611 vtophys(&sc->Rx_list[i].hw_list); 612 #ifdef DIAGNOSTIC 613 if (sc->Rx_list[i-1].hw_list.fwd & 0x7) 614 printf("%s: physical addr 0x%x of list not " 615 "properly aligned\n", 616 sc->sc_dev.dv_xname, 617 sc->Rx_list[i-1].hw_list.fwd); 618 #endif 619 sc->Tx_list[i-1].next = &sc->Tx_list[i]; 620 } 621 } 622 sc->Rx_list[TL_NBUF-1].next = NULL; 623 sc->Rx_list[TL_NBUF-1].hw_list.fwd = 0; 624 sc->Tx_list[TL_NBUF-1].next = NULL; 625 626 sc->active_Rx = &sc->Rx_list[0]; 627 sc->last_Rx = &sc->Rx_list[TL_NBUF-1]; 628 sc->active_Tx = sc->last_Tx = NULL; 629 sc->Free_Tx = &sc->Tx_list[0]; 630 631 if (nullbuf == NULL) 632 nullbuf = malloc(ETHER_MIN_TX, M_DEVBUF, M_NOWAIT); 633 if (nullbuf == NULL) { 634 printf("%s: can't allocate space for pad buffer\n", 635 sc->sc_dev.dv_xname); 636 sc->tl_if.if_flags &= ~IFF_UP; 637 splx(s); 638 return ENOMEM; 639 } 640 bzero(nullbuf, ETHER_MIN_TX); 641 642 /* set media */ 643 mii_mediachg(&sc->tl_mii); 644 645 /* start ticks calls */ 646 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 647 /* write adress of Rx list and enable interrupts */ 648 TL_HR_WRITE(sc, TL_HOST_CH_PARM, vtophys(&sc->Rx_list[0].hw_list)); 649 TL_HR_WRITE(sc, TL_HOST_CMD, 650 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn); 651 sc->tl_if.if_flags |= IFF_RUNNING; 652 sc->tl_if.if_flags &= ~IFF_OACTIVE; 653 return 0; 654 } 655 656 657 static u_int32_t 658 tl_intreg_read(sc, reg) 659 tl_softc_t *sc; 660 u_int32_t reg; 661 { 662 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 663 return TL_HR_READ(sc, TL_HOST_DIO_DATA); 664 } 665 666 static u_int8_t 667 tl_intreg_read_byte(sc, reg) 668 tl_softc_t *sc; 669 u_int32_t reg; 670 { 671 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 672 (reg & (~0x07)) & TL_HOST_DIOADR_MASK); 673 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07)); 674 } 675 676 static void 677 tl_intreg_write(sc, reg, val) 678 tl_softc_t *sc; 679 u_int32_t reg; 680 u_int32_t val; 681 { 682 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 683 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val); 684 } 685 686 static void 687 tl_intreg_write_byte(sc, reg, val) 688 tl_softc_t *sc; 689 u_int32_t reg; 690 u_int8_t val; 691 { 692 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 693 (reg & (~0x03)) & TL_HOST_DIOADR_MASK); 694 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val); 695 } 696 697 void 698 tl_mii_sync(sc) 699 struct tl_softc *sc; 700 { 701 int i; 702 703 netsio_clr(sc, TL_NETSIO_MTXEN); 704 for (i = 0; i < 32; i++) { 705 netsio_clr(sc, TL_NETSIO_MCLK); 706 netsio_set(sc, TL_NETSIO_MCLK); 707 } 708 } 709 710 void 711 tl_mii_sendbits(sc, data, nbits) 712 struct tl_softc *sc; 713 u_int32_t data; 714 int nbits; 715 { 716 int i; 717 718 netsio_set(sc, TL_NETSIO_MTXEN); 719 for (i = 1 << (nbits - 1); i; i = i >> 1) { 720 netsio_clr(sc, TL_NETSIO_MCLK); 721 netsio_read(sc, TL_NETSIO_MCLK); 722 if (data & i) 723 netsio_set(sc, TL_NETSIO_MDATA); 724 else 725 netsio_clr(sc, TL_NETSIO_MDATA); 726 netsio_set(sc, TL_NETSIO_MCLK); 727 netsio_read(sc, TL_NETSIO_MCLK); 728 } 729 } 730 731 int 732 tl_mii_read(self, phy, reg) 733 struct device *self; 734 int phy, reg; 735 { 736 struct tl_softc *sc = (struct tl_softc *)self; 737 int val = 0, i, err; 738 739 /* 740 * Read the PHY register by manually driving the MII control lines. 741 */ 742 743 tl_mii_sync(sc); 744 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 745 tl_mii_sendbits(sc, MII_COMMAND_READ, 2); 746 tl_mii_sendbits(sc, phy, 5); 747 tl_mii_sendbits(sc, reg, 5); 748 749 netsio_clr(sc, TL_NETSIO_MTXEN); 750 netsio_clr(sc, TL_NETSIO_MCLK); 751 netsio_set(sc, TL_NETSIO_MCLK); 752 netsio_clr(sc, TL_NETSIO_MCLK); 753 754 err = netsio_read(sc, TL_NETSIO_MDATA); 755 netsio_set(sc, TL_NETSIO_MCLK); 756 757 /* Even if an error occurs, must still clock out the cycle. */ 758 for (i = 0; i < 16; i++) { 759 val <<= 1; 760 netsio_clr(sc, TL_NETSIO_MCLK); 761 if (err == 0 && netsio_read(sc, TL_NETSIO_MDATA)) 762 val |= 1; 763 netsio_set(sc, TL_NETSIO_MCLK); 764 } 765 netsio_clr(sc, TL_NETSIO_MCLK); 766 netsio_set(sc, TL_NETSIO_MCLK); 767 768 return (err ? 0 : val); 769 } 770 771 void 772 tl_mii_write(self, phy, reg, val) 773 struct device *self; 774 int phy, reg, val; 775 { 776 struct tl_softc *sc = (struct tl_softc *)self; 777 778 /* 779 * Write the PHY register by manually driving the MII control lines. 780 */ 781 782 tl_mii_sync(sc); 783 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 784 tl_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 785 tl_mii_sendbits(sc, phy, 5); 786 tl_mii_sendbits(sc, reg, 5); 787 tl_mii_sendbits(sc, MII_COMMAND_ACK, 2); 788 tl_mii_sendbits(sc, val, 16); 789 790 netsio_clr(sc, TL_NETSIO_MCLK); 791 netsio_set(sc, TL_NETSIO_MCLK); 792 } 793 794 void 795 tl_statchg(self) 796 struct device *self; 797 { 798 tl_softc_t *sc = (struct tl_softc *)self; 799 u_int32_t reg; 800 801 #ifdef TLDEBUG 802 printf("tl_statchg, media %x\n", sc->tl_ifmedia.ifm_media); 803 #endif 804 805 /* 806 * We must keep the ThunderLAN and the PHY in sync as 807 * to the status of full-duplex! 808 */ 809 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 810 if (sc->tl_mii.mii_media_active & IFM_FDX) 811 reg |= TL_NETCOMMAND_DUPLEX; 812 else 813 reg &= ~TL_NETCOMMAND_DUPLEX; 814 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 815 } 816 817 void tl_i2c_set(v, bit) 818 void *v; 819 u_int8_t bit; 820 { 821 tl_softc_t *sc = v; 822 823 switch (bit) { 824 case I2C_DATA: 825 netsio_set(sc, TL_NETSIO_EDATA); 826 break; 827 case I2C_CLOCK: 828 netsio_set(sc, TL_NETSIO_ECLOCK); 829 break; 830 case I2C_TXEN: 831 netsio_set(sc, TL_NETSIO_ETXEN); 832 break; 833 default: 834 printf("tl_i2c_set: unknown bit %d\n", bit); 835 } 836 return; 837 } 838 839 void tl_i2c_clr(v, bit) 840 void *v; 841 u_int8_t bit; 842 { 843 tl_softc_t *sc = v; 844 845 switch (bit) { 846 case I2C_DATA: 847 netsio_clr(sc, TL_NETSIO_EDATA); 848 break; 849 case I2C_CLOCK: 850 netsio_clr(sc, TL_NETSIO_ECLOCK); 851 break; 852 case I2C_TXEN: 853 netsio_clr(sc, TL_NETSIO_ETXEN); 854 break; 855 default: 856 printf("tl_i2c_clr: unknown bit %d\n", bit); 857 } 858 return; 859 } 860 861 int tl_i2c_read(v, bit) 862 void *v; 863 u_int8_t bit; 864 { 865 tl_softc_t *sc = v; 866 867 switch (bit) { 868 case I2C_DATA: 869 return netsio_read(sc, TL_NETSIO_EDATA); 870 break; 871 case I2C_CLOCK: 872 return netsio_read(sc, TL_NETSIO_ECLOCK); 873 break; 874 case I2C_TXEN: 875 return netsio_read(sc, TL_NETSIO_ETXEN); 876 break; 877 default: 878 printf("tl_i2c_read: unknown bit %d\n", bit); 879 return -1; 880 } 881 } 882 883 static int 884 tl_intr(v) 885 void *v; 886 { 887 tl_softc_t *sc = v; 888 struct ifnet *ifp = &sc->tl_if; 889 struct Rx_list *Rx; 890 struct Tx_list *Tx; 891 struct mbuf *m; 892 u_int32_t int_type, int_reg; 893 int ack = 0; 894 int size; 895 896 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR); 897 int_type = int_reg & TL_INTR_MASK; 898 if (int_type == 0) 899 return 0; 900 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX) 901 printf("%s: interrupt type %x, intr_reg %x\n", sc->sc_dev.dv_xname, 902 int_type, int_reg); 903 #endif 904 /* disable interrupts */ 905 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 906 switch(int_type & TL_INTR_MASK) { 907 case TL_INTR_RxEOF: 908 while(sc->active_Rx->hw_list.stat & TL_RX_CSTAT_CPLT) { 909 /* dequeue and requeue at end of list */ 910 ack++; 911 Rx = sc->active_Rx; 912 sc->active_Rx = Rx->next; 913 m = Rx->m; 914 size = Rx->hw_list.stat >> 16; 915 #ifdef TLDEBUG_RX 916 printf("tl_intr: RX list complete, Rx %p, size=%d\n", 917 Rx, size); 918 #endif 919 if (tl_add_RxBuff(Rx, m ) == 0) { 920 /* 921 * No new mbuf, reuse the same. This means 922 * that this packet 923 * is lost 924 */ 925 m = NULL; 926 #ifdef TL_PRIV_STATS 927 sc->ierr_nomem++; 928 #endif 929 #ifdef TLDEBUG 930 printf("%s: out of mbuf, lost input packet\n", 931 sc->sc_dev.dv_xname); 932 #endif 933 } 934 Rx->next = NULL; 935 Rx->hw_list.fwd = 0; 936 sc->last_Rx->hw_list.fwd = vtophys(&Rx->hw_list); 937 #ifdef DIAGNOSTIC 938 if (sc->last_Rx->hw_list.fwd & 0x7) 939 printf("%s: physical addr 0x%x of list not " 940 "properly aligned\n", 941 sc->sc_dev.dv_xname, 942 sc->last_Rx->hw_list.fwd); 943 #endif 944 sc->last_Rx->next = Rx; 945 sc->last_Rx = Rx; 946 947 /* deliver packet */ 948 if (m) { 949 struct ether_header *eh; 950 if (size < sizeof(struct ether_header)) { 951 m_freem(m); 952 continue; 953 } 954 m->m_pkthdr.rcvif = ifp; 955 m->m_pkthdr.len = m->m_len = size; 956 eh = mtod(m, struct ether_header *); 957 #ifdef TLDEBUG_RX 958 printf("tl_intr: Rx packet:\n"); 959 ether_printheader(eh); 960 #endif 961 #if NBPFILTER > 0 962 if (ifp->if_bpf) { 963 bpf_tap(ifp->if_bpf, 964 mtod(m, caddr_t), size); 965 /* 966 * Only pass this packet up 967 * if it is for us. 968 */ 969 if ((ifp->if_flags & IFF_PROMISC) && 970 /* !mcast and !bcast */ 971 (eh->ether_dhost[0] & 1) == 0 && 972 bcmp(eh->ether_dhost, 973 LLADDR(ifp->if_sadl), 974 sizeof(eh->ether_dhost)) != 0) { 975 m_freem(m); 976 continue; 977 } 978 } 979 #endif /* NBPFILTER > 0 */ 980 (*ifp->if_input)(ifp, m); 981 } 982 } 983 #ifdef TLDEBUG_RX 984 printf("TL_INTR_RxEOF: ack %d\n", ack); 985 #else 986 if (ack == 0) { 987 printf("%s: EOF intr without anything to read !\n", 988 sc->sc_dev.dv_xname); 989 tl_reset(sc); 990 /* shedule reinit of the board */ 991 callout_reset(&sc->tl_restart_ch, 1, tl_restart, sc); 992 return(1); 993 } 994 #endif 995 break; 996 case TL_INTR_RxEOC: 997 ack++; 998 #ifdef TLDEBUG_RX 999 printf("TL_INTR_RxEOC: ack %d\n", ack); 1000 #endif 1001 #ifdef DIAGNOSTIC 1002 if (sc->active_Rx->hw_list.stat & TL_RX_CSTAT_CPLT) { 1003 printf("%s: Rx EOC interrupt and active Rx list not " 1004 "cleared\n", sc->sc_dev.dv_xname); 1005 return 0; 1006 } else 1007 #endif 1008 { 1009 /* 1010 * write adress of Rx list and send Rx GO command, ack 1011 * interrupt and enable interrupts in one command 1012 */ 1013 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 1014 vtophys(&sc->active_Rx->hw_list)); 1015 TL_HR_WRITE(sc, TL_HOST_CMD, 1016 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type | 1017 HOST_CMD_ACK | HOST_CMD_IntOn); 1018 return 1; 1019 } 1020 case TL_INTR_TxEOF: 1021 case TL_INTR_TxEOC: 1022 while ((Tx = sc->active_Tx) != NULL) { 1023 if((Tx->hw_list.stat & TL_TX_CSTAT_CPLT) == 0) 1024 break; 1025 ack++; 1026 #ifdef TLDEBUG_TX 1027 printf("TL_INTR_TxEOC: list 0x%xp done\n", 1028 vtophys(&Tx->hw_list)); 1029 #endif 1030 Tx->hw_list.stat = 0; 1031 m_freem(Tx->m); 1032 Tx->m = NULL; 1033 sc->active_Tx = Tx->next; 1034 if (sc->active_Tx == NULL) 1035 sc->last_Tx = NULL; 1036 Tx->next = sc->Free_Tx; 1037 sc->Free_Tx = Tx; 1038 } 1039 /* if this was an EOC, ACK immediatly */ 1040 if (int_type == TL_INTR_TxEOC) { 1041 #ifdef TLDEBUG_TX 1042 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n", 1043 ack); 1044 #endif 1045 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type | 1046 HOST_CMD_ACK | HOST_CMD_IntOn); 1047 if ( sc->active_Tx != NULL) { 1048 /* needs a Tx go command */ 1049 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 1050 vtophys(&sc->active_Tx->hw_list)); 1051 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1052 } 1053 sc->tl_if.if_timer = 0; 1054 if (sc->tl_if.if_snd.ifq_head != NULL) 1055 tl_ifstart(&sc->tl_if); 1056 return 1; 1057 } 1058 #ifdef TLDEBUG 1059 else { 1060 printf("TL_INTR_TxEOF: ack %d\n", ack); 1061 } 1062 #endif 1063 sc->tl_if.if_timer = 0; 1064 if (sc->tl_if.if_snd.ifq_head != NULL) 1065 tl_ifstart(&sc->tl_if); 1066 break; 1067 case TL_INTR_Stat: 1068 ack++; 1069 #ifdef TLDEBUG 1070 printf("TL_INTR_Stat: ack %d\n", ack); 1071 #endif 1072 tl_read_stats(sc); 1073 break; 1074 case TL_INTR_Adc: 1075 if (int_reg & TL_INTVec_MASK) { 1076 /* adapter check conditions */ 1077 printf("%s: check condition, intvect=0x%x, " 1078 "ch_param=0x%x\n", sc->sc_dev.dv_xname, 1079 int_reg & TL_INTVec_MASK, 1080 TL_HR_READ(sc, TL_HOST_CH_PARM)); 1081 tl_reset(sc); 1082 /* shedule reinit of the board */ 1083 callout_reset(&sc->tl_restart_ch, 1, tl_restart, sc); 1084 return(1); 1085 } else { 1086 u_int8_t netstat; 1087 /* Network status */ 1088 netstat = 1089 tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts); 1090 printf("%s: network status, NetSts=%x\n", 1091 sc->sc_dev.dv_xname, netstat); 1092 /* Ack interrupts */ 1093 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts, 1094 netstat); 1095 ack++; 1096 } 1097 break; 1098 default: 1099 printf("%s: unhandled interrupt code %x!\n", 1100 sc->sc_dev.dv_xname, int_type); 1101 ack++; 1102 } 1103 1104 if (ack) { 1105 /* Ack the interrupt and enable interrupts */ 1106 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK | 1107 HOST_CMD_IntOn); 1108 return 1; 1109 } 1110 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */ 1111 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn); 1112 return 0; 1113 } 1114 1115 static int 1116 tl_ifioctl(ifp, cmd, data) 1117 struct ifnet *ifp; 1118 ioctl_cmd_t cmd; 1119 caddr_t data; 1120 { 1121 struct tl_softc *sc = ifp->if_softc; 1122 struct ifreq *ifr = (struct ifreq *)data; 1123 int s, error; 1124 1125 s = splnet(); 1126 switch(cmd) { 1127 case SIOCSIFADDR: { 1128 struct ifaddr *ifa = (struct ifaddr *)data; 1129 sc->tl_if.if_flags |= IFF_UP; 1130 if ((error = tl_init(sc)) != NULL) { 1131 sc->tl_if.if_flags &= ~IFF_UP; 1132 break; 1133 } 1134 switch (ifa->ifa_addr->sa_family) { 1135 #ifdef INET 1136 case AF_INET: 1137 arp_ifinit(ifp, ifa); 1138 break; 1139 #endif 1140 #ifdef NS 1141 case AF_NS: { 1142 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1143 1144 if (ns_nullhost(*ina)) 1145 ina->x_host = 1146 *(union ns_host*) LLADDR(ifp->if_sadl); 1147 else 1148 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1149 ifp->if_addrlen); 1150 break; 1151 } 1152 #endif 1153 default: 1154 break; 1155 } 1156 break; 1157 } 1158 case SIOCSIFFLAGS: 1159 { 1160 u_int8_t reg; 1161 /* 1162 * If interface is marked up and not running, then start it. 1163 * If it is marked down and running, stop it. 1164 */ 1165 if (ifp->if_flags & IFF_UP) { 1166 if ((ifp->if_flags & IFF_RUNNING) == 0) { 1167 error = tl_init(sc); 1168 /* all flags have been handled by init */ 1169 break; 1170 } 1171 error = 0; 1172 reg = tl_intreg_read_byte(sc, 1173 TL_INT_NET + TL_INT_NetCmd); 1174 if (ifp->if_flags & IFF_PROMISC) 1175 reg |= TL_NETCOMMAND_CAF; 1176 else 1177 reg &= ~TL_NETCOMMAND_CAF; 1178 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 1179 reg); 1180 #ifdef TL_PRIV_STATS 1181 if (ifp->if_flags & IFF_LINK0) { 1182 ifp->if_flags &= ~IFF_LINK0; 1183 printf("%s errors statistics\n", 1184 sc->sc_dev.dv_xname); 1185 printf(" %4d RX buffer overrun\n", 1186 sc->ierr_overr); 1187 printf(" %4d RX code error\n", 1188 sc->ierr_code); 1189 printf(" %4d RX crc error\n", 1190 sc->ierr_crc); 1191 printf(" %4d RX out of memory\n", 1192 sc->ierr_nomem); 1193 printf(" %4d TX buffer underrun\n", 1194 sc->oerr_underr); 1195 printf(" %4d TX deffered frames\n", 1196 sc->oerr_deffered); 1197 printf(" %4d TX single collisions\n", 1198 sc->oerr_coll); 1199 printf(" %4d TX multi collisions\n", 1200 sc->oerr_multicoll); 1201 printf(" %4d TX exessive collisions\n", 1202 sc->oerr_exesscoll); 1203 printf(" %4d TX late collisions\n", 1204 sc->oerr_latecoll); 1205 printf(" %4d TX carrier loss\n", 1206 sc->oerr_carrloss); 1207 printf(" %4d TX mbuf copy\n", 1208 sc->oerr_mcopy); 1209 } 1210 #endif 1211 } else { 1212 if (ifp->if_flags & IFF_RUNNING) 1213 tl_shutdown(sc); 1214 error = 0; 1215 } 1216 break; 1217 } 1218 case SIOCADDMULTI: 1219 case SIOCDELMULTI: 1220 /* 1221 * Update multicast listeners 1222 */ 1223 if (cmd == SIOCADDMULTI) 1224 error = ether_addmulti(ifr, &sc->tl_ec); 1225 else 1226 error = ether_delmulti(ifr, &sc->tl_ec); 1227 if (error == ENETRESET) { 1228 tl_addr_filter(sc); 1229 error = 0; 1230 } 1231 break; 1232 case SIOCSIFMEDIA: 1233 case SIOCGIFMEDIA: 1234 error = ifmedia_ioctl(ifp, ifr, &sc->tl_mii.mii_media, cmd); 1235 break; 1236 default: 1237 error = EINVAL; 1238 } 1239 splx(s); 1240 return error; 1241 } 1242 1243 static void 1244 tl_ifstart(ifp) 1245 struct ifnet *ifp; 1246 { 1247 tl_softc_t *sc = ifp->if_softc; 1248 struct mbuf *m, *mb_head; 1249 struct Tx_list *Tx; 1250 int segment, size; 1251 1252 txloop: 1253 /* If we don't have more space ... */ 1254 if (sc->Free_Tx == NULL) { 1255 #ifdef TLDEBUG 1256 printf("tl_ifstart: No free TX list\n"); 1257 #endif 1258 return; 1259 } 1260 /* Grab a paquet for output */ 1261 IF_DEQUEUE(&ifp->if_snd, mb_head); 1262 if (mb_head == NULL) { 1263 #ifdef TLDEBUG_TX 1264 printf("tl_ifstart: nothing to send\n"); 1265 #endif 1266 return; 1267 } 1268 Tx = sc->Free_Tx; 1269 sc->Free_Tx = Tx->next; 1270 /* 1271 * Go through each of the mbufs in the chain and initialize 1272 * the transmit list descriptors with the physical address 1273 * and size of the mbuf. 1274 */ 1275 tbdinit: 1276 bzero(Tx, sizeof(struct Tx_list)); 1277 Tx->m = mb_head; 1278 size = 0; 1279 for (m = mb_head, segment = 0; m != NULL ; m = m->m_next) { 1280 if (m->m_len != 0) { 1281 if (segment == TL_NSEG) 1282 break; 1283 size += m->m_len; 1284 Tx->hw_list.seg[segment].data_addr = 1285 vtophys(mtod(m, vaddr_t)); 1286 Tx->hw_list.seg[segment].data_count = m->m_len; 1287 segment++; 1288 } 1289 } 1290 if (m != NULL || (size < ETHER_MIN_TX && segment == TL_NSEG)) { 1291 /* 1292 * We ran out of segments, or we will. We have to recopy this 1293 * mbuf chain first. 1294 */ 1295 struct mbuf *mn; 1296 #ifdef TLDEBUG_TX 1297 printf("tl_ifstart: need to copy mbuf\n"); 1298 #endif 1299 #ifdef TL_PRIV_STATS 1300 sc->oerr_mcopy++; 1301 #endif 1302 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1303 if (mn == NULL) { 1304 m_freem(mb_head); 1305 goto bad; 1306 } 1307 if (mb_head->m_pkthdr.len > MHLEN) { 1308 MCLGET(mn, M_DONTWAIT); 1309 if ((mn->m_flags & M_EXT) == 0) { 1310 m_freem(mn); 1311 m_freem(mb_head); 1312 goto bad; 1313 } 1314 } 1315 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1316 mtod(mn, caddr_t)); 1317 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1318 m_freem(mb_head); 1319 mb_head = mn; 1320 goto tbdinit; 1321 } 1322 /* We are at end of mbuf chain. check the size and 1323 * see if it needs to be extended 1324 */ 1325 if (size < ETHER_MIN_TX) { 1326 #ifdef DIAGNOSTIC 1327 if (segment >= TL_NSEG) { 1328 panic("tl_ifstart: to much segmets (%d)\n", segment); 1329 } 1330 #endif 1331 /* 1332 * add the nullbuf in the seg 1333 */ 1334 Tx->hw_list.seg[segment].data_count = 1335 ETHER_MIN_TX - size; 1336 Tx->hw_list.seg[segment].data_addr = 1337 vtophys(nullbuf); 1338 size = ETHER_MIN_TX; 1339 segment++; 1340 } 1341 /* The list is done, finish the list init */ 1342 Tx->hw_list.seg[segment-1].data_count |= 1343 TL_LAST_SEG; 1344 Tx->hw_list.stat = (size << 16) | 0x3000; 1345 #ifdef TLDEBUG_TX 1346 printf("%s: sending, Tx : stat = 0x%x\n", sc->sc_dev.dv_xname, 1347 Tx->hw_list.stat); 1348 #if 0 1349 for(segment = 0; segment < TL_NSEG; segment++) { 1350 printf(" seg %d addr 0x%x len 0x%x\n", 1351 segment, 1352 Tx->hw_list.seg[segment].data_addr, 1353 Tx->hw_list.seg[segment].data_count); 1354 } 1355 #endif 1356 #endif 1357 sc->opkt++; 1358 if (sc->active_Tx == NULL) { 1359 sc->active_Tx = sc->last_Tx = Tx; 1360 #ifdef TLDEBUG_TX 1361 printf("%s: Tx GO, addr=0x%x\n", sc->sc_dev.dv_xname, 1362 vtophys(&Tx->hw_list)); 1363 #endif 1364 TL_HR_WRITE(sc, TL_HOST_CH_PARM, vtophys(&Tx->hw_list)); 1365 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1366 } else { 1367 #ifdef TLDEBUG_TX 1368 printf("%s: Tx addr=0x%x queued\n", sc->sc_dev.dv_xname, 1369 vtophys(&Tx->hw_list)); 1370 #endif 1371 sc->last_Tx->hw_list.fwd = vtophys(&Tx->hw_list); 1372 sc->last_Tx->next = Tx; 1373 sc->last_Tx = Tx; 1374 #ifdef DIAGNOSTIC 1375 if (sc->last_Tx->hw_list.fwd & 0x7) 1376 printf("%s: physical addr 0x%x of list not properly " 1377 "aligned\n", 1378 sc->sc_dev.dv_xname, sc->last_Rx->hw_list.fwd); 1379 #endif 1380 } 1381 #if NBPFILTER > 0 1382 /* Pass packet to bpf if there is a listener */ 1383 if (ifp->if_bpf) 1384 bpf_mtap(ifp->if_bpf, mb_head); 1385 #endif 1386 /* 1387 * Set a 5 second timer just in case we don't hear from the card again. 1388 */ 1389 ifp->if_timer = 5; 1390 goto txloop; 1391 bad: 1392 #ifdef TLDEBUG 1393 printf("tl_ifstart: Out of mbuf, Tx pkt lost\n"); 1394 #endif 1395 Tx->next = sc->Free_Tx; 1396 sc->Free_Tx = Tx; 1397 return; 1398 } 1399 1400 static void 1401 tl_ifwatchdog(ifp) 1402 struct ifnet *ifp; 1403 { 1404 tl_softc_t *sc = ifp->if_softc; 1405 1406 if ((ifp->if_flags & IFF_RUNNING) == 0) 1407 return; 1408 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1409 ifp->if_oerrors++; 1410 tl_init(sc); 1411 } 1412 1413 static int 1414 tl_mediachange(ifp) 1415 struct ifnet *ifp; 1416 { 1417 1418 if (ifp->if_flags & IFF_UP) 1419 tl_init(ifp->if_softc); 1420 return (0); 1421 } 1422 1423 static void 1424 tl_mediastatus(ifp, ifmr) 1425 struct ifnet *ifp; 1426 struct ifmediareq *ifmr; 1427 { 1428 tl_softc_t *sc = ifp->if_softc; 1429 1430 mii_pollstat(&sc->tl_mii); 1431 ifmr->ifm_active = sc->tl_mii.mii_media_active; 1432 ifmr->ifm_status = sc->tl_mii.mii_media_status; 1433 } 1434 1435 static int tl_add_RxBuff(Rx, oldm) 1436 struct Rx_list *Rx; 1437 struct mbuf *oldm; 1438 { 1439 struct mbuf *m; 1440 1441 MGETHDR(m, M_DONTWAIT, MT_DATA); 1442 if (m != NULL) { 1443 MCLGET(m, M_DONTWAIT); 1444 if ((m->m_flags & M_EXT) == 0) { 1445 m_freem(m); 1446 if (oldm == NULL) 1447 return 0; 1448 m = oldm; 1449 m->m_data = m->m_ext.ext_buf; 1450 } 1451 } else { 1452 if (oldm == NULL) 1453 return 0; 1454 m = oldm; 1455 m->m_data = m->m_ext.ext_buf; 1456 } 1457 /* 1458 * Move the data pointer up so that the incoming data packet 1459 * will be 32-bit aligned. 1460 */ 1461 m->m_data += 2; 1462 1463 /* (re)init the Rx_list struct */ 1464 1465 Rx->m = m; 1466 Rx->hw_list.stat = ((MCLBYTES -2) << 16) | 0x3000; 1467 Rx->hw_list.seg.data_count = (MCLBYTES -2); 1468 Rx->hw_list.seg.data_addr = vtophys(m->m_data); 1469 return (m != oldm); 1470 } 1471 1472 static void tl_ticks(v) 1473 void *v; 1474 { 1475 tl_softc_t *sc = v; 1476 1477 tl_read_stats(sc); 1478 1479 /* Tick the MII. */ 1480 mii_tick(&sc->tl_mii); 1481 1482 if (sc->opkt > 0) { 1483 if (sc->oerr_exesscoll > sc->opkt / 100) { 1484 /* exess collisions */ 1485 if (sc->tl_flags & TL_IFACT) /* only print once */ 1486 printf("%s: no carrier\n", 1487 sc->sc_dev.dv_xname); 1488 sc->tl_flags &= ~TL_IFACT; 1489 } else 1490 sc->tl_flags |= TL_IFACT; 1491 sc->oerr_exesscoll = sc->opkt = 0; 1492 sc->tl_lasttx = 0; 1493 } else { 1494 sc->tl_lasttx++; 1495 if (sc->tl_lasttx >= TL_IDLETIME) { 1496 /* 1497 * No TX activity in the last TL_IDLETIME seconds. 1498 * sends a LLC Class1 TEST pkt 1499 */ 1500 struct mbuf *m; 1501 int s; 1502 MGETHDR(m, M_DONTWAIT, MT_DATA); 1503 if (m != NULL) { 1504 #ifdef TLDEBUG 1505 printf("tl_ticks: sending LLC test pkt\n"); 1506 #endif 1507 bcopy(sc->tl_enaddr, 1508 mtod(m, struct ether_header *)->ether_dhost, 1509 6); 1510 bcopy(sc->tl_enaddr, 1511 mtod(m, struct ether_header *)->ether_shost, 1512 6); 1513 mtod(m, struct ether_header *)->ether_type = 1514 htons(3); 1515 mtod(m, unsigned char *)[14] = 0; 1516 mtod(m, unsigned char *)[15] = 0; 1517 mtod(m, unsigned char *)[16] = 0xE3; 1518 /* LLC Class1 TEST (no poll) */ 1519 m->m_len = m->m_pkthdr.len = 1520 sizeof(struct ether_header) + 3; 1521 s = splnet(); 1522 IF_PREPEND(&sc->tl_if.if_snd, m); 1523 tl_ifstart(&sc->tl_if); 1524 splx(s); 1525 } 1526 } 1527 } 1528 1529 /* read statistics every seconds */ 1530 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 1531 } 1532 1533 static void 1534 tl_read_stats(sc) 1535 tl_softc_t *sc; 1536 { 1537 u_int32_t reg; 1538 int ierr_overr; 1539 int ierr_code; 1540 int ierr_crc; 1541 int oerr_underr; 1542 int oerr_deffered; 1543 int oerr_coll; 1544 int oerr_multicoll; 1545 int oerr_exesscoll; 1546 int oerr_latecoll; 1547 int oerr_carrloss; 1548 struct ifnet *ifp = &sc->tl_if; 1549 1550 reg = tl_intreg_read(sc, TL_INT_STATS_TX); 1551 ifp->if_opackets += reg & 0x00ffffff; 1552 oerr_underr = reg >> 24; 1553 1554 reg = tl_intreg_read(sc, TL_INT_STATS_RX); 1555 ifp->if_ipackets += reg & 0x00ffffff; 1556 ierr_overr = reg >> 24; 1557 1558 reg = tl_intreg_read(sc, TL_INT_STATS_FERR); 1559 ierr_crc = (reg & TL_FERR_CRC) >> 16; 1560 ierr_code = (reg & TL_FERR_CODE) >> 24; 1561 oerr_deffered = (reg & TL_FERR_DEF); 1562 1563 reg = tl_intreg_read(sc, TL_INT_STATS_COLL); 1564 oerr_multicoll = (reg & TL_COL_MULTI); 1565 oerr_coll = (reg & TL_COL_SINGLE) >> 16; 1566 1567 reg = tl_intreg_read(sc, TL_INT_LERR); 1568 oerr_exesscoll = (reg & TL_LERR_ECOLL); 1569 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8; 1570 oerr_carrloss = (reg & TL_LERR_CL) >> 16; 1571 1572 1573 sc->stats_exesscoll += oerr_exesscoll; 1574 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll + 1575 oerr_carrloss; 1576 ifp->if_collisions += oerr_coll + oerr_multicoll; 1577 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc; 1578 1579 if (ierr_overr) 1580 printf("%s: receiver ring buffer overrun\n", 1581 sc->sc_dev.dv_xname); 1582 if (oerr_underr) 1583 printf("%s: transmit buffer underrun\n", 1584 sc->sc_dev.dv_xname); 1585 #ifdef TL_PRIV_STATS 1586 sc->ierr_overr += ierr_overr; 1587 sc->ierr_code += ierr_code; 1588 sc->ierr_crc += ierr_crc; 1589 sc->oerr_underr += oerr_underr; 1590 sc->oerr_deffered += oerr_deffered; 1591 sc->oerr_coll += oerr_coll; 1592 sc->oerr_multicoll += oerr_multicoll; 1593 sc->oerr_exesscoll += oerr_exesscoll; 1594 sc->oerr_latecoll += oerr_latecoll; 1595 sc->oerr_carrloss += oerr_carrloss; 1596 #endif 1597 } 1598 1599 static void tl_addr_filter(sc) 1600 tl_softc_t *sc; 1601 { 1602 struct ether_multistep step; 1603 struct ether_multi *enm; 1604 u_int32_t hash[2] = {0, 0}; 1605 int i; 1606 1607 sc->tl_if.if_flags &= ~IFF_ALLMULTI; 1608 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm); 1609 while (enm != NULL) { 1610 #ifdef TLDEBUG 1611 printf("tl_addr_filter: addrs %s %s\n", 1612 ether_sprintf(enm->enm_addrlo), 1613 ether_sprintf(enm->enm_addrhi)); 1614 #endif 1615 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1616 i = tl_multicast_hash(enm->enm_addrlo); 1617 hash[i/32] |= 1 << (i%32); 1618 } else { 1619 hash[0] = hash[1] = 0xffffffff; 1620 sc->tl_if.if_flags |= IFF_ALLMULTI; 1621 break; 1622 } 1623 ETHER_NEXT_MULTI(step, enm); 1624 } 1625 #ifdef TLDEBUG 1626 printf("tl_addr_filer: hash1 %x has2 %x\n", hash[0], hash[1]); 1627 #endif 1628 tl_intreg_write(sc, TL_INT_HASH1, hash[0]); 1629 tl_intreg_write(sc, TL_INT_HASH2, hash[1]); 1630 } 1631 1632 static int tl_multicast_hash(a) 1633 u_int8_t *a; 1634 { 1635 int hash; 1636 1637 #define DA(addr,bit) (addr[5 - (bit/8)] & (1 << bit%8)) 1638 #define xor8(a,b,c,d,e,f,g,h) (((a != 0) + (b != 0) + (c != 0) + (d != 0) + (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1639 1640 hash = xor8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1641 DA(a,36), DA(a,42)); 1642 hash |= xor8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1643 DA(a,37), DA(a,43)) << 1; 1644 hash |= xor8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1645 DA(a,38), DA(a,44)) << 2; 1646 hash |= xor8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1647 DA(a,39), DA(a,45)) << 3; 1648 hash |= xor8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1649 DA(a,40), DA(a,46)) << 4; 1650 hash |= xor8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1651 DA(a,41), DA(a,47)) << 5; 1652 1653 return hash; 1654 } 1655 1656 #if defined(TLDEBUG_RX) 1657 void 1658 ether_printheader(eh) 1659 struct ether_header *eh; 1660 { 1661 u_char *c = (char*)eh; 1662 int i; 1663 for (i=0; i<sizeof(struct ether_header); i++) 1664 printf("%x ", (u_int)c[i]); 1665 printf("\n"); 1666 } 1667 #endif 1668