1 /* $NetBSD: if_tl.c,v 1.56 2002/10/02 16:51:33 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Texas Instruments ThunderLAN ethernet controller 34 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A) 35 * available from www.ti.com 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_tl.c,v 1.56 2002/10/02 16:51:33 thorpej Exp $"); 40 41 #undef TLDEBUG 42 #define TL_PRIV_STATS 43 #undef TLDEBUG_RX 44 #undef TLDEBUG_TX 45 #undef TLDEBUG_ADDR 46 47 #include "opt_inet.h" 48 #include "opt_ns.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/mbuf.h> 53 #include <sys/protosw.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/malloc.h> 58 #include <sys/kernel.h> 59 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 60 #include <sys/device.h> 61 62 #include <net/if.h> 63 #if defined(SIOCSIFMEDIA) 64 #include <net/if_media.h> 65 #endif 66 #include <net/if_types.h> 67 #include <net/if_dl.h> 68 #include <net/route.h> 69 #include <net/netisr.h> 70 71 #include "bpfilter.h" 72 #if NBPFILTER > 0 73 #include <net/bpf.h> 74 #include <net/bpfdesc.h> 75 #endif 76 77 #ifdef INET 78 #include <netinet/in.h> 79 #include <netinet/in_systm.h> 80 #include <netinet/in_var.h> 81 #include <netinet/ip.h> 82 #endif 83 84 #ifdef NS 85 #include <netns/ns.h> 86 #include <netns/ns_if.h> 87 #endif 88 89 #if defined(__NetBSD__) 90 #include <net/if_ether.h> 91 #include <uvm/uvm_extern.h> 92 #if defined(INET) 93 #include <netinet/if_inarp.h> 94 #endif 95 96 #include <machine/bus.h> 97 #include <machine/intr.h> 98 99 #include <dev/pci/pcireg.h> 100 #include <dev/pci/pcivar.h> 101 #include <dev/pci/pcidevs.h> 102 103 #include <dev/i2c/i2c_bus.h> 104 #include <dev/i2c/i2c_eeprom.h> 105 106 #include <dev/mii/mii.h> 107 #include <dev/mii/miivar.h> 108 109 #include <dev/mii/tlphyvar.h> 110 111 #include <dev/pci/if_tlregs.h> 112 #include <dev/pci/if_tlvar.h> 113 #endif /* __NetBSD__ */ 114 115 /* number of transmit/receive buffers */ 116 #ifndef TL_NBUF 117 #define TL_NBUF 10 118 #endif 119 120 static int tl_pci_match __P((struct device *, struct cfdata *, void *)); 121 static void tl_pci_attach __P((struct device *, struct device *, void *)); 122 static int tl_intr __P((void *)); 123 124 static int tl_ifioctl __P((struct ifnet *, ioctl_cmd_t, caddr_t)); 125 static int tl_mediachange __P((struct ifnet *)); 126 static void tl_mediastatus __P((struct ifnet *, struct ifmediareq *)); 127 static void tl_ifwatchdog __P((struct ifnet *)); 128 static void tl_shutdown __P((void*)); 129 130 static void tl_ifstart __P((struct ifnet *)); 131 static void tl_reset __P((tl_softc_t*)); 132 static int tl_init __P((struct ifnet *)); 133 static void tl_stop __P((struct ifnet *, int)); 134 static void tl_restart __P((void *)); 135 static int tl_add_RxBuff __P((tl_softc_t*, struct Rx_list*, struct mbuf*)); 136 static void tl_read_stats __P((tl_softc_t*)); 137 static void tl_ticks __P((void*)); 138 static int tl_multicast_hash __P((u_int8_t*)); 139 static void tl_addr_filter __P((tl_softc_t*)); 140 141 static u_int32_t tl_intreg_read __P((tl_softc_t*, u_int32_t)); 142 static void tl_intreg_write __P((tl_softc_t*, u_int32_t, u_int32_t)); 143 static u_int8_t tl_intreg_read_byte __P((tl_softc_t*, u_int32_t)); 144 static void tl_intreg_write_byte __P((tl_softc_t*, u_int32_t, u_int8_t)); 145 146 void tl_mii_sync __P((struct tl_softc *)); 147 void tl_mii_sendbits __P((struct tl_softc *, u_int32_t, int)); 148 149 150 #if defined(TLDEBUG_RX) 151 static void ether_printheader __P((struct ether_header*)); 152 #endif 153 154 int tl_mii_read __P((struct device *, int, int)); 155 void tl_mii_write __P((struct device *, int, int, int)); 156 157 void tl_statchg __P((struct device *)); 158 159 void tl_i2c_set __P((void*, u_int8_t)); 160 void tl_i2c_clr __P((void*, u_int8_t)); 161 int tl_i2c_read __P((void*, u_int8_t)); 162 163 static __inline void netsio_clr __P((tl_softc_t*, u_int8_t)); 164 static __inline void netsio_set __P((tl_softc_t*, u_int8_t)); 165 static __inline u_int8_t netsio_read __P((tl_softc_t*, u_int8_t)); 166 static __inline void netsio_clr(sc, bits) 167 tl_softc_t* sc; 168 u_int8_t bits; 169 { 170 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 171 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits)); 172 } 173 static __inline void netsio_set(sc, bits) 174 tl_softc_t* sc; 175 u_int8_t bits; 176 { 177 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 178 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits); 179 } 180 static __inline u_int8_t netsio_read(sc, bits) 181 tl_softc_t* sc; 182 u_int8_t bits; 183 { 184 return (tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits); 185 } 186 187 CFATTACH_DECL(tl, sizeof(tl_softc_t), 188 tl_pci_match, tl_pci_attach, NULL, NULL); 189 190 const struct tl_product_desc tl_compaq_products[] = { 191 { PCI_PRODUCT_COMPAQ_N100TX, TLPHY_MEDIA_NO_10_T, 192 "Compaq Netelligent 10/100 TX" }, 193 { PCI_PRODUCT_COMPAQ_N10T, TLPHY_MEDIA_10_5, 194 "Compaq Netelligent 10 T" }, 195 { PCI_PRODUCT_COMPAQ_IntNF3P, TLPHY_MEDIA_10_2, 196 "Compaq Integrated NetFlex 3/P" }, 197 { PCI_PRODUCT_COMPAQ_IntPL100TX, TLPHY_MEDIA_10_2|TLPHY_MEDIA_NO_10_T, 198 "Compaq ProLiant Integrated Netelligent 10/100 TX" }, 199 { PCI_PRODUCT_COMPAQ_DPNet100TX, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 200 "Compaq Dual Port Netelligent 10/100 TX" }, 201 { PCI_PRODUCT_COMPAQ_DP4000, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 202 "Compaq Deskpro 4000 5233MMX" }, 203 { PCI_PRODUCT_COMPAQ_NF3P_BNC, TLPHY_MEDIA_10_2, 204 "Compaq NetFlex 3/P w/ BNC" }, 205 { PCI_PRODUCT_COMPAQ_NF3P, TLPHY_MEDIA_10_5, 206 "Compaq NetFlex 3/P" }, 207 { 0, 0, NULL }, 208 }; 209 210 const struct tl_product_desc tl_ti_products[] = { 211 /* 212 * Built-in Ethernet on the TI TravelMate 5000 213 * docking station; better product description? 214 */ 215 { PCI_PRODUCT_TI_TLAN, 0, 216 "Texas Instruments ThunderLAN" }, 217 { 0, 0, NULL }, 218 }; 219 220 struct tl_vendor_desc { 221 u_int32_t tv_vendor; 222 const struct tl_product_desc *tv_products; 223 }; 224 225 const struct tl_vendor_desc tl_vendors[] = { 226 { PCI_VENDOR_COMPAQ, tl_compaq_products }, 227 { PCI_VENDOR_TI, tl_ti_products }, 228 { 0, NULL }, 229 }; 230 231 const struct tl_product_desc *tl_lookup_product __P((u_int32_t)); 232 233 const struct tl_product_desc * 234 tl_lookup_product(id) 235 u_int32_t id; 236 { 237 const struct tl_product_desc *tp; 238 const struct tl_vendor_desc *tv; 239 240 for (tv = tl_vendors; tv->tv_products != NULL; tv++) 241 if (PCI_VENDOR(id) == tv->tv_vendor) 242 break; 243 244 if ((tp = tv->tv_products) == NULL) 245 return (NULL); 246 247 for (; tp->tp_desc != NULL; tp++) 248 if (PCI_PRODUCT(id) == tp->tp_product) 249 break; 250 251 if (tp->tp_desc == NULL) 252 return (NULL); 253 254 return (tp); 255 } 256 257 static int 258 tl_pci_match(parent, match, aux) 259 struct device *parent; 260 struct cfdata *match; 261 void *aux; 262 { 263 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 264 265 if (tl_lookup_product(pa->pa_id) != NULL) 266 return (1); 267 268 return (0); 269 } 270 271 static void 272 tl_pci_attach(parent, self, aux) 273 struct device * parent; 274 struct device * self; 275 void * aux; 276 { 277 tl_softc_t *sc = (tl_softc_t *)self; 278 struct pci_attach_args * const pa = (struct pci_attach_args *) aux; 279 const struct tl_product_desc *tp; 280 struct ifnet * const ifp = &sc->tl_if; 281 bus_space_tag_t iot, memt; 282 bus_space_handle_t ioh, memh; 283 pci_intr_handle_t intrhandle; 284 const char *intrstr; 285 int i, tmp, ioh_valid, memh_valid; 286 int reg_io, reg_mem; 287 pcireg_t reg10, reg14; 288 pcireg_t csr; 289 290 printf("\n"); 291 292 callout_init(&sc->tl_tick_ch); 293 callout_init(&sc->tl_restart_ch); 294 295 tp = tl_lookup_product(pa->pa_id); 296 if (tp == NULL) 297 panic("tl_pci_attach: impossible"); 298 sc->tl_product = tp; 299 300 /* 301 * Map the card space. First we have to find the I/O and MEM 302 * registers. I/O is supposed to be at 0x10, MEM at 0x14, 303 * but some boards (Compaq Netflex 3/P PCI) seem to have it reversed. 304 * The ThunderLAN manual is not consistent about this either (there 305 * are both cases in code examples). 306 */ 307 reg10 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x10); 308 reg14 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x14); 309 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_IO) 310 reg_io = 0x10; 311 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_IO) 312 reg_io = 0x14; 313 else 314 reg_io = 0; 315 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_MEM) 316 reg_mem = 0x10; 317 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_MEM) 318 reg_mem = 0x14; 319 else 320 reg_mem = 0; 321 322 if (reg_io != 0) 323 ioh_valid = (pci_mapreg_map(pa, reg_io, PCI_MAPREG_TYPE_IO, 324 0, &iot, &ioh, NULL, NULL) == 0); 325 else 326 ioh_valid = 0; 327 if (reg_mem != 0) 328 memh_valid = (pci_mapreg_map(pa, PCI_CBMA, 329 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 330 0, &memt, &memh, NULL, NULL) == 0); 331 else 332 memh_valid = 0; 333 334 if (ioh_valid) { 335 sc->tl_bustag = iot; 336 sc->tl_bushandle = ioh; 337 } else if (memh_valid) { 338 sc->tl_bustag = memt; 339 sc->tl_bushandle = memh; 340 } else { 341 printf("%s: unable to map device registers\n", 342 sc->sc_dev.dv_xname); 343 return; 344 } 345 sc->tl_dmatag = pa->pa_dmat; 346 347 /* Enable the device. */ 348 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 349 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 350 csr | PCI_COMMAND_MASTER_ENABLE); 351 352 printf("%s: %s\n", sc->sc_dev.dv_xname, tp->tp_desc); 353 354 tl_reset(sc); 355 356 /* fill in the i2c struct */ 357 sc->i2cbus.adapter_softc = sc; 358 sc->i2cbus.set_bit = tl_i2c_set; 359 sc->i2cbus.clr_bit = tl_i2c_clr; 360 sc->i2cbus.read_bit = tl_i2c_read; 361 362 #ifdef TLDEBUG 363 printf("default values of INTreg: 0x%x\n", 364 tl_intreg_read(sc, TL_INT_Defaults)); 365 #endif 366 367 /* read mac addr */ 368 for (i=0; i<ETHER_ADDR_LEN; i++) { 369 tmp = i2c_eeprom_read(&sc->i2cbus, 0x83 + i); 370 if (tmp < 0) { 371 printf("%s: error reading Ethernet adress\n", 372 sc->sc_dev.dv_xname); 373 return; 374 } else { 375 sc->tl_enaddr[i] = tmp; 376 } 377 } 378 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 379 ether_sprintf(sc->tl_enaddr)); 380 381 /* Map and establish interrupts */ 382 if (pci_intr_map(pa, &intrhandle)) { 383 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 384 return; 385 } 386 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 387 sc->tl_if.if_softc = sc; 388 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 389 tl_intr, sc); 390 if (sc->tl_ih == NULL) { 391 printf("%s: couldn't establish interrupt", 392 sc->sc_dev.dv_xname); 393 if (intrstr != NULL) 394 printf(" at %s", intrstr); 395 printf("\n"); 396 return; 397 } 398 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 399 400 /* init these pointers, so that tl_shutdown won't try to read them */ 401 sc->Rx_list = NULL; 402 sc->Tx_list = NULL; 403 404 /* allocate DMA-safe memory for control structs */ 405 if (bus_dmamem_alloc(sc->tl_dmatag, 406 PAGE_SIZE, 0, PAGE_SIZE, 407 &sc->ctrl_segs, 1, &sc->ctrl_nsegs, BUS_DMA_NOWAIT) != 0 || 408 bus_dmamem_map(sc->tl_dmatag, &sc->ctrl_segs, 409 sc->ctrl_nsegs, PAGE_SIZE, (caddr_t*)&sc->ctrl, 410 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0) { 411 printf("%s: can't allocate DMA memory for lists\n", 412 sc->sc_dev.dv_xname); 413 return; 414 } 415 /* 416 * Add shutdown hook so that DMA is disabled prior to reboot. Not 417 * doing 418 * reboot before the driver initializes. 419 */ 420 (void) shutdownhook_establish(tl_shutdown, ifp); 421 422 /* 423 * Initialize our media structures and probe the MII. 424 * 425 * Note that we don't care about the media instance. We 426 * are expecting to have multiple PHYs on the 10/100 cards, 427 * and on those cards we exclude the internal PHY from providing 428 * 10baseT. By ignoring the instance, it allows us to not have 429 * to specify it on the command line when switching media. 430 */ 431 sc->tl_mii.mii_ifp = ifp; 432 sc->tl_mii.mii_readreg = tl_mii_read; 433 sc->tl_mii.mii_writereg = tl_mii_write; 434 sc->tl_mii.mii_statchg = tl_statchg; 435 ifmedia_init(&sc->tl_mii.mii_media, IFM_IMASK, tl_mediachange, 436 tl_mediastatus); 437 mii_attach(self, &sc->tl_mii, 0xffffffff, MII_PHY_ANY, 438 MII_OFFSET_ANY, 0); 439 if (LIST_FIRST(&sc->tl_mii.mii_phys) == NULL) { 440 ifmedia_add(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 441 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE); 442 } else 443 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_AUTO); 444 445 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 446 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 447 ifp->if_ioctl = tl_ifioctl; 448 ifp->if_start = tl_ifstart; 449 ifp->if_watchdog = tl_ifwatchdog; 450 ifp->if_init = tl_init; 451 ifp->if_stop = tl_stop; 452 ifp->if_timer = 0; 453 IFQ_SET_READY(&ifp->if_snd); 454 if_attach(ifp); 455 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr); 456 } 457 458 static void 459 tl_reset(sc) 460 tl_softc_t *sc; 461 { 462 int i; 463 464 /* read stats */ 465 if (sc->tl_if.if_flags & IFF_RUNNING) { 466 callout_stop(&sc->tl_tick_ch); 467 tl_read_stats(sc); 468 } 469 /* Reset adapter */ 470 TL_HR_WRITE(sc, TL_HOST_CMD, 471 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst); 472 DELAY(100000); 473 /* Disable interrupts */ 474 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 475 /* setup aregs & hash */ 476 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 477 tl_intreg_write(sc, i, 0); 478 #ifdef TLDEBUG_ADDR 479 printf("Areg & hash registers: \n"); 480 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 481 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 482 #endif 483 /* Setup NetConfig */ 484 tl_intreg_write(sc, TL_INT_NetConfig, 485 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN); 486 /* Bsize: accept default */ 487 /* TX commit in Acommit: accept default */ 488 /* Load Ld_tmr and Ld_thr */ 489 /* Ld_tmr = 3 */ 490 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr); 491 /* Ld_thr = 0 */ 492 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr); 493 /* Unreset MII */ 494 netsio_set(sc, TL_NETSIO_NMRST); 495 DELAY(100000); 496 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 497 } 498 499 static void tl_shutdown(v) 500 void *v; 501 { 502 tl_stop(v, 1); 503 } 504 505 static void tl_stop(ifp, disable) 506 struct ifnet *ifp; 507 int disable; 508 { 509 tl_softc_t *sc = ifp->if_softc; 510 struct Tx_list *Tx; 511 int i; 512 513 if ((ifp->if_flags & IFF_RUNNING) == 0) 514 return; 515 /* disable interrupts */ 516 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 517 /* stop TX and RX channels */ 518 TL_HR_WRITE(sc, TL_HOST_CMD, 519 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes); 520 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP); 521 DELAY(100000); 522 523 /* stop statistics reading loop, read stats */ 524 callout_stop(&sc->tl_tick_ch); 525 tl_read_stats(sc); 526 527 /* Down the MII. */ 528 mii_down(&sc->tl_mii); 529 530 /* deallocate memory allocations */ 531 if (sc->Rx_list) { 532 for (i=0; i< TL_NBUF; i++) { 533 if (sc->Rx_list[i].m) { 534 bus_dmamap_unload(sc->tl_dmatag, 535 sc->Rx_list[i].m_dmamap); 536 m_freem(sc->Rx_list[i].m); 537 } 538 bus_dmamap_destroy(sc->tl_dmatag, 539 sc->Rx_list[i].m_dmamap); 540 sc->Rx_list[i].m = NULL; 541 } 542 free(sc->Rx_list, M_DEVBUF); 543 sc->Rx_list = NULL; 544 bus_dmamap_unload(sc->tl_dmatag, sc->Rx_dmamap); 545 bus_dmamap_destroy(sc->tl_dmatag, sc->Rx_dmamap); 546 sc->hw_Rx_list = NULL; 547 while ((Tx = sc->active_Tx) != NULL) { 548 Tx->hw_list->stat = 0; 549 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 550 bus_dmamap_destroy(sc->tl_dmatag, Tx->m_dmamap); 551 m_freem(Tx->m); 552 sc->active_Tx = Tx->next; 553 Tx->next = sc->Free_Tx; 554 sc->Free_Tx = Tx; 555 } 556 sc->last_Tx = NULL; 557 free(sc->Tx_list, M_DEVBUF); 558 sc->Tx_list = NULL; 559 bus_dmamap_unload(sc->tl_dmatag, sc->Tx_dmamap); 560 bus_dmamap_destroy(sc->tl_dmatag, sc->Tx_dmamap); 561 sc->hw_Tx_list = NULL; 562 } 563 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 564 ifp->if_timer = 0; 565 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 566 } 567 568 static void tl_restart(v) 569 void *v; 570 { 571 tl_init(v); 572 } 573 574 static int tl_init(ifp) 575 struct ifnet *ifp; 576 { 577 tl_softc_t *sc = ifp->if_softc; 578 int i, s, error; 579 char *errstring; 580 char *nullbuf; 581 582 s = splnet(); 583 /* cancel any pending IO */ 584 tl_stop(ifp, 1); 585 tl_reset(sc); 586 if ((sc->tl_if.if_flags & IFF_UP) == 0) { 587 splx(s); 588 return 0; 589 } 590 /* Set various register to reasonable value */ 591 /* setup NetCmd in promisc mode if needed */ 592 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0; 593 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 594 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i); 595 /* Max receive size : MCLBYTES */ 596 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff); 597 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH, 598 (MCLBYTES >> 8) & 0xff); 599 600 /* init MAC addr */ 601 for (i = 0; i < ETHER_ADDR_LEN; i++) 602 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]); 603 /* add multicast filters */ 604 tl_addr_filter(sc); 605 #ifdef TLDEBUG_ADDR 606 printf("Wrote Mac addr, Areg & hash registers are now: \n"); 607 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 608 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 609 #endif 610 611 /* Pre-allocate receivers mbuf, make the lists */ 612 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF, 613 M_NOWAIT|M_ZERO); 614 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF, 615 M_NOWAIT|M_ZERO); 616 if (sc->Rx_list == NULL || sc->Tx_list == NULL) { 617 errstring = "out of memory for lists"; 618 error = ENOMEM; 619 goto bad; 620 } 621 error = bus_dmamap_create(sc->tl_dmatag, 622 sizeof(struct tl_Rx_list) * TL_NBUF, 1, 623 sizeof(struct tl_Rx_list) * TL_NBUF, 0, BUS_DMA_WAITOK, 624 &sc->Rx_dmamap); 625 if (error == 0) 626 error = bus_dmamap_create(sc->tl_dmatag, 627 sizeof(struct tl_Tx_list) * TL_NBUF, 1, 628 sizeof(struct tl_Tx_list) * TL_NBUF, 0, BUS_DMA_WAITOK, 629 &sc->Tx_dmamap); 630 if (error == 0) 631 error = bus_dmamap_create(sc->tl_dmatag, ETHER_MIN_TX, 1, 632 ETHER_MIN_TX, 0, BUS_DMA_WAITOK, 633 &sc->null_dmamap); 634 if (error) { 635 errstring = "can't allocate DMA maps for lists"; 636 goto bad; 637 } 638 memset(sc->ctrl, 0, PAGE_SIZE); 639 sc->hw_Rx_list = (void *)sc->ctrl; 640 sc->hw_Tx_list = 641 (void *)(sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF); 642 nullbuf = sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF + 643 sizeof(struct tl_Tx_list) * TL_NBUF; 644 error = bus_dmamap_load(sc->tl_dmatag, sc->Rx_dmamap, 645 sc->hw_Rx_list, sizeof(struct tl_Rx_list) * TL_NBUF, NULL, 646 BUS_DMA_WAITOK); 647 if (error == 0) 648 error = bus_dmamap_load(sc->tl_dmatag, sc->Tx_dmamap, 649 sc->hw_Tx_list, sizeof(struct tl_Tx_list) * TL_NBUF, NULL, 650 BUS_DMA_WAITOK); 651 if (error == 0) 652 error = bus_dmamap_load(sc->tl_dmatag, sc->null_dmamap, 653 nullbuf, ETHER_MIN_TX, NULL, BUS_DMA_WAITOK); 654 if (error) { 655 errstring = "can't DMA map DMA memory for lists"; 656 goto bad; 657 } 658 for (i=0; i< TL_NBUF; i++) { 659 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 660 1, MCLBYTES, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 661 &sc->Rx_list[i].m_dmamap); 662 if (error == 0) { 663 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 664 TL_NSEG, MCLBYTES, 0, 665 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 666 &sc->Tx_list[i].m_dmamap); 667 } 668 if (error) { 669 errstring = "can't allocate DMA maps for mbufs"; 670 goto bad; 671 } 672 sc->Rx_list[i].hw_list = &sc->hw_Rx_list[i]; 673 sc->Rx_list[i].hw_listaddr = sc->Rx_dmamap->dm_segs[0].ds_addr 674 + sizeof(struct tl_Rx_list) * i; 675 sc->Tx_list[i].hw_list = &sc->hw_Tx_list[i]; 676 sc->Tx_list[i].hw_listaddr = sc->Tx_dmamap->dm_segs[0].ds_addr 677 + sizeof(struct tl_Tx_list) * i; 678 if (tl_add_RxBuff(sc, &sc->Rx_list[i], NULL) == 0) { 679 errstring = "out of mbuf for receive list"; 680 error = ENOMEM; 681 goto bad; 682 } 683 if (i > 0) { /* chain the list */ 684 sc->Rx_list[i-1].next = &sc->Rx_list[i]; 685 sc->hw_Rx_list[i-1].fwd = 686 htole32(sc->Rx_list[i].hw_listaddr); 687 sc->Tx_list[i-1].next = &sc->Tx_list[i]; 688 } 689 } 690 sc->hw_Rx_list[TL_NBUF-1].fwd = 0; 691 sc->Rx_list[TL_NBUF-1].next = NULL; 692 sc->hw_Tx_list[TL_NBUF-1].fwd = 0; 693 sc->Tx_list[TL_NBUF-1].next = NULL; 694 695 sc->active_Rx = &sc->Rx_list[0]; 696 sc->last_Rx = &sc->Rx_list[TL_NBUF-1]; 697 sc->active_Tx = sc->last_Tx = NULL; 698 sc->Free_Tx = &sc->Tx_list[0]; 699 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 700 sizeof(struct tl_Rx_list) * TL_NBUF, 701 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 702 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 703 sizeof(struct tl_Tx_list) * TL_NBUF, 704 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 705 bus_dmamap_sync(sc->tl_dmatag, sc->null_dmamap, 0, ETHER_MIN_TX, 706 BUS_DMASYNC_PREWRITE); 707 708 /* set media */ 709 mii_mediachg(&sc->tl_mii); 710 711 /* start ticks calls */ 712 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 713 /* write adress of Rx list and enable interrupts */ 714 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->Rx_list[0].hw_listaddr); 715 TL_HR_WRITE(sc, TL_HOST_CMD, 716 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn); 717 sc->tl_if.if_flags |= IFF_RUNNING; 718 sc->tl_if.if_flags &= ~IFF_OACTIVE; 719 return 0; 720 bad: 721 printf("%s: %s\n", sc->sc_dev.dv_xname, errstring); 722 splx(s); 723 return error; 724 } 725 726 727 static u_int32_t 728 tl_intreg_read(sc, reg) 729 tl_softc_t *sc; 730 u_int32_t reg; 731 { 732 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 733 return TL_HR_READ(sc, TL_HOST_DIO_DATA); 734 } 735 736 static u_int8_t 737 tl_intreg_read_byte(sc, reg) 738 tl_softc_t *sc; 739 u_int32_t reg; 740 { 741 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 742 (reg & (~0x07)) & TL_HOST_DIOADR_MASK); 743 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07)); 744 } 745 746 static void 747 tl_intreg_write(sc, reg, val) 748 tl_softc_t *sc; 749 u_int32_t reg; 750 u_int32_t val; 751 { 752 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 753 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val); 754 } 755 756 static void 757 tl_intreg_write_byte(sc, reg, val) 758 tl_softc_t *sc; 759 u_int32_t reg; 760 u_int8_t val; 761 { 762 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 763 (reg & (~0x03)) & TL_HOST_DIOADR_MASK); 764 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val); 765 } 766 767 void 768 tl_mii_sync(sc) 769 struct tl_softc *sc; 770 { 771 int i; 772 773 netsio_clr(sc, TL_NETSIO_MTXEN); 774 for (i = 0; i < 32; i++) { 775 netsio_clr(sc, TL_NETSIO_MCLK); 776 netsio_set(sc, TL_NETSIO_MCLK); 777 } 778 } 779 780 void 781 tl_mii_sendbits(sc, data, nbits) 782 struct tl_softc *sc; 783 u_int32_t data; 784 int nbits; 785 { 786 int i; 787 788 netsio_set(sc, TL_NETSIO_MTXEN); 789 for (i = 1 << (nbits - 1); i; i = i >> 1) { 790 netsio_clr(sc, TL_NETSIO_MCLK); 791 netsio_read(sc, TL_NETSIO_MCLK); 792 if (data & i) 793 netsio_set(sc, TL_NETSIO_MDATA); 794 else 795 netsio_clr(sc, TL_NETSIO_MDATA); 796 netsio_set(sc, TL_NETSIO_MCLK); 797 netsio_read(sc, TL_NETSIO_MCLK); 798 } 799 } 800 801 int 802 tl_mii_read(self, phy, reg) 803 struct device *self; 804 int phy, reg; 805 { 806 struct tl_softc *sc = (struct tl_softc *)self; 807 int val = 0, i, err; 808 809 /* 810 * Read the PHY register by manually driving the MII control lines. 811 */ 812 813 tl_mii_sync(sc); 814 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 815 tl_mii_sendbits(sc, MII_COMMAND_READ, 2); 816 tl_mii_sendbits(sc, phy, 5); 817 tl_mii_sendbits(sc, reg, 5); 818 819 netsio_clr(sc, TL_NETSIO_MTXEN); 820 netsio_clr(sc, TL_NETSIO_MCLK); 821 netsio_set(sc, TL_NETSIO_MCLK); 822 netsio_clr(sc, TL_NETSIO_MCLK); 823 824 err = netsio_read(sc, TL_NETSIO_MDATA); 825 netsio_set(sc, TL_NETSIO_MCLK); 826 827 /* Even if an error occurs, must still clock out the cycle. */ 828 for (i = 0; i < 16; i++) { 829 val <<= 1; 830 netsio_clr(sc, TL_NETSIO_MCLK); 831 if (err == 0 && netsio_read(sc, TL_NETSIO_MDATA)) 832 val |= 1; 833 netsio_set(sc, TL_NETSIO_MCLK); 834 } 835 netsio_clr(sc, TL_NETSIO_MCLK); 836 netsio_set(sc, TL_NETSIO_MCLK); 837 838 return (err ? 0 : val); 839 } 840 841 void 842 tl_mii_write(self, phy, reg, val) 843 struct device *self; 844 int phy, reg, val; 845 { 846 struct tl_softc *sc = (struct tl_softc *)self; 847 848 /* 849 * Write the PHY register by manually driving the MII control lines. 850 */ 851 852 tl_mii_sync(sc); 853 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 854 tl_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 855 tl_mii_sendbits(sc, phy, 5); 856 tl_mii_sendbits(sc, reg, 5); 857 tl_mii_sendbits(sc, MII_COMMAND_ACK, 2); 858 tl_mii_sendbits(sc, val, 16); 859 860 netsio_clr(sc, TL_NETSIO_MCLK); 861 netsio_set(sc, TL_NETSIO_MCLK); 862 } 863 864 void 865 tl_statchg(self) 866 struct device *self; 867 { 868 tl_softc_t *sc = (struct tl_softc *)self; 869 u_int32_t reg; 870 871 #ifdef TLDEBUG 872 printf("tl_statchg, media %x\n", sc->tl_ifmedia.ifm_media); 873 #endif 874 875 /* 876 * We must keep the ThunderLAN and the PHY in sync as 877 * to the status of full-duplex! 878 */ 879 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 880 if (sc->tl_mii.mii_media_active & IFM_FDX) 881 reg |= TL_NETCOMMAND_DUPLEX; 882 else 883 reg &= ~TL_NETCOMMAND_DUPLEX; 884 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 885 } 886 887 void tl_i2c_set(v, bit) 888 void *v; 889 u_int8_t bit; 890 { 891 tl_softc_t *sc = v; 892 893 switch (bit) { 894 case I2C_DATA: 895 netsio_set(sc, TL_NETSIO_EDATA); 896 break; 897 case I2C_CLOCK: 898 netsio_set(sc, TL_NETSIO_ECLOCK); 899 break; 900 case I2C_TXEN: 901 netsio_set(sc, TL_NETSIO_ETXEN); 902 break; 903 default: 904 printf("tl_i2c_set: unknown bit %d\n", bit); 905 } 906 return; 907 } 908 909 void tl_i2c_clr(v, bit) 910 void *v; 911 u_int8_t bit; 912 { 913 tl_softc_t *sc = v; 914 915 switch (bit) { 916 case I2C_DATA: 917 netsio_clr(sc, TL_NETSIO_EDATA); 918 break; 919 case I2C_CLOCK: 920 netsio_clr(sc, TL_NETSIO_ECLOCK); 921 break; 922 case I2C_TXEN: 923 netsio_clr(sc, TL_NETSIO_ETXEN); 924 break; 925 default: 926 printf("tl_i2c_clr: unknown bit %d\n", bit); 927 } 928 return; 929 } 930 931 int tl_i2c_read(v, bit) 932 void *v; 933 u_int8_t bit; 934 { 935 tl_softc_t *sc = v; 936 937 switch (bit) { 938 case I2C_DATA: 939 return netsio_read(sc, TL_NETSIO_EDATA); 940 break; 941 case I2C_CLOCK: 942 return netsio_read(sc, TL_NETSIO_ECLOCK); 943 break; 944 case I2C_TXEN: 945 return netsio_read(sc, TL_NETSIO_ETXEN); 946 break; 947 default: 948 printf("tl_i2c_read: unknown bit %d\n", bit); 949 return -1; 950 } 951 } 952 953 static int 954 tl_intr(v) 955 void *v; 956 { 957 tl_softc_t *sc = v; 958 struct ifnet *ifp = &sc->tl_if; 959 struct Rx_list *Rx; 960 struct Tx_list *Tx; 961 struct mbuf *m; 962 u_int32_t int_type, int_reg; 963 int ack = 0; 964 int size; 965 966 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR); 967 int_type = int_reg & TL_INTR_MASK; 968 if (int_type == 0) 969 return 0; 970 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX) 971 printf("%s: interrupt type %x, intr_reg %x\n", sc->sc_dev.dv_xname, 972 int_type, int_reg); 973 #endif 974 /* disable interrupts */ 975 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 976 switch(int_type & TL_INTR_MASK) { 977 case TL_INTR_RxEOF: 978 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 979 sizeof(struct tl_Rx_list) * TL_NBUF, 980 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 981 while(le32toh(sc->active_Rx->hw_list->stat) & 982 TL_RX_CSTAT_CPLT) { 983 /* dequeue and requeue at end of list */ 984 ack++; 985 Rx = sc->active_Rx; 986 sc->active_Rx = Rx->next; 987 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 988 MCLBYTES, BUS_DMASYNC_POSTREAD); 989 bus_dmamap_unload(sc->tl_dmatag, Rx->m_dmamap); 990 m = Rx->m; 991 size = le32toh(Rx->hw_list->stat) >> 16; 992 #ifdef TLDEBUG_RX 993 printf("tl_intr: RX list complete, Rx %p, size=%d\n", 994 Rx, size); 995 #endif 996 if (tl_add_RxBuff(sc, Rx, m ) == 0) { 997 /* 998 * No new mbuf, reuse the same. This means 999 * that this packet 1000 * is lost 1001 */ 1002 m = NULL; 1003 #ifdef TL_PRIV_STATS 1004 sc->ierr_nomem++; 1005 #endif 1006 #ifdef TLDEBUG 1007 printf("%s: out of mbuf, lost input packet\n", 1008 sc->sc_dev.dv_xname); 1009 #endif 1010 } 1011 Rx->next = NULL; 1012 Rx->hw_list->fwd = 0; 1013 sc->last_Rx->hw_list->fwd = htole32(Rx->hw_listaddr); 1014 sc->last_Rx->next = Rx; 1015 sc->last_Rx = Rx; 1016 1017 /* deliver packet */ 1018 if (m) { 1019 if (size < sizeof(struct ether_header)) { 1020 m_freem(m); 1021 continue; 1022 } 1023 m->m_pkthdr.rcvif = ifp; 1024 m->m_pkthdr.len = m->m_len = size; 1025 #ifdef TLDEBUG_RX 1026 { struct ether_header *eh = 1027 mtod(m, struct ether_header *); 1028 printf("tl_intr: Rx packet:\n"); 1029 ether_printheader(eh); } 1030 #endif 1031 #if NBPFILTER > 0 1032 if (ifp->if_bpf) 1033 bpf_mtap(ifp->if_bpf, m); 1034 #endif /* NBPFILTER > 0 */ 1035 (*ifp->if_input)(ifp, m); 1036 } 1037 } 1038 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1039 sizeof(struct tl_Rx_list) * TL_NBUF, 1040 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1041 #ifdef TLDEBUG_RX 1042 printf("TL_INTR_RxEOF: ack %d\n", ack); 1043 #else 1044 if (ack == 0) { 1045 printf("%s: EOF intr without anything to read !\n", 1046 sc->sc_dev.dv_xname); 1047 tl_reset(sc); 1048 /* shedule reinit of the board */ 1049 callout_reset(&sc->tl_restart_ch, 1, tl_restart, sc); 1050 return(1); 1051 } 1052 #endif 1053 break; 1054 case TL_INTR_RxEOC: 1055 ack++; 1056 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1057 sizeof(struct tl_Rx_list) * TL_NBUF, 1058 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1059 #ifdef TLDEBUG_RX 1060 printf("TL_INTR_RxEOC: ack %d\n", ack); 1061 #endif 1062 #ifdef DIAGNOSTIC 1063 if (le32toh(sc->active_Rx->hw_list->stat) & TL_RX_CSTAT_CPLT) { 1064 printf("%s: Rx EOC interrupt and active Tx list not " 1065 "cleared\n", sc->sc_dev.dv_xname); 1066 return 0; 1067 } else 1068 #endif 1069 { 1070 /* 1071 * write adress of Rx list and send Rx GO command, ack 1072 * interrupt and enable interrupts in one command 1073 */ 1074 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->active_Rx->hw_listaddr); 1075 TL_HR_WRITE(sc, TL_HOST_CMD, 1076 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type | 1077 HOST_CMD_ACK | HOST_CMD_IntOn); 1078 return 1; 1079 } 1080 case TL_INTR_TxEOF: 1081 case TL_INTR_TxEOC: 1082 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1083 sizeof(struct tl_Tx_list) * TL_NBUF, 1084 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1085 while ((Tx = sc->active_Tx) != NULL) { 1086 if((le32toh(Tx->hw_list->stat) & TL_TX_CSTAT_CPLT) == 0) 1087 break; 1088 ack++; 1089 #ifdef TLDEBUG_TX 1090 printf("TL_INTR_TxEOC: list 0x%x done\n", 1091 (int)Tx->hw_listaddr); 1092 #endif 1093 Tx->hw_list->stat = 0; 1094 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, 1095 MCLBYTES, BUS_DMASYNC_POSTWRITE); 1096 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1097 m_freem(Tx->m); 1098 Tx->m = NULL; 1099 sc->active_Tx = Tx->next; 1100 if (sc->active_Tx == NULL) 1101 sc->last_Tx = NULL; 1102 Tx->next = sc->Free_Tx; 1103 sc->Free_Tx = Tx; 1104 } 1105 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1106 sizeof(struct tl_Tx_list) * TL_NBUF, 1107 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1108 /* if this was an EOC, ACK immediatly */ 1109 if (ack) 1110 sc->tl_if.if_flags &= ~IFF_OACTIVE; 1111 if (int_type == TL_INTR_TxEOC) { 1112 #ifdef TLDEBUG_TX 1113 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n", 1114 ack); 1115 #endif 1116 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type | 1117 HOST_CMD_ACK | HOST_CMD_IntOn); 1118 if ( sc->active_Tx != NULL) { 1119 /* needs a Tx go command */ 1120 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 1121 sc->active_Tx->hw_listaddr); 1122 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1123 } 1124 sc->tl_if.if_timer = 0; 1125 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0) 1126 tl_ifstart(&sc->tl_if); 1127 return 1; 1128 } 1129 #ifdef TLDEBUG 1130 else { 1131 printf("TL_INTR_TxEOF: ack %d\n", ack); 1132 } 1133 #endif 1134 sc->tl_if.if_timer = 0; 1135 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0) 1136 tl_ifstart(&sc->tl_if); 1137 break; 1138 case TL_INTR_Stat: 1139 ack++; 1140 #ifdef TLDEBUG 1141 printf("TL_INTR_Stat: ack %d\n", ack); 1142 #endif 1143 tl_read_stats(sc); 1144 break; 1145 case TL_INTR_Adc: 1146 if (int_reg & TL_INTVec_MASK) { 1147 /* adapter check conditions */ 1148 printf("%s: check condition, intvect=0x%x, " 1149 "ch_param=0x%x\n", sc->sc_dev.dv_xname, 1150 int_reg & TL_INTVec_MASK, 1151 TL_HR_READ(sc, TL_HOST_CH_PARM)); 1152 tl_reset(sc); 1153 /* shedule reinit of the board */ 1154 callout_reset(&sc->tl_restart_ch, 1, tl_restart, sc); 1155 return(1); 1156 } else { 1157 u_int8_t netstat; 1158 /* Network status */ 1159 netstat = 1160 tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts); 1161 printf("%s: network status, NetSts=%x\n", 1162 sc->sc_dev.dv_xname, netstat); 1163 /* Ack interrupts */ 1164 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts, 1165 netstat); 1166 ack++; 1167 } 1168 break; 1169 default: 1170 printf("%s: unhandled interrupt code %x!\n", 1171 sc->sc_dev.dv_xname, int_type); 1172 ack++; 1173 } 1174 1175 if (ack) { 1176 /* Ack the interrupt and enable interrupts */ 1177 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK | 1178 HOST_CMD_IntOn); 1179 return 1; 1180 } 1181 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */ 1182 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn); 1183 return 0; 1184 } 1185 1186 static int 1187 tl_ifioctl(ifp, cmd, data) 1188 struct ifnet *ifp; 1189 ioctl_cmd_t cmd; 1190 caddr_t data; 1191 { 1192 struct tl_softc *sc = ifp->if_softc; 1193 struct ifreq *ifr = (struct ifreq *)data; 1194 int s, error; 1195 1196 s = splnet(); 1197 switch(cmd) { 1198 case SIOCSIFMEDIA: 1199 case SIOCGIFMEDIA: 1200 error = ifmedia_ioctl(ifp, ifr, &sc->tl_mii.mii_media, cmd); 1201 break; 1202 default: 1203 error = ether_ioctl(ifp, cmd, data); 1204 if (error == ENETRESET) { 1205 tl_addr_filter(sc); 1206 error = 0; 1207 } 1208 } 1209 splx(s); 1210 return error; 1211 } 1212 1213 static void 1214 tl_ifstart(ifp) 1215 struct ifnet *ifp; 1216 { 1217 tl_softc_t *sc = ifp->if_softc; 1218 struct mbuf *mb_head; 1219 struct Tx_list *Tx; 1220 int segment, size; 1221 int again, error; 1222 1223 if ((sc->tl_if.if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1224 return; 1225 txloop: 1226 /* If we don't have more space ... */ 1227 if (sc->Free_Tx == NULL) { 1228 #ifdef TLDEBUG 1229 printf("tl_ifstart: No free TX list\n"); 1230 #endif 1231 sc->tl_if.if_flags |= IFF_OACTIVE; 1232 return; 1233 } 1234 /* Grab a paquet for output */ 1235 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1236 if (mb_head == NULL) { 1237 #ifdef TLDEBUG_TX 1238 printf("tl_ifstart: nothing to send\n"); 1239 #endif 1240 return; 1241 } 1242 Tx = sc->Free_Tx; 1243 sc->Free_Tx = Tx->next; 1244 Tx->next = NULL; 1245 again = 0; 1246 /* 1247 * Go through each of the mbufs in the chain and initialize 1248 * the transmit list descriptors with the physical address 1249 * and size of the mbuf. 1250 */ 1251 tbdinit: 1252 memset(Tx->hw_list, 0, sizeof(struct tl_Tx_list)); 1253 Tx->m = mb_head; 1254 size = mb_head->m_pkthdr.len; 1255 if ((error = bus_dmamap_load_mbuf(sc->tl_dmatag, Tx->m_dmamap, mb_head, 1256 BUS_DMA_NOWAIT)) || (size < ETHER_MIN_TX && 1257 Tx->m_dmamap->dm_nsegs == TL_NSEG)) { 1258 struct mbuf *mn; 1259 /* 1260 * We ran out of segments, or we will. We have to recopy this 1261 * mbuf chain first. 1262 */ 1263 if (error == 0) 1264 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1265 if (again) { 1266 /* already copyed, can't do much more */ 1267 m_freem(mb_head); 1268 goto bad; 1269 } 1270 again = 1; 1271 #ifdef TLDEBUG_TX 1272 printf("tl_ifstart: need to copy mbuf\n"); 1273 #endif 1274 #ifdef TL_PRIV_STATS 1275 sc->oerr_mcopy++; 1276 #endif 1277 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1278 if (mn == NULL) { 1279 m_freem(mb_head); 1280 goto bad; 1281 } 1282 if (mb_head->m_pkthdr.len > MHLEN) { 1283 MCLGET(mn, M_DONTWAIT); 1284 if ((mn->m_flags & M_EXT) == 0) { 1285 m_freem(mn); 1286 m_freem(mb_head); 1287 goto bad; 1288 } 1289 } 1290 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1291 mtod(mn, caddr_t)); 1292 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1293 m_freem(mb_head); 1294 mb_head = mn; 1295 goto tbdinit; 1296 } 1297 for (segment = 0; segment < Tx->m_dmamap->dm_nsegs; segment++) { 1298 Tx->hw_list->seg[segment].data_addr = 1299 htole32(Tx->m_dmamap->dm_segs[segment].ds_addr); 1300 Tx->hw_list->seg[segment].data_count = 1301 htole32(Tx->m_dmamap->dm_segs[segment].ds_len); 1302 } 1303 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, size, 1304 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1305 /* We are at end of mbuf chain. check the size and 1306 * see if it needs to be extended 1307 */ 1308 if (size < ETHER_MIN_TX) { 1309 #ifdef DIAGNOSTIC 1310 if (segment >= TL_NSEG) { 1311 panic("tl_ifstart: to much segmets (%d)", segment); 1312 } 1313 #endif 1314 /* 1315 * add the nullbuf in the seg 1316 */ 1317 Tx->hw_list->seg[segment].data_count = 1318 htole32(ETHER_MIN_TX - size); 1319 Tx->hw_list->seg[segment].data_addr = 1320 htole32(sc->null_dmamap->dm_segs[0].ds_addr); 1321 size = ETHER_MIN_TX; 1322 segment++; 1323 } 1324 /* The list is done, finish the list init */ 1325 Tx->hw_list->seg[segment-1].data_count |= 1326 htole32(TL_LAST_SEG); 1327 Tx->hw_list->stat = htole32((size << 16) | 0x3000); 1328 #ifdef TLDEBUG_TX 1329 printf("%s: sending, Tx : stat = 0x%x\n", sc->sc_dev.dv_xname, 1330 le32toh(Tx->hw_list->stat)); 1331 #if 0 1332 for(segment = 0; segment < TL_NSEG; segment++) { 1333 printf(" seg %d addr 0x%x len 0x%x\n", 1334 segment, 1335 le32toh(Tx->hw_list->seg[segment].data_addr), 1336 le32toh(Tx->hw_list->seg[segment].data_count)); 1337 } 1338 #endif 1339 #endif 1340 if (sc->active_Tx == NULL) { 1341 sc->active_Tx = sc->last_Tx = Tx; 1342 #ifdef TLDEBUG_TX 1343 printf("%s: Tx GO, addr=0x%ux\n", sc->sc_dev.dv_xname, 1344 (int)Tx->hw_listaddr); 1345 #endif 1346 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1347 sizeof(struct tl_Tx_list) * TL_NBUF, 1348 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1349 TL_HR_WRITE(sc, TL_HOST_CH_PARM, Tx->hw_listaddr); 1350 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1351 } else { 1352 #ifdef TLDEBUG_TX 1353 printf("%s: Tx addr=0x%ux queued\n", sc->sc_dev.dv_xname, 1354 (int)Tx->hw_listaddr); 1355 #endif 1356 sc->last_Tx->hw_list->fwd = htole32(Tx->hw_listaddr); 1357 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1358 sizeof(struct tl_Tx_list) * TL_NBUF, 1359 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1360 sc->last_Tx->next = Tx; 1361 sc->last_Tx = Tx; 1362 #ifdef DIAGNOSTIC 1363 if (sc->last_Tx->hw_list->fwd & 0x7) 1364 printf("%s: physical addr 0x%x of list not properly " 1365 "aligned\n", 1366 sc->sc_dev.dv_xname, sc->last_Rx->hw_list->fwd); 1367 #endif 1368 } 1369 #if NBPFILTER > 0 1370 /* Pass packet to bpf if there is a listener */ 1371 if (ifp->if_bpf) 1372 bpf_mtap(ifp->if_bpf, mb_head); 1373 #endif 1374 /* 1375 * Set a 5 second timer just in case we don't hear from the card again. 1376 */ 1377 ifp->if_timer = 5; 1378 goto txloop; 1379 bad: 1380 #ifdef TLDEBUG 1381 printf("tl_ifstart: Out of mbuf, Tx pkt lost\n"); 1382 #endif 1383 Tx->next = sc->Free_Tx; 1384 sc->Free_Tx = Tx; 1385 return; 1386 } 1387 1388 static void 1389 tl_ifwatchdog(ifp) 1390 struct ifnet *ifp; 1391 { 1392 tl_softc_t *sc = ifp->if_softc; 1393 1394 if ((ifp->if_flags & IFF_RUNNING) == 0) 1395 return; 1396 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1397 ifp->if_oerrors++; 1398 tl_init(ifp); 1399 } 1400 1401 static int 1402 tl_mediachange(ifp) 1403 struct ifnet *ifp; 1404 { 1405 1406 if (ifp->if_flags & IFF_UP) 1407 tl_init(ifp); 1408 return (0); 1409 } 1410 1411 static void 1412 tl_mediastatus(ifp, ifmr) 1413 struct ifnet *ifp; 1414 struct ifmediareq *ifmr; 1415 { 1416 tl_softc_t *sc = ifp->if_softc; 1417 1418 mii_pollstat(&sc->tl_mii); 1419 ifmr->ifm_active = sc->tl_mii.mii_media_active; 1420 ifmr->ifm_status = sc->tl_mii.mii_media_status; 1421 } 1422 1423 static int tl_add_RxBuff(sc, Rx, oldm) 1424 tl_softc_t *sc; 1425 struct Rx_list *Rx; 1426 struct mbuf *oldm; 1427 { 1428 struct mbuf *m; 1429 int error; 1430 1431 MGETHDR(m, M_DONTWAIT, MT_DATA); 1432 if (m != NULL) { 1433 MCLGET(m, M_DONTWAIT); 1434 if ((m->m_flags & M_EXT) == 0) { 1435 m_freem(m); 1436 if (oldm == NULL) 1437 return 0; 1438 m = oldm; 1439 m->m_data = m->m_ext.ext_buf; 1440 } 1441 } else { 1442 if (oldm == NULL) 1443 return 0; 1444 m = oldm; 1445 m->m_data = m->m_ext.ext_buf; 1446 } 1447 1448 /* (re)init the Rx_list struct */ 1449 1450 Rx->m = m; 1451 if ((error = bus_dmamap_load(sc->tl_dmatag, Rx->m_dmamap, 1452 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1453 printf("%s: bus_dmamap_load() failed (error %d) for " 1454 "tl_add_RxBuff\n", sc->sc_dev.dv_xname, error); 1455 printf("size %d (%d)\n", m->m_pkthdr.len, MCLBYTES); 1456 m_freem(m); 1457 Rx->m = NULL; 1458 return 0; 1459 } 1460 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 1461 MCLBYTES, BUS_DMASYNC_PREREAD); 1462 /* 1463 * Move the data pointer up so that the incoming data packet 1464 * will be 32-bit aligned. 1465 */ 1466 m->m_data += 2; 1467 1468 Rx->hw_list->stat = 1469 htole32(((Rx->m_dmamap->dm_segs[0].ds_len -2) << 16) | 0x3000); 1470 Rx->hw_list->seg.data_count = 1471 htole32(Rx->m_dmamap->dm_segs[0].ds_len -2); 1472 Rx->hw_list->seg.data_addr = 1473 htole32(Rx->m_dmamap->dm_segs[0].ds_addr + 2); 1474 return (m != oldm); 1475 } 1476 1477 static void tl_ticks(v) 1478 void *v; 1479 { 1480 tl_softc_t *sc = v; 1481 1482 tl_read_stats(sc); 1483 1484 /* Tick the MII. */ 1485 mii_tick(&sc->tl_mii); 1486 1487 /* read statistics every seconds */ 1488 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 1489 } 1490 1491 static void 1492 tl_read_stats(sc) 1493 tl_softc_t *sc; 1494 { 1495 u_int32_t reg; 1496 int ierr_overr; 1497 int ierr_code; 1498 int ierr_crc; 1499 int oerr_underr; 1500 int oerr_deffered; 1501 int oerr_coll; 1502 int oerr_multicoll; 1503 int oerr_exesscoll; 1504 int oerr_latecoll; 1505 int oerr_carrloss; 1506 struct ifnet *ifp = &sc->tl_if; 1507 1508 reg = tl_intreg_read(sc, TL_INT_STATS_TX); 1509 ifp->if_opackets += reg & 0x00ffffff; 1510 oerr_underr = reg >> 24; 1511 1512 reg = tl_intreg_read(sc, TL_INT_STATS_RX); 1513 ifp->if_ipackets += reg & 0x00ffffff; 1514 ierr_overr = reg >> 24; 1515 1516 reg = tl_intreg_read(sc, TL_INT_STATS_FERR); 1517 ierr_crc = (reg & TL_FERR_CRC) >> 16; 1518 ierr_code = (reg & TL_FERR_CODE) >> 24; 1519 oerr_deffered = (reg & TL_FERR_DEF); 1520 1521 reg = tl_intreg_read(sc, TL_INT_STATS_COLL); 1522 oerr_multicoll = (reg & TL_COL_MULTI); 1523 oerr_coll = (reg & TL_COL_SINGLE) >> 16; 1524 1525 reg = tl_intreg_read(sc, TL_INT_LERR); 1526 oerr_exesscoll = (reg & TL_LERR_ECOLL); 1527 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8; 1528 oerr_carrloss = (reg & TL_LERR_CL) >> 16; 1529 1530 1531 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll + 1532 oerr_carrloss; 1533 ifp->if_collisions += oerr_coll + oerr_multicoll; 1534 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc; 1535 1536 if (ierr_overr) 1537 printf("%s: receiver ring buffer overrun\n", 1538 sc->sc_dev.dv_xname); 1539 if (oerr_underr) 1540 printf("%s: transmit buffer underrun\n", 1541 sc->sc_dev.dv_xname); 1542 #ifdef TL_PRIV_STATS 1543 sc->ierr_overr += ierr_overr; 1544 sc->ierr_code += ierr_code; 1545 sc->ierr_crc += ierr_crc; 1546 sc->oerr_underr += oerr_underr; 1547 sc->oerr_deffered += oerr_deffered; 1548 sc->oerr_coll += oerr_coll; 1549 sc->oerr_multicoll += oerr_multicoll; 1550 sc->oerr_exesscoll += oerr_exesscoll; 1551 sc->oerr_latecoll += oerr_latecoll; 1552 sc->oerr_carrloss += oerr_carrloss; 1553 #endif 1554 } 1555 1556 static void tl_addr_filter(sc) 1557 tl_softc_t *sc; 1558 { 1559 struct ether_multistep step; 1560 struct ether_multi *enm; 1561 u_int32_t hash[2] = {0, 0}; 1562 int i; 1563 1564 sc->tl_if.if_flags &= ~IFF_ALLMULTI; 1565 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm); 1566 while (enm != NULL) { 1567 #ifdef TLDEBUG 1568 printf("tl_addr_filter: addrs %s %s\n", 1569 ether_sprintf(enm->enm_addrlo), 1570 ether_sprintf(enm->enm_addrhi)); 1571 #endif 1572 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1573 i = tl_multicast_hash(enm->enm_addrlo); 1574 hash[i/32] |= 1 << (i%32); 1575 } else { 1576 hash[0] = hash[1] = 0xffffffff; 1577 sc->tl_if.if_flags |= IFF_ALLMULTI; 1578 break; 1579 } 1580 ETHER_NEXT_MULTI(step, enm); 1581 } 1582 #ifdef TLDEBUG 1583 printf("tl_addr_filer: hash1 %x has2 %x\n", hash[0], hash[1]); 1584 #endif 1585 tl_intreg_write(sc, TL_INT_HASH1, hash[0]); 1586 tl_intreg_write(sc, TL_INT_HASH2, hash[1]); 1587 } 1588 1589 static int tl_multicast_hash(a) 1590 u_int8_t *a; 1591 { 1592 int hash; 1593 1594 #define DA(addr,bit) (addr[5 - (bit/8)] & (1 << bit%8)) 1595 #define xor8(a,b,c,d,e,f,g,h) (((a != 0) + (b != 0) + (c != 0) + (d != 0) + (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1596 1597 hash = xor8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1598 DA(a,36), DA(a,42)); 1599 hash |= xor8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1600 DA(a,37), DA(a,43)) << 1; 1601 hash |= xor8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1602 DA(a,38), DA(a,44)) << 2; 1603 hash |= xor8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1604 DA(a,39), DA(a,45)) << 3; 1605 hash |= xor8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1606 DA(a,40), DA(a,46)) << 4; 1607 hash |= xor8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1608 DA(a,41), DA(a,47)) << 5; 1609 1610 return hash; 1611 } 1612 1613 #if defined(TLDEBUG_RX) 1614 void 1615 ether_printheader(eh) 1616 struct ether_header *eh; 1617 { 1618 u_char *c = (char*)eh; 1619 int i; 1620 for (i=0; i<sizeof(struct ether_header); i++) 1621 printf("%x ", (u_int)c[i]); 1622 printf("\n"); 1623 } 1624 #endif 1625