1 /* $NetBSD: if_tl.c,v 1.57 2003/03/19 17:23:26 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Texas Instruments ThunderLAN ethernet controller 34 * ThunderLAN Programmer's Guide (TI Literature Number SPWU013A) 35 * available from www.ti.com 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: if_tl.c,v 1.57 2003/03/19 17:23:26 bouyer Exp $"); 40 41 #undef TLDEBUG 42 #define TL_PRIV_STATS 43 #undef TLDEBUG_RX 44 #undef TLDEBUG_TX 45 #undef TLDEBUG_ADDR 46 47 #include "opt_inet.h" 48 #include "opt_ns.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/mbuf.h> 53 #include <sys/protosw.h> 54 #include <sys/socket.h> 55 #include <sys/ioctl.h> 56 #include <sys/errno.h> 57 #include <sys/malloc.h> 58 #include <sys/kernel.h> 59 #include <sys/proc.h> /* only for declaration of wakeup() used by vm.h */ 60 #include <sys/device.h> 61 62 #include <net/if.h> 63 #if defined(SIOCSIFMEDIA) 64 #include <net/if_media.h> 65 #endif 66 #include <net/if_types.h> 67 #include <net/if_dl.h> 68 #include <net/route.h> 69 #include <net/netisr.h> 70 71 #include "bpfilter.h" 72 #if NBPFILTER > 0 73 #include <net/bpf.h> 74 #include <net/bpfdesc.h> 75 #endif 76 77 #ifdef INET 78 #include <netinet/in.h> 79 #include <netinet/in_systm.h> 80 #include <netinet/in_var.h> 81 #include <netinet/ip.h> 82 #endif 83 84 #ifdef NS 85 #include <netns/ns.h> 86 #include <netns/ns_if.h> 87 #endif 88 89 #if defined(__NetBSD__) 90 #include <net/if_ether.h> 91 #include <uvm/uvm_extern.h> 92 #if defined(INET) 93 #include <netinet/if_inarp.h> 94 #endif 95 96 #include <machine/bus.h> 97 #include <machine/intr.h> 98 99 #include <dev/pci/pcireg.h> 100 #include <dev/pci/pcivar.h> 101 #include <dev/pci/pcidevs.h> 102 103 #include <dev/i2c/i2c_bus.h> 104 #include <dev/i2c/i2c_eeprom.h> 105 106 #include <dev/mii/mii.h> 107 #include <dev/mii/miivar.h> 108 109 #include <dev/mii/tlphyvar.h> 110 111 #include <dev/pci/if_tlregs.h> 112 #include <dev/pci/if_tlvar.h> 113 #endif /* __NetBSD__ */ 114 115 /* number of transmit/receive buffers */ 116 #ifndef TL_NBUF 117 #define TL_NBUF 10 118 #endif 119 120 static int tl_pci_match __P((struct device *, struct cfdata *, void *)); 121 static void tl_pci_attach __P((struct device *, struct device *, void *)); 122 static int tl_intr __P((void *)); 123 124 static int tl_ifioctl __P((struct ifnet *, ioctl_cmd_t, caddr_t)); 125 static int tl_mediachange __P((struct ifnet *)); 126 static void tl_mediastatus __P((struct ifnet *, struct ifmediareq *)); 127 static void tl_ifwatchdog __P((struct ifnet *)); 128 static void tl_shutdown __P((void*)); 129 130 static void tl_ifstart __P((struct ifnet *)); 131 static void tl_reset __P((tl_softc_t*)); 132 static int tl_init __P((struct ifnet *)); 133 static void tl_stop __P((struct ifnet *, int)); 134 static void tl_restart __P((void *)); 135 static int tl_add_RxBuff __P((tl_softc_t*, struct Rx_list*, struct mbuf*)); 136 static void tl_read_stats __P((tl_softc_t*)); 137 static void tl_ticks __P((void*)); 138 static int tl_multicast_hash __P((u_int8_t*)); 139 static void tl_addr_filter __P((tl_softc_t*)); 140 141 static u_int32_t tl_intreg_read __P((tl_softc_t*, u_int32_t)); 142 static void tl_intreg_write __P((tl_softc_t*, u_int32_t, u_int32_t)); 143 static u_int8_t tl_intreg_read_byte __P((tl_softc_t*, u_int32_t)); 144 static void tl_intreg_write_byte __P((tl_softc_t*, u_int32_t, u_int8_t)); 145 146 void tl_mii_sync __P((struct tl_softc *)); 147 void tl_mii_sendbits __P((struct tl_softc *, u_int32_t, int)); 148 149 150 #if defined(TLDEBUG_RX) 151 static void ether_printheader __P((struct ether_header*)); 152 #endif 153 154 int tl_mii_read __P((struct device *, int, int)); 155 void tl_mii_write __P((struct device *, int, int, int)); 156 157 void tl_statchg __P((struct device *)); 158 159 void tl_i2c_set __P((void*, u_int8_t)); 160 void tl_i2c_clr __P((void*, u_int8_t)); 161 int tl_i2c_read __P((void*, u_int8_t)); 162 163 static __inline void netsio_clr __P((tl_softc_t*, u_int8_t)); 164 static __inline void netsio_set __P((tl_softc_t*, u_int8_t)); 165 static __inline u_int8_t netsio_read __P((tl_softc_t*, u_int8_t)); 166 static __inline void netsio_clr(sc, bits) 167 tl_softc_t* sc; 168 u_int8_t bits; 169 { 170 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 171 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & (~bits)); 172 } 173 static __inline void netsio_set(sc, bits) 174 tl_softc_t* sc; 175 u_int8_t bits; 176 { 177 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetSio, 178 tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) | bits); 179 } 180 static __inline u_int8_t netsio_read(sc, bits) 181 tl_softc_t* sc; 182 u_int8_t bits; 183 { 184 return (tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetSio) & bits); 185 } 186 187 CFATTACH_DECL(tl, sizeof(tl_softc_t), 188 tl_pci_match, tl_pci_attach, NULL, NULL); 189 190 const struct tl_product_desc tl_compaq_products[] = { 191 { PCI_PRODUCT_COMPAQ_N100TX, TLPHY_MEDIA_NO_10_T, 192 "Compaq Netelligent 10/100 TX" }, 193 { PCI_PRODUCT_COMPAQ_N10T, TLPHY_MEDIA_10_5, 194 "Compaq Netelligent 10 T" }, 195 { PCI_PRODUCT_COMPAQ_IntNF3P, TLPHY_MEDIA_10_2, 196 "Compaq Integrated NetFlex 3/P" }, 197 { PCI_PRODUCT_COMPAQ_IntPL100TX, TLPHY_MEDIA_10_2|TLPHY_MEDIA_NO_10_T, 198 "Compaq ProLiant Integrated Netelligent 10/100 TX" }, 199 { PCI_PRODUCT_COMPAQ_DPNet100TX, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 200 "Compaq Dual Port Netelligent 10/100 TX" }, 201 { PCI_PRODUCT_COMPAQ_DP4000, TLPHY_MEDIA_10_5|TLPHY_MEDIA_NO_10_T, 202 "Compaq Deskpro 4000 5233MMX" }, 203 { PCI_PRODUCT_COMPAQ_NF3P_BNC, TLPHY_MEDIA_10_2, 204 "Compaq NetFlex 3/P w/ BNC" }, 205 { PCI_PRODUCT_COMPAQ_NF3P, TLPHY_MEDIA_10_5, 206 "Compaq NetFlex 3/P" }, 207 { 0, 0, NULL }, 208 }; 209 210 const struct tl_product_desc tl_ti_products[] = { 211 /* 212 * Built-in Ethernet on the TI TravelMate 5000 213 * docking station; better product description? 214 */ 215 { PCI_PRODUCT_TI_TLAN, 0, 216 "Texas Instruments ThunderLAN" }, 217 { 0, 0, NULL }, 218 }; 219 220 struct tl_vendor_desc { 221 u_int32_t tv_vendor; 222 const struct tl_product_desc *tv_products; 223 }; 224 225 const struct tl_vendor_desc tl_vendors[] = { 226 { PCI_VENDOR_COMPAQ, tl_compaq_products }, 227 { PCI_VENDOR_TI, tl_ti_products }, 228 { 0, NULL }, 229 }; 230 231 const struct tl_product_desc *tl_lookup_product __P((u_int32_t)); 232 233 const struct tl_product_desc * 234 tl_lookup_product(id) 235 u_int32_t id; 236 { 237 const struct tl_product_desc *tp; 238 const struct tl_vendor_desc *tv; 239 240 for (tv = tl_vendors; tv->tv_products != NULL; tv++) 241 if (PCI_VENDOR(id) == tv->tv_vendor) 242 break; 243 244 if ((tp = tv->tv_products) == NULL) 245 return (NULL); 246 247 for (; tp->tp_desc != NULL; tp++) 248 if (PCI_PRODUCT(id) == tp->tp_product) 249 break; 250 251 if (tp->tp_desc == NULL) 252 return (NULL); 253 254 return (tp); 255 } 256 257 static int 258 tl_pci_match(parent, match, aux) 259 struct device *parent; 260 struct cfdata *match; 261 void *aux; 262 { 263 struct pci_attach_args *pa = (struct pci_attach_args *) aux; 264 265 if (tl_lookup_product(pa->pa_id) != NULL) 266 return (1); 267 268 return (0); 269 } 270 271 static void 272 tl_pci_attach(parent, self, aux) 273 struct device * parent; 274 struct device * self; 275 void * aux; 276 { 277 tl_softc_t *sc = (tl_softc_t *)self; 278 struct pci_attach_args * const pa = (struct pci_attach_args *) aux; 279 const struct tl_product_desc *tp; 280 struct ifnet * const ifp = &sc->tl_if; 281 bus_space_tag_t iot, memt; 282 bus_space_handle_t ioh, memh; 283 pci_intr_handle_t intrhandle; 284 const char *intrstr; 285 int i, tmp, ioh_valid, memh_valid; 286 int reg_io, reg_mem; 287 pcireg_t reg10, reg14; 288 pcireg_t csr; 289 290 printf("\n"); 291 292 callout_init(&sc->tl_tick_ch); 293 callout_init(&sc->tl_restart_ch); 294 295 tp = tl_lookup_product(pa->pa_id); 296 if (tp == NULL) 297 panic("tl_pci_attach: impossible"); 298 sc->tl_product = tp; 299 300 /* 301 * Map the card space. First we have to find the I/O and MEM 302 * registers. I/O is supposed to be at 0x10, MEM at 0x14, 303 * but some boards (Compaq Netflex 3/P PCI) seem to have it reversed. 304 * The ThunderLAN manual is not consistent about this either (there 305 * are both cases in code examples). 306 */ 307 reg10 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x10); 308 reg14 = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x14); 309 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_IO) 310 reg_io = 0x10; 311 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_IO) 312 reg_io = 0x14; 313 else 314 reg_io = 0; 315 if (PCI_MAPREG_TYPE(reg10) == PCI_MAPREG_TYPE_MEM) 316 reg_mem = 0x10; 317 else if (PCI_MAPREG_TYPE(reg14) == PCI_MAPREG_TYPE_MEM) 318 reg_mem = 0x14; 319 else 320 reg_mem = 0; 321 322 if (reg_io != 0) 323 ioh_valid = (pci_mapreg_map(pa, reg_io, PCI_MAPREG_TYPE_IO, 324 0, &iot, &ioh, NULL, NULL) == 0); 325 else 326 ioh_valid = 0; 327 if (reg_mem != 0) 328 memh_valid = (pci_mapreg_map(pa, PCI_CBMA, 329 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 330 0, &memt, &memh, NULL, NULL) == 0); 331 else 332 memh_valid = 0; 333 334 if (ioh_valid) { 335 sc->tl_bustag = iot; 336 sc->tl_bushandle = ioh; 337 } else if (memh_valid) { 338 sc->tl_bustag = memt; 339 sc->tl_bushandle = memh; 340 } else { 341 printf("%s: unable to map device registers\n", 342 sc->sc_dev.dv_xname); 343 return; 344 } 345 sc->tl_dmatag = pa->pa_dmat; 346 347 /* Enable the device. */ 348 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 349 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 350 csr | PCI_COMMAND_MASTER_ENABLE); 351 352 printf("%s: %s\n", sc->sc_dev.dv_xname, tp->tp_desc); 353 354 tl_reset(sc); 355 356 /* fill in the i2c struct */ 357 sc->i2cbus.adapter_softc = sc; 358 sc->i2cbus.set_bit = tl_i2c_set; 359 sc->i2cbus.clr_bit = tl_i2c_clr; 360 sc->i2cbus.read_bit = tl_i2c_read; 361 362 #ifdef TLDEBUG 363 printf("default values of INTreg: 0x%x\n", 364 tl_intreg_read(sc, TL_INT_Defaults)); 365 #endif 366 367 /* read mac addr */ 368 for (i=0; i<ETHER_ADDR_LEN; i++) { 369 tmp = i2c_eeprom_read(&sc->i2cbus, 0x83 + i); 370 if (tmp < 0) { 371 printf("%s: error reading Ethernet adress\n", 372 sc->sc_dev.dv_xname); 373 return; 374 } else { 375 sc->tl_enaddr[i] = tmp; 376 } 377 } 378 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 379 ether_sprintf(sc->tl_enaddr)); 380 381 /* Map and establish interrupts */ 382 if (pci_intr_map(pa, &intrhandle)) { 383 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 384 return; 385 } 386 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 387 sc->tl_if.if_softc = sc; 388 sc->tl_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_NET, 389 tl_intr, sc); 390 if (sc->tl_ih == NULL) { 391 printf("%s: couldn't establish interrupt", 392 sc->sc_dev.dv_xname); 393 if (intrstr != NULL) 394 printf(" at %s", intrstr); 395 printf("\n"); 396 return; 397 } 398 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 399 400 /* init these pointers, so that tl_shutdown won't try to read them */ 401 sc->Rx_list = NULL; 402 sc->Tx_list = NULL; 403 404 /* allocate DMA-safe memory for control structs */ 405 if (bus_dmamem_alloc(sc->tl_dmatag, 406 PAGE_SIZE, 0, PAGE_SIZE, 407 &sc->ctrl_segs, 1, &sc->ctrl_nsegs, BUS_DMA_NOWAIT) != 0 || 408 bus_dmamem_map(sc->tl_dmatag, &sc->ctrl_segs, 409 sc->ctrl_nsegs, PAGE_SIZE, (caddr_t*)&sc->ctrl, 410 BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0) { 411 printf("%s: can't allocate DMA memory for lists\n", 412 sc->sc_dev.dv_xname); 413 return; 414 } 415 /* 416 * Add shutdown hook so that DMA is disabled prior to reboot. Not 417 * doing 418 * reboot before the driver initializes. 419 */ 420 (void) shutdownhook_establish(tl_shutdown, ifp); 421 422 /* 423 * Initialize our media structures and probe the MII. 424 * 425 * Note that we don't care about the media instance. We 426 * are expecting to have multiple PHYs on the 10/100 cards, 427 * and on those cards we exclude the internal PHY from providing 428 * 10baseT. By ignoring the instance, it allows us to not have 429 * to specify it on the command line when switching media. 430 */ 431 sc->tl_mii.mii_ifp = ifp; 432 sc->tl_mii.mii_readreg = tl_mii_read; 433 sc->tl_mii.mii_writereg = tl_mii_write; 434 sc->tl_mii.mii_statchg = tl_statchg; 435 ifmedia_init(&sc->tl_mii.mii_media, IFM_IMASK, tl_mediachange, 436 tl_mediastatus); 437 mii_attach(self, &sc->tl_mii, 0xffffffff, MII_PHY_ANY, 438 MII_OFFSET_ANY, 0); 439 if (LIST_FIRST(&sc->tl_mii.mii_phys) == NULL) { 440 ifmedia_add(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 441 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_NONE); 442 } else 443 ifmedia_set(&sc->tl_mii.mii_media, IFM_ETHER|IFM_AUTO); 444 445 /* 446 * We can support 802.1Q VLAN-sized frames. 447 */ 448 sc->tl_ec.ec_capabilities |= ETHERCAP_VLAN_MTU; 449 450 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 451 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST; 452 ifp->if_ioctl = tl_ifioctl; 453 ifp->if_start = tl_ifstart; 454 ifp->if_watchdog = tl_ifwatchdog; 455 ifp->if_init = tl_init; 456 ifp->if_stop = tl_stop; 457 ifp->if_timer = 0; 458 IFQ_SET_READY(&ifp->if_snd); 459 if_attach(ifp); 460 ether_ifattach(&(sc)->tl_if, (sc)->tl_enaddr); 461 } 462 463 static void 464 tl_reset(sc) 465 tl_softc_t *sc; 466 { 467 int i; 468 469 /* read stats */ 470 if (sc->tl_if.if_flags & IFF_RUNNING) { 471 callout_stop(&sc->tl_tick_ch); 472 tl_read_stats(sc); 473 } 474 /* Reset adapter */ 475 TL_HR_WRITE(sc, TL_HOST_CMD, 476 TL_HR_READ(sc, TL_HOST_CMD) | HOST_CMD_Ad_Rst); 477 DELAY(100000); 478 /* Disable interrupts */ 479 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 480 /* setup aregs & hash */ 481 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 482 tl_intreg_write(sc, i, 0); 483 #ifdef TLDEBUG_ADDR 484 printf("Areg & hash registers: \n"); 485 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 486 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 487 #endif 488 /* Setup NetConfig */ 489 tl_intreg_write(sc, TL_INT_NetConfig, 490 TL_NETCONFIG_1F | TL_NETCONFIG_1chn | TL_NETCONFIG_PHY_EN); 491 /* Bsize: accept default */ 492 /* TX commit in Acommit: accept default */ 493 /* Load Ld_tmr and Ld_thr */ 494 /* Ld_tmr = 3 */ 495 TL_HR_WRITE(sc, TL_HOST_CMD, 0x3 | HOST_CMD_LdTmr); 496 /* Ld_thr = 0 */ 497 TL_HR_WRITE(sc, TL_HOST_CMD, 0x0 | HOST_CMD_LdThr); 498 /* Unreset MII */ 499 netsio_set(sc, TL_NETSIO_NMRST); 500 DELAY(100000); 501 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 502 } 503 504 static void tl_shutdown(v) 505 void *v; 506 { 507 tl_stop(v, 1); 508 } 509 510 static void tl_stop(ifp, disable) 511 struct ifnet *ifp; 512 int disable; 513 { 514 tl_softc_t *sc = ifp->if_softc; 515 struct Tx_list *Tx; 516 int i; 517 518 if ((ifp->if_flags & IFF_RUNNING) == 0) 519 return; 520 /* disable interrupts */ 521 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 522 /* stop TX and RX channels */ 523 TL_HR_WRITE(sc, TL_HOST_CMD, 524 HOST_CMD_STOP | HOST_CMD_RT | HOST_CMD_Nes); 525 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_STOP); 526 DELAY(100000); 527 528 /* stop statistics reading loop, read stats */ 529 callout_stop(&sc->tl_tick_ch); 530 tl_read_stats(sc); 531 532 /* Down the MII. */ 533 mii_down(&sc->tl_mii); 534 535 /* deallocate memory allocations */ 536 if (sc->Rx_list) { 537 for (i=0; i< TL_NBUF; i++) { 538 if (sc->Rx_list[i].m) { 539 bus_dmamap_unload(sc->tl_dmatag, 540 sc->Rx_list[i].m_dmamap); 541 m_freem(sc->Rx_list[i].m); 542 } 543 bus_dmamap_destroy(sc->tl_dmatag, 544 sc->Rx_list[i].m_dmamap); 545 sc->Rx_list[i].m = NULL; 546 } 547 free(sc->Rx_list, M_DEVBUF); 548 sc->Rx_list = NULL; 549 bus_dmamap_unload(sc->tl_dmatag, sc->Rx_dmamap); 550 bus_dmamap_destroy(sc->tl_dmatag, sc->Rx_dmamap); 551 sc->hw_Rx_list = NULL; 552 while ((Tx = sc->active_Tx) != NULL) { 553 Tx->hw_list->stat = 0; 554 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 555 bus_dmamap_destroy(sc->tl_dmatag, Tx->m_dmamap); 556 m_freem(Tx->m); 557 sc->active_Tx = Tx->next; 558 Tx->next = sc->Free_Tx; 559 sc->Free_Tx = Tx; 560 } 561 sc->last_Tx = NULL; 562 free(sc->Tx_list, M_DEVBUF); 563 sc->Tx_list = NULL; 564 bus_dmamap_unload(sc->tl_dmatag, sc->Tx_dmamap); 565 bus_dmamap_destroy(sc->tl_dmatag, sc->Tx_dmamap); 566 sc->hw_Tx_list = NULL; 567 } 568 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 569 ifp->if_timer = 0; 570 sc->tl_mii.mii_media_status &= ~IFM_ACTIVE; 571 } 572 573 static void tl_restart(v) 574 void *v; 575 { 576 tl_init(v); 577 } 578 579 static int tl_init(ifp) 580 struct ifnet *ifp; 581 { 582 tl_softc_t *sc = ifp->if_softc; 583 int i, s, error; 584 char *errstring; 585 char *nullbuf; 586 587 s = splnet(); 588 /* cancel any pending IO */ 589 tl_stop(ifp, 1); 590 tl_reset(sc); 591 if ((sc->tl_if.if_flags & IFF_UP) == 0) { 592 splx(s); 593 return 0; 594 } 595 /* Set various register to reasonable value */ 596 /* setup NetCmd in promisc mode if needed */ 597 i = (ifp->if_flags & IFF_PROMISC) ? TL_NETCOMMAND_CAF : 0; 598 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, 599 TL_NETCOMMAND_NRESET | TL_NETCOMMAND_NWRAP | i); 600 /* Max receive size : MCLBYTES */ 601 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxL, MCLBYTES & 0xff); 602 tl_intreg_write_byte(sc, TL_INT_MISC + TL_MISC_MaxRxH, 603 (MCLBYTES >> 8) & 0xff); 604 605 /* init MAC addr */ 606 for (i = 0; i < ETHER_ADDR_LEN; i++) 607 tl_intreg_write_byte(sc, TL_INT_Areg0 + i , sc->tl_enaddr[i]); 608 /* add multicast filters */ 609 tl_addr_filter(sc); 610 #ifdef TLDEBUG_ADDR 611 printf("Wrote Mac addr, Areg & hash registers are now: \n"); 612 for (i = TL_INT_Areg0; i <= TL_INT_HASH2; i = i + 4) 613 printf(" reg %x: %x\n", i, tl_intreg_read(sc, i)); 614 #endif 615 616 /* Pre-allocate receivers mbuf, make the lists */ 617 sc->Rx_list = malloc(sizeof(struct Rx_list) * TL_NBUF, M_DEVBUF, 618 M_NOWAIT|M_ZERO); 619 sc->Tx_list = malloc(sizeof(struct Tx_list) * TL_NBUF, M_DEVBUF, 620 M_NOWAIT|M_ZERO); 621 if (sc->Rx_list == NULL || sc->Tx_list == NULL) { 622 errstring = "out of memory for lists"; 623 error = ENOMEM; 624 goto bad; 625 } 626 error = bus_dmamap_create(sc->tl_dmatag, 627 sizeof(struct tl_Rx_list) * TL_NBUF, 1, 628 sizeof(struct tl_Rx_list) * TL_NBUF, 0, BUS_DMA_WAITOK, 629 &sc->Rx_dmamap); 630 if (error == 0) 631 error = bus_dmamap_create(sc->tl_dmatag, 632 sizeof(struct tl_Tx_list) * TL_NBUF, 1, 633 sizeof(struct tl_Tx_list) * TL_NBUF, 0, BUS_DMA_WAITOK, 634 &sc->Tx_dmamap); 635 if (error == 0) 636 error = bus_dmamap_create(sc->tl_dmatag, ETHER_MIN_TX, 1, 637 ETHER_MIN_TX, 0, BUS_DMA_WAITOK, 638 &sc->null_dmamap); 639 if (error) { 640 errstring = "can't allocate DMA maps for lists"; 641 goto bad; 642 } 643 memset(sc->ctrl, 0, PAGE_SIZE); 644 sc->hw_Rx_list = (void *)sc->ctrl; 645 sc->hw_Tx_list = 646 (void *)(sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF); 647 nullbuf = sc->ctrl + sizeof(struct tl_Rx_list) * TL_NBUF + 648 sizeof(struct tl_Tx_list) * TL_NBUF; 649 error = bus_dmamap_load(sc->tl_dmatag, sc->Rx_dmamap, 650 sc->hw_Rx_list, sizeof(struct tl_Rx_list) * TL_NBUF, NULL, 651 BUS_DMA_WAITOK); 652 if (error == 0) 653 error = bus_dmamap_load(sc->tl_dmatag, sc->Tx_dmamap, 654 sc->hw_Tx_list, sizeof(struct tl_Tx_list) * TL_NBUF, NULL, 655 BUS_DMA_WAITOK); 656 if (error == 0) 657 error = bus_dmamap_load(sc->tl_dmatag, sc->null_dmamap, 658 nullbuf, ETHER_MIN_TX, NULL, BUS_DMA_WAITOK); 659 if (error) { 660 errstring = "can't DMA map DMA memory for lists"; 661 goto bad; 662 } 663 for (i=0; i< TL_NBUF; i++) { 664 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 665 1, MCLBYTES, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 666 &sc->Rx_list[i].m_dmamap); 667 if (error == 0) { 668 error = bus_dmamap_create(sc->tl_dmatag, MCLBYTES, 669 TL_NSEG, MCLBYTES, 0, 670 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, 671 &sc->Tx_list[i].m_dmamap); 672 } 673 if (error) { 674 errstring = "can't allocate DMA maps for mbufs"; 675 goto bad; 676 } 677 sc->Rx_list[i].hw_list = &sc->hw_Rx_list[i]; 678 sc->Rx_list[i].hw_listaddr = sc->Rx_dmamap->dm_segs[0].ds_addr 679 + sizeof(struct tl_Rx_list) * i; 680 sc->Tx_list[i].hw_list = &sc->hw_Tx_list[i]; 681 sc->Tx_list[i].hw_listaddr = sc->Tx_dmamap->dm_segs[0].ds_addr 682 + sizeof(struct tl_Tx_list) * i; 683 if (tl_add_RxBuff(sc, &sc->Rx_list[i], NULL) == 0) { 684 errstring = "out of mbuf for receive list"; 685 error = ENOMEM; 686 goto bad; 687 } 688 if (i > 0) { /* chain the list */ 689 sc->Rx_list[i-1].next = &sc->Rx_list[i]; 690 sc->hw_Rx_list[i-1].fwd = 691 htole32(sc->Rx_list[i].hw_listaddr); 692 sc->Tx_list[i-1].next = &sc->Tx_list[i]; 693 } 694 } 695 sc->hw_Rx_list[TL_NBUF-1].fwd = 0; 696 sc->Rx_list[TL_NBUF-1].next = NULL; 697 sc->hw_Tx_list[TL_NBUF-1].fwd = 0; 698 sc->Tx_list[TL_NBUF-1].next = NULL; 699 700 sc->active_Rx = &sc->Rx_list[0]; 701 sc->last_Rx = &sc->Rx_list[TL_NBUF-1]; 702 sc->active_Tx = sc->last_Tx = NULL; 703 sc->Free_Tx = &sc->Tx_list[0]; 704 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 705 sizeof(struct tl_Rx_list) * TL_NBUF, 706 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 707 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 708 sizeof(struct tl_Tx_list) * TL_NBUF, 709 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 710 bus_dmamap_sync(sc->tl_dmatag, sc->null_dmamap, 0, ETHER_MIN_TX, 711 BUS_DMASYNC_PREWRITE); 712 713 /* set media */ 714 mii_mediachg(&sc->tl_mii); 715 716 /* start ticks calls */ 717 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 718 /* write adress of Rx list and enable interrupts */ 719 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->Rx_list[0].hw_listaddr); 720 TL_HR_WRITE(sc, TL_HOST_CMD, 721 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | HOST_CMD_IntOn); 722 sc->tl_if.if_flags |= IFF_RUNNING; 723 sc->tl_if.if_flags &= ~IFF_OACTIVE; 724 return 0; 725 bad: 726 printf("%s: %s\n", sc->sc_dev.dv_xname, errstring); 727 splx(s); 728 return error; 729 } 730 731 732 static u_int32_t 733 tl_intreg_read(sc, reg) 734 tl_softc_t *sc; 735 u_int32_t reg; 736 { 737 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 738 return TL_HR_READ(sc, TL_HOST_DIO_DATA); 739 } 740 741 static u_int8_t 742 tl_intreg_read_byte(sc, reg) 743 tl_softc_t *sc; 744 u_int32_t reg; 745 { 746 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 747 (reg & (~0x07)) & TL_HOST_DIOADR_MASK); 748 return TL_HR_READ_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x07)); 749 } 750 751 static void 752 tl_intreg_write(sc, reg, val) 753 tl_softc_t *sc; 754 u_int32_t reg; 755 u_int32_t val; 756 { 757 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, reg & TL_HOST_DIOADR_MASK); 758 TL_HR_WRITE(sc, TL_HOST_DIO_DATA, val); 759 } 760 761 static void 762 tl_intreg_write_byte(sc, reg, val) 763 tl_softc_t *sc; 764 u_int32_t reg; 765 u_int8_t val; 766 { 767 TL_HR_WRITE(sc, TL_HOST_INTR_DIOADR, 768 (reg & (~0x03)) & TL_HOST_DIOADR_MASK); 769 TL_HR_WRITE_BYTE(sc, TL_HOST_DIO_DATA + (reg & 0x03), val); 770 } 771 772 void 773 tl_mii_sync(sc) 774 struct tl_softc *sc; 775 { 776 int i; 777 778 netsio_clr(sc, TL_NETSIO_MTXEN); 779 for (i = 0; i < 32; i++) { 780 netsio_clr(sc, TL_NETSIO_MCLK); 781 netsio_set(sc, TL_NETSIO_MCLK); 782 } 783 } 784 785 void 786 tl_mii_sendbits(sc, data, nbits) 787 struct tl_softc *sc; 788 u_int32_t data; 789 int nbits; 790 { 791 int i; 792 793 netsio_set(sc, TL_NETSIO_MTXEN); 794 for (i = 1 << (nbits - 1); i; i = i >> 1) { 795 netsio_clr(sc, TL_NETSIO_MCLK); 796 netsio_read(sc, TL_NETSIO_MCLK); 797 if (data & i) 798 netsio_set(sc, TL_NETSIO_MDATA); 799 else 800 netsio_clr(sc, TL_NETSIO_MDATA); 801 netsio_set(sc, TL_NETSIO_MCLK); 802 netsio_read(sc, TL_NETSIO_MCLK); 803 } 804 } 805 806 int 807 tl_mii_read(self, phy, reg) 808 struct device *self; 809 int phy, reg; 810 { 811 struct tl_softc *sc = (struct tl_softc *)self; 812 int val = 0, i, err; 813 814 /* 815 * Read the PHY register by manually driving the MII control lines. 816 */ 817 818 tl_mii_sync(sc); 819 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 820 tl_mii_sendbits(sc, MII_COMMAND_READ, 2); 821 tl_mii_sendbits(sc, phy, 5); 822 tl_mii_sendbits(sc, reg, 5); 823 824 netsio_clr(sc, TL_NETSIO_MTXEN); 825 netsio_clr(sc, TL_NETSIO_MCLK); 826 netsio_set(sc, TL_NETSIO_MCLK); 827 netsio_clr(sc, TL_NETSIO_MCLK); 828 829 err = netsio_read(sc, TL_NETSIO_MDATA); 830 netsio_set(sc, TL_NETSIO_MCLK); 831 832 /* Even if an error occurs, must still clock out the cycle. */ 833 for (i = 0; i < 16; i++) { 834 val <<= 1; 835 netsio_clr(sc, TL_NETSIO_MCLK); 836 if (err == 0 && netsio_read(sc, TL_NETSIO_MDATA)) 837 val |= 1; 838 netsio_set(sc, TL_NETSIO_MCLK); 839 } 840 netsio_clr(sc, TL_NETSIO_MCLK); 841 netsio_set(sc, TL_NETSIO_MCLK); 842 843 return (err ? 0 : val); 844 } 845 846 void 847 tl_mii_write(self, phy, reg, val) 848 struct device *self; 849 int phy, reg, val; 850 { 851 struct tl_softc *sc = (struct tl_softc *)self; 852 853 /* 854 * Write the PHY register by manually driving the MII control lines. 855 */ 856 857 tl_mii_sync(sc); 858 tl_mii_sendbits(sc, MII_COMMAND_START, 2); 859 tl_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 860 tl_mii_sendbits(sc, phy, 5); 861 tl_mii_sendbits(sc, reg, 5); 862 tl_mii_sendbits(sc, MII_COMMAND_ACK, 2); 863 tl_mii_sendbits(sc, val, 16); 864 865 netsio_clr(sc, TL_NETSIO_MCLK); 866 netsio_set(sc, TL_NETSIO_MCLK); 867 } 868 869 void 870 tl_statchg(self) 871 struct device *self; 872 { 873 tl_softc_t *sc = (struct tl_softc *)self; 874 u_int32_t reg; 875 876 #ifdef TLDEBUG 877 printf("tl_statchg, media %x\n", sc->tl_ifmedia.ifm_media); 878 #endif 879 880 /* 881 * We must keep the ThunderLAN and the PHY in sync as 882 * to the status of full-duplex! 883 */ 884 reg = tl_intreg_read_byte(sc, TL_INT_NET + TL_INT_NetCmd); 885 if (sc->tl_mii.mii_media_active & IFM_FDX) 886 reg |= TL_NETCOMMAND_DUPLEX; 887 else 888 reg &= ~TL_NETCOMMAND_DUPLEX; 889 tl_intreg_write_byte(sc, TL_INT_NET + TL_INT_NetCmd, reg); 890 } 891 892 void tl_i2c_set(v, bit) 893 void *v; 894 u_int8_t bit; 895 { 896 tl_softc_t *sc = v; 897 898 switch (bit) { 899 case I2C_DATA: 900 netsio_set(sc, TL_NETSIO_EDATA); 901 break; 902 case I2C_CLOCK: 903 netsio_set(sc, TL_NETSIO_ECLOCK); 904 break; 905 case I2C_TXEN: 906 netsio_set(sc, TL_NETSIO_ETXEN); 907 break; 908 default: 909 printf("tl_i2c_set: unknown bit %d\n", bit); 910 } 911 return; 912 } 913 914 void tl_i2c_clr(v, bit) 915 void *v; 916 u_int8_t bit; 917 { 918 tl_softc_t *sc = v; 919 920 switch (bit) { 921 case I2C_DATA: 922 netsio_clr(sc, TL_NETSIO_EDATA); 923 break; 924 case I2C_CLOCK: 925 netsio_clr(sc, TL_NETSIO_ECLOCK); 926 break; 927 case I2C_TXEN: 928 netsio_clr(sc, TL_NETSIO_ETXEN); 929 break; 930 default: 931 printf("tl_i2c_clr: unknown bit %d\n", bit); 932 } 933 return; 934 } 935 936 int tl_i2c_read(v, bit) 937 void *v; 938 u_int8_t bit; 939 { 940 tl_softc_t *sc = v; 941 942 switch (bit) { 943 case I2C_DATA: 944 return netsio_read(sc, TL_NETSIO_EDATA); 945 break; 946 case I2C_CLOCK: 947 return netsio_read(sc, TL_NETSIO_ECLOCK); 948 break; 949 case I2C_TXEN: 950 return netsio_read(sc, TL_NETSIO_ETXEN); 951 break; 952 default: 953 printf("tl_i2c_read: unknown bit %d\n", bit); 954 return -1; 955 } 956 } 957 958 static int 959 tl_intr(v) 960 void *v; 961 { 962 tl_softc_t *sc = v; 963 struct ifnet *ifp = &sc->tl_if; 964 struct Rx_list *Rx; 965 struct Tx_list *Tx; 966 struct mbuf *m; 967 u_int32_t int_type, int_reg; 968 int ack = 0; 969 int size; 970 971 int_reg = TL_HR_READ(sc, TL_HOST_INTR_DIOADR); 972 int_type = int_reg & TL_INTR_MASK; 973 if (int_type == 0) 974 return 0; 975 #if defined(TLDEBUG_RX) || defined(TLDEBUG_TX) 976 printf("%s: interrupt type %x, intr_reg %x\n", sc->sc_dev.dv_xname, 977 int_type, int_reg); 978 #endif 979 /* disable interrupts */ 980 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOff); 981 switch(int_type & TL_INTR_MASK) { 982 case TL_INTR_RxEOF: 983 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 984 sizeof(struct tl_Rx_list) * TL_NBUF, 985 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 986 while(le32toh(sc->active_Rx->hw_list->stat) & 987 TL_RX_CSTAT_CPLT) { 988 /* dequeue and requeue at end of list */ 989 ack++; 990 Rx = sc->active_Rx; 991 sc->active_Rx = Rx->next; 992 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 993 MCLBYTES, BUS_DMASYNC_POSTREAD); 994 bus_dmamap_unload(sc->tl_dmatag, Rx->m_dmamap); 995 m = Rx->m; 996 size = le32toh(Rx->hw_list->stat) >> 16; 997 #ifdef TLDEBUG_RX 998 printf("tl_intr: RX list complete, Rx %p, size=%d\n", 999 Rx, size); 1000 #endif 1001 if (tl_add_RxBuff(sc, Rx, m ) == 0) { 1002 /* 1003 * No new mbuf, reuse the same. This means 1004 * that this packet 1005 * is lost 1006 */ 1007 m = NULL; 1008 #ifdef TL_PRIV_STATS 1009 sc->ierr_nomem++; 1010 #endif 1011 #ifdef TLDEBUG 1012 printf("%s: out of mbuf, lost input packet\n", 1013 sc->sc_dev.dv_xname); 1014 #endif 1015 } 1016 Rx->next = NULL; 1017 Rx->hw_list->fwd = 0; 1018 sc->last_Rx->hw_list->fwd = htole32(Rx->hw_listaddr); 1019 sc->last_Rx->next = Rx; 1020 sc->last_Rx = Rx; 1021 1022 /* deliver packet */ 1023 if (m) { 1024 if (size < sizeof(struct ether_header)) { 1025 m_freem(m); 1026 continue; 1027 } 1028 m->m_pkthdr.rcvif = ifp; 1029 m->m_pkthdr.len = m->m_len = size; 1030 #ifdef TLDEBUG_RX 1031 { struct ether_header *eh = 1032 mtod(m, struct ether_header *); 1033 printf("tl_intr: Rx packet:\n"); 1034 ether_printheader(eh); } 1035 #endif 1036 #if NBPFILTER > 0 1037 if (ifp->if_bpf) 1038 bpf_mtap(ifp->if_bpf, m); 1039 #endif /* NBPFILTER > 0 */ 1040 (*ifp->if_input)(ifp, m); 1041 } 1042 } 1043 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1044 sizeof(struct tl_Rx_list) * TL_NBUF, 1045 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1046 #ifdef TLDEBUG_RX 1047 printf("TL_INTR_RxEOF: ack %d\n", ack); 1048 #else 1049 if (ack == 0) { 1050 printf("%s: EOF intr without anything to read !\n", 1051 sc->sc_dev.dv_xname); 1052 tl_reset(sc); 1053 /* shedule reinit of the board */ 1054 callout_reset(&sc->tl_restart_ch, 1, tl_restart, sc); 1055 return(1); 1056 } 1057 #endif 1058 break; 1059 case TL_INTR_RxEOC: 1060 ack++; 1061 bus_dmamap_sync(sc->tl_dmatag, sc->Rx_dmamap, 0, 1062 sizeof(struct tl_Rx_list) * TL_NBUF, 1063 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1064 #ifdef TLDEBUG_RX 1065 printf("TL_INTR_RxEOC: ack %d\n", ack); 1066 #endif 1067 #ifdef DIAGNOSTIC 1068 if (le32toh(sc->active_Rx->hw_list->stat) & TL_RX_CSTAT_CPLT) { 1069 printf("%s: Rx EOC interrupt and active Tx list not " 1070 "cleared\n", sc->sc_dev.dv_xname); 1071 return 0; 1072 } else 1073 #endif 1074 { 1075 /* 1076 * write adress of Rx list and send Rx GO command, ack 1077 * interrupt and enable interrupts in one command 1078 */ 1079 TL_HR_WRITE(sc, TL_HOST_CH_PARM, sc->active_Rx->hw_listaddr); 1080 TL_HR_WRITE(sc, TL_HOST_CMD, 1081 HOST_CMD_GO | HOST_CMD_RT | HOST_CMD_Nes | ack | int_type | 1082 HOST_CMD_ACK | HOST_CMD_IntOn); 1083 return 1; 1084 } 1085 case TL_INTR_TxEOF: 1086 case TL_INTR_TxEOC: 1087 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1088 sizeof(struct tl_Tx_list) * TL_NBUF, 1089 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1090 while ((Tx = sc->active_Tx) != NULL) { 1091 if((le32toh(Tx->hw_list->stat) & TL_TX_CSTAT_CPLT) == 0) 1092 break; 1093 ack++; 1094 #ifdef TLDEBUG_TX 1095 printf("TL_INTR_TxEOC: list 0x%x done\n", 1096 (int)Tx->hw_listaddr); 1097 #endif 1098 Tx->hw_list->stat = 0; 1099 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, 1100 MCLBYTES, BUS_DMASYNC_POSTWRITE); 1101 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1102 m_freem(Tx->m); 1103 Tx->m = NULL; 1104 sc->active_Tx = Tx->next; 1105 if (sc->active_Tx == NULL) 1106 sc->last_Tx = NULL; 1107 Tx->next = sc->Free_Tx; 1108 sc->Free_Tx = Tx; 1109 } 1110 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1111 sizeof(struct tl_Tx_list) * TL_NBUF, 1112 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1113 /* if this was an EOC, ACK immediatly */ 1114 if (ack) 1115 sc->tl_if.if_flags &= ~IFF_OACTIVE; 1116 if (int_type == TL_INTR_TxEOC) { 1117 #ifdef TLDEBUG_TX 1118 printf("TL_INTR_TxEOC: ack %d (will be set to 1)\n", 1119 ack); 1120 #endif 1121 TL_HR_WRITE(sc, TL_HOST_CMD, 1 | int_type | 1122 HOST_CMD_ACK | HOST_CMD_IntOn); 1123 if ( sc->active_Tx != NULL) { 1124 /* needs a Tx go command */ 1125 TL_HR_WRITE(sc, TL_HOST_CH_PARM, 1126 sc->active_Tx->hw_listaddr); 1127 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1128 } 1129 sc->tl_if.if_timer = 0; 1130 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0) 1131 tl_ifstart(&sc->tl_if); 1132 return 1; 1133 } 1134 #ifdef TLDEBUG 1135 else { 1136 printf("TL_INTR_TxEOF: ack %d\n", ack); 1137 } 1138 #endif 1139 sc->tl_if.if_timer = 0; 1140 if (IFQ_IS_EMPTY(&sc->tl_if.if_snd) == 0) 1141 tl_ifstart(&sc->tl_if); 1142 break; 1143 case TL_INTR_Stat: 1144 ack++; 1145 #ifdef TLDEBUG 1146 printf("TL_INTR_Stat: ack %d\n", ack); 1147 #endif 1148 tl_read_stats(sc); 1149 break; 1150 case TL_INTR_Adc: 1151 if (int_reg & TL_INTVec_MASK) { 1152 /* adapter check conditions */ 1153 printf("%s: check condition, intvect=0x%x, " 1154 "ch_param=0x%x\n", sc->sc_dev.dv_xname, 1155 int_reg & TL_INTVec_MASK, 1156 TL_HR_READ(sc, TL_HOST_CH_PARM)); 1157 tl_reset(sc); 1158 /* shedule reinit of the board */ 1159 callout_reset(&sc->tl_restart_ch, 1, tl_restart, sc); 1160 return(1); 1161 } else { 1162 u_int8_t netstat; 1163 /* Network status */ 1164 netstat = 1165 tl_intreg_read_byte(sc, TL_INT_NET+TL_INT_NetSts); 1166 printf("%s: network status, NetSts=%x\n", 1167 sc->sc_dev.dv_xname, netstat); 1168 /* Ack interrupts */ 1169 tl_intreg_write_byte(sc, TL_INT_NET+TL_INT_NetSts, 1170 netstat); 1171 ack++; 1172 } 1173 break; 1174 default: 1175 printf("%s: unhandled interrupt code %x!\n", 1176 sc->sc_dev.dv_xname, int_type); 1177 ack++; 1178 } 1179 1180 if (ack) { 1181 /* Ack the interrupt and enable interrupts */ 1182 TL_HR_WRITE(sc, TL_HOST_CMD, ack | int_type | HOST_CMD_ACK | 1183 HOST_CMD_IntOn); 1184 return 1; 1185 } 1186 /* ack = 0 ; interrupt was perhaps not our. Just enable interrupts */ 1187 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_IntOn); 1188 return 0; 1189 } 1190 1191 static int 1192 tl_ifioctl(ifp, cmd, data) 1193 struct ifnet *ifp; 1194 ioctl_cmd_t cmd; 1195 caddr_t data; 1196 { 1197 struct tl_softc *sc = ifp->if_softc; 1198 struct ifreq *ifr = (struct ifreq *)data; 1199 int s, error; 1200 1201 s = splnet(); 1202 switch(cmd) { 1203 case SIOCSIFMEDIA: 1204 case SIOCGIFMEDIA: 1205 error = ifmedia_ioctl(ifp, ifr, &sc->tl_mii.mii_media, cmd); 1206 break; 1207 default: 1208 error = ether_ioctl(ifp, cmd, data); 1209 if (error == ENETRESET) { 1210 tl_addr_filter(sc); 1211 error = 0; 1212 } 1213 } 1214 splx(s); 1215 return error; 1216 } 1217 1218 static void 1219 tl_ifstart(ifp) 1220 struct ifnet *ifp; 1221 { 1222 tl_softc_t *sc = ifp->if_softc; 1223 struct mbuf *mb_head; 1224 struct Tx_list *Tx; 1225 int segment, size; 1226 int again, error; 1227 1228 if ((sc->tl_if.if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 1229 return; 1230 txloop: 1231 /* If we don't have more space ... */ 1232 if (sc->Free_Tx == NULL) { 1233 #ifdef TLDEBUG 1234 printf("tl_ifstart: No free TX list\n"); 1235 #endif 1236 sc->tl_if.if_flags |= IFF_OACTIVE; 1237 return; 1238 } 1239 /* Grab a paquet for output */ 1240 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1241 if (mb_head == NULL) { 1242 #ifdef TLDEBUG_TX 1243 printf("tl_ifstart: nothing to send\n"); 1244 #endif 1245 return; 1246 } 1247 Tx = sc->Free_Tx; 1248 sc->Free_Tx = Tx->next; 1249 Tx->next = NULL; 1250 again = 0; 1251 /* 1252 * Go through each of the mbufs in the chain and initialize 1253 * the transmit list descriptors with the physical address 1254 * and size of the mbuf. 1255 */ 1256 tbdinit: 1257 memset(Tx->hw_list, 0, sizeof(struct tl_Tx_list)); 1258 Tx->m = mb_head; 1259 size = mb_head->m_pkthdr.len; 1260 if ((error = bus_dmamap_load_mbuf(sc->tl_dmatag, Tx->m_dmamap, mb_head, 1261 BUS_DMA_NOWAIT)) || (size < ETHER_MIN_TX && 1262 Tx->m_dmamap->dm_nsegs == TL_NSEG)) { 1263 struct mbuf *mn; 1264 /* 1265 * We ran out of segments, or we will. We have to recopy this 1266 * mbuf chain first. 1267 */ 1268 if (error == 0) 1269 bus_dmamap_unload(sc->tl_dmatag, Tx->m_dmamap); 1270 if (again) { 1271 /* already copyed, can't do much more */ 1272 m_freem(mb_head); 1273 goto bad; 1274 } 1275 again = 1; 1276 #ifdef TLDEBUG_TX 1277 printf("tl_ifstart: need to copy mbuf\n"); 1278 #endif 1279 #ifdef TL_PRIV_STATS 1280 sc->oerr_mcopy++; 1281 #endif 1282 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1283 if (mn == NULL) { 1284 m_freem(mb_head); 1285 goto bad; 1286 } 1287 if (mb_head->m_pkthdr.len > MHLEN) { 1288 MCLGET(mn, M_DONTWAIT); 1289 if ((mn->m_flags & M_EXT) == 0) { 1290 m_freem(mn); 1291 m_freem(mb_head); 1292 goto bad; 1293 } 1294 } 1295 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1296 mtod(mn, caddr_t)); 1297 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1298 m_freem(mb_head); 1299 mb_head = mn; 1300 goto tbdinit; 1301 } 1302 for (segment = 0; segment < Tx->m_dmamap->dm_nsegs; segment++) { 1303 Tx->hw_list->seg[segment].data_addr = 1304 htole32(Tx->m_dmamap->dm_segs[segment].ds_addr); 1305 Tx->hw_list->seg[segment].data_count = 1306 htole32(Tx->m_dmamap->dm_segs[segment].ds_len); 1307 } 1308 bus_dmamap_sync(sc->tl_dmatag, Tx->m_dmamap, 0, size, 1309 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1310 /* We are at end of mbuf chain. check the size and 1311 * see if it needs to be extended 1312 */ 1313 if (size < ETHER_MIN_TX) { 1314 #ifdef DIAGNOSTIC 1315 if (segment >= TL_NSEG) { 1316 panic("tl_ifstart: to much segmets (%d)", segment); 1317 } 1318 #endif 1319 /* 1320 * add the nullbuf in the seg 1321 */ 1322 Tx->hw_list->seg[segment].data_count = 1323 htole32(ETHER_MIN_TX - size); 1324 Tx->hw_list->seg[segment].data_addr = 1325 htole32(sc->null_dmamap->dm_segs[0].ds_addr); 1326 size = ETHER_MIN_TX; 1327 segment++; 1328 } 1329 /* The list is done, finish the list init */ 1330 Tx->hw_list->seg[segment-1].data_count |= 1331 htole32(TL_LAST_SEG); 1332 Tx->hw_list->stat = htole32((size << 16) | 0x3000); 1333 #ifdef TLDEBUG_TX 1334 printf("%s: sending, Tx : stat = 0x%x\n", sc->sc_dev.dv_xname, 1335 le32toh(Tx->hw_list->stat)); 1336 #if 0 1337 for(segment = 0; segment < TL_NSEG; segment++) { 1338 printf(" seg %d addr 0x%x len 0x%x\n", 1339 segment, 1340 le32toh(Tx->hw_list->seg[segment].data_addr), 1341 le32toh(Tx->hw_list->seg[segment].data_count)); 1342 } 1343 #endif 1344 #endif 1345 if (sc->active_Tx == NULL) { 1346 sc->active_Tx = sc->last_Tx = Tx; 1347 #ifdef TLDEBUG_TX 1348 printf("%s: Tx GO, addr=0x%ux\n", sc->sc_dev.dv_xname, 1349 (int)Tx->hw_listaddr); 1350 #endif 1351 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1352 sizeof(struct tl_Tx_list) * TL_NBUF, 1353 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1354 TL_HR_WRITE(sc, TL_HOST_CH_PARM, Tx->hw_listaddr); 1355 TL_HR_WRITE(sc, TL_HOST_CMD, HOST_CMD_GO); 1356 } else { 1357 #ifdef TLDEBUG_TX 1358 printf("%s: Tx addr=0x%ux queued\n", sc->sc_dev.dv_xname, 1359 (int)Tx->hw_listaddr); 1360 #endif 1361 sc->last_Tx->hw_list->fwd = htole32(Tx->hw_listaddr); 1362 bus_dmamap_sync(sc->tl_dmatag, sc->Tx_dmamap, 0, 1363 sizeof(struct tl_Tx_list) * TL_NBUF, 1364 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1365 sc->last_Tx->next = Tx; 1366 sc->last_Tx = Tx; 1367 #ifdef DIAGNOSTIC 1368 if (sc->last_Tx->hw_list->fwd & 0x7) 1369 printf("%s: physical addr 0x%x of list not properly " 1370 "aligned\n", 1371 sc->sc_dev.dv_xname, sc->last_Rx->hw_list->fwd); 1372 #endif 1373 } 1374 #if NBPFILTER > 0 1375 /* Pass packet to bpf if there is a listener */ 1376 if (ifp->if_bpf) 1377 bpf_mtap(ifp->if_bpf, mb_head); 1378 #endif 1379 /* 1380 * Set a 5 second timer just in case we don't hear from the card again. 1381 */ 1382 ifp->if_timer = 5; 1383 goto txloop; 1384 bad: 1385 #ifdef TLDEBUG 1386 printf("tl_ifstart: Out of mbuf, Tx pkt lost\n"); 1387 #endif 1388 Tx->next = sc->Free_Tx; 1389 sc->Free_Tx = Tx; 1390 return; 1391 } 1392 1393 static void 1394 tl_ifwatchdog(ifp) 1395 struct ifnet *ifp; 1396 { 1397 tl_softc_t *sc = ifp->if_softc; 1398 1399 if ((ifp->if_flags & IFF_RUNNING) == 0) 1400 return; 1401 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1402 ifp->if_oerrors++; 1403 tl_init(ifp); 1404 } 1405 1406 static int 1407 tl_mediachange(ifp) 1408 struct ifnet *ifp; 1409 { 1410 1411 if (ifp->if_flags & IFF_UP) 1412 tl_init(ifp); 1413 return (0); 1414 } 1415 1416 static void 1417 tl_mediastatus(ifp, ifmr) 1418 struct ifnet *ifp; 1419 struct ifmediareq *ifmr; 1420 { 1421 tl_softc_t *sc = ifp->if_softc; 1422 1423 mii_pollstat(&sc->tl_mii); 1424 ifmr->ifm_active = sc->tl_mii.mii_media_active; 1425 ifmr->ifm_status = sc->tl_mii.mii_media_status; 1426 } 1427 1428 static int tl_add_RxBuff(sc, Rx, oldm) 1429 tl_softc_t *sc; 1430 struct Rx_list *Rx; 1431 struct mbuf *oldm; 1432 { 1433 struct mbuf *m; 1434 int error; 1435 1436 MGETHDR(m, M_DONTWAIT, MT_DATA); 1437 if (m != NULL) { 1438 MCLGET(m, M_DONTWAIT); 1439 if ((m->m_flags & M_EXT) == 0) { 1440 m_freem(m); 1441 if (oldm == NULL) 1442 return 0; 1443 m = oldm; 1444 m->m_data = m->m_ext.ext_buf; 1445 } 1446 } else { 1447 if (oldm == NULL) 1448 return 0; 1449 m = oldm; 1450 m->m_data = m->m_ext.ext_buf; 1451 } 1452 1453 /* (re)init the Rx_list struct */ 1454 1455 Rx->m = m; 1456 if ((error = bus_dmamap_load(sc->tl_dmatag, Rx->m_dmamap, 1457 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1458 printf("%s: bus_dmamap_load() failed (error %d) for " 1459 "tl_add_RxBuff\n", sc->sc_dev.dv_xname, error); 1460 printf("size %d (%d)\n", m->m_pkthdr.len, MCLBYTES); 1461 m_freem(m); 1462 Rx->m = NULL; 1463 return 0; 1464 } 1465 bus_dmamap_sync(sc->tl_dmatag, Rx->m_dmamap, 0, 1466 MCLBYTES, BUS_DMASYNC_PREREAD); 1467 /* 1468 * Move the data pointer up so that the incoming data packet 1469 * will be 32-bit aligned. 1470 */ 1471 m->m_data += 2; 1472 1473 Rx->hw_list->stat = 1474 htole32(((Rx->m_dmamap->dm_segs[0].ds_len -2) << 16) | 0x3000); 1475 Rx->hw_list->seg.data_count = 1476 htole32(Rx->m_dmamap->dm_segs[0].ds_len -2); 1477 Rx->hw_list->seg.data_addr = 1478 htole32(Rx->m_dmamap->dm_segs[0].ds_addr + 2); 1479 return (m != oldm); 1480 } 1481 1482 static void tl_ticks(v) 1483 void *v; 1484 { 1485 tl_softc_t *sc = v; 1486 1487 tl_read_stats(sc); 1488 1489 /* Tick the MII. */ 1490 mii_tick(&sc->tl_mii); 1491 1492 /* read statistics every seconds */ 1493 callout_reset(&sc->tl_tick_ch, hz, tl_ticks, sc); 1494 } 1495 1496 static void 1497 tl_read_stats(sc) 1498 tl_softc_t *sc; 1499 { 1500 u_int32_t reg; 1501 int ierr_overr; 1502 int ierr_code; 1503 int ierr_crc; 1504 int oerr_underr; 1505 int oerr_deffered; 1506 int oerr_coll; 1507 int oerr_multicoll; 1508 int oerr_exesscoll; 1509 int oerr_latecoll; 1510 int oerr_carrloss; 1511 struct ifnet *ifp = &sc->tl_if; 1512 1513 reg = tl_intreg_read(sc, TL_INT_STATS_TX); 1514 ifp->if_opackets += reg & 0x00ffffff; 1515 oerr_underr = reg >> 24; 1516 1517 reg = tl_intreg_read(sc, TL_INT_STATS_RX); 1518 ifp->if_ipackets += reg & 0x00ffffff; 1519 ierr_overr = reg >> 24; 1520 1521 reg = tl_intreg_read(sc, TL_INT_STATS_FERR); 1522 ierr_crc = (reg & TL_FERR_CRC) >> 16; 1523 ierr_code = (reg & TL_FERR_CODE) >> 24; 1524 oerr_deffered = (reg & TL_FERR_DEF); 1525 1526 reg = tl_intreg_read(sc, TL_INT_STATS_COLL); 1527 oerr_multicoll = (reg & TL_COL_MULTI); 1528 oerr_coll = (reg & TL_COL_SINGLE) >> 16; 1529 1530 reg = tl_intreg_read(sc, TL_INT_LERR); 1531 oerr_exesscoll = (reg & TL_LERR_ECOLL); 1532 oerr_latecoll = (reg & TL_LERR_LCOLL) >> 8; 1533 oerr_carrloss = (reg & TL_LERR_CL) >> 16; 1534 1535 1536 ifp->if_oerrors += oerr_underr + oerr_exesscoll + oerr_latecoll + 1537 oerr_carrloss; 1538 ifp->if_collisions += oerr_coll + oerr_multicoll; 1539 ifp->if_ierrors += ierr_overr + ierr_code + ierr_crc; 1540 1541 if (ierr_overr) 1542 printf("%s: receiver ring buffer overrun\n", 1543 sc->sc_dev.dv_xname); 1544 if (oerr_underr) 1545 printf("%s: transmit buffer underrun\n", 1546 sc->sc_dev.dv_xname); 1547 #ifdef TL_PRIV_STATS 1548 sc->ierr_overr += ierr_overr; 1549 sc->ierr_code += ierr_code; 1550 sc->ierr_crc += ierr_crc; 1551 sc->oerr_underr += oerr_underr; 1552 sc->oerr_deffered += oerr_deffered; 1553 sc->oerr_coll += oerr_coll; 1554 sc->oerr_multicoll += oerr_multicoll; 1555 sc->oerr_exesscoll += oerr_exesscoll; 1556 sc->oerr_latecoll += oerr_latecoll; 1557 sc->oerr_carrloss += oerr_carrloss; 1558 #endif 1559 } 1560 1561 static void tl_addr_filter(sc) 1562 tl_softc_t *sc; 1563 { 1564 struct ether_multistep step; 1565 struct ether_multi *enm; 1566 u_int32_t hash[2] = {0, 0}; 1567 int i; 1568 1569 sc->tl_if.if_flags &= ~IFF_ALLMULTI; 1570 ETHER_FIRST_MULTI(step, &sc->tl_ec, enm); 1571 while (enm != NULL) { 1572 #ifdef TLDEBUG 1573 printf("tl_addr_filter: addrs %s %s\n", 1574 ether_sprintf(enm->enm_addrlo), 1575 ether_sprintf(enm->enm_addrhi)); 1576 #endif 1577 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) == 0) { 1578 i = tl_multicast_hash(enm->enm_addrlo); 1579 hash[i/32] |= 1 << (i%32); 1580 } else { 1581 hash[0] = hash[1] = 0xffffffff; 1582 sc->tl_if.if_flags |= IFF_ALLMULTI; 1583 break; 1584 } 1585 ETHER_NEXT_MULTI(step, enm); 1586 } 1587 #ifdef TLDEBUG 1588 printf("tl_addr_filer: hash1 %x has2 %x\n", hash[0], hash[1]); 1589 #endif 1590 tl_intreg_write(sc, TL_INT_HASH1, hash[0]); 1591 tl_intreg_write(sc, TL_INT_HASH2, hash[1]); 1592 } 1593 1594 static int tl_multicast_hash(a) 1595 u_int8_t *a; 1596 { 1597 int hash; 1598 1599 #define DA(addr,bit) (addr[5 - (bit/8)] & (1 << bit%8)) 1600 #define xor8(a,b,c,d,e,f,g,h) (((a != 0) + (b != 0) + (c != 0) + (d != 0) + (e != 0) + (f != 0) + (g != 0) + (h != 0)) & 1) 1601 1602 hash = xor8( DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24), DA(a,30), 1603 DA(a,36), DA(a,42)); 1604 hash |= xor8( DA(a,1), DA(a, 7), DA(a,13), DA(a,19), DA(a,25), DA(a,31), 1605 DA(a,37), DA(a,43)) << 1; 1606 hash |= xor8( DA(a,2), DA(a, 8), DA(a,14), DA(a,20), DA(a,26), DA(a,32), 1607 DA(a,38), DA(a,44)) << 2; 1608 hash |= xor8( DA(a,3), DA(a, 9), DA(a,15), DA(a,21), DA(a,27), DA(a,33), 1609 DA(a,39), DA(a,45)) << 3; 1610 hash |= xor8( DA(a,4), DA(a,10), DA(a,16), DA(a,22), DA(a,28), DA(a,34), 1611 DA(a,40), DA(a,46)) << 4; 1612 hash |= xor8( DA(a,5), DA(a,11), DA(a,17), DA(a,23), DA(a,29), DA(a,35), 1613 DA(a,41), DA(a,47)) << 5; 1614 1615 return hash; 1616 } 1617 1618 #if defined(TLDEBUG_RX) 1619 void 1620 ether_printheader(eh) 1621 struct ether_header *eh; 1622 { 1623 u_char *c = (char*)eh; 1624 int i; 1625 for (i=0; i<sizeof(struct ether_header); i++) 1626 printf("%x ", (u_int)c[i]); 1627 printf("\n"); 1628 } 1629 #endif 1630