1 /* $NetBSD: if_ti.c,v 1.79 2007/11/07 00:23:19 ad Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_ti.c,v 1.15 1999/08/14 15:45:03 wpaul Exp 35 */ 36 37 /* 38 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 39 * Manuals, sample driver and firmware source kits are available 40 * from http://www.alteon.com/support/openkits. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 49 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 50 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 51 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 52 * filtering and jumbo (9014 byte) frames. The hardware is largely 53 * controlled by firmware, which must be loaded into the NIC during 54 * initialization. 55 * 56 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 57 * revision, which supports new features such as extended commands, 58 * extended jumbo receive ring desciptors and a mini receive ring. 59 * 60 * Alteon Networks is to be commended for releasing such a vast amount 61 * of development material for the Tigon NIC without requiring an NDA 62 * (although they really should have done it a long time ago). With 63 * any luck, the other vendors will finally wise up and follow Alteon's 64 * stellar example. 65 * 66 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 67 * this driver by #including it as a C header file. This bloats the 68 * driver somewhat, but it's the easiest method considering that the 69 * driver code and firmware code need to be kept in sync. The source 70 * for the firmware is not provided with the FreeBSD distribution since 71 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 72 * 73 * The following people deserve special thanks: 74 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 75 * for testing 76 * - Raymond Lee of Netgear, for providing a pair of Netgear 77 * GA620 Tigon 2 boards for testing 78 * - Ulf Zimmermann, for bringing the GA620 to my attention and 79 * convincing me to write this driver. 80 * - Andrew Gallatin for providing FreeBSD/Alpha support. 81 */ 82 83 #include <sys/cdefs.h> 84 __KERNEL_RCSID(0, "$NetBSD: if_ti.c,v 1.79 2007/11/07 00:23:19 ad Exp $"); 85 86 #include "bpfilter.h" 87 #include "opt_inet.h" 88 89 #include <sys/param.h> 90 #include <sys/systm.h> 91 #include <sys/sockio.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/socket.h> 96 #include <sys/queue.h> 97 #include <sys/device.h> 98 #include <sys/reboot.h> 99 100 #include <uvm/uvm_extern.h> 101 102 #include <net/if.h> 103 #include <net/if_arp.h> 104 #include <net/if_ether.h> 105 #include <net/if_dl.h> 106 #include <net/if_media.h> 107 108 #if NBPFILTER > 0 109 #include <net/bpf.h> 110 #endif 111 112 #ifdef INET 113 #include <netinet/in.h> 114 #include <netinet/if_inarp.h> 115 #include <netinet/in_systm.h> 116 #include <netinet/ip.h> 117 #endif 118 119 120 #include <sys/bus.h> 121 122 #include <dev/pci/pcireg.h> 123 #include <dev/pci/pcivar.h> 124 #include <dev/pci/pcidevs.h> 125 126 #include <dev/pci/if_tireg.h> 127 128 #include <dev/microcode/tigon/ti_fw.h> 129 #include <dev/microcode/tigon/ti_fw2.h> 130 131 /* 132 * Various supported device vendors/types and their names. 133 */ 134 135 static const struct ti_type ti_devs[] = { 136 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC, 137 "Alteon AceNIC 1000BASE-SX Ethernet" }, 138 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC_COPPER, 139 "Alteon AceNIC 1000BASE-T Ethernet" }, 140 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C985, 141 "3Com 3c985-SX Gigabit Ethernet" }, 142 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620, 143 "Netgear GA620 1000BASE-SX Ethernet" }, 144 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620T, 145 "Netgear GA620 1000BASE-T Ethernet" }, 146 { PCI_VENDOR_SGI, PCI_PRODUCT_SGI_TIGON, 147 "Silicon Graphics Gigabit Ethernet" }, 148 { 0, 0, NULL } 149 }; 150 151 static const struct ti_type *ti_type_match(struct pci_attach_args *); 152 static int ti_probe(struct device *, struct cfdata *, void *); 153 static void ti_attach(struct device *, struct device *, void *); 154 static void ti_shutdown(void *); 155 static void ti_txeof_tigon1(struct ti_softc *); 156 static void ti_txeof_tigon2(struct ti_softc *); 157 static void ti_rxeof(struct ti_softc *); 158 159 static void ti_stats_update(struct ti_softc *); 160 static int ti_encap_tigon1(struct ti_softc *, struct mbuf *, u_int32_t *); 161 static int ti_encap_tigon2(struct ti_softc *, struct mbuf *, u_int32_t *); 162 163 static int ti_intr(void *); 164 static void ti_start(struct ifnet *); 165 static int ti_ioctl(struct ifnet *, u_long, void *); 166 static void ti_init(void *); 167 static void ti_init2(struct ti_softc *); 168 static void ti_stop(struct ti_softc *); 169 static void ti_watchdog(struct ifnet *); 170 static int ti_ifmedia_upd(struct ifnet *); 171 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 172 173 static u_int32_t ti_eeprom_putbyte(struct ti_softc *, int); 174 static u_int8_t ti_eeprom_getbyte(struct ti_softc *, int, u_int8_t *); 175 static int ti_read_eeprom(struct ti_softc *, void *, int, int); 176 177 static void ti_add_mcast(struct ti_softc *, struct ether_addr *); 178 static void ti_del_mcast(struct ti_softc *, struct ether_addr *); 179 static void ti_setmulti(struct ti_softc *); 180 181 static void ti_mem(struct ti_softc *, u_int32_t, u_int32_t, const void *); 182 static void ti_loadfw(struct ti_softc *); 183 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 184 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, void *, int); 185 static void ti_handle_events(struct ti_softc *); 186 static int ti_alloc_jumbo_mem(struct ti_softc *); 187 static void *ti_jalloc(struct ti_softc *); 188 static void ti_jfree(struct mbuf *, void *, size_t, void *); 189 static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *, bus_dmamap_t); 190 static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *, bus_dmamap_t); 191 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 192 static int ti_init_rx_ring_std(struct ti_softc *); 193 static void ti_free_rx_ring_std(struct ti_softc *); 194 static int ti_init_rx_ring_jumbo(struct ti_softc *); 195 static void ti_free_rx_ring_jumbo(struct ti_softc *); 196 static int ti_init_rx_ring_mini(struct ti_softc *); 197 static void ti_free_rx_ring_mini(struct ti_softc *); 198 static void ti_free_tx_ring(struct ti_softc *); 199 static int ti_init_tx_ring(struct ti_softc *); 200 201 static int ti_64bitslot_war(struct ti_softc *); 202 static int ti_chipinit(struct ti_softc *); 203 static int ti_gibinit(struct ti_softc *); 204 205 static int ti_ether_ioctl(struct ifnet *, u_long, void *); 206 207 CFATTACH_DECL(ti, sizeof(struct ti_softc), 208 ti_probe, ti_attach, NULL, NULL); 209 210 /* 211 * Send an instruction or address to the EEPROM, check for ACK. 212 */ 213 static u_int32_t 214 ti_eeprom_putbyte(struct ti_softc *sc, int byte) 215 { 216 int i, ack = 0; 217 218 /* 219 * Make sure we're in TX mode. 220 */ 221 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 222 223 /* 224 * Feed in each bit and stobe the clock. 225 */ 226 for (i = 0x80; i; i >>= 1) { 227 if (byte & i) { 228 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 229 } else { 230 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 231 } 232 DELAY(1); 233 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 234 DELAY(1); 235 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 236 } 237 238 /* 239 * Turn off TX mode. 240 */ 241 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 242 243 /* 244 * Check for ack. 245 */ 246 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 247 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 248 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 249 250 return (ack); 251 } 252 253 /* 254 * Read a byte of data stored in the EEPROM at address 'addr.' 255 * We have to send two address bytes since the EEPROM can hold 256 * more than 256 bytes of data. 257 */ 258 static u_int8_t 259 ti_eeprom_getbyte(struct ti_softc *sc, int addr, u_int8_t *dest) 260 { 261 int i; 262 u_int8_t byte = 0; 263 264 EEPROM_START(); 265 266 /* 267 * Send write control code to EEPROM. 268 */ 269 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 270 printf("%s: failed to send write command, status: %x\n", 271 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 272 return (1); 273 } 274 275 /* 276 * Send first byte of address of byte we want to read. 277 */ 278 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 279 printf("%s: failed to send address, status: %x\n", 280 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 281 return (1); 282 } 283 /* 284 * Send second byte address of byte we want to read. 285 */ 286 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 287 printf("%s: failed to send address, status: %x\n", 288 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 289 return (1); 290 } 291 292 EEPROM_STOP(); 293 EEPROM_START(); 294 /* 295 * Send read control code to EEPROM. 296 */ 297 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 298 printf("%s: failed to send read command, status: %x\n", 299 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 300 return (1); 301 } 302 303 /* 304 * Start reading bits from EEPROM. 305 */ 306 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 307 for (i = 0x80; i; i >>= 1) { 308 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 309 DELAY(1); 310 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 311 byte |= i; 312 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 313 DELAY(1); 314 } 315 316 EEPROM_STOP(); 317 318 /* 319 * No ACK generated for read, so just return byte. 320 */ 321 322 *dest = byte; 323 324 return (0); 325 } 326 327 /* 328 * Read a sequence of bytes from the EEPROM. 329 */ 330 static int 331 ti_read_eeprom(struct ti_softc *sc, void *destv, int off, int cnt) 332 { 333 char *dest = destv; 334 int err = 0, i; 335 u_int8_t byte = 0; 336 337 for (i = 0; i < cnt; i++) { 338 err = ti_eeprom_getbyte(sc, off + i, &byte); 339 if (err) 340 break; 341 *(dest + i) = byte; 342 } 343 344 return (err ? 1 : 0); 345 } 346 347 /* 348 * NIC memory access function. Can be used to either clear a section 349 * of NIC local memory or (if tbuf is non-NULL) copy data into it. 350 */ 351 static void 352 ti_mem(struct ti_softc *sc, u_int32_t addr, u_int32_t len, const void *xbuf) 353 { 354 int segptr, segsize, cnt; 355 const void *ptr; 356 357 segptr = addr; 358 cnt = len; 359 ptr = xbuf; 360 361 while (cnt) { 362 if (cnt < TI_WINLEN) 363 segsize = cnt; 364 else 365 segsize = TI_WINLEN - (segptr % TI_WINLEN); 366 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 367 if (xbuf == NULL) { 368 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 369 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, 370 segsize / 4); 371 } else { 372 #ifdef __BUS_SPACE_HAS_STREAM_METHODS 373 bus_space_write_region_stream_4(sc->ti_btag, 374 sc->ti_bhandle, 375 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 376 (const u_int32_t *)ptr, segsize / 4); 377 #else 378 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 379 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 380 (const u_int32_t *)ptr, segsize / 4); 381 #endif 382 ptr = (const char *)ptr + segsize; 383 } 384 segptr += segsize; 385 cnt -= segsize; 386 } 387 388 return; 389 } 390 391 /* 392 * Load firmware image into the NIC. Check that the firmware revision 393 * is acceptable and see if we want the firmware for the Tigon 1 or 394 * Tigon 2. 395 */ 396 static void 397 ti_loadfw(struct ti_softc *sc) 398 { 399 switch (sc->ti_hwrev) { 400 case TI_HWREV_TIGON: 401 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 402 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 403 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 404 printf("%s: firmware revision mismatch; want " 405 "%d.%d.%d, got %d.%d.%d\n", sc->sc_dev.dv_xname, 406 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 407 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 408 tigonFwReleaseMinor, tigonFwReleaseFix); 409 return; 410 } 411 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText); 412 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData); 413 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, tigonFwRodata); 414 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 415 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 416 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 417 break; 418 case TI_HWREV_TIGON_II: 419 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 420 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 421 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 422 printf("%s: firmware revision mismatch; want " 423 "%d.%d.%d, got %d.%d.%d\n", sc->sc_dev.dv_xname, 424 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 425 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 426 tigon2FwReleaseMinor, tigon2FwReleaseFix); 427 return; 428 } 429 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, tigon2FwText); 430 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, tigon2FwData); 431 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 432 tigon2FwRodata); 433 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 434 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 435 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 436 break; 437 default: 438 printf("%s: can't load firmware: unknown hardware rev\n", 439 sc->sc_dev.dv_xname); 440 break; 441 } 442 443 return; 444 } 445 446 /* 447 * Send the NIC a command via the command ring. 448 */ 449 static void 450 ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd) 451 { 452 u_int32_t index; 453 454 index = sc->ti_cmd_saved_prodidx; 455 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 456 TI_INC(index, TI_CMD_RING_CNT); 457 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 458 sc->ti_cmd_saved_prodidx = index; 459 } 460 461 /* 462 * Send the NIC an extended command. The 'len' parameter specifies the 463 * number of command slots to include after the initial command. 464 */ 465 static void 466 ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, void *argv, int len) 467 { 468 char *arg = argv; 469 u_int32_t index; 470 int i; 471 472 index = sc->ti_cmd_saved_prodidx; 473 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 474 TI_INC(index, TI_CMD_RING_CNT); 475 for (i = 0; i < len; i++) { 476 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 477 *(u_int32_t *)(&arg[i * 4])); 478 TI_INC(index, TI_CMD_RING_CNT); 479 } 480 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 481 sc->ti_cmd_saved_prodidx = index; 482 } 483 484 /* 485 * Handle events that have triggered interrupts. 486 */ 487 static void 488 ti_handle_events(struct ti_softc *sc) 489 { 490 struct ti_event_desc *e; 491 492 if (sc->ti_rdata->ti_event_ring == NULL) 493 return; 494 495 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 496 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 497 switch (TI_EVENT_EVENT(e)) { 498 case TI_EV_LINKSTAT_CHANGED: 499 sc->ti_linkstat = TI_EVENT_CODE(e); 500 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) 501 printf("%s: 10/100 link up\n", 502 sc->sc_dev.dv_xname); 503 else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) 504 printf("%s: gigabit link up\n", 505 sc->sc_dev.dv_xname); 506 else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 507 printf("%s: link down\n", 508 sc->sc_dev.dv_xname); 509 break; 510 case TI_EV_ERROR: 511 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD) 512 printf("%s: invalid command\n", 513 sc->sc_dev.dv_xname); 514 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD) 515 printf("%s: unknown command\n", 516 sc->sc_dev.dv_xname); 517 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG) 518 printf("%s: bad config data\n", 519 sc->sc_dev.dv_xname); 520 break; 521 case TI_EV_FIRMWARE_UP: 522 ti_init2(sc); 523 break; 524 case TI_EV_STATS_UPDATED: 525 ti_stats_update(sc); 526 break; 527 case TI_EV_RESET_JUMBO_RING: 528 case TI_EV_MCAST_UPDATED: 529 /* Who cares. */ 530 break; 531 default: 532 printf("%s: unknown event: %d\n", 533 sc->sc_dev.dv_xname, TI_EVENT_EVENT(e)); 534 break; 535 } 536 /* Advance the consumer index. */ 537 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 538 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 539 } 540 541 return; 542 } 543 544 /* 545 * Memory management for the jumbo receive ring is a pain in the 546 * butt. We need to allocate at least 9018 bytes of space per frame, 547 * _and_ it has to be contiguous (unless you use the extended 548 * jumbo descriptor format). Using malloc() all the time won't 549 * work: malloc() allocates memory in powers of two, which means we 550 * would end up wasting a considerable amount of space by allocating 551 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 552 * to do our own memory management. 553 * 554 * The driver needs to allocate a contiguous chunk of memory at boot 555 * time. We then chop this up ourselves into 9K pieces and use them 556 * as external mbuf storage. 557 * 558 * One issue here is how much memory to allocate. The jumbo ring has 559 * 256 slots in it, but at 9K per slot than can consume over 2MB of 560 * RAM. This is a bit much, especially considering we also need 561 * RAM for the standard ring and mini ring (on the Tigon 2). To 562 * save space, we only actually allocate enough memory for 64 slots 563 * by default, which works out to between 500 and 600K. This can 564 * be tuned by changing a #define in if_tireg.h. 565 */ 566 567 static int 568 ti_alloc_jumbo_mem(struct ti_softc *sc) 569 { 570 char *ptr; 571 int i; 572 struct ti_jpool_entry *entry; 573 bus_dma_segment_t dmaseg; 574 int error, dmanseg; 575 576 /* Grab a big chunk o' storage. */ 577 if ((error = bus_dmamem_alloc(sc->sc_dmat, 578 TI_JMEM, PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 579 BUS_DMA_NOWAIT)) != 0) { 580 printf("%s: can't allocate jumbo buffer, error = %d\n", 581 sc->sc_dev.dv_xname, error); 582 return (error); 583 } 584 585 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 586 TI_JMEM, (void **)&sc->ti_cdata.ti_jumbo_buf, 587 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 588 printf("%s: can't map jumbo buffer, error = %d\n", 589 sc->sc_dev.dv_xname, error); 590 return (error); 591 } 592 593 if ((error = bus_dmamap_create(sc->sc_dmat, 594 TI_JMEM, 1, 595 TI_JMEM, 0, BUS_DMA_NOWAIT, 596 &sc->jumbo_dmamap)) != 0) { 597 printf("%s: can't create jumbo buffer DMA map, error = %d\n", 598 sc->sc_dev.dv_xname, error); 599 return (error); 600 } 601 602 if ((error = bus_dmamap_load(sc->sc_dmat, sc->jumbo_dmamap, 603 sc->ti_cdata.ti_jumbo_buf, TI_JMEM, NULL, 604 BUS_DMA_NOWAIT)) != 0) { 605 printf("%s: can't load jumbo buffer DMA map, error = %d\n", 606 sc->sc_dev.dv_xname, error); 607 return (error); 608 } 609 sc->jumbo_dmaaddr = sc->jumbo_dmamap->dm_segs[0].ds_addr; 610 611 SIMPLEQ_INIT(&sc->ti_jfree_listhead); 612 SIMPLEQ_INIT(&sc->ti_jinuse_listhead); 613 614 /* 615 * Now divide it up into 9K pieces and save the addresses 616 * in an array. 617 */ 618 ptr = sc->ti_cdata.ti_jumbo_buf; 619 for (i = 0; i < TI_JSLOTS; i++) { 620 sc->ti_cdata.ti_jslots[i] = ptr; 621 ptr += TI_JLEN; 622 entry = malloc(sizeof(struct ti_jpool_entry), 623 M_DEVBUF, M_NOWAIT); 624 if (entry == NULL) { 625 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF); 626 sc->ti_cdata.ti_jumbo_buf = NULL; 627 printf("%s: no memory for jumbo " 628 "buffer queue!\n", sc->sc_dev.dv_xname); 629 return (ENOBUFS); 630 } 631 entry->slot = i; 632 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, 633 jpool_entries); 634 } 635 636 return (0); 637 } 638 639 /* 640 * Allocate a jumbo buffer. 641 */ 642 static void * 643 ti_jalloc(struct ti_softc *sc) 644 { 645 struct ti_jpool_entry *entry; 646 647 entry = SIMPLEQ_FIRST(&sc->ti_jfree_listhead); 648 649 if (entry == NULL) { 650 printf("%s: no free jumbo buffers\n", sc->sc_dev.dv_xname); 651 return (NULL); 652 } 653 654 SIMPLEQ_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 655 SIMPLEQ_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 656 657 return (sc->ti_cdata.ti_jslots[entry->slot]); 658 } 659 660 /* 661 * Release a jumbo buffer. 662 */ 663 static void 664 ti_jfree(struct mbuf *m, void *tbuf, size_t size, void *arg) 665 { 666 struct ti_softc *sc; 667 int i, s; 668 struct ti_jpool_entry *entry; 669 670 /* Extract the softc struct pointer. */ 671 sc = (struct ti_softc *)arg; 672 673 if (sc == NULL) 674 panic("ti_jfree: didn't get softc pointer!"); 675 676 /* calculate the slot this buffer belongs to */ 677 678 i = ((char *)tbuf 679 - (char *)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 680 681 if ((i < 0) || (i >= TI_JSLOTS)) 682 panic("ti_jfree: asked to free buffer that we don't manage!"); 683 684 s = splvm(); 685 entry = SIMPLEQ_FIRST(&sc->ti_jinuse_listhead); 686 if (entry == NULL) 687 panic("ti_jfree: buffer not in use!"); 688 entry->slot = i; 689 SIMPLEQ_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 690 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 691 692 if (__predict_true(m != NULL)) 693 pool_cache_put(mb_cache, m); 694 splx(s); 695 } 696 697 698 /* 699 * Intialize a standard receive ring descriptor. 700 */ 701 static int 702 ti_newbuf_std(struct ti_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap) 703 { 704 struct mbuf *m_new = NULL; 705 struct ti_rx_desc *r; 706 int error; 707 708 if (dmamap == NULL) { 709 /* if (m) panic() */ 710 711 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 712 MCLBYTES, 0, BUS_DMA_NOWAIT, 713 &dmamap)) != 0) { 714 printf("%s: can't create recv map, error = %d\n", 715 sc->sc_dev.dv_xname, error); 716 return (ENOMEM); 717 } 718 } 719 sc->std_dmamap[i] = dmamap; 720 721 if (m == NULL) { 722 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 723 if (m_new == NULL) { 724 printf("%s: mbuf allocation failed " 725 "-- packet dropped!\n", sc->sc_dev.dv_xname); 726 return (ENOBUFS); 727 } 728 729 MCLGET(m_new, M_DONTWAIT); 730 if (!(m_new->m_flags & M_EXT)) { 731 printf("%s: cluster allocation failed " 732 "-- packet dropped!\n", sc->sc_dev.dv_xname); 733 m_freem(m_new); 734 return (ENOBUFS); 735 } 736 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 737 m_adj(m_new, ETHER_ALIGN); 738 739 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 740 mtod(m_new, void *), m_new->m_len, NULL, 741 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 742 printf("%s: can't load recv map, error = %d\n", 743 sc->sc_dev.dv_xname, error); 744 return (ENOMEM); 745 } 746 } else { 747 m_new = m; 748 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 749 m_new->m_data = m_new->m_ext.ext_buf; 750 m_adj(m_new, ETHER_ALIGN); 751 752 /* reuse the dmamap */ 753 } 754 755 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 756 r = &sc->ti_rdata->ti_rx_std_ring[i]; 757 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 758 r->ti_type = TI_BDTYPE_RECV_BD; 759 r->ti_flags = 0; 760 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx) 761 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 762 if (sc->ethercom.ec_if.if_capenable & 763 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 764 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 765 r->ti_len = m_new->m_len; /* == ds_len */ 766 r->ti_idx = i; 767 768 return (0); 769 } 770 771 /* 772 * Intialize a mini receive ring descriptor. This only applies to 773 * the Tigon 2. 774 */ 775 static int 776 ti_newbuf_mini(struct ti_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap) 777 { 778 struct mbuf *m_new = NULL; 779 struct ti_rx_desc *r; 780 int error; 781 782 if (dmamap == NULL) { 783 /* if (m) panic() */ 784 785 if ((error = bus_dmamap_create(sc->sc_dmat, MHLEN, 1, 786 MHLEN, 0, BUS_DMA_NOWAIT, 787 &dmamap)) != 0) { 788 printf("%s: can't create recv map, error = %d\n", 789 sc->sc_dev.dv_xname, error); 790 return (ENOMEM); 791 } 792 } 793 sc->mini_dmamap[i] = dmamap; 794 795 if (m == NULL) { 796 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 797 if (m_new == NULL) { 798 printf("%s: mbuf allocation failed " 799 "-- packet dropped!\n", sc->sc_dev.dv_xname); 800 return (ENOBUFS); 801 } 802 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 803 m_adj(m_new, ETHER_ALIGN); 804 805 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 806 mtod(m_new, void *), m_new->m_len, NULL, 807 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 808 printf("%s: can't load recv map, error = %d\n", 809 sc->sc_dev.dv_xname, error); 810 return (ENOMEM); 811 } 812 } else { 813 m_new = m; 814 m_new->m_data = m_new->m_pktdat; 815 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 816 m_adj(m_new, ETHER_ALIGN); 817 818 /* reuse the dmamap */ 819 } 820 821 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 822 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 823 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 824 r->ti_type = TI_BDTYPE_RECV_BD; 825 r->ti_flags = TI_BDFLAG_MINI_RING; 826 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx) 827 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 828 if (sc->ethercom.ec_if.if_capenable & 829 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 830 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 831 r->ti_len = m_new->m_len; /* == ds_len */ 832 r->ti_idx = i; 833 834 return (0); 835 } 836 837 /* 838 * Initialize a jumbo receive ring descriptor. This allocates 839 * a jumbo buffer from the pool managed internally by the driver. 840 */ 841 static int 842 ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *m) 843 { 844 struct mbuf *m_new = NULL; 845 struct ti_rx_desc *r; 846 847 if (m == NULL) { 848 void * tbuf = NULL; 849 850 /* Allocate the mbuf. */ 851 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 852 if (m_new == NULL) { 853 printf("%s: mbuf allocation failed " 854 "-- packet dropped!\n", sc->sc_dev.dv_xname); 855 return (ENOBUFS); 856 } 857 858 /* Allocate the jumbo buffer */ 859 tbuf = ti_jalloc(sc); 860 if (tbuf == NULL) { 861 m_freem(m_new); 862 printf("%s: jumbo allocation failed " 863 "-- packet dropped!\n", sc->sc_dev.dv_xname); 864 return (ENOBUFS); 865 } 866 867 /* Attach the buffer to the mbuf. */ 868 MEXTADD(m_new, tbuf, ETHER_MAX_LEN_JUMBO, 869 M_DEVBUF, ti_jfree, sc); 870 m_new->m_flags |= M_EXT_RW; 871 m_new->m_len = m_new->m_pkthdr.len = ETHER_MAX_LEN_JUMBO; 872 } else { 873 m_new = m; 874 m_new->m_data = m_new->m_ext.ext_buf; 875 m_new->m_ext.ext_size = ETHER_MAX_LEN_JUMBO; 876 } 877 878 m_adj(m_new, ETHER_ALIGN); 879 /* Set up the descriptor. */ 880 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 881 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 882 TI_HOSTADDR(r->ti_addr) = sc->jumbo_dmaaddr + 883 (mtod(m_new, char *) - (char *)sc->ti_cdata.ti_jumbo_buf); 884 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 885 r->ti_flags = TI_BDFLAG_JUMBO_RING; 886 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx) 887 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 888 if (sc->ethercom.ec_if.if_capenable & 889 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 890 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 891 r->ti_len = m_new->m_len; 892 r->ti_idx = i; 893 894 return (0); 895 } 896 897 /* 898 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 899 * that's 1MB or memory, which is a lot. For now, we fill only the first 900 * 256 ring entries and hope that our CPU is fast enough to keep up with 901 * the NIC. 902 */ 903 static int 904 ti_init_rx_ring_std(struct ti_softc *sc) 905 { 906 int i; 907 struct ti_cmd_desc cmd; 908 909 for (i = 0; i < TI_SSLOTS; i++) { 910 if (ti_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 911 return (ENOBUFS); 912 }; 913 914 TI_UPDATE_STDPROD(sc, i - 1); 915 sc->ti_std = i - 1; 916 917 return (0); 918 } 919 920 static void 921 ti_free_rx_ring_std(struct ti_softc *sc) 922 { 923 int i; 924 925 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 926 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 927 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 928 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 929 930 /* if (sc->std_dmamap[i] == 0) panic() */ 931 bus_dmamap_destroy(sc->sc_dmat, sc->std_dmamap[i]); 932 sc->std_dmamap[i] = 0; 933 } 934 memset((char *)&sc->ti_rdata->ti_rx_std_ring[i], 0, 935 sizeof(struct ti_rx_desc)); 936 } 937 938 return; 939 } 940 941 static int 942 ti_init_rx_ring_jumbo(struct ti_softc *sc) 943 { 944 int i; 945 struct ti_cmd_desc cmd; 946 947 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 948 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 949 return (ENOBUFS); 950 }; 951 952 TI_UPDATE_JUMBOPROD(sc, i - 1); 953 sc->ti_jumbo = i - 1; 954 955 return (0); 956 } 957 958 static void 959 ti_free_rx_ring_jumbo(struct ti_softc *sc) 960 { 961 int i; 962 963 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 964 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 965 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 966 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 967 } 968 memset((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 0, 969 sizeof(struct ti_rx_desc)); 970 } 971 972 return; 973 } 974 975 static int 976 ti_init_rx_ring_mini(struct ti_softc *sc) 977 { 978 int i; 979 980 for (i = 0; i < TI_MSLOTS; i++) { 981 if (ti_newbuf_mini(sc, i, NULL, 0) == ENOBUFS) 982 return (ENOBUFS); 983 }; 984 985 TI_UPDATE_MINIPROD(sc, i - 1); 986 sc->ti_mini = i - 1; 987 988 return (0); 989 } 990 991 static void 992 ti_free_rx_ring_mini(struct ti_softc *sc) 993 { 994 int i; 995 996 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 997 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 998 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 999 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1000 1001 /* if (sc->mini_dmamap[i] == 0) panic() */ 1002 bus_dmamap_destroy(sc->sc_dmat, sc->mini_dmamap[i]); 1003 sc->mini_dmamap[i] = 0; 1004 } 1005 memset((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 0, 1006 sizeof(struct ti_rx_desc)); 1007 } 1008 1009 return; 1010 } 1011 1012 static void 1013 ti_free_tx_ring(struct ti_softc *sc) 1014 { 1015 int i; 1016 struct txdmamap_pool_entry *dma; 1017 1018 if (sc->ti_rdata->ti_tx_ring == NULL) 1019 return; 1020 1021 for (i = 0; i < TI_TX_RING_CNT; i++) { 1022 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1023 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1024 sc->ti_cdata.ti_tx_chain[i] = NULL; 1025 1026 /* if (sc->txdma[i] == 0) panic() */ 1027 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1028 link); 1029 sc->txdma[i] = 0; 1030 } 1031 memset((char *)&sc->ti_rdata->ti_tx_ring[i], 0, 1032 sizeof(struct ti_tx_desc)); 1033 } 1034 1035 while ((dma = SIMPLEQ_FIRST(&sc->txdma_list))) { 1036 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 1037 bus_dmamap_destroy(sc->sc_dmat, dma->dmamap); 1038 free(dma, M_DEVBUF); 1039 } 1040 1041 return; 1042 } 1043 1044 static int 1045 ti_init_tx_ring(struct ti_softc *sc) 1046 { 1047 int i, error; 1048 bus_dmamap_t dmamap; 1049 struct txdmamap_pool_entry *dma; 1050 1051 sc->ti_txcnt = 0; 1052 sc->ti_tx_saved_considx = 0; 1053 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1054 1055 SIMPLEQ_INIT(&sc->txdma_list); 1056 for (i = 0; i < TI_RSLOTS; i++) { 1057 /* I've seen mbufs with 30 fragments. */ 1058 if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_MAX_LEN_JUMBO, 1059 40, ETHER_MAX_LEN_JUMBO, 0, 1060 BUS_DMA_NOWAIT, &dmamap)) != 0) { 1061 printf("%s: can't create tx map, error = %d\n", 1062 sc->sc_dev.dv_xname, error); 1063 return (ENOMEM); 1064 } 1065 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1066 if (!dma) { 1067 printf("%s: can't alloc txdmamap_pool_entry\n", 1068 sc->sc_dev.dv_xname); 1069 bus_dmamap_destroy(sc->sc_dmat, dmamap); 1070 return (ENOMEM); 1071 } 1072 dma->dmamap = dmamap; 1073 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 1074 } 1075 1076 return (0); 1077 } 1078 1079 /* 1080 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1081 * but we have to support the old way too so that Tigon 1 cards will 1082 * work. 1083 */ 1084 static void 1085 ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr) 1086 { 1087 struct ti_cmd_desc cmd; 1088 u_int16_t *m; 1089 u_int32_t ext[2] = {0, 0}; 1090 1091 m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1092 1093 switch (sc->ti_hwrev) { 1094 case TI_HWREV_TIGON: 1095 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1096 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1097 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1098 break; 1099 case TI_HWREV_TIGON_II: 1100 ext[0] = htons(m[0]); 1101 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1102 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (void *)&ext, 2); 1103 break; 1104 default: 1105 printf("%s: unknown hwrev\n", sc->sc_dev.dv_xname); 1106 break; 1107 } 1108 1109 return; 1110 } 1111 1112 static void 1113 ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr) 1114 { 1115 struct ti_cmd_desc cmd; 1116 u_int16_t *m; 1117 u_int32_t ext[2] = {0, 0}; 1118 1119 m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1120 1121 switch (sc->ti_hwrev) { 1122 case TI_HWREV_TIGON: 1123 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1124 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1125 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1126 break; 1127 case TI_HWREV_TIGON_II: 1128 ext[0] = htons(m[0]); 1129 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1130 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (void *)&ext, 2); 1131 break; 1132 default: 1133 printf("%s: unknown hwrev\n", sc->sc_dev.dv_xname); 1134 break; 1135 } 1136 1137 return; 1138 } 1139 1140 /* 1141 * Configure the Tigon's multicast address filter. 1142 * 1143 * The actual multicast table management is a bit of a pain, thanks to 1144 * slight brain damage on the part of both Alteon and us. With our 1145 * multicast code, we are only alerted when the multicast address table 1146 * changes and at that point we only have the current list of addresses: 1147 * we only know the current state, not the previous state, so we don't 1148 * actually know what addresses were removed or added. The firmware has 1149 * state, but we can't get our grubby mits on it, and there is no 'delete 1150 * all multicast addresses' command. Hence, we have to maintain our own 1151 * state so we know what addresses have been programmed into the NIC at 1152 * any given time. 1153 */ 1154 static void 1155 ti_setmulti(struct ti_softc *sc) 1156 { 1157 struct ifnet *ifp; 1158 struct ti_cmd_desc cmd; 1159 struct ti_mc_entry *mc; 1160 u_int32_t intrs; 1161 struct ether_multi *enm; 1162 struct ether_multistep step; 1163 1164 ifp = &sc->ethercom.ec_if; 1165 1166 /* Disable interrupts. */ 1167 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1168 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1169 1170 /* First, zot all the existing filters. */ 1171 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1172 ti_del_mcast(sc, &mc->mc_addr); 1173 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1174 free(mc, M_DEVBUF); 1175 } 1176 1177 /* 1178 * Remember all multicast addresses so that we can delete them 1179 * later. Punt if there is a range of addresses or memory shortage. 1180 */ 1181 ETHER_FIRST_MULTI(step, &sc->ethercom, enm); 1182 while (enm != NULL) { 1183 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1184 ETHER_ADDR_LEN) != 0) 1185 goto allmulti; 1186 if ((mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, 1187 M_NOWAIT)) == NULL) 1188 goto allmulti; 1189 memcpy(&mc->mc_addr, enm->enm_addrlo, ETHER_ADDR_LEN); 1190 SIMPLEQ_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1191 ETHER_NEXT_MULTI(step, enm); 1192 } 1193 1194 /* Accept only programmed multicast addresses */ 1195 ifp->if_flags &= ~IFF_ALLMULTI; 1196 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1197 1198 /* Now program new ones. */ 1199 SIMPLEQ_FOREACH(mc, &sc->ti_mc_listhead, mc_entries) 1200 ti_add_mcast(sc, &mc->mc_addr); 1201 1202 /* Re-enable interrupts. */ 1203 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1204 1205 return; 1206 1207 allmulti: 1208 /* No need to keep individual multicast addresses */ 1209 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1210 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1211 free(mc, M_DEVBUF); 1212 } 1213 1214 /* Accept all multicast addresses */ 1215 ifp->if_flags |= IFF_ALLMULTI; 1216 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1217 1218 /* Re-enable interrupts. */ 1219 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1220 } 1221 1222 /* 1223 * Check to see if the BIOS has configured us for a 64 bit slot when 1224 * we aren't actually in one. If we detect this condition, we can work 1225 * around it on the Tigon 2 by setting a bit in the PCI state register, 1226 * but for the Tigon 1 we must give up and abort the interface attach. 1227 */ 1228 static int 1229 ti_64bitslot_war(struct ti_softc *sc) 1230 { 1231 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1232 CSR_WRITE_4(sc, 0x600, 0); 1233 CSR_WRITE_4(sc, 0x604, 0); 1234 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1235 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1236 if (sc->ti_hwrev == TI_HWREV_TIGON) 1237 return (EINVAL); 1238 else { 1239 TI_SETBIT(sc, TI_PCI_STATE, 1240 TI_PCISTATE_32BIT_BUS); 1241 return (0); 1242 } 1243 } 1244 } 1245 1246 return (0); 1247 } 1248 1249 /* 1250 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1251 * self-test results. 1252 */ 1253 static int 1254 ti_chipinit(struct ti_softc *sc) 1255 { 1256 u_int32_t cacheline; 1257 u_int32_t pci_writemax = 0; 1258 u_int32_t rev; 1259 1260 /* Initialize link to down state. */ 1261 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1262 1263 /* Set endianness before we access any non-PCI registers. */ 1264 #if BYTE_ORDER == BIG_ENDIAN 1265 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1266 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1267 #else 1268 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1269 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1270 #endif 1271 1272 /* Check the ROM failed bit to see if self-tests passed. */ 1273 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1274 printf("%s: board self-diagnostics failed!\n", 1275 sc->sc_dev.dv_xname); 1276 return (ENODEV); 1277 } 1278 1279 /* Halt the CPU. */ 1280 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1281 1282 /* Figure out the hardware revision. */ 1283 rev = CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK; 1284 switch (rev) { 1285 case TI_REV_TIGON_I: 1286 sc->ti_hwrev = TI_HWREV_TIGON; 1287 break; 1288 case TI_REV_TIGON_II: 1289 sc->ti_hwrev = TI_HWREV_TIGON_II; 1290 break; 1291 default: 1292 printf("%s: unsupported chip revision 0x%x\n", 1293 sc->sc_dev.dv_xname, rev); 1294 return (ENODEV); 1295 } 1296 1297 /* Do special setup for Tigon 2. */ 1298 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1299 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1300 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 1301 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1302 } 1303 1304 /* Set up the PCI state register. */ 1305 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1306 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1307 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1308 } 1309 1310 /* Clear the read/write max DMA parameters. */ 1311 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1312 TI_PCISTATE_READ_MAXDMA)); 1313 1314 /* Get cache line size. */ 1315 cacheline = PCI_CACHELINE(CSR_READ_4(sc, PCI_BHLC_REG)); 1316 1317 /* 1318 * If the system has set enabled the PCI memory write 1319 * and invalidate command in the command register, set 1320 * the write max parameter accordingly. This is necessary 1321 * to use MWI with the Tigon 2. 1322 */ 1323 if (CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1324 & PCI_COMMAND_INVALIDATE_ENABLE) { 1325 switch (cacheline) { 1326 case 1: 1327 case 4: 1328 case 8: 1329 case 16: 1330 case 32: 1331 case 64: 1332 break; 1333 default: 1334 /* Disable PCI memory write and invalidate. */ 1335 if (bootverbose) 1336 printf("%s: cache line size %d not " 1337 "supported; disabling PCI MWI\n", 1338 sc->sc_dev.dv_xname, cacheline); 1339 CSR_WRITE_4(sc, PCI_COMMAND_STATUS_REG, 1340 CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1341 & ~PCI_COMMAND_INVALIDATE_ENABLE); 1342 break; 1343 } 1344 } 1345 1346 #ifdef __brokenalpha__ 1347 /* 1348 * From the Alteon sample driver: 1349 * Must insure that we do not cross an 8K (bytes) boundary 1350 * for DMA reads. Our highest limit is 1K bytes. This is a 1351 * restriction on some ALPHA platforms with early revision 1352 * 21174 PCI chipsets, such as the AlphaPC 164lx 1353 */ 1354 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1355 #else 1356 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1357 #endif 1358 1359 /* This sets the min dma param all the way up (0xff). */ 1360 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1361 1362 /* Configure DMA variables. */ 1363 #if BYTE_ORDER == BIG_ENDIAN 1364 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1365 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1366 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1367 TI_OPMODE_DONT_FRAG_JUMBO); 1368 #else 1369 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1370 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1371 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1372 #endif 1373 1374 /* 1375 * Only allow 1 DMA channel to be active at a time. 1376 * I don't think this is a good idea, but without it 1377 * the firmware racks up lots of nicDmaReadRingFull 1378 * errors. 1379 * Incompatible with hardware assisted checksums. 1380 */ 1381 if ((sc->ethercom.ec_if.if_capenable & 1382 (IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1383 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 1384 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx)) == 0) 1385 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1386 1387 /* Recommended settings from Tigon manual. */ 1388 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1389 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1390 1391 if (ti_64bitslot_war(sc)) { 1392 printf("%s: bios thinks we're in a 64 bit slot, " 1393 "but we aren't", sc->sc_dev.dv_xname); 1394 return (EINVAL); 1395 } 1396 1397 return (0); 1398 } 1399 1400 /* 1401 * Initialize the general information block and firmware, and 1402 * start the CPU(s) running. 1403 */ 1404 static int 1405 ti_gibinit(struct ti_softc *sc) 1406 { 1407 struct ti_rcb *rcb; 1408 int i; 1409 struct ifnet *ifp; 1410 1411 ifp = &sc->ethercom.ec_if; 1412 1413 /* Disable interrupts for now. */ 1414 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1415 1416 /* Tell the chip where to find the general information block. */ 1417 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1418 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, TI_CDGIBADDR(sc)); 1419 1420 /* Load the firmware into SRAM. */ 1421 ti_loadfw(sc); 1422 1423 /* Set up the contents of the general info and ring control blocks. */ 1424 1425 /* Set up the event ring and producer pointer. */ 1426 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1427 1428 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDEVENTADDR(sc, 0); 1429 rcb->ti_flags = 0; 1430 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1431 TI_CDEVPRODADDR(sc); 1432 1433 sc->ti_ev_prodidx.ti_idx = 0; 1434 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1435 sc->ti_ev_saved_considx = 0; 1436 1437 /* Set up the command ring and producer mailbox. */ 1438 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1439 1440 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1441 rcb->ti_flags = 0; 1442 rcb->ti_max_len = 0; 1443 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1444 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1445 } 1446 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1447 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1448 sc->ti_cmd_saved_prodidx = 0; 1449 1450 /* 1451 * Assign the address of the stats refresh buffer. 1452 * We re-use the current stats buffer for this to 1453 * conserve memory. 1454 */ 1455 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1456 TI_CDSTATSADDR(sc); 1457 1458 /* Set up the standard receive ring. */ 1459 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1460 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXSTDADDR(sc, 0); 1461 rcb->ti_max_len = ETHER_MAX_LEN; 1462 rcb->ti_flags = 0; 1463 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1464 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1465 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 1466 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1467 if (VLAN_ATTACHED(&sc->ethercom)) 1468 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1469 1470 /* Set up the jumbo receive ring. */ 1471 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1472 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXJUMBOADDR(sc, 0); 1473 rcb->ti_max_len = ETHER_MAX_LEN_JUMBO; 1474 rcb->ti_flags = 0; 1475 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1476 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1477 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 1478 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1479 if (VLAN_ATTACHED(&sc->ethercom)) 1480 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1481 1482 /* 1483 * Set up the mini ring. Only activated on the 1484 * Tigon 2 but the slot in the config block is 1485 * still there on the Tigon 1. 1486 */ 1487 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1488 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXMINIADDR(sc, 0); 1489 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1490 if (sc->ti_hwrev == TI_HWREV_TIGON) 1491 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1492 else 1493 rcb->ti_flags = 0; 1494 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1495 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1496 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 1497 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1498 if (VLAN_ATTACHED(&sc->ethercom)) 1499 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1500 1501 /* 1502 * Set up the receive return ring. 1503 */ 1504 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1505 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXRTNADDR(sc, 0); 1506 rcb->ti_flags = 0; 1507 rcb->ti_max_len = TI_RETURN_RING_CNT; 1508 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1509 TI_CDRTNPRODADDR(sc); 1510 1511 /* 1512 * Set up the tx ring. Note: for the Tigon 2, we have the option 1513 * of putting the transmit ring in the host's address space and 1514 * letting the chip DMA it instead of leaving the ring in the NIC's 1515 * memory and accessing it through the shared memory region. We 1516 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1517 * so we have to revert to the shared memory scheme if we detect 1518 * a Tigon 1 chip. 1519 */ 1520 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1521 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1522 sc->ti_tx_ring_nic = 1523 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1524 } 1525 memset((char *)sc->ti_rdata->ti_tx_ring, 0, 1526 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1527 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1528 if (sc->ti_hwrev == TI_HWREV_TIGON) 1529 rcb->ti_flags = 0; 1530 else 1531 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1532 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) 1533 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1534 /* 1535 * When we get the packet, there is a pseudo-header seed already 1536 * in the th_sum or uh_sum field. Make sure the firmware doesn't 1537 * compute the pseudo-header checksum again! 1538 */ 1539 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 1540 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM| 1541 TI_RCB_FLAG_NO_PHDR_CKSUM; 1542 if (VLAN_ATTACHED(&sc->ethercom)) 1543 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1544 rcb->ti_max_len = TI_TX_RING_CNT; 1545 if (sc->ti_hwrev == TI_HWREV_TIGON) 1546 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1547 else 1548 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDTXADDR(sc, 0); 1549 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1550 TI_CDTXCONSADDR(sc); 1551 1552 /* 1553 * We're done frobbing the General Information Block. Sync 1554 * it. Note we take care of the first stats sync here, as 1555 * well. 1556 */ 1557 TI_CDGIBSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1558 1559 /* Set up tuneables */ 1560 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN) || 1561 (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 1562 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1563 (sc->ti_rx_coal_ticks / 10)); 1564 else 1565 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1566 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1567 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1568 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1569 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1570 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1571 1572 /* Turn interrupts on. */ 1573 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1574 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1575 1576 /* Start CPU. */ 1577 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1578 1579 return (0); 1580 } 1581 1582 /* 1583 * look for id in the device list, returning the first match 1584 */ 1585 static const struct ti_type * 1586 ti_type_match(struct pci_attach_args *pa) 1587 { 1588 const struct ti_type *t; 1589 1590 t = ti_devs; 1591 while (t->ti_name != NULL) { 1592 if ((PCI_VENDOR(pa->pa_id) == t->ti_vid) && 1593 (PCI_PRODUCT(pa->pa_id) == t->ti_did)) { 1594 return (t); 1595 } 1596 t++; 1597 } 1598 1599 return (NULL); 1600 } 1601 1602 /* 1603 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1604 * against our list and return its name if we find a match. 1605 */ 1606 static int 1607 ti_probe(struct device *parent, struct cfdata *match, void *aux) 1608 { 1609 struct pci_attach_args *pa = aux; 1610 const struct ti_type *t; 1611 1612 t = ti_type_match(pa); 1613 1614 return ((t == NULL) ? 0 : 1); 1615 } 1616 1617 static void 1618 ti_attach(struct device *parent, struct device *self, void *aux) 1619 { 1620 u_int32_t command; 1621 struct ifnet *ifp; 1622 struct ti_softc *sc; 1623 u_int8_t eaddr[ETHER_ADDR_LEN]; 1624 struct pci_attach_args *pa = aux; 1625 pci_chipset_tag_t pc = pa->pa_pc; 1626 pci_intr_handle_t ih; 1627 const char *intrstr = NULL; 1628 bus_dma_segment_t dmaseg; 1629 int error, dmanseg, nolinear; 1630 const struct ti_type *t; 1631 1632 t = ti_type_match(pa); 1633 if (t == NULL) { 1634 printf("ti_attach: were did the card go ?\n"); 1635 return; 1636 } 1637 1638 printf(": %s (rev. 0x%02x)\n", t->ti_name, PCI_REVISION(pa->pa_class)); 1639 1640 sc = (struct ti_softc *)self; 1641 1642 /* 1643 * Map control/status registers. 1644 */ 1645 nolinear = 0; 1646 if (pci_mapreg_map(pa, 0x10, 1647 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1648 BUS_SPACE_MAP_LINEAR , &sc->ti_btag, &sc->ti_bhandle, 1649 NULL, NULL)) { 1650 nolinear = 1; 1651 if (pci_mapreg_map(pa, 0x10, 1652 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1653 0 , &sc->ti_btag, &sc->ti_bhandle, NULL, NULL)) { 1654 printf(": can't map memory space\n"); 1655 return; 1656 } 1657 } 1658 if (nolinear == 0) 1659 sc->ti_vhandle = bus_space_vaddr(sc->ti_btag, sc->ti_bhandle); 1660 else 1661 sc->ti_vhandle = NULL; 1662 1663 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1664 command |= PCI_COMMAND_MASTER_ENABLE; 1665 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1666 1667 /* Allocate interrupt */ 1668 if (pci_intr_map(pa, &ih)) { 1669 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 1670 return; 1671 } 1672 intrstr = pci_intr_string(pc, ih); 1673 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ti_intr, sc); 1674 if (sc->sc_ih == NULL) { 1675 printf("%s: couldn't establish interrupt", 1676 sc->sc_dev.dv_xname); 1677 if (intrstr != NULL) 1678 printf(" at %s", intrstr); 1679 printf("\n"); 1680 return; 1681 } 1682 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 1683 /* 1684 * Add shutdown hook so that DMA is disabled prior to reboot. Not 1685 * doing do could allow DMA to corrupt kernel memory during the 1686 * reboot before the driver initializes. 1687 */ 1688 (void) shutdownhook_establish(ti_shutdown, sc); 1689 1690 if (ti_chipinit(sc)) { 1691 printf("%s: chip initialization failed\n", self->dv_xname); 1692 goto fail2; 1693 } 1694 1695 /* 1696 * Deal with some chip diffrences. 1697 */ 1698 switch (sc->ti_hwrev) { 1699 case TI_HWREV_TIGON: 1700 sc->sc_tx_encap = ti_encap_tigon1; 1701 sc->sc_tx_eof = ti_txeof_tigon1; 1702 if (nolinear == 1) 1703 printf("%s: memory space not mapped linear\n", 1704 self->dv_xname); 1705 break; 1706 1707 case TI_HWREV_TIGON_II: 1708 sc->sc_tx_encap = ti_encap_tigon2; 1709 sc->sc_tx_eof = ti_txeof_tigon2; 1710 break; 1711 1712 default: 1713 printf("%s: Unknown chip version: %d\n", self->dv_xname, 1714 sc->ti_hwrev); 1715 goto fail2; 1716 } 1717 1718 /* Zero out the NIC's on-board SRAM. */ 1719 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1720 1721 /* Init again -- zeroing memory may have clobbered some registers. */ 1722 if (ti_chipinit(sc)) { 1723 printf("%s: chip initialization failed\n", self->dv_xname); 1724 goto fail2; 1725 } 1726 1727 /* 1728 * Get station address from the EEPROM. Note: the manual states 1729 * that the MAC address is at offset 0x8c, however the data is 1730 * stored as two longwords (since that's how it's loaded into 1731 * the NIC). This means the MAC address is actually preceded 1732 * by two zero bytes. We need to skip over those. 1733 */ 1734 if (ti_read_eeprom(sc, (void *)&eaddr, 1735 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1736 printf("%s: failed to read station address\n", self->dv_xname); 1737 goto fail2; 1738 } 1739 1740 /* 1741 * A Tigon chip was detected. Inform the world. 1742 */ 1743 printf("%s: Ethernet address: %s\n", self->dv_xname, 1744 ether_sprintf(eaddr)); 1745 1746 sc->sc_dmat = pa->pa_dmat; 1747 1748 /* Allocate the general information block and ring buffers. */ 1749 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1750 sizeof(struct ti_ring_data), PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 1751 BUS_DMA_NOWAIT)) != 0) { 1752 printf("%s: can't allocate ring buffer, error = %d\n", 1753 sc->sc_dev.dv_xname, error); 1754 goto fail2; 1755 } 1756 1757 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 1758 sizeof(struct ti_ring_data), (void **)&sc->ti_rdata, 1759 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1760 printf("%s: can't map ring buffer, error = %d\n", 1761 sc->sc_dev.dv_xname, error); 1762 goto fail2; 1763 } 1764 1765 if ((error = bus_dmamap_create(sc->sc_dmat, 1766 sizeof(struct ti_ring_data), 1, 1767 sizeof(struct ti_ring_data), 0, BUS_DMA_NOWAIT, 1768 &sc->info_dmamap)) != 0) { 1769 printf("%s: can't create ring buffer DMA map, error = %d\n", 1770 sc->sc_dev.dv_xname, error); 1771 goto fail2; 1772 } 1773 1774 if ((error = bus_dmamap_load(sc->sc_dmat, sc->info_dmamap, 1775 sc->ti_rdata, sizeof(struct ti_ring_data), NULL, 1776 BUS_DMA_NOWAIT)) != 0) { 1777 printf("%s: can't load ring buffer DMA map, error = %d\n", 1778 sc->sc_dev.dv_xname, error); 1779 goto fail2; 1780 } 1781 1782 sc->info_dmaaddr = sc->info_dmamap->dm_segs[0].ds_addr; 1783 1784 memset(sc->ti_rdata, 0, sizeof(struct ti_ring_data)); 1785 1786 /* Try to allocate memory for jumbo buffers. */ 1787 if (ti_alloc_jumbo_mem(sc)) { 1788 printf("%s: jumbo buffer allocation failed\n", self->dv_xname); 1789 goto fail2; 1790 } 1791 1792 SIMPLEQ_INIT(&sc->ti_mc_listhead); 1793 1794 /* 1795 * We really need a better way to tell a 1000baseT card 1796 * from a 1000baseSX one, since in theory there could be 1797 * OEMed 1000baseT cards from lame vendors who aren't 1798 * clever enough to change the PCI ID. For the moment 1799 * though, the AceNIC is the only copper card available. 1800 */ 1801 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALTEON && 1802 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALTEON_ACENIC_COPPER) || 1803 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NETGEAR && 1804 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NETGEAR_GA620T)) 1805 sc->ti_copper = 1; 1806 else 1807 sc->ti_copper = 0; 1808 1809 /* Set default tuneable values. */ 1810 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1811 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1812 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1813 sc->ti_rx_max_coal_bds = 64; 1814 sc->ti_tx_max_coal_bds = 128; 1815 sc->ti_tx_buf_ratio = 21; 1816 1817 /* Set up ifnet structure */ 1818 ifp = &sc->ethercom.ec_if; 1819 ifp->if_softc = sc; 1820 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1821 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1822 ifp->if_ioctl = ti_ioctl; 1823 ifp->if_start = ti_start; 1824 ifp->if_watchdog = ti_watchdog; 1825 IFQ_SET_READY(&ifp->if_snd); 1826 1827 #if 0 1828 /* 1829 * XXX This is not really correct -- we don't necessarily 1830 * XXX want to queue up as many as we can transmit at the 1831 * XXX upper layer like that. Someone with a board should 1832 * XXX check to see how this affects performance. 1833 */ 1834 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1835 #endif 1836 1837 /* 1838 * We can support 802.1Q VLAN-sized frames. 1839 */ 1840 sc->ethercom.ec_capabilities |= 1841 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 1842 1843 /* 1844 * We can do IPv4, TCPv4, and UDPv4 checksums in hardware. 1845 */ 1846 ifp->if_capabilities |= 1847 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1848 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1849 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1850 1851 /* Set up ifmedia support. */ 1852 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1853 if (sc->ti_copper) { 1854 /* 1855 * Copper cards allow manual 10/100 mode selection, 1856 * but not manual 1000baseT mode selection. Why? 1857 * Because currently there's no way to specify the 1858 * master/slave setting through the firmware interface, 1859 * so Alteon decided to just bag it and handle it 1860 * via autonegotiation. 1861 */ 1862 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1863 ifmedia_add(&sc->ifmedia, 1864 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1865 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 1866 ifmedia_add(&sc->ifmedia, 1867 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 1868 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 1869 ifmedia_add(&sc->ifmedia, 1870 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 1871 } else { 1872 /* Fiber cards don't support 10/100 modes. */ 1873 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1874 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1875 } 1876 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1877 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1878 1879 /* 1880 * Call MI attach routines. 1881 */ 1882 if_attach(ifp); 1883 ether_ifattach(ifp, eaddr); 1884 1885 return; 1886 fail2: 1887 pci_intr_disestablish(pc, sc->sc_ih); 1888 return; 1889 } 1890 1891 /* 1892 * Frame reception handling. This is called if there's a frame 1893 * on the receive return list. 1894 * 1895 * Note: we have to be able to handle three possibilities here: 1896 * 1) the frame is from the mini receive ring (can only happen) 1897 * on Tigon 2 boards) 1898 * 2) the frame is from the jumbo receive ring 1899 * 3) the frame is from the standard receive ring 1900 */ 1901 1902 static void 1903 ti_rxeof(struct ti_softc *sc) 1904 { 1905 struct ifnet *ifp; 1906 struct ti_cmd_desc cmd; 1907 1908 ifp = &sc->ethercom.ec_if; 1909 1910 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1911 struct ti_rx_desc *cur_rx; 1912 u_int32_t rxidx; 1913 struct mbuf *m = NULL; 1914 struct ether_header *eh; 1915 bus_dmamap_t dmamap; 1916 1917 cur_rx = 1918 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1919 rxidx = cur_rx->ti_idx; 1920 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1921 1922 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1923 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1924 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1925 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1926 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1927 ifp->if_ierrors++; 1928 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1929 continue; 1930 } 1931 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) 1932 == ENOBUFS) { 1933 ifp->if_ierrors++; 1934 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1935 continue; 1936 } 1937 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1938 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1939 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1940 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1941 dmamap = sc->mini_dmamap[rxidx]; 1942 sc->mini_dmamap[rxidx] = 0; 1943 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1944 ifp->if_ierrors++; 1945 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1946 continue; 1947 } 1948 if (ti_newbuf_mini(sc, sc->ti_mini, NULL, dmamap) 1949 == ENOBUFS) { 1950 ifp->if_ierrors++; 1951 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1952 continue; 1953 } 1954 } else { 1955 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1956 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1957 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1958 dmamap = sc->std_dmamap[rxidx]; 1959 sc->std_dmamap[rxidx] = 0; 1960 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1961 ifp->if_ierrors++; 1962 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 1963 continue; 1964 } 1965 if (ti_newbuf_std(sc, sc->ti_std, NULL, dmamap) 1966 == ENOBUFS) { 1967 ifp->if_ierrors++; 1968 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 1969 continue; 1970 } 1971 } 1972 1973 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 1974 ifp->if_ipackets++; 1975 m->m_pkthdr.rcvif = ifp; 1976 1977 #if NBPFILTER > 0 1978 /* 1979 * Handle BPF listeners. Let the BPF user see the packet, but 1980 * don't pass it up to the ether_input() layer unless it's 1981 * a broadcast packet, multicast packet, matches our ethernet 1982 * address or the interface is in promiscuous mode. 1983 */ 1984 if (ifp->if_bpf) 1985 bpf_mtap(ifp->if_bpf, m); 1986 #endif 1987 1988 eh = mtod(m, struct ether_header *); 1989 switch (ntohs(eh->ether_type)) { 1990 #ifdef INET 1991 case ETHERTYPE_IP: 1992 { 1993 struct ip *ip = (struct ip *) (eh + 1); 1994 1995 /* 1996 * Note the Tigon firmware does not invert 1997 * the checksum for us, hence the XOR. 1998 */ 1999 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2000 if ((cur_rx->ti_ip_cksum ^ 0xffff) != 0) 2001 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2002 /* 2003 * ntohs() the constant so the compiler can 2004 * optimize... 2005 * 2006 * XXX Figure out a sane way to deal with 2007 * fragmented packets. 2008 */ 2009 if ((ip->ip_off & htons(IP_MF|IP_OFFMASK)) == 0) { 2010 switch (ip->ip_p) { 2011 case IPPROTO_TCP: 2012 m->m_pkthdr.csum_data = 2013 cur_rx->ti_tcp_udp_cksum; 2014 m->m_pkthdr.csum_flags |= 2015 M_CSUM_TCPv4|M_CSUM_DATA; 2016 break; 2017 case IPPROTO_UDP: 2018 m->m_pkthdr.csum_data = 2019 cur_rx->ti_tcp_udp_cksum; 2020 m->m_pkthdr.csum_flags |= 2021 M_CSUM_UDPv4|M_CSUM_DATA; 2022 break; 2023 default: 2024 /* Nothing */; 2025 } 2026 } 2027 break; 2028 } 2029 #endif 2030 default: 2031 /* Nothing. */ 2032 break; 2033 } 2034 2035 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 2036 VLAN_INPUT_TAG(ifp, m, 2037 /* ti_vlan_tag also has the priority, trim it */ 2038 cur_rx->ti_vlan_tag & 4095, 2039 continue); 2040 } 2041 2042 (*ifp->if_input)(ifp, m); 2043 } 2044 2045 /* Only necessary on the Tigon 1. */ 2046 if (sc->ti_hwrev == TI_HWREV_TIGON) 2047 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2048 sc->ti_rx_saved_considx); 2049 2050 TI_UPDATE_STDPROD(sc, sc->ti_std); 2051 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2052 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2053 } 2054 2055 static void 2056 ti_txeof_tigon1(struct ti_softc *sc) 2057 { 2058 struct ti_tx_desc *cur_tx = NULL; 2059 struct ifnet *ifp; 2060 struct txdmamap_pool_entry *dma; 2061 2062 ifp = &sc->ethercom.ec_if; 2063 2064 /* 2065 * Go through our tx ring and free mbufs for those 2066 * frames that have been sent. 2067 */ 2068 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2069 u_int32_t idx = 0; 2070 2071 idx = sc->ti_tx_saved_considx; 2072 if (idx > 383) 2073 CSR_WRITE_4(sc, TI_WINBASE, 2074 TI_TX_RING_BASE + 6144); 2075 else if (idx > 255) 2076 CSR_WRITE_4(sc, TI_WINBASE, 2077 TI_TX_RING_BASE + 4096); 2078 else if (idx > 127) 2079 CSR_WRITE_4(sc, TI_WINBASE, 2080 TI_TX_RING_BASE + 2048); 2081 else 2082 CSR_WRITE_4(sc, TI_WINBASE, 2083 TI_TX_RING_BASE); 2084 cur_tx = &sc->ti_tx_ring_nic[idx % 128]; 2085 if (cur_tx->ti_flags & TI_BDFLAG_END) 2086 ifp->if_opackets++; 2087 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2088 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2089 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2090 2091 dma = sc->txdma[idx]; 2092 KDASSERT(dma != NULL); 2093 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2094 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2095 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2096 2097 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2098 sc->txdma[idx] = NULL; 2099 } 2100 sc->ti_txcnt--; 2101 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2102 ifp->if_timer = 0; 2103 } 2104 2105 if (cur_tx != NULL) 2106 ifp->if_flags &= ~IFF_OACTIVE; 2107 } 2108 2109 static void 2110 ti_txeof_tigon2(struct ti_softc *sc) 2111 { 2112 struct ti_tx_desc *cur_tx = NULL; 2113 struct ifnet *ifp; 2114 struct txdmamap_pool_entry *dma; 2115 int firstidx, cnt; 2116 2117 ifp = &sc->ethercom.ec_if; 2118 2119 /* 2120 * Go through our tx ring and free mbufs for those 2121 * frames that have been sent. 2122 */ 2123 firstidx = sc->ti_tx_saved_considx; 2124 cnt = 0; 2125 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2126 u_int32_t idx = 0; 2127 2128 idx = sc->ti_tx_saved_considx; 2129 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2130 if (cur_tx->ti_flags & TI_BDFLAG_END) 2131 ifp->if_opackets++; 2132 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2133 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2134 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2135 2136 dma = sc->txdma[idx]; 2137 KDASSERT(dma != NULL); 2138 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2139 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2140 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2141 2142 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2143 sc->txdma[idx] = NULL; 2144 } 2145 cnt++; 2146 sc->ti_txcnt--; 2147 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2148 ifp->if_timer = 0; 2149 } 2150 2151 if (cnt != 0) 2152 TI_CDTXSYNC(sc, firstidx, cnt, BUS_DMASYNC_POSTWRITE); 2153 2154 if (cur_tx != NULL) 2155 ifp->if_flags &= ~IFF_OACTIVE; 2156 } 2157 2158 static int 2159 ti_intr(void *xsc) 2160 { 2161 struct ti_softc *sc; 2162 struct ifnet *ifp; 2163 2164 sc = xsc; 2165 ifp = &sc->ethercom.ec_if; 2166 2167 #ifdef notdef 2168 /* Avoid this for now -- checking this register is expensive. */ 2169 /* Make sure this is really our interrupt. */ 2170 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 2171 return (0); 2172 #endif 2173 2174 /* Ack interrupt and stop others from occuring. */ 2175 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2176 2177 if (ifp->if_flags & IFF_RUNNING) { 2178 /* Check RX return ring producer/consumer */ 2179 ti_rxeof(sc); 2180 2181 /* Check TX ring producer/consumer */ 2182 (*sc->sc_tx_eof)(sc); 2183 } 2184 2185 ti_handle_events(sc); 2186 2187 /* Re-enable interrupts. */ 2188 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2189 2190 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2191 IFQ_IS_EMPTY(&ifp->if_snd) == 0) 2192 ti_start(ifp); 2193 2194 return (1); 2195 } 2196 2197 static void 2198 ti_stats_update(struct ti_softc *sc) 2199 { 2200 struct ifnet *ifp; 2201 2202 ifp = &sc->ethercom.ec_if; 2203 2204 TI_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 2205 2206 ifp->if_collisions += 2207 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2208 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2209 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2210 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2211 ifp->if_collisions; 2212 2213 TI_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 2214 } 2215 2216 /* 2217 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2218 * pointers to descriptors. 2219 */ 2220 static int 2221 ti_encap_tigon1(struct ti_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 2222 { 2223 struct ti_tx_desc *f = NULL; 2224 u_int32_t frag, cur, cnt = 0; 2225 struct txdmamap_pool_entry *dma; 2226 bus_dmamap_t dmamap; 2227 int error, i; 2228 struct m_tag *mtag; 2229 u_int16_t csum_flags = 0; 2230 2231 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2232 if (dma == NULL) { 2233 return ENOMEM; 2234 } 2235 dmamap = dma->dmamap; 2236 2237 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2238 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2239 if (error) { 2240 struct mbuf *m; 2241 int j = 0; 2242 for (m = m_head; m; m = m->m_next) 2243 j++; 2244 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2245 "error %d\n", m_head->m_pkthdr.len, j, error); 2246 return (ENOMEM); 2247 } 2248 2249 cur = frag = *txidx; 2250 2251 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2252 /* IP header checksum field must be 0! */ 2253 csum_flags |= TI_BDFLAG_IP_CKSUM; 2254 } 2255 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2256 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2257 2258 /* XXX fragmented packet checksum capability? */ 2259 2260 /* 2261 * Start packing the mbufs in this chain into 2262 * the fragment pointers. Stop when we run out 2263 * of fragments or hit the end of the mbuf chain. 2264 */ 2265 for (i = 0; i < dmamap->dm_nsegs; i++) { 2266 if (frag > 383) 2267 CSR_WRITE_4(sc, TI_WINBASE, 2268 TI_TX_RING_BASE + 6144); 2269 else if (frag > 255) 2270 CSR_WRITE_4(sc, TI_WINBASE, 2271 TI_TX_RING_BASE + 4096); 2272 else if (frag > 127) 2273 CSR_WRITE_4(sc, TI_WINBASE, 2274 TI_TX_RING_BASE + 2048); 2275 else 2276 CSR_WRITE_4(sc, TI_WINBASE, 2277 TI_TX_RING_BASE); 2278 f = &sc->ti_tx_ring_nic[frag % 128]; 2279 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2280 break; 2281 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2282 f->ti_len = dmamap->dm_segs[i].ds_len; 2283 f->ti_flags = csum_flags; 2284 if ((mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m_head))) { 2285 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2286 f->ti_vlan_tag = VLAN_TAG_VALUE(mtag); 2287 } else { 2288 f->ti_vlan_tag = 0; 2289 } 2290 /* 2291 * Sanity check: avoid coming within 16 descriptors 2292 * of the end of the ring. 2293 */ 2294 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2295 return (ENOBUFS); 2296 cur = frag; 2297 TI_INC(frag, TI_TX_RING_CNT); 2298 cnt++; 2299 } 2300 2301 if (i < dmamap->dm_nsegs) 2302 return (ENOBUFS); 2303 2304 if (frag == sc->ti_tx_saved_considx) 2305 return (ENOBUFS); 2306 2307 sc->ti_tx_ring_nic[cur % 128].ti_flags |= 2308 TI_BDFLAG_END; 2309 2310 /* Sync the packet's DMA map. */ 2311 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2312 BUS_DMASYNC_PREWRITE); 2313 2314 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2315 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 2316 sc->txdma[cur] = dma; 2317 sc->ti_txcnt += cnt; 2318 2319 *txidx = frag; 2320 2321 return (0); 2322 } 2323 2324 static int 2325 ti_encap_tigon2(struct ti_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 2326 { 2327 struct ti_tx_desc *f = NULL; 2328 u_int32_t frag, firstfrag, cur, cnt = 0; 2329 struct txdmamap_pool_entry *dma; 2330 bus_dmamap_t dmamap; 2331 int error, i; 2332 struct m_tag *mtag; 2333 u_int16_t csum_flags = 0; 2334 2335 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2336 if (dma == NULL) { 2337 return ENOMEM; 2338 } 2339 dmamap = dma->dmamap; 2340 2341 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2342 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2343 if (error) { 2344 struct mbuf *m; 2345 int j = 0; 2346 for (m = m_head; m; m = m->m_next) 2347 j++; 2348 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2349 "error %d\n", m_head->m_pkthdr.len, j, error); 2350 return (ENOMEM); 2351 } 2352 2353 cur = firstfrag = frag = *txidx; 2354 2355 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2356 /* IP header checksum field must be 0! */ 2357 csum_flags |= TI_BDFLAG_IP_CKSUM; 2358 } 2359 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2360 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2361 2362 /* XXX fragmented packet checksum capability? */ 2363 2364 /* 2365 * Start packing the mbufs in this chain into 2366 * the fragment pointers. Stop when we run out 2367 * of fragments or hit the end of the mbuf chain. 2368 */ 2369 for (i = 0; i < dmamap->dm_nsegs; i++) { 2370 f = &sc->ti_rdata->ti_tx_ring[frag]; 2371 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2372 break; 2373 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2374 f->ti_len = dmamap->dm_segs[i].ds_len; 2375 f->ti_flags = csum_flags; 2376 if ((mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m_head))) { 2377 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2378 f->ti_vlan_tag = VLAN_TAG_VALUE(mtag); 2379 } else { 2380 f->ti_vlan_tag = 0; 2381 } 2382 /* 2383 * Sanity check: avoid coming within 16 descriptors 2384 * of the end of the ring. 2385 */ 2386 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2387 return (ENOBUFS); 2388 cur = frag; 2389 TI_INC(frag, TI_TX_RING_CNT); 2390 cnt++; 2391 } 2392 2393 if (i < dmamap->dm_nsegs) 2394 return (ENOBUFS); 2395 2396 if (frag == sc->ti_tx_saved_considx) 2397 return (ENOBUFS); 2398 2399 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2400 2401 /* Sync the packet's DMA map. */ 2402 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2403 BUS_DMASYNC_PREWRITE); 2404 2405 /* Sync the descriptors we are using. */ 2406 TI_CDTXSYNC(sc, firstfrag, cnt, BUS_DMASYNC_PREWRITE); 2407 2408 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2409 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 2410 sc->txdma[cur] = dma; 2411 sc->ti_txcnt += cnt; 2412 2413 *txidx = frag; 2414 2415 return (0); 2416 } 2417 2418 /* 2419 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2420 * to the mbuf data regions directly in the transmit descriptors. 2421 */ 2422 static void 2423 ti_start(struct ifnet *ifp) 2424 { 2425 struct ti_softc *sc; 2426 struct mbuf *m_head = NULL; 2427 u_int32_t prodidx = 0; 2428 2429 sc = ifp->if_softc; 2430 2431 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2432 2433 while (sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2434 IFQ_POLL(&ifp->if_snd, m_head); 2435 if (m_head == NULL) 2436 break; 2437 2438 /* 2439 * Pack the data into the transmit ring. If we 2440 * don't have room, set the OACTIVE flag and wait 2441 * for the NIC to drain the ring. 2442 */ 2443 if ((*sc->sc_tx_encap)(sc, m_head, &prodidx)) { 2444 ifp->if_flags |= IFF_OACTIVE; 2445 break; 2446 } 2447 2448 IFQ_DEQUEUE(&ifp->if_snd, m_head); 2449 2450 /* 2451 * If there's a BPF listener, bounce a copy of this frame 2452 * to him. 2453 */ 2454 #if NBPFILTER > 0 2455 if (ifp->if_bpf) 2456 bpf_mtap(ifp->if_bpf, m_head); 2457 #endif 2458 } 2459 2460 /* Transmit */ 2461 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2462 2463 /* 2464 * Set a timeout in case the chip goes out to lunch. 2465 */ 2466 ifp->if_timer = 5; 2467 } 2468 2469 static void 2470 ti_init(void *xsc) 2471 { 2472 struct ti_softc *sc = xsc; 2473 int s; 2474 2475 s = splnet(); 2476 2477 /* Cancel pending I/O and flush buffers. */ 2478 ti_stop(sc); 2479 2480 /* Init the gen info block, ring control blocks and firmware. */ 2481 if (ti_gibinit(sc)) { 2482 printf("%s: initialization failure\n", sc->sc_dev.dv_xname); 2483 splx(s); 2484 return; 2485 } 2486 2487 splx(s); 2488 } 2489 2490 static void 2491 ti_init2(struct ti_softc *sc) 2492 { 2493 struct ti_cmd_desc cmd; 2494 struct ifnet *ifp; 2495 const u_int8_t *m; 2496 struct ifmedia *ifm; 2497 int tmp; 2498 2499 ifp = &sc->ethercom.ec_if; 2500 2501 /* Specify MTU and interface index. */ 2502 CSR_WRITE_4(sc, TI_GCR_IFINDEX, device_unit(&sc->sc_dev)); /* ??? */ 2503 2504 tmp = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 2505 if (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2506 tmp += ETHER_VLAN_ENCAP_LEN; 2507 CSR_WRITE_4(sc, TI_GCR_IFMTU, tmp); 2508 2509 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2510 2511 /* Load our MAC address. */ 2512 m = (const u_int8_t *)CLLADDR(ifp->if_sadl); 2513 CSR_WRITE_4(sc, TI_GCR_PAR0, (m[0] << 8) | m[1]); 2514 CSR_WRITE_4(sc, TI_GCR_PAR1, (m[2] << 24) | (m[3] << 16) 2515 | (m[4] << 8) | m[5]); 2516 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2517 2518 /* Enable or disable promiscuous mode as needed. */ 2519 if (ifp->if_flags & IFF_PROMISC) { 2520 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2521 } else { 2522 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2523 } 2524 2525 /* Program multicast filter. */ 2526 ti_setmulti(sc); 2527 2528 /* 2529 * If this is a Tigon 1, we should tell the 2530 * firmware to use software packet filtering. 2531 */ 2532 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2533 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2534 } 2535 2536 /* Init RX ring. */ 2537 ti_init_rx_ring_std(sc); 2538 2539 /* Init jumbo RX ring. */ 2540 if (ifp->if_mtu > (MCLBYTES - ETHER_HDR_LEN - ETHER_CRC_LEN)) 2541 ti_init_rx_ring_jumbo(sc); 2542 2543 /* 2544 * If this is a Tigon 2, we can also configure the 2545 * mini ring. 2546 */ 2547 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2548 ti_init_rx_ring_mini(sc); 2549 2550 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2551 sc->ti_rx_saved_considx = 0; 2552 2553 /* Init TX ring. */ 2554 ti_init_tx_ring(sc); 2555 2556 /* Tell firmware we're alive. */ 2557 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2558 2559 /* Enable host interrupts. */ 2560 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2561 2562 ifp->if_flags |= IFF_RUNNING; 2563 ifp->if_flags &= ~IFF_OACTIVE; 2564 2565 /* 2566 * Make sure to set media properly. We have to do this 2567 * here since we have to issue commands in order to set 2568 * the link negotiation and we can't issue commands until 2569 * the firmware is running. 2570 */ 2571 ifm = &sc->ifmedia; 2572 tmp = ifm->ifm_media; 2573 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2574 ti_ifmedia_upd(ifp); 2575 ifm->ifm_media = tmp; 2576 } 2577 2578 /* 2579 * Set media options. 2580 */ 2581 static int 2582 ti_ifmedia_upd(struct ifnet *ifp) 2583 { 2584 struct ti_softc *sc; 2585 struct ifmedia *ifm; 2586 struct ti_cmd_desc cmd; 2587 2588 sc = ifp->if_softc; 2589 ifm = &sc->ifmedia; 2590 2591 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2592 return (EINVAL); 2593 2594 switch (IFM_SUBTYPE(ifm->ifm_media)) { 2595 case IFM_AUTO: 2596 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2597 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 2598 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2599 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2600 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 2601 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2602 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2603 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2604 break; 2605 case IFM_1000_SX: 2606 case IFM_1000_T: 2607 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2608 CSR_WRITE_4(sc, TI_GCR_GLINK, 2609 TI_GLNK_PREF|TI_GLNK_1000MB|TI_GLNK_FULL_DUPLEX| 2610 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2611 } else { 2612 CSR_WRITE_4(sc, TI_GCR_GLINK, 2613 TI_GLNK_PREF|TI_GLNK_1000MB| 2614 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2615 } 2616 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2617 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2618 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2619 break; 2620 case IFM_100_FX: 2621 case IFM_10_FL: 2622 case IFM_100_TX: 2623 case IFM_10_T: 2624 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2625 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 2626 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2627 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 2628 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2629 } else { 2630 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2631 } 2632 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2633 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2634 } else { 2635 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2636 } 2637 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2638 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2639 break; 2640 } 2641 2642 sc->ethercom.ec_if.if_baudrate = 2643 ifmedia_baudrate(ifm->ifm_media); 2644 2645 return (0); 2646 } 2647 2648 /* 2649 * Report current media status. 2650 */ 2651 static void 2652 ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2653 { 2654 struct ti_softc *sc; 2655 u_int32_t media = 0; 2656 2657 sc = ifp->if_softc; 2658 2659 ifmr->ifm_status = IFM_AVALID; 2660 ifmr->ifm_active = IFM_ETHER; 2661 2662 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2663 return; 2664 2665 ifmr->ifm_status |= IFM_ACTIVE; 2666 2667 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2668 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2669 if (sc->ti_copper) 2670 ifmr->ifm_active |= IFM_1000_T; 2671 else 2672 ifmr->ifm_active |= IFM_1000_SX; 2673 if (media & TI_GLNK_FULL_DUPLEX) 2674 ifmr->ifm_active |= IFM_FDX; 2675 else 2676 ifmr->ifm_active |= IFM_HDX; 2677 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2678 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2679 if (sc->ti_copper) { 2680 if (media & TI_LNK_100MB) 2681 ifmr->ifm_active |= IFM_100_TX; 2682 if (media & TI_LNK_10MB) 2683 ifmr->ifm_active |= IFM_10_T; 2684 } else { 2685 if (media & TI_LNK_100MB) 2686 ifmr->ifm_active |= IFM_100_FX; 2687 if (media & TI_LNK_10MB) 2688 ifmr->ifm_active |= IFM_10_FL; 2689 } 2690 if (media & TI_LNK_FULL_DUPLEX) 2691 ifmr->ifm_active |= IFM_FDX; 2692 if (media & TI_LNK_HALF_DUPLEX) 2693 ifmr->ifm_active |= IFM_HDX; 2694 } 2695 2696 sc->ethercom.ec_if.if_baudrate = 2697 ifmedia_baudrate(sc->ifmedia.ifm_media); 2698 } 2699 2700 static int 2701 ti_ether_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2702 { 2703 struct ifaddr *ifa = (struct ifaddr *) data; 2704 struct ti_softc *sc = ifp->if_softc; 2705 2706 if ((ifp->if_flags & IFF_UP) == 0) { 2707 ifp->if_flags |= IFF_UP; 2708 ti_init(sc); 2709 } 2710 2711 switch (cmd) { 2712 case SIOCSIFADDR: 2713 2714 switch (ifa->ifa_addr->sa_family) { 2715 #ifdef INET 2716 case AF_INET: 2717 arp_ifinit(ifp, ifa); 2718 break; 2719 #endif 2720 default: 2721 break; 2722 } 2723 break; 2724 2725 default: 2726 return (EINVAL); 2727 } 2728 2729 return (0); 2730 } 2731 2732 static int 2733 ti_ioctl(struct ifnet *ifp, u_long command, void *data) 2734 { 2735 struct ti_softc *sc = ifp->if_softc; 2736 struct ifreq *ifr = (struct ifreq *) data; 2737 int s, error = 0; 2738 struct ti_cmd_desc cmd; 2739 2740 s = splnet(); 2741 2742 switch (command) { 2743 case SIOCSIFADDR: 2744 case SIOCGIFADDR: 2745 error = ti_ether_ioctl(ifp, command, data); 2746 break; 2747 case SIOCSIFMTU: 2748 if (ifr->ifr_mtu > ETHERMTU_JUMBO) 2749 error = EINVAL; 2750 else { 2751 ifp->if_mtu = ifr->ifr_mtu; 2752 ti_init(sc); 2753 } 2754 break; 2755 case SIOCSIFFLAGS: 2756 if (ifp->if_flags & IFF_UP) { 2757 /* 2758 * If only the state of the PROMISC flag changed, 2759 * then just use the 'set promisc mode' command 2760 * instead of reinitializing the entire NIC. Doing 2761 * a full re-init means reloading the firmware and 2762 * waiting for it to start up, which may take a 2763 * second or two. 2764 */ 2765 if (ifp->if_flags & IFF_RUNNING && 2766 ifp->if_flags & IFF_PROMISC && 2767 !(sc->ti_if_flags & IFF_PROMISC)) { 2768 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2769 TI_CMD_CODE_PROMISC_ENB, 0); 2770 } else if (ifp->if_flags & IFF_RUNNING && 2771 !(ifp->if_flags & IFF_PROMISC) && 2772 sc->ti_if_flags & IFF_PROMISC) { 2773 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2774 TI_CMD_CODE_PROMISC_DIS, 0); 2775 } else 2776 ti_init(sc); 2777 } else { 2778 if (ifp->if_flags & IFF_RUNNING) { 2779 ti_stop(sc); 2780 } 2781 } 2782 sc->ti_if_flags = ifp->if_flags; 2783 error = 0; 2784 break; 2785 case SIOCADDMULTI: 2786 case SIOCDELMULTI: 2787 if ((error = ether_ioctl(ifp, command, data)) == ENETRESET) { 2788 if (ifp->if_flags & IFF_RUNNING) 2789 ti_setmulti(sc); 2790 error = 0; 2791 } 2792 break; 2793 case SIOCSIFMEDIA: 2794 case SIOCGIFMEDIA: 2795 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2796 break; 2797 default: 2798 error = EINVAL; 2799 break; 2800 } 2801 2802 (void)splx(s); 2803 2804 return (error); 2805 } 2806 2807 static void 2808 ti_watchdog(struct ifnet *ifp) 2809 { 2810 struct ti_softc *sc; 2811 2812 sc = ifp->if_softc; 2813 2814 printf("%s: watchdog timeout -- resetting\n", sc->sc_dev.dv_xname); 2815 ti_stop(sc); 2816 ti_init(sc); 2817 2818 ifp->if_oerrors++; 2819 } 2820 2821 /* 2822 * Stop the adapter and free any mbufs allocated to the 2823 * RX and TX lists. 2824 */ 2825 static void 2826 ti_stop(struct ti_softc *sc) 2827 { 2828 struct ifnet *ifp; 2829 struct ti_cmd_desc cmd; 2830 2831 ifp = &sc->ethercom.ec_if; 2832 2833 /* Disable host interrupts. */ 2834 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2835 /* 2836 * Tell firmware we're shutting down. 2837 */ 2838 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2839 2840 /* Halt and reinitialize. */ 2841 ti_chipinit(sc); 2842 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2843 ti_chipinit(sc); 2844 2845 /* Free the RX lists. */ 2846 ti_free_rx_ring_std(sc); 2847 2848 /* Free jumbo RX list. */ 2849 ti_free_rx_ring_jumbo(sc); 2850 2851 /* Free mini RX list. */ 2852 ti_free_rx_ring_mini(sc); 2853 2854 /* Free TX buffers. */ 2855 ti_free_tx_ring(sc); 2856 2857 sc->ti_ev_prodidx.ti_idx = 0; 2858 sc->ti_return_prodidx.ti_idx = 0; 2859 sc->ti_tx_considx.ti_idx = 0; 2860 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2861 2862 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2863 } 2864 2865 /* 2866 * Stop all chip I/O so that the kernel's probe routines don't 2867 * get confused by errant DMAs when rebooting. 2868 */ 2869 static void 2870 ti_shutdown(void *v) 2871 { 2872 struct ti_softc *sc = v; 2873 2874 ti_chipinit(sc); 2875 } 2876