1 /* $NetBSD: if_ti.c,v 1.88 2010/01/19 22:07:01 pooka Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_ti.c,v 1.15 1999/08/14 15:45:03 wpaul Exp 35 */ 36 37 /* 38 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 39 * Manuals, sample driver and firmware source kits are available 40 * from http://www.alteon.com/support/openkits. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 49 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 50 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 51 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 52 * filtering and jumbo (9014 byte) frames. The hardware is largely 53 * controlled by firmware, which must be loaded into the NIC during 54 * initialization. 55 * 56 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 57 * revision, which supports new features such as extended commands, 58 * extended jumbo receive ring desciptors and a mini receive ring. 59 * 60 * Alteon Networks is to be commended for releasing such a vast amount 61 * of development material for the Tigon NIC without requiring an NDA 62 * (although they really should have done it a long time ago). With 63 * any luck, the other vendors will finally wise up and follow Alteon's 64 * stellar example. 65 * 66 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 67 * this driver by #including it as a C header file. This bloats the 68 * driver somewhat, but it's the easiest method considering that the 69 * driver code and firmware code need to be kept in sync. The source 70 * for the firmware is not provided with the FreeBSD distribution since 71 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 72 * 73 * The following people deserve special thanks: 74 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 75 * for testing 76 * - Raymond Lee of Netgear, for providing a pair of Netgear 77 * GA620 Tigon 2 boards for testing 78 * - Ulf Zimmermann, for bringing the GA620 to my attention and 79 * convincing me to write this driver. 80 * - Andrew Gallatin for providing FreeBSD/Alpha support. 81 */ 82 83 #include <sys/cdefs.h> 84 __KERNEL_RCSID(0, "$NetBSD: if_ti.c,v 1.88 2010/01/19 22:07:01 pooka Exp $"); 85 86 #include "opt_inet.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/queue.h> 96 #include <sys/device.h> 97 #include <sys/reboot.h> 98 99 #include <uvm/uvm_extern.h> 100 101 #include <net/if.h> 102 #include <net/if_arp.h> 103 #include <net/if_ether.h> 104 #include <net/if_dl.h> 105 #include <net/if_media.h> 106 107 #include <net/bpf.h> 108 109 #ifdef INET 110 #include <netinet/in.h> 111 #include <netinet/if_inarp.h> 112 #include <netinet/in_systm.h> 113 #include <netinet/ip.h> 114 #endif 115 116 117 #include <sys/bus.h> 118 119 #include <dev/pci/pcireg.h> 120 #include <dev/pci/pcivar.h> 121 #include <dev/pci/pcidevs.h> 122 123 #include <dev/pci/if_tireg.h> 124 125 #include <dev/microcode/tigon/ti_fw.h> 126 #include <dev/microcode/tigon/ti_fw2.h> 127 128 /* 129 * Various supported device vendors/types and their names. 130 */ 131 132 static const struct ti_type ti_devs[] = { 133 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC, 134 "Alteon AceNIC 1000BASE-SX Ethernet" }, 135 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC_COPPER, 136 "Alteon AceNIC 1000BASE-T Ethernet" }, 137 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C985, 138 "3Com 3c985-SX Gigabit Ethernet" }, 139 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620, 140 "Netgear GA620 1000BASE-SX Ethernet" }, 141 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620T, 142 "Netgear GA620 1000BASE-T Ethernet" }, 143 { PCI_VENDOR_SGI, PCI_PRODUCT_SGI_TIGON, 144 "Silicon Graphics Gigabit Ethernet" }, 145 { 0, 0, NULL } 146 }; 147 148 static const struct ti_type *ti_type_match(struct pci_attach_args *); 149 static int ti_probe(device_t, cfdata_t, void *); 150 static void ti_attach(device_t, device_t, void *); 151 static bool ti_shutdown(device_t, int); 152 static void ti_txeof_tigon1(struct ti_softc *); 153 static void ti_txeof_tigon2(struct ti_softc *); 154 static void ti_rxeof(struct ti_softc *); 155 156 static void ti_stats_update(struct ti_softc *); 157 static int ti_encap_tigon1(struct ti_softc *, struct mbuf *, u_int32_t *); 158 static int ti_encap_tigon2(struct ti_softc *, struct mbuf *, u_int32_t *); 159 160 static int ti_intr(void *); 161 static void ti_start(struct ifnet *); 162 static int ti_ioctl(struct ifnet *, u_long, void *); 163 static void ti_init(void *); 164 static void ti_init2(struct ti_softc *); 165 static void ti_stop(struct ti_softc *); 166 static void ti_watchdog(struct ifnet *); 167 static int ti_ifmedia_upd(struct ifnet *); 168 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 169 170 static u_int32_t ti_eeprom_putbyte(struct ti_softc *, int); 171 static u_int8_t ti_eeprom_getbyte(struct ti_softc *, int, u_int8_t *); 172 static int ti_read_eeprom(struct ti_softc *, void *, int, int); 173 174 static void ti_add_mcast(struct ti_softc *, struct ether_addr *); 175 static void ti_del_mcast(struct ti_softc *, struct ether_addr *); 176 static void ti_setmulti(struct ti_softc *); 177 178 static void ti_mem(struct ti_softc *, u_int32_t, u_int32_t, const void *); 179 static void ti_loadfw(struct ti_softc *); 180 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 181 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, void *, int); 182 static void ti_handle_events(struct ti_softc *); 183 static int ti_alloc_jumbo_mem(struct ti_softc *); 184 static void *ti_jalloc(struct ti_softc *); 185 static void ti_jfree(struct mbuf *, void *, size_t, void *); 186 static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *, bus_dmamap_t); 187 static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *, bus_dmamap_t); 188 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 189 static int ti_init_rx_ring_std(struct ti_softc *); 190 static void ti_free_rx_ring_std(struct ti_softc *); 191 static int ti_init_rx_ring_jumbo(struct ti_softc *); 192 static void ti_free_rx_ring_jumbo(struct ti_softc *); 193 static int ti_init_rx_ring_mini(struct ti_softc *); 194 static void ti_free_rx_ring_mini(struct ti_softc *); 195 static void ti_free_tx_ring(struct ti_softc *); 196 static int ti_init_tx_ring(struct ti_softc *); 197 198 static int ti_64bitslot_war(struct ti_softc *); 199 static int ti_chipinit(struct ti_softc *); 200 static int ti_gibinit(struct ti_softc *); 201 202 static int ti_ether_ioctl(struct ifnet *, u_long, void *); 203 204 CFATTACH_DECL(ti, sizeof(struct ti_softc), 205 ti_probe, ti_attach, NULL, NULL); 206 207 /* 208 * Send an instruction or address to the EEPROM, check for ACK. 209 */ 210 static u_int32_t 211 ti_eeprom_putbyte(struct ti_softc *sc, int byte) 212 { 213 int i, ack = 0; 214 215 /* 216 * Make sure we're in TX mode. 217 */ 218 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 219 220 /* 221 * Feed in each bit and stobe the clock. 222 */ 223 for (i = 0x80; i; i >>= 1) { 224 if (byte & i) { 225 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 226 } else { 227 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 228 } 229 DELAY(1); 230 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 231 DELAY(1); 232 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 233 } 234 235 /* 236 * Turn off TX mode. 237 */ 238 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 239 240 /* 241 * Check for ack. 242 */ 243 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 244 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 245 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 246 247 return (ack); 248 } 249 250 /* 251 * Read a byte of data stored in the EEPROM at address 'addr.' 252 * We have to send two address bytes since the EEPROM can hold 253 * more than 256 bytes of data. 254 */ 255 static u_int8_t 256 ti_eeprom_getbyte(struct ti_softc *sc, int addr, u_int8_t *dest) 257 { 258 int i; 259 u_int8_t byte = 0; 260 261 EEPROM_START(); 262 263 /* 264 * Send write control code to EEPROM. 265 */ 266 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 267 printf("%s: failed to send write command, status: %x\n", 268 device_xname(&sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 269 return (1); 270 } 271 272 /* 273 * Send first byte of address of byte we want to read. 274 */ 275 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 276 printf("%s: failed to send address, status: %x\n", 277 device_xname(&sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 278 return (1); 279 } 280 /* 281 * Send second byte address of byte we want to read. 282 */ 283 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 284 printf("%s: failed to send address, status: %x\n", 285 device_xname(&sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 286 return (1); 287 } 288 289 EEPROM_STOP(); 290 EEPROM_START(); 291 /* 292 * Send read control code to EEPROM. 293 */ 294 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 295 printf("%s: failed to send read command, status: %x\n", 296 device_xname(&sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 297 return (1); 298 } 299 300 /* 301 * Start reading bits from EEPROM. 302 */ 303 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 304 for (i = 0x80; i; i >>= 1) { 305 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 306 DELAY(1); 307 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 308 byte |= i; 309 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 310 DELAY(1); 311 } 312 313 EEPROM_STOP(); 314 315 /* 316 * No ACK generated for read, so just return byte. 317 */ 318 319 *dest = byte; 320 321 return (0); 322 } 323 324 /* 325 * Read a sequence of bytes from the EEPROM. 326 */ 327 static int 328 ti_read_eeprom(struct ti_softc *sc, void *destv, int off, int cnt) 329 { 330 char *dest = destv; 331 int err = 0, i; 332 u_int8_t byte = 0; 333 334 for (i = 0; i < cnt; i++) { 335 err = ti_eeprom_getbyte(sc, off + i, &byte); 336 if (err) 337 break; 338 *(dest + i) = byte; 339 } 340 341 return (err ? 1 : 0); 342 } 343 344 /* 345 * NIC memory access function. Can be used to either clear a section 346 * of NIC local memory or (if tbuf is non-NULL) copy data into it. 347 */ 348 static void 349 ti_mem(struct ti_softc *sc, u_int32_t addr, u_int32_t len, const void *xbuf) 350 { 351 int segptr, segsize, cnt; 352 const void *ptr; 353 354 segptr = addr; 355 cnt = len; 356 ptr = xbuf; 357 358 while (cnt) { 359 if (cnt < TI_WINLEN) 360 segsize = cnt; 361 else 362 segsize = TI_WINLEN - (segptr % TI_WINLEN); 363 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 364 if (xbuf == NULL) { 365 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 366 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, 367 segsize / 4); 368 } else { 369 #ifdef __BUS_SPACE_HAS_STREAM_METHODS 370 bus_space_write_region_stream_4(sc->ti_btag, 371 sc->ti_bhandle, 372 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 373 (const u_int32_t *)ptr, segsize / 4); 374 #else 375 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 376 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 377 (const u_int32_t *)ptr, segsize / 4); 378 #endif 379 ptr = (const char *)ptr + segsize; 380 } 381 segptr += segsize; 382 cnt -= segsize; 383 } 384 385 return; 386 } 387 388 /* 389 * Load firmware image into the NIC. Check that the firmware revision 390 * is acceptable and see if we want the firmware for the Tigon 1 or 391 * Tigon 2. 392 */ 393 static void 394 ti_loadfw(struct ti_softc *sc) 395 { 396 switch (sc->ti_hwrev) { 397 case TI_HWREV_TIGON: 398 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 399 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 400 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 401 printf("%s: firmware revision mismatch; want " 402 "%d.%d.%d, got %d.%d.%d\n", device_xname(&sc->sc_dev), 403 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 404 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 405 tigonFwReleaseMinor, tigonFwReleaseFix); 406 return; 407 } 408 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText); 409 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData); 410 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, tigonFwRodata); 411 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 412 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 413 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 414 break; 415 case TI_HWREV_TIGON_II: 416 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 417 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 418 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 419 printf("%s: firmware revision mismatch; want " 420 "%d.%d.%d, got %d.%d.%d\n", device_xname(&sc->sc_dev), 421 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 422 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 423 tigon2FwReleaseMinor, tigon2FwReleaseFix); 424 return; 425 } 426 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, tigon2FwText); 427 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, tigon2FwData); 428 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 429 tigon2FwRodata); 430 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 431 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 432 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 433 break; 434 default: 435 printf("%s: can't load firmware: unknown hardware rev\n", 436 device_xname(&sc->sc_dev)); 437 break; 438 } 439 440 return; 441 } 442 443 /* 444 * Send the NIC a command via the command ring. 445 */ 446 static void 447 ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd) 448 { 449 u_int32_t index; 450 451 index = sc->ti_cmd_saved_prodidx; 452 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 453 TI_INC(index, TI_CMD_RING_CNT); 454 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 455 sc->ti_cmd_saved_prodidx = index; 456 } 457 458 /* 459 * Send the NIC an extended command. The 'len' parameter specifies the 460 * number of command slots to include after the initial command. 461 */ 462 static void 463 ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, void *argv, int len) 464 { 465 char *arg = argv; 466 u_int32_t index; 467 int i; 468 469 index = sc->ti_cmd_saved_prodidx; 470 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 471 TI_INC(index, TI_CMD_RING_CNT); 472 for (i = 0; i < len; i++) { 473 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 474 *(u_int32_t *)(&arg[i * 4])); 475 TI_INC(index, TI_CMD_RING_CNT); 476 } 477 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 478 sc->ti_cmd_saved_prodidx = index; 479 } 480 481 /* 482 * Handle events that have triggered interrupts. 483 */ 484 static void 485 ti_handle_events(struct ti_softc *sc) 486 { 487 struct ti_event_desc *e; 488 489 if (sc->ti_rdata->ti_event_ring == NULL) 490 return; 491 492 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 493 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 494 switch (TI_EVENT_EVENT(e)) { 495 case TI_EV_LINKSTAT_CHANGED: 496 sc->ti_linkstat = TI_EVENT_CODE(e); 497 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) 498 printf("%s: 10/100 link up\n", 499 device_xname(&sc->sc_dev)); 500 else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) 501 printf("%s: gigabit link up\n", 502 device_xname(&sc->sc_dev)); 503 else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 504 printf("%s: link down\n", 505 device_xname(&sc->sc_dev)); 506 break; 507 case TI_EV_ERROR: 508 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD) 509 printf("%s: invalid command\n", 510 device_xname(&sc->sc_dev)); 511 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD) 512 printf("%s: unknown command\n", 513 device_xname(&sc->sc_dev)); 514 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG) 515 printf("%s: bad config data\n", 516 device_xname(&sc->sc_dev)); 517 break; 518 case TI_EV_FIRMWARE_UP: 519 ti_init2(sc); 520 break; 521 case TI_EV_STATS_UPDATED: 522 ti_stats_update(sc); 523 break; 524 case TI_EV_RESET_JUMBO_RING: 525 case TI_EV_MCAST_UPDATED: 526 /* Who cares. */ 527 break; 528 default: 529 printf("%s: unknown event: %d\n", 530 device_xname(&sc->sc_dev), TI_EVENT_EVENT(e)); 531 break; 532 } 533 /* Advance the consumer index. */ 534 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 535 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 536 } 537 538 return; 539 } 540 541 /* 542 * Memory management for the jumbo receive ring is a pain in the 543 * butt. We need to allocate at least 9018 bytes of space per frame, 544 * _and_ it has to be contiguous (unless you use the extended 545 * jumbo descriptor format). Using malloc() all the time won't 546 * work: malloc() allocates memory in powers of two, which means we 547 * would end up wasting a considerable amount of space by allocating 548 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 549 * to do our own memory management. 550 * 551 * The driver needs to allocate a contiguous chunk of memory at boot 552 * time. We then chop this up ourselves into 9K pieces and use them 553 * as external mbuf storage. 554 * 555 * One issue here is how much memory to allocate. The jumbo ring has 556 * 256 slots in it, but at 9K per slot than can consume over 2MB of 557 * RAM. This is a bit much, especially considering we also need 558 * RAM for the standard ring and mini ring (on the Tigon 2). To 559 * save space, we only actually allocate enough memory for 64 slots 560 * by default, which works out to between 500 and 600K. This can 561 * be tuned by changing a #define in if_tireg.h. 562 */ 563 564 static int 565 ti_alloc_jumbo_mem(struct ti_softc *sc) 566 { 567 char *ptr; 568 int i; 569 struct ti_jpool_entry *entry; 570 bus_dma_segment_t dmaseg; 571 int error, dmanseg; 572 573 /* Grab a big chunk o' storage. */ 574 if ((error = bus_dmamem_alloc(sc->sc_dmat, 575 TI_JMEM, PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 576 BUS_DMA_NOWAIT)) != 0) { 577 aprint_error_dev(&sc->sc_dev, "can't allocate jumbo buffer, error = %d\n", 578 error); 579 return (error); 580 } 581 582 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 583 TI_JMEM, (void **)&sc->ti_cdata.ti_jumbo_buf, 584 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 585 aprint_error_dev(&sc->sc_dev, "can't map jumbo buffer, error = %d\n", 586 error); 587 return (error); 588 } 589 590 if ((error = bus_dmamap_create(sc->sc_dmat, 591 TI_JMEM, 1, 592 TI_JMEM, 0, BUS_DMA_NOWAIT, 593 &sc->jumbo_dmamap)) != 0) { 594 aprint_error_dev(&sc->sc_dev, "can't create jumbo buffer DMA map, error = %d\n", 595 error); 596 return (error); 597 } 598 599 if ((error = bus_dmamap_load(sc->sc_dmat, sc->jumbo_dmamap, 600 sc->ti_cdata.ti_jumbo_buf, TI_JMEM, NULL, 601 BUS_DMA_NOWAIT)) != 0) { 602 aprint_error_dev(&sc->sc_dev, "can't load jumbo buffer DMA map, error = %d\n", 603 error); 604 return (error); 605 } 606 sc->jumbo_dmaaddr = sc->jumbo_dmamap->dm_segs[0].ds_addr; 607 608 SIMPLEQ_INIT(&sc->ti_jfree_listhead); 609 SIMPLEQ_INIT(&sc->ti_jinuse_listhead); 610 611 /* 612 * Now divide it up into 9K pieces and save the addresses 613 * in an array. 614 */ 615 ptr = sc->ti_cdata.ti_jumbo_buf; 616 for (i = 0; i < TI_JSLOTS; i++) { 617 sc->ti_cdata.ti_jslots[i] = ptr; 618 ptr += TI_JLEN; 619 entry = malloc(sizeof(struct ti_jpool_entry), 620 M_DEVBUF, M_NOWAIT); 621 if (entry == NULL) { 622 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF); 623 sc->ti_cdata.ti_jumbo_buf = NULL; 624 printf("%s: no memory for jumbo " 625 "buffer queue!\n", device_xname(&sc->sc_dev)); 626 return (ENOBUFS); 627 } 628 entry->slot = i; 629 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, 630 jpool_entries); 631 } 632 633 return (0); 634 } 635 636 /* 637 * Allocate a jumbo buffer. 638 */ 639 static void * 640 ti_jalloc(struct ti_softc *sc) 641 { 642 struct ti_jpool_entry *entry; 643 644 entry = SIMPLEQ_FIRST(&sc->ti_jfree_listhead); 645 646 if (entry == NULL) { 647 printf("%s: no free jumbo buffers\n", device_xname(&sc->sc_dev)); 648 return (NULL); 649 } 650 651 SIMPLEQ_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 652 SIMPLEQ_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 653 654 return (sc->ti_cdata.ti_jslots[entry->slot]); 655 } 656 657 /* 658 * Release a jumbo buffer. 659 */ 660 static void 661 ti_jfree(struct mbuf *m, void *tbuf, size_t size, void *arg) 662 { 663 struct ti_softc *sc; 664 int i, s; 665 struct ti_jpool_entry *entry; 666 667 /* Extract the softc struct pointer. */ 668 sc = (struct ti_softc *)arg; 669 670 if (sc == NULL) 671 panic("ti_jfree: didn't get softc pointer!"); 672 673 /* calculate the slot this buffer belongs to */ 674 675 i = ((char *)tbuf 676 - (char *)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 677 678 if ((i < 0) || (i >= TI_JSLOTS)) 679 panic("ti_jfree: asked to free buffer that we don't manage!"); 680 681 s = splvm(); 682 entry = SIMPLEQ_FIRST(&sc->ti_jinuse_listhead); 683 if (entry == NULL) 684 panic("ti_jfree: buffer not in use!"); 685 entry->slot = i; 686 SIMPLEQ_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 687 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 688 689 if (__predict_true(m != NULL)) 690 pool_cache_put(mb_cache, m); 691 splx(s); 692 } 693 694 695 /* 696 * Intialize a standard receive ring descriptor. 697 */ 698 static int 699 ti_newbuf_std(struct ti_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap) 700 { 701 struct mbuf *m_new = NULL; 702 struct ti_rx_desc *r; 703 int error; 704 705 if (dmamap == NULL) { 706 /* if (m) panic() */ 707 708 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 709 MCLBYTES, 0, BUS_DMA_NOWAIT, 710 &dmamap)) != 0) { 711 aprint_error_dev(&sc->sc_dev, "can't create recv map, error = %d\n", 712 error); 713 return (ENOMEM); 714 } 715 } 716 sc->std_dmamap[i] = dmamap; 717 718 if (m == NULL) { 719 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 720 if (m_new == NULL) { 721 aprint_error_dev(&sc->sc_dev, "mbuf allocation failed " 722 "-- packet dropped!\n"); 723 return (ENOBUFS); 724 } 725 726 MCLGET(m_new, M_DONTWAIT); 727 if (!(m_new->m_flags & M_EXT)) { 728 aprint_error_dev(&sc->sc_dev, "cluster allocation failed " 729 "-- packet dropped!\n"); 730 m_freem(m_new); 731 return (ENOBUFS); 732 } 733 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 734 m_adj(m_new, ETHER_ALIGN); 735 736 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 737 mtod(m_new, void *), m_new->m_len, NULL, 738 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 739 aprint_error_dev(&sc->sc_dev, "can't load recv map, error = %d\n", 740 error); 741 return (ENOMEM); 742 } 743 } else { 744 m_new = m; 745 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 746 m_new->m_data = m_new->m_ext.ext_buf; 747 m_adj(m_new, ETHER_ALIGN); 748 749 /* reuse the dmamap */ 750 } 751 752 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 753 r = &sc->ti_rdata->ti_rx_std_ring[i]; 754 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 755 r->ti_type = TI_BDTYPE_RECV_BD; 756 r->ti_flags = 0; 757 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx) 758 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 759 if (sc->ethercom.ec_if.if_capenable & 760 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 761 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 762 r->ti_len = m_new->m_len; /* == ds_len */ 763 r->ti_idx = i; 764 765 return (0); 766 } 767 768 /* 769 * Intialize a mini receive ring descriptor. This only applies to 770 * the Tigon 2. 771 */ 772 static int 773 ti_newbuf_mini(struct ti_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap) 774 { 775 struct mbuf *m_new = NULL; 776 struct ti_rx_desc *r; 777 int error; 778 779 if (dmamap == NULL) { 780 /* if (m) panic() */ 781 782 if ((error = bus_dmamap_create(sc->sc_dmat, MHLEN, 1, 783 MHLEN, 0, BUS_DMA_NOWAIT, 784 &dmamap)) != 0) { 785 aprint_error_dev(&sc->sc_dev, "can't create recv map, error = %d\n", 786 error); 787 return (ENOMEM); 788 } 789 } 790 sc->mini_dmamap[i] = dmamap; 791 792 if (m == NULL) { 793 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 794 if (m_new == NULL) { 795 aprint_error_dev(&sc->sc_dev, "mbuf allocation failed " 796 "-- packet dropped!\n"); 797 return (ENOBUFS); 798 } 799 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 800 m_adj(m_new, ETHER_ALIGN); 801 802 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 803 mtod(m_new, void *), m_new->m_len, NULL, 804 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 805 aprint_error_dev(&sc->sc_dev, "can't load recv map, error = %d\n", 806 error); 807 return (ENOMEM); 808 } 809 } else { 810 m_new = m; 811 m_new->m_data = m_new->m_pktdat; 812 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 813 m_adj(m_new, ETHER_ALIGN); 814 815 /* reuse the dmamap */ 816 } 817 818 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 819 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 820 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 821 r->ti_type = TI_BDTYPE_RECV_BD; 822 r->ti_flags = TI_BDFLAG_MINI_RING; 823 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx) 824 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 825 if (sc->ethercom.ec_if.if_capenable & 826 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 827 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 828 r->ti_len = m_new->m_len; /* == ds_len */ 829 r->ti_idx = i; 830 831 return (0); 832 } 833 834 /* 835 * Initialize a jumbo receive ring descriptor. This allocates 836 * a jumbo buffer from the pool managed internally by the driver. 837 */ 838 static int 839 ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *m) 840 { 841 struct mbuf *m_new = NULL; 842 struct ti_rx_desc *r; 843 844 if (m == NULL) { 845 void * tbuf = NULL; 846 847 /* Allocate the mbuf. */ 848 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 849 if (m_new == NULL) { 850 aprint_error_dev(&sc->sc_dev, "mbuf allocation failed " 851 "-- packet dropped!\n"); 852 return (ENOBUFS); 853 } 854 855 /* Allocate the jumbo buffer */ 856 tbuf = ti_jalloc(sc); 857 if (tbuf == NULL) { 858 m_freem(m_new); 859 aprint_error_dev(&sc->sc_dev, "jumbo allocation failed " 860 "-- packet dropped!\n"); 861 return (ENOBUFS); 862 } 863 864 /* Attach the buffer to the mbuf. */ 865 MEXTADD(m_new, tbuf, ETHER_MAX_LEN_JUMBO, 866 M_DEVBUF, ti_jfree, sc); 867 m_new->m_flags |= M_EXT_RW; 868 m_new->m_len = m_new->m_pkthdr.len = ETHER_MAX_LEN_JUMBO; 869 } else { 870 m_new = m; 871 m_new->m_data = m_new->m_ext.ext_buf; 872 m_new->m_ext.ext_size = ETHER_MAX_LEN_JUMBO; 873 } 874 875 m_adj(m_new, ETHER_ALIGN); 876 /* Set up the descriptor. */ 877 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 878 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 879 TI_HOSTADDR(r->ti_addr) = sc->jumbo_dmaaddr + 880 (mtod(m_new, char *) - (char *)sc->ti_cdata.ti_jumbo_buf); 881 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 882 r->ti_flags = TI_BDFLAG_JUMBO_RING; 883 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx) 884 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 885 if (sc->ethercom.ec_if.if_capenable & 886 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 887 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 888 r->ti_len = m_new->m_len; 889 r->ti_idx = i; 890 891 return (0); 892 } 893 894 /* 895 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 896 * that's 1MB or memory, which is a lot. For now, we fill only the first 897 * 256 ring entries and hope that our CPU is fast enough to keep up with 898 * the NIC. 899 */ 900 static int 901 ti_init_rx_ring_std(struct ti_softc *sc) 902 { 903 int i; 904 struct ti_cmd_desc cmd; 905 906 for (i = 0; i < TI_SSLOTS; i++) { 907 if (ti_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 908 return (ENOBUFS); 909 }; 910 911 TI_UPDATE_STDPROD(sc, i - 1); 912 sc->ti_std = i - 1; 913 914 return (0); 915 } 916 917 static void 918 ti_free_rx_ring_std(struct ti_softc *sc) 919 { 920 int i; 921 922 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 923 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 924 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 925 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 926 927 /* if (sc->std_dmamap[i] == 0) panic() */ 928 bus_dmamap_destroy(sc->sc_dmat, sc->std_dmamap[i]); 929 sc->std_dmamap[i] = 0; 930 } 931 memset((char *)&sc->ti_rdata->ti_rx_std_ring[i], 0, 932 sizeof(struct ti_rx_desc)); 933 } 934 935 return; 936 } 937 938 static int 939 ti_init_rx_ring_jumbo(struct ti_softc *sc) 940 { 941 int i; 942 struct ti_cmd_desc cmd; 943 944 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 945 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 946 return (ENOBUFS); 947 }; 948 949 TI_UPDATE_JUMBOPROD(sc, i - 1); 950 sc->ti_jumbo = i - 1; 951 952 return (0); 953 } 954 955 static void 956 ti_free_rx_ring_jumbo(struct ti_softc *sc) 957 { 958 int i; 959 960 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 961 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 962 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 963 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 964 } 965 memset((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 0, 966 sizeof(struct ti_rx_desc)); 967 } 968 969 return; 970 } 971 972 static int 973 ti_init_rx_ring_mini(struct ti_softc *sc) 974 { 975 int i; 976 977 for (i = 0; i < TI_MSLOTS; i++) { 978 if (ti_newbuf_mini(sc, i, NULL, 0) == ENOBUFS) 979 return (ENOBUFS); 980 }; 981 982 TI_UPDATE_MINIPROD(sc, i - 1); 983 sc->ti_mini = i - 1; 984 985 return (0); 986 } 987 988 static void 989 ti_free_rx_ring_mini(struct ti_softc *sc) 990 { 991 int i; 992 993 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 994 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 995 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 996 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 997 998 /* if (sc->mini_dmamap[i] == 0) panic() */ 999 bus_dmamap_destroy(sc->sc_dmat, sc->mini_dmamap[i]); 1000 sc->mini_dmamap[i] = 0; 1001 } 1002 memset((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 0, 1003 sizeof(struct ti_rx_desc)); 1004 } 1005 1006 return; 1007 } 1008 1009 static void 1010 ti_free_tx_ring(struct ti_softc *sc) 1011 { 1012 int i; 1013 struct txdmamap_pool_entry *dma; 1014 1015 if (sc->ti_rdata->ti_tx_ring == NULL) 1016 return; 1017 1018 for (i = 0; i < TI_TX_RING_CNT; i++) { 1019 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1020 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1021 sc->ti_cdata.ti_tx_chain[i] = NULL; 1022 1023 /* if (sc->txdma[i] == 0) panic() */ 1024 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1025 link); 1026 sc->txdma[i] = 0; 1027 } 1028 memset((char *)&sc->ti_rdata->ti_tx_ring[i], 0, 1029 sizeof(struct ti_tx_desc)); 1030 } 1031 1032 while ((dma = SIMPLEQ_FIRST(&sc->txdma_list))) { 1033 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 1034 bus_dmamap_destroy(sc->sc_dmat, dma->dmamap); 1035 free(dma, M_DEVBUF); 1036 } 1037 1038 return; 1039 } 1040 1041 static int 1042 ti_init_tx_ring(struct ti_softc *sc) 1043 { 1044 int i, error; 1045 bus_dmamap_t dmamap; 1046 struct txdmamap_pool_entry *dma; 1047 1048 sc->ti_txcnt = 0; 1049 sc->ti_tx_saved_considx = 0; 1050 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1051 1052 SIMPLEQ_INIT(&sc->txdma_list); 1053 for (i = 0; i < TI_RSLOTS; i++) { 1054 /* I've seen mbufs with 30 fragments. */ 1055 if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_MAX_LEN_JUMBO, 1056 40, ETHER_MAX_LEN_JUMBO, 0, 1057 BUS_DMA_NOWAIT, &dmamap)) != 0) { 1058 aprint_error_dev(&sc->sc_dev, "can't create tx map, error = %d\n", 1059 error); 1060 return (ENOMEM); 1061 } 1062 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1063 if (!dma) { 1064 aprint_error_dev(&sc->sc_dev, "can't alloc txdmamap_pool_entry\n"); 1065 bus_dmamap_destroy(sc->sc_dmat, dmamap); 1066 return (ENOMEM); 1067 } 1068 dma->dmamap = dmamap; 1069 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 1070 } 1071 1072 return (0); 1073 } 1074 1075 /* 1076 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1077 * but we have to support the old way too so that Tigon 1 cards will 1078 * work. 1079 */ 1080 static void 1081 ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr) 1082 { 1083 struct ti_cmd_desc cmd; 1084 u_int16_t *m; 1085 u_int32_t ext[2] = {0, 0}; 1086 1087 m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1088 1089 switch (sc->ti_hwrev) { 1090 case TI_HWREV_TIGON: 1091 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1092 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1093 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1094 break; 1095 case TI_HWREV_TIGON_II: 1096 ext[0] = htons(m[0]); 1097 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1098 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (void *)&ext, 2); 1099 break; 1100 default: 1101 printf("%s: unknown hwrev\n", device_xname(&sc->sc_dev)); 1102 break; 1103 } 1104 1105 return; 1106 } 1107 1108 static void 1109 ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr) 1110 { 1111 struct ti_cmd_desc cmd; 1112 u_int16_t *m; 1113 u_int32_t ext[2] = {0, 0}; 1114 1115 m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1116 1117 switch (sc->ti_hwrev) { 1118 case TI_HWREV_TIGON: 1119 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1120 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1121 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1122 break; 1123 case TI_HWREV_TIGON_II: 1124 ext[0] = htons(m[0]); 1125 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1126 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (void *)&ext, 2); 1127 break; 1128 default: 1129 printf("%s: unknown hwrev\n", device_xname(&sc->sc_dev)); 1130 break; 1131 } 1132 1133 return; 1134 } 1135 1136 /* 1137 * Configure the Tigon's multicast address filter. 1138 * 1139 * The actual multicast table management is a bit of a pain, thanks to 1140 * slight brain damage on the part of both Alteon and us. With our 1141 * multicast code, we are only alerted when the multicast address table 1142 * changes and at that point we only have the current list of addresses: 1143 * we only know the current state, not the previous state, so we don't 1144 * actually know what addresses were removed or added. The firmware has 1145 * state, but we can't get our grubby mits on it, and there is no 'delete 1146 * all multicast addresses' command. Hence, we have to maintain our own 1147 * state so we know what addresses have been programmed into the NIC at 1148 * any given time. 1149 */ 1150 static void 1151 ti_setmulti(struct ti_softc *sc) 1152 { 1153 struct ifnet *ifp; 1154 struct ti_cmd_desc cmd; 1155 struct ti_mc_entry *mc; 1156 u_int32_t intrs; 1157 struct ether_multi *enm; 1158 struct ether_multistep step; 1159 1160 ifp = &sc->ethercom.ec_if; 1161 1162 /* Disable interrupts. */ 1163 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1164 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1165 1166 /* First, zot all the existing filters. */ 1167 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1168 ti_del_mcast(sc, &mc->mc_addr); 1169 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1170 free(mc, M_DEVBUF); 1171 } 1172 1173 /* 1174 * Remember all multicast addresses so that we can delete them 1175 * later. Punt if there is a range of addresses or memory shortage. 1176 */ 1177 ETHER_FIRST_MULTI(step, &sc->ethercom, enm); 1178 while (enm != NULL) { 1179 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1180 ETHER_ADDR_LEN) != 0) 1181 goto allmulti; 1182 if ((mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, 1183 M_NOWAIT)) == NULL) 1184 goto allmulti; 1185 memcpy(&mc->mc_addr, enm->enm_addrlo, ETHER_ADDR_LEN); 1186 SIMPLEQ_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1187 ETHER_NEXT_MULTI(step, enm); 1188 } 1189 1190 /* Accept only programmed multicast addresses */ 1191 ifp->if_flags &= ~IFF_ALLMULTI; 1192 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1193 1194 /* Now program new ones. */ 1195 SIMPLEQ_FOREACH(mc, &sc->ti_mc_listhead, mc_entries) 1196 ti_add_mcast(sc, &mc->mc_addr); 1197 1198 /* Re-enable interrupts. */ 1199 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1200 1201 return; 1202 1203 allmulti: 1204 /* No need to keep individual multicast addresses */ 1205 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1206 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1207 free(mc, M_DEVBUF); 1208 } 1209 1210 /* Accept all multicast addresses */ 1211 ifp->if_flags |= IFF_ALLMULTI; 1212 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1213 1214 /* Re-enable interrupts. */ 1215 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1216 } 1217 1218 /* 1219 * Check to see if the BIOS has configured us for a 64 bit slot when 1220 * we aren't actually in one. If we detect this condition, we can work 1221 * around it on the Tigon 2 by setting a bit in the PCI state register, 1222 * but for the Tigon 1 we must give up and abort the interface attach. 1223 */ 1224 static int 1225 ti_64bitslot_war(struct ti_softc *sc) 1226 { 1227 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1228 CSR_WRITE_4(sc, 0x600, 0); 1229 CSR_WRITE_4(sc, 0x604, 0); 1230 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1231 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1232 if (sc->ti_hwrev == TI_HWREV_TIGON) 1233 return (EINVAL); 1234 else { 1235 TI_SETBIT(sc, TI_PCI_STATE, 1236 TI_PCISTATE_32BIT_BUS); 1237 return (0); 1238 } 1239 } 1240 } 1241 1242 return (0); 1243 } 1244 1245 /* 1246 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1247 * self-test results. 1248 */ 1249 static int 1250 ti_chipinit(struct ti_softc *sc) 1251 { 1252 u_int32_t cacheline; 1253 u_int32_t pci_writemax = 0; 1254 u_int32_t rev; 1255 1256 /* Initialize link to down state. */ 1257 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1258 1259 /* Set endianness before we access any non-PCI registers. */ 1260 #if BYTE_ORDER == BIG_ENDIAN 1261 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1262 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1263 #else 1264 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1265 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1266 #endif 1267 1268 /* Check the ROM failed bit to see if self-tests passed. */ 1269 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1270 printf("%s: board self-diagnostics failed!\n", 1271 device_xname(&sc->sc_dev)); 1272 return (ENODEV); 1273 } 1274 1275 /* Halt the CPU. */ 1276 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1277 1278 /* Figure out the hardware revision. */ 1279 rev = CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK; 1280 switch (rev) { 1281 case TI_REV_TIGON_I: 1282 sc->ti_hwrev = TI_HWREV_TIGON; 1283 break; 1284 case TI_REV_TIGON_II: 1285 sc->ti_hwrev = TI_HWREV_TIGON_II; 1286 break; 1287 default: 1288 printf("%s: unsupported chip revision 0x%x\n", 1289 device_xname(&sc->sc_dev), rev); 1290 return (ENODEV); 1291 } 1292 1293 /* Do special setup for Tigon 2. */ 1294 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1295 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1296 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 1297 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1298 } 1299 1300 /* Set up the PCI state register. */ 1301 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1302 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1303 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1304 } 1305 1306 /* Clear the read/write max DMA parameters. */ 1307 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1308 TI_PCISTATE_READ_MAXDMA)); 1309 1310 /* Get cache line size. */ 1311 cacheline = PCI_CACHELINE(CSR_READ_4(sc, PCI_BHLC_REG)); 1312 1313 /* 1314 * If the system has set enabled the PCI memory write 1315 * and invalidate command in the command register, set 1316 * the write max parameter accordingly. This is necessary 1317 * to use MWI with the Tigon 2. 1318 */ 1319 if (CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1320 & PCI_COMMAND_INVALIDATE_ENABLE) { 1321 switch (cacheline) { 1322 case 1: 1323 case 4: 1324 case 8: 1325 case 16: 1326 case 32: 1327 case 64: 1328 break; 1329 default: 1330 /* Disable PCI memory write and invalidate. */ 1331 if (bootverbose) 1332 printf("%s: cache line size %d not " 1333 "supported; disabling PCI MWI\n", 1334 device_xname(&sc->sc_dev), cacheline); 1335 CSR_WRITE_4(sc, PCI_COMMAND_STATUS_REG, 1336 CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1337 & ~PCI_COMMAND_INVALIDATE_ENABLE); 1338 break; 1339 } 1340 } 1341 1342 #ifdef __brokenalpha__ 1343 /* 1344 * From the Alteon sample driver: 1345 * Must insure that we do not cross an 8K (bytes) boundary 1346 * for DMA reads. Our highest limit is 1K bytes. This is a 1347 * restriction on some ALPHA platforms with early revision 1348 * 21174 PCI chipsets, such as the AlphaPC 164lx 1349 */ 1350 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1351 #else 1352 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1353 #endif 1354 1355 /* This sets the min dma param all the way up (0xff). */ 1356 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1357 1358 /* Configure DMA variables. */ 1359 #if BYTE_ORDER == BIG_ENDIAN 1360 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1361 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1362 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1363 TI_OPMODE_DONT_FRAG_JUMBO); 1364 #else 1365 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1366 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1367 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1368 #endif 1369 1370 /* 1371 * Only allow 1 DMA channel to be active at a time. 1372 * I don't think this is a good idea, but without it 1373 * the firmware racks up lots of nicDmaReadRingFull 1374 * errors. 1375 * Incompatible with hardware assisted checksums. 1376 */ 1377 if ((sc->ethercom.ec_if.if_capenable & 1378 (IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1379 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 1380 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx)) == 0) 1381 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1382 1383 /* Recommended settings from Tigon manual. */ 1384 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1385 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1386 1387 if (ti_64bitslot_war(sc)) { 1388 printf("%s: bios thinks we're in a 64 bit slot, " 1389 "but we aren't", device_xname(&sc->sc_dev)); 1390 return (EINVAL); 1391 } 1392 1393 return (0); 1394 } 1395 1396 /* 1397 * Initialize the general information block and firmware, and 1398 * start the CPU(s) running. 1399 */ 1400 static int 1401 ti_gibinit(struct ti_softc *sc) 1402 { 1403 struct ti_rcb *rcb; 1404 int i; 1405 struct ifnet *ifp; 1406 1407 ifp = &sc->ethercom.ec_if; 1408 1409 /* Disable interrupts for now. */ 1410 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1411 1412 /* Tell the chip where to find the general information block. */ 1413 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1414 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, TI_CDGIBADDR(sc)); 1415 1416 /* Load the firmware into SRAM. */ 1417 ti_loadfw(sc); 1418 1419 /* Set up the contents of the general info and ring control blocks. */ 1420 1421 /* Set up the event ring and producer pointer. */ 1422 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1423 1424 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDEVENTADDR(sc, 0); 1425 rcb->ti_flags = 0; 1426 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1427 TI_CDEVPRODADDR(sc); 1428 1429 sc->ti_ev_prodidx.ti_idx = 0; 1430 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1431 sc->ti_ev_saved_considx = 0; 1432 1433 /* Set up the command ring and producer mailbox. */ 1434 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1435 1436 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1437 rcb->ti_flags = 0; 1438 rcb->ti_max_len = 0; 1439 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1440 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1441 } 1442 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1443 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1444 sc->ti_cmd_saved_prodidx = 0; 1445 1446 /* 1447 * Assign the address of the stats refresh buffer. 1448 * We re-use the current stats buffer for this to 1449 * conserve memory. 1450 */ 1451 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1452 TI_CDSTATSADDR(sc); 1453 1454 /* Set up the standard receive ring. */ 1455 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1456 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXSTDADDR(sc, 0); 1457 rcb->ti_max_len = ETHER_MAX_LEN; 1458 rcb->ti_flags = 0; 1459 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1460 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1461 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 1462 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1463 if (VLAN_ATTACHED(&sc->ethercom)) 1464 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1465 1466 /* Set up the jumbo receive ring. */ 1467 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1468 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXJUMBOADDR(sc, 0); 1469 rcb->ti_max_len = ETHER_MAX_LEN_JUMBO; 1470 rcb->ti_flags = 0; 1471 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1472 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1473 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 1474 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1475 if (VLAN_ATTACHED(&sc->ethercom)) 1476 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1477 1478 /* 1479 * Set up the mini ring. Only activated on the 1480 * Tigon 2 but the slot in the config block is 1481 * still there on the Tigon 1. 1482 */ 1483 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1484 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXMINIADDR(sc, 0); 1485 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1486 if (sc->ti_hwrev == TI_HWREV_TIGON) 1487 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1488 else 1489 rcb->ti_flags = 0; 1490 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1491 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1492 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx|IFCAP_CSUM_UDPv4_Rx)) 1493 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1494 if (VLAN_ATTACHED(&sc->ethercom)) 1495 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1496 1497 /* 1498 * Set up the receive return ring. 1499 */ 1500 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1501 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXRTNADDR(sc, 0); 1502 rcb->ti_flags = 0; 1503 rcb->ti_max_len = TI_RETURN_RING_CNT; 1504 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1505 TI_CDRTNPRODADDR(sc); 1506 1507 /* 1508 * Set up the tx ring. Note: for the Tigon 2, we have the option 1509 * of putting the transmit ring in the host's address space and 1510 * letting the chip DMA it instead of leaving the ring in the NIC's 1511 * memory and accessing it through the shared memory region. We 1512 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1513 * so we have to revert to the shared memory scheme if we detect 1514 * a Tigon 1 chip. 1515 */ 1516 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1517 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1518 sc->ti_tx_ring_nic = 1519 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1520 } 1521 memset((char *)sc->ti_rdata->ti_tx_ring, 0, 1522 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1523 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1524 if (sc->ti_hwrev == TI_HWREV_TIGON) 1525 rcb->ti_flags = 0; 1526 else 1527 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1528 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) 1529 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1530 /* 1531 * When we get the packet, there is a pseudo-header seed already 1532 * in the th_sum or uh_sum field. Make sure the firmware doesn't 1533 * compute the pseudo-header checksum again! 1534 */ 1535 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Tx|IFCAP_CSUM_UDPv4_Tx)) 1536 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM| 1537 TI_RCB_FLAG_NO_PHDR_CKSUM; 1538 if (VLAN_ATTACHED(&sc->ethercom)) 1539 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1540 rcb->ti_max_len = TI_TX_RING_CNT; 1541 if (sc->ti_hwrev == TI_HWREV_TIGON) 1542 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1543 else 1544 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDTXADDR(sc, 0); 1545 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1546 TI_CDTXCONSADDR(sc); 1547 1548 /* 1549 * We're done frobbing the General Information Block. Sync 1550 * it. Note we take care of the first stats sync here, as 1551 * well. 1552 */ 1553 TI_CDGIBSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1554 1555 /* Set up tuneables */ 1556 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN) || 1557 (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 1558 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1559 (sc->ti_rx_coal_ticks / 10)); 1560 else 1561 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1562 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1563 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1564 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1565 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1566 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1567 1568 /* Turn interrupts on. */ 1569 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1570 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1571 1572 /* Start CPU. */ 1573 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1574 1575 return (0); 1576 } 1577 1578 /* 1579 * look for id in the device list, returning the first match 1580 */ 1581 static const struct ti_type * 1582 ti_type_match(struct pci_attach_args *pa) 1583 { 1584 const struct ti_type *t; 1585 1586 t = ti_devs; 1587 while (t->ti_name != NULL) { 1588 if ((PCI_VENDOR(pa->pa_id) == t->ti_vid) && 1589 (PCI_PRODUCT(pa->pa_id) == t->ti_did)) { 1590 return (t); 1591 } 1592 t++; 1593 } 1594 1595 return (NULL); 1596 } 1597 1598 /* 1599 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1600 * against our list and return its name if we find a match. 1601 */ 1602 static int 1603 ti_probe(device_t parent, cfdata_t match, void *aux) 1604 { 1605 struct pci_attach_args *pa = aux; 1606 const struct ti_type *t; 1607 1608 t = ti_type_match(pa); 1609 1610 return ((t == NULL) ? 0 : 1); 1611 } 1612 1613 static void 1614 ti_attach(device_t parent, device_t self, void *aux) 1615 { 1616 u_int32_t command; 1617 struct ifnet *ifp; 1618 struct ti_softc *sc; 1619 u_int8_t eaddr[ETHER_ADDR_LEN]; 1620 struct pci_attach_args *pa = aux; 1621 pci_chipset_tag_t pc = pa->pa_pc; 1622 pci_intr_handle_t ih; 1623 const char *intrstr = NULL; 1624 bus_dma_segment_t dmaseg; 1625 int error, dmanseg, nolinear; 1626 const struct ti_type *t; 1627 1628 t = ti_type_match(pa); 1629 if (t == NULL) { 1630 printf("ti_attach: were did the card go ?\n"); 1631 return; 1632 } 1633 1634 printf(": %s (rev. 0x%02x)\n", t->ti_name, PCI_REVISION(pa->pa_class)); 1635 1636 sc = device_private(self); 1637 1638 /* 1639 * Map control/status registers. 1640 */ 1641 nolinear = 0; 1642 if (pci_mapreg_map(pa, 0x10, 1643 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1644 BUS_SPACE_MAP_LINEAR , &sc->ti_btag, &sc->ti_bhandle, 1645 NULL, NULL)) { 1646 nolinear = 1; 1647 if (pci_mapreg_map(pa, 0x10, 1648 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1649 0 , &sc->ti_btag, &sc->ti_bhandle, NULL, NULL)) { 1650 printf(": can't map memory space\n"); 1651 return; 1652 } 1653 } 1654 if (nolinear == 0) 1655 sc->ti_vhandle = bus_space_vaddr(sc->ti_btag, sc->ti_bhandle); 1656 else 1657 sc->ti_vhandle = NULL; 1658 1659 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1660 command |= PCI_COMMAND_MASTER_ENABLE; 1661 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1662 1663 /* Allocate interrupt */ 1664 if (pci_intr_map(pa, &ih)) { 1665 aprint_error_dev(&sc->sc_dev, "couldn't map interrupt\n"); 1666 return; 1667 } 1668 intrstr = pci_intr_string(pc, ih); 1669 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ti_intr, sc); 1670 if (sc->sc_ih == NULL) { 1671 aprint_error_dev(&sc->sc_dev, "couldn't establish interrupt"); 1672 if (intrstr != NULL) 1673 aprint_error(" at %s", intrstr); 1674 aprint_error("\n"); 1675 return; 1676 } 1677 aprint_normal_dev(&sc->sc_dev, "interrupting at %s\n", intrstr); 1678 1679 if (ti_chipinit(sc)) { 1680 aprint_error_dev(self, "chip initialization failed\n"); 1681 goto fail2; 1682 } 1683 1684 /* 1685 * Deal with some chip diffrences. 1686 */ 1687 switch (sc->ti_hwrev) { 1688 case TI_HWREV_TIGON: 1689 sc->sc_tx_encap = ti_encap_tigon1; 1690 sc->sc_tx_eof = ti_txeof_tigon1; 1691 if (nolinear == 1) 1692 aprint_error_dev(self, "memory space not mapped linear\n"); 1693 break; 1694 1695 case TI_HWREV_TIGON_II: 1696 sc->sc_tx_encap = ti_encap_tigon2; 1697 sc->sc_tx_eof = ti_txeof_tigon2; 1698 break; 1699 1700 default: 1701 printf("%s: Unknown chip version: %d\n", device_xname(self), 1702 sc->ti_hwrev); 1703 goto fail2; 1704 } 1705 1706 /* Zero out the NIC's on-board SRAM. */ 1707 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1708 1709 /* Init again -- zeroing memory may have clobbered some registers. */ 1710 if (ti_chipinit(sc)) { 1711 aprint_error_dev(self, "chip initialization failed\n"); 1712 goto fail2; 1713 } 1714 1715 /* 1716 * Get station address from the EEPROM. Note: the manual states 1717 * that the MAC address is at offset 0x8c, however the data is 1718 * stored as two longwords (since that's how it's loaded into 1719 * the NIC). This means the MAC address is actually preceded 1720 * by two zero bytes. We need to skip over those. 1721 */ 1722 if (ti_read_eeprom(sc, (void *)&eaddr, 1723 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1724 aprint_error_dev(self, "failed to read station address\n"); 1725 goto fail2; 1726 } 1727 1728 /* 1729 * A Tigon chip was detected. Inform the world. 1730 */ 1731 aprint_error_dev(self, "Ethernet address: %s\n", 1732 ether_sprintf(eaddr)); 1733 1734 sc->sc_dmat = pa->pa_dmat; 1735 1736 /* Allocate the general information block and ring buffers. */ 1737 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1738 sizeof(struct ti_ring_data), PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 1739 BUS_DMA_NOWAIT)) != 0) { 1740 aprint_error_dev(&sc->sc_dev, "can't allocate ring buffer, error = %d\n", 1741 error); 1742 goto fail2; 1743 } 1744 1745 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 1746 sizeof(struct ti_ring_data), (void **)&sc->ti_rdata, 1747 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1748 aprint_error_dev(&sc->sc_dev, "can't map ring buffer, error = %d\n", 1749 error); 1750 goto fail2; 1751 } 1752 1753 if ((error = bus_dmamap_create(sc->sc_dmat, 1754 sizeof(struct ti_ring_data), 1, 1755 sizeof(struct ti_ring_data), 0, BUS_DMA_NOWAIT, 1756 &sc->info_dmamap)) != 0) { 1757 aprint_error_dev(&sc->sc_dev, "can't create ring buffer DMA map, error = %d\n", 1758 error); 1759 goto fail2; 1760 } 1761 1762 if ((error = bus_dmamap_load(sc->sc_dmat, sc->info_dmamap, 1763 sc->ti_rdata, sizeof(struct ti_ring_data), NULL, 1764 BUS_DMA_NOWAIT)) != 0) { 1765 aprint_error_dev(&sc->sc_dev, "can't load ring buffer DMA map, error = %d\n", 1766 error); 1767 goto fail2; 1768 } 1769 1770 sc->info_dmaaddr = sc->info_dmamap->dm_segs[0].ds_addr; 1771 1772 memset(sc->ti_rdata, 0, sizeof(struct ti_ring_data)); 1773 1774 /* Try to allocate memory for jumbo buffers. */ 1775 if (ti_alloc_jumbo_mem(sc)) { 1776 aprint_error_dev(self, "jumbo buffer allocation failed\n"); 1777 goto fail2; 1778 } 1779 1780 SIMPLEQ_INIT(&sc->ti_mc_listhead); 1781 1782 /* 1783 * We really need a better way to tell a 1000baseT card 1784 * from a 1000baseSX one, since in theory there could be 1785 * OEMed 1000baseT cards from lame vendors who aren't 1786 * clever enough to change the PCI ID. For the moment 1787 * though, the AceNIC is the only copper card available. 1788 */ 1789 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALTEON && 1790 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALTEON_ACENIC_COPPER) || 1791 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NETGEAR && 1792 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NETGEAR_GA620T)) 1793 sc->ti_copper = 1; 1794 else 1795 sc->ti_copper = 0; 1796 1797 /* Set default tuneable values. */ 1798 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1799 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1800 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1801 sc->ti_rx_max_coal_bds = 64; 1802 sc->ti_tx_max_coal_bds = 128; 1803 sc->ti_tx_buf_ratio = 21; 1804 1805 /* Set up ifnet structure */ 1806 ifp = &sc->ethercom.ec_if; 1807 ifp->if_softc = sc; 1808 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 1809 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1810 ifp->if_ioctl = ti_ioctl; 1811 ifp->if_start = ti_start; 1812 ifp->if_watchdog = ti_watchdog; 1813 IFQ_SET_READY(&ifp->if_snd); 1814 1815 #if 0 1816 /* 1817 * XXX This is not really correct -- we don't necessarily 1818 * XXX want to queue up as many as we can transmit at the 1819 * XXX upper layer like that. Someone with a board should 1820 * XXX check to see how this affects performance. 1821 */ 1822 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1823 #endif 1824 1825 /* 1826 * We can support 802.1Q VLAN-sized frames. 1827 */ 1828 sc->ethercom.ec_capabilities |= 1829 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 1830 1831 /* 1832 * We can do IPv4, TCPv4, and UDPv4 checksums in hardware. 1833 */ 1834 ifp->if_capabilities |= 1835 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1836 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1837 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1838 1839 /* Set up ifmedia support. */ 1840 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1841 if (sc->ti_copper) { 1842 /* 1843 * Copper cards allow manual 10/100 mode selection, 1844 * but not manual 1000baseT mode selection. Why? 1845 * Because currently there's no way to specify the 1846 * master/slave setting through the firmware interface, 1847 * so Alteon decided to just bag it and handle it 1848 * via autonegotiation. 1849 */ 1850 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1851 ifmedia_add(&sc->ifmedia, 1852 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1853 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 1854 ifmedia_add(&sc->ifmedia, 1855 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 1856 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 1857 ifmedia_add(&sc->ifmedia, 1858 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 1859 } else { 1860 /* Fiber cards don't support 10/100 modes. */ 1861 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1862 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1863 } 1864 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1865 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1866 1867 /* 1868 * Call MI attach routines. 1869 */ 1870 if_attach(ifp); 1871 ether_ifattach(ifp, eaddr); 1872 1873 /* 1874 * Add shutdown hook so that DMA is disabled prior to reboot. Not 1875 * doing do could allow DMA to corrupt kernel memory during the 1876 * reboot before the driver initializes. 1877 */ 1878 if (pmf_device_register1(self, NULL, NULL, ti_shutdown)) 1879 pmf_class_network_register(self, ifp); 1880 else 1881 aprint_error_dev(self, "couldn't establish power handler\n"); 1882 1883 return; 1884 fail2: 1885 pci_intr_disestablish(pc, sc->sc_ih); 1886 return; 1887 } 1888 1889 /* 1890 * Frame reception handling. This is called if there's a frame 1891 * on the receive return list. 1892 * 1893 * Note: we have to be able to handle three possibilities here: 1894 * 1) the frame is from the mini receive ring (can only happen) 1895 * on Tigon 2 boards) 1896 * 2) the frame is from the jumbo receive ring 1897 * 3) the frame is from the standard receive ring 1898 */ 1899 1900 static void 1901 ti_rxeof(struct ti_softc *sc) 1902 { 1903 struct ifnet *ifp; 1904 struct ti_cmd_desc cmd; 1905 1906 ifp = &sc->ethercom.ec_if; 1907 1908 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1909 struct ti_rx_desc *cur_rx; 1910 u_int32_t rxidx; 1911 struct mbuf *m = NULL; 1912 struct ether_header *eh; 1913 bus_dmamap_t dmamap; 1914 1915 cur_rx = 1916 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1917 rxidx = cur_rx->ti_idx; 1918 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1919 1920 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1921 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1922 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1923 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1924 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1925 ifp->if_ierrors++; 1926 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1927 continue; 1928 } 1929 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) 1930 == ENOBUFS) { 1931 ifp->if_ierrors++; 1932 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1933 continue; 1934 } 1935 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1936 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1937 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1938 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1939 dmamap = sc->mini_dmamap[rxidx]; 1940 sc->mini_dmamap[rxidx] = 0; 1941 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1942 ifp->if_ierrors++; 1943 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1944 continue; 1945 } 1946 if (ti_newbuf_mini(sc, sc->ti_mini, NULL, dmamap) 1947 == ENOBUFS) { 1948 ifp->if_ierrors++; 1949 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1950 continue; 1951 } 1952 } else { 1953 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1954 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1955 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1956 dmamap = sc->std_dmamap[rxidx]; 1957 sc->std_dmamap[rxidx] = 0; 1958 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1959 ifp->if_ierrors++; 1960 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 1961 continue; 1962 } 1963 if (ti_newbuf_std(sc, sc->ti_std, NULL, dmamap) 1964 == ENOBUFS) { 1965 ifp->if_ierrors++; 1966 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 1967 continue; 1968 } 1969 } 1970 1971 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 1972 ifp->if_ipackets++; 1973 m->m_pkthdr.rcvif = ifp; 1974 1975 /* 1976 * Handle BPF listeners. Let the BPF user see the packet, but 1977 * don't pass it up to the ether_input() layer unless it's 1978 * a broadcast packet, multicast packet, matches our ethernet 1979 * address or the interface is in promiscuous mode. 1980 */ 1981 if (ifp->if_bpf) 1982 bpf_ops->bpf_mtap(ifp->if_bpf, m); 1983 1984 eh = mtod(m, struct ether_header *); 1985 switch (ntohs(eh->ether_type)) { 1986 #ifdef INET 1987 case ETHERTYPE_IP: 1988 { 1989 struct ip *ip = (struct ip *) (eh + 1); 1990 1991 /* 1992 * Note the Tigon firmware does not invert 1993 * the checksum for us, hence the XOR. 1994 */ 1995 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1996 if ((cur_rx->ti_ip_cksum ^ 0xffff) != 0) 1997 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1998 /* 1999 * ntohs() the constant so the compiler can 2000 * optimize... 2001 * 2002 * XXX Figure out a sane way to deal with 2003 * fragmented packets. 2004 */ 2005 if ((ip->ip_off & htons(IP_MF|IP_OFFMASK)) == 0) { 2006 switch (ip->ip_p) { 2007 case IPPROTO_TCP: 2008 m->m_pkthdr.csum_data = 2009 cur_rx->ti_tcp_udp_cksum; 2010 m->m_pkthdr.csum_flags |= 2011 M_CSUM_TCPv4|M_CSUM_DATA; 2012 break; 2013 case IPPROTO_UDP: 2014 m->m_pkthdr.csum_data = 2015 cur_rx->ti_tcp_udp_cksum; 2016 m->m_pkthdr.csum_flags |= 2017 M_CSUM_UDPv4|M_CSUM_DATA; 2018 break; 2019 default: 2020 /* Nothing */; 2021 } 2022 } 2023 break; 2024 } 2025 #endif 2026 default: 2027 /* Nothing. */ 2028 break; 2029 } 2030 2031 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 2032 VLAN_INPUT_TAG(ifp, m, 2033 /* ti_vlan_tag also has the priority, trim it */ 2034 cur_rx->ti_vlan_tag & 4095, 2035 continue); 2036 } 2037 2038 (*ifp->if_input)(ifp, m); 2039 } 2040 2041 /* Only necessary on the Tigon 1. */ 2042 if (sc->ti_hwrev == TI_HWREV_TIGON) 2043 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2044 sc->ti_rx_saved_considx); 2045 2046 TI_UPDATE_STDPROD(sc, sc->ti_std); 2047 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2048 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2049 } 2050 2051 static void 2052 ti_txeof_tigon1(struct ti_softc *sc) 2053 { 2054 struct ti_tx_desc *cur_tx = NULL; 2055 struct ifnet *ifp; 2056 struct txdmamap_pool_entry *dma; 2057 2058 ifp = &sc->ethercom.ec_if; 2059 2060 /* 2061 * Go through our tx ring and free mbufs for those 2062 * frames that have been sent. 2063 */ 2064 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2065 u_int32_t idx = 0; 2066 2067 idx = sc->ti_tx_saved_considx; 2068 if (idx > 383) 2069 CSR_WRITE_4(sc, TI_WINBASE, 2070 TI_TX_RING_BASE + 6144); 2071 else if (idx > 255) 2072 CSR_WRITE_4(sc, TI_WINBASE, 2073 TI_TX_RING_BASE + 4096); 2074 else if (idx > 127) 2075 CSR_WRITE_4(sc, TI_WINBASE, 2076 TI_TX_RING_BASE + 2048); 2077 else 2078 CSR_WRITE_4(sc, TI_WINBASE, 2079 TI_TX_RING_BASE); 2080 cur_tx = &sc->ti_tx_ring_nic[idx % 128]; 2081 if (cur_tx->ti_flags & TI_BDFLAG_END) 2082 ifp->if_opackets++; 2083 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2084 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2085 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2086 2087 dma = sc->txdma[idx]; 2088 KDASSERT(dma != NULL); 2089 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2090 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2091 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2092 2093 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2094 sc->txdma[idx] = NULL; 2095 } 2096 sc->ti_txcnt--; 2097 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2098 ifp->if_timer = 0; 2099 } 2100 2101 if (cur_tx != NULL) 2102 ifp->if_flags &= ~IFF_OACTIVE; 2103 } 2104 2105 static void 2106 ti_txeof_tigon2(struct ti_softc *sc) 2107 { 2108 struct ti_tx_desc *cur_tx = NULL; 2109 struct ifnet *ifp; 2110 struct txdmamap_pool_entry *dma; 2111 int firstidx, cnt; 2112 2113 ifp = &sc->ethercom.ec_if; 2114 2115 /* 2116 * Go through our tx ring and free mbufs for those 2117 * frames that have been sent. 2118 */ 2119 firstidx = sc->ti_tx_saved_considx; 2120 cnt = 0; 2121 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2122 u_int32_t idx = 0; 2123 2124 idx = sc->ti_tx_saved_considx; 2125 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2126 if (cur_tx->ti_flags & TI_BDFLAG_END) 2127 ifp->if_opackets++; 2128 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2129 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2130 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2131 2132 dma = sc->txdma[idx]; 2133 KDASSERT(dma != NULL); 2134 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2135 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2136 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2137 2138 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2139 sc->txdma[idx] = NULL; 2140 } 2141 cnt++; 2142 sc->ti_txcnt--; 2143 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2144 ifp->if_timer = 0; 2145 } 2146 2147 if (cnt != 0) 2148 TI_CDTXSYNC(sc, firstidx, cnt, BUS_DMASYNC_POSTWRITE); 2149 2150 if (cur_tx != NULL) 2151 ifp->if_flags &= ~IFF_OACTIVE; 2152 } 2153 2154 static int 2155 ti_intr(void *xsc) 2156 { 2157 struct ti_softc *sc; 2158 struct ifnet *ifp; 2159 2160 sc = xsc; 2161 ifp = &sc->ethercom.ec_if; 2162 2163 #ifdef notdef 2164 /* Avoid this for now -- checking this register is expensive. */ 2165 /* Make sure this is really our interrupt. */ 2166 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 2167 return (0); 2168 #endif 2169 2170 /* Ack interrupt and stop others from occuring. */ 2171 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2172 2173 if (ifp->if_flags & IFF_RUNNING) { 2174 /* Check RX return ring producer/consumer */ 2175 ti_rxeof(sc); 2176 2177 /* Check TX ring producer/consumer */ 2178 (*sc->sc_tx_eof)(sc); 2179 } 2180 2181 ti_handle_events(sc); 2182 2183 /* Re-enable interrupts. */ 2184 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2185 2186 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2187 IFQ_IS_EMPTY(&ifp->if_snd) == 0) 2188 ti_start(ifp); 2189 2190 return (1); 2191 } 2192 2193 static void 2194 ti_stats_update(struct ti_softc *sc) 2195 { 2196 struct ifnet *ifp; 2197 2198 ifp = &sc->ethercom.ec_if; 2199 2200 TI_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 2201 2202 ifp->if_collisions += 2203 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2204 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2205 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2206 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2207 ifp->if_collisions; 2208 2209 TI_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 2210 } 2211 2212 /* 2213 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2214 * pointers to descriptors. 2215 */ 2216 static int 2217 ti_encap_tigon1(struct ti_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 2218 { 2219 struct ti_tx_desc *f = NULL; 2220 u_int32_t frag, cur, cnt = 0; 2221 struct txdmamap_pool_entry *dma; 2222 bus_dmamap_t dmamap; 2223 int error, i; 2224 struct m_tag *mtag; 2225 u_int16_t csum_flags = 0; 2226 2227 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2228 if (dma == NULL) { 2229 return ENOMEM; 2230 } 2231 dmamap = dma->dmamap; 2232 2233 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2234 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2235 if (error) { 2236 struct mbuf *m; 2237 int j = 0; 2238 for (m = m_head; m; m = m->m_next) 2239 j++; 2240 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2241 "error %d\n", m_head->m_pkthdr.len, j, error); 2242 return (ENOMEM); 2243 } 2244 2245 cur = frag = *txidx; 2246 2247 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2248 /* IP header checksum field must be 0! */ 2249 csum_flags |= TI_BDFLAG_IP_CKSUM; 2250 } 2251 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2252 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2253 2254 /* XXX fragmented packet checksum capability? */ 2255 2256 /* 2257 * Start packing the mbufs in this chain into 2258 * the fragment pointers. Stop when we run out 2259 * of fragments or hit the end of the mbuf chain. 2260 */ 2261 for (i = 0; i < dmamap->dm_nsegs; i++) { 2262 if (frag > 383) 2263 CSR_WRITE_4(sc, TI_WINBASE, 2264 TI_TX_RING_BASE + 6144); 2265 else if (frag > 255) 2266 CSR_WRITE_4(sc, TI_WINBASE, 2267 TI_TX_RING_BASE + 4096); 2268 else if (frag > 127) 2269 CSR_WRITE_4(sc, TI_WINBASE, 2270 TI_TX_RING_BASE + 2048); 2271 else 2272 CSR_WRITE_4(sc, TI_WINBASE, 2273 TI_TX_RING_BASE); 2274 f = &sc->ti_tx_ring_nic[frag % 128]; 2275 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2276 break; 2277 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2278 f->ti_len = dmamap->dm_segs[i].ds_len; 2279 f->ti_flags = csum_flags; 2280 if ((mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m_head))) { 2281 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2282 f->ti_vlan_tag = VLAN_TAG_VALUE(mtag); 2283 } else { 2284 f->ti_vlan_tag = 0; 2285 } 2286 /* 2287 * Sanity check: avoid coming within 16 descriptors 2288 * of the end of the ring. 2289 */ 2290 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2291 return (ENOBUFS); 2292 cur = frag; 2293 TI_INC(frag, TI_TX_RING_CNT); 2294 cnt++; 2295 } 2296 2297 if (i < dmamap->dm_nsegs) 2298 return (ENOBUFS); 2299 2300 if (frag == sc->ti_tx_saved_considx) 2301 return (ENOBUFS); 2302 2303 sc->ti_tx_ring_nic[cur % 128].ti_flags |= 2304 TI_BDFLAG_END; 2305 2306 /* Sync the packet's DMA map. */ 2307 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2308 BUS_DMASYNC_PREWRITE); 2309 2310 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2311 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 2312 sc->txdma[cur] = dma; 2313 sc->ti_txcnt += cnt; 2314 2315 *txidx = frag; 2316 2317 return (0); 2318 } 2319 2320 static int 2321 ti_encap_tigon2(struct ti_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 2322 { 2323 struct ti_tx_desc *f = NULL; 2324 u_int32_t frag, firstfrag, cur, cnt = 0; 2325 struct txdmamap_pool_entry *dma; 2326 bus_dmamap_t dmamap; 2327 int error, i; 2328 struct m_tag *mtag; 2329 u_int16_t csum_flags = 0; 2330 2331 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2332 if (dma == NULL) { 2333 return ENOMEM; 2334 } 2335 dmamap = dma->dmamap; 2336 2337 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2338 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2339 if (error) { 2340 struct mbuf *m; 2341 int j = 0; 2342 for (m = m_head; m; m = m->m_next) 2343 j++; 2344 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2345 "error %d\n", m_head->m_pkthdr.len, j, error); 2346 return (ENOMEM); 2347 } 2348 2349 cur = firstfrag = frag = *txidx; 2350 2351 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2352 /* IP header checksum field must be 0! */ 2353 csum_flags |= TI_BDFLAG_IP_CKSUM; 2354 } 2355 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2356 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2357 2358 /* XXX fragmented packet checksum capability? */ 2359 2360 /* 2361 * Start packing the mbufs in this chain into 2362 * the fragment pointers. Stop when we run out 2363 * of fragments or hit the end of the mbuf chain. 2364 */ 2365 for (i = 0; i < dmamap->dm_nsegs; i++) { 2366 f = &sc->ti_rdata->ti_tx_ring[frag]; 2367 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2368 break; 2369 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2370 f->ti_len = dmamap->dm_segs[i].ds_len; 2371 f->ti_flags = csum_flags; 2372 if ((mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m_head))) { 2373 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2374 f->ti_vlan_tag = VLAN_TAG_VALUE(mtag); 2375 } else { 2376 f->ti_vlan_tag = 0; 2377 } 2378 /* 2379 * Sanity check: avoid coming within 16 descriptors 2380 * of the end of the ring. 2381 */ 2382 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2383 return (ENOBUFS); 2384 cur = frag; 2385 TI_INC(frag, TI_TX_RING_CNT); 2386 cnt++; 2387 } 2388 2389 if (i < dmamap->dm_nsegs) 2390 return (ENOBUFS); 2391 2392 if (frag == sc->ti_tx_saved_considx) 2393 return (ENOBUFS); 2394 2395 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2396 2397 /* Sync the packet's DMA map. */ 2398 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2399 BUS_DMASYNC_PREWRITE); 2400 2401 /* Sync the descriptors we are using. */ 2402 TI_CDTXSYNC(sc, firstfrag, cnt, BUS_DMASYNC_PREWRITE); 2403 2404 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2405 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 2406 sc->txdma[cur] = dma; 2407 sc->ti_txcnt += cnt; 2408 2409 *txidx = frag; 2410 2411 return (0); 2412 } 2413 2414 /* 2415 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2416 * to the mbuf data regions directly in the transmit descriptors. 2417 */ 2418 static void 2419 ti_start(struct ifnet *ifp) 2420 { 2421 struct ti_softc *sc; 2422 struct mbuf *m_head = NULL; 2423 u_int32_t prodidx = 0; 2424 2425 sc = ifp->if_softc; 2426 2427 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2428 2429 while (sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2430 IFQ_POLL(&ifp->if_snd, m_head); 2431 if (m_head == NULL) 2432 break; 2433 2434 /* 2435 * Pack the data into the transmit ring. If we 2436 * don't have room, set the OACTIVE flag and wait 2437 * for the NIC to drain the ring. 2438 */ 2439 if ((*sc->sc_tx_encap)(sc, m_head, &prodidx)) { 2440 ifp->if_flags |= IFF_OACTIVE; 2441 break; 2442 } 2443 2444 IFQ_DEQUEUE(&ifp->if_snd, m_head); 2445 2446 /* 2447 * If there's a BPF listener, bounce a copy of this frame 2448 * to him. 2449 */ 2450 if (ifp->if_bpf) 2451 bpf_ops->bpf_mtap(ifp->if_bpf, m_head); 2452 } 2453 2454 /* Transmit */ 2455 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2456 2457 /* 2458 * Set a timeout in case the chip goes out to lunch. 2459 */ 2460 ifp->if_timer = 5; 2461 } 2462 2463 static void 2464 ti_init(void *xsc) 2465 { 2466 struct ti_softc *sc = xsc; 2467 int s; 2468 2469 s = splnet(); 2470 2471 /* Cancel pending I/O and flush buffers. */ 2472 ti_stop(sc); 2473 2474 /* Init the gen info block, ring control blocks and firmware. */ 2475 if (ti_gibinit(sc)) { 2476 aprint_error_dev(&sc->sc_dev, "initialization failure\n"); 2477 splx(s); 2478 return; 2479 } 2480 2481 splx(s); 2482 } 2483 2484 static void 2485 ti_init2(struct ti_softc *sc) 2486 { 2487 struct ti_cmd_desc cmd; 2488 struct ifnet *ifp; 2489 const u_int8_t *m; 2490 struct ifmedia *ifm; 2491 int tmp; 2492 2493 ifp = &sc->ethercom.ec_if; 2494 2495 /* Specify MTU and interface index. */ 2496 CSR_WRITE_4(sc, TI_GCR_IFINDEX, device_unit(&sc->sc_dev)); /* ??? */ 2497 2498 tmp = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 2499 if (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2500 tmp += ETHER_VLAN_ENCAP_LEN; 2501 CSR_WRITE_4(sc, TI_GCR_IFMTU, tmp); 2502 2503 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2504 2505 /* Load our MAC address. */ 2506 m = (const u_int8_t *)CLLADDR(ifp->if_sadl); 2507 CSR_WRITE_4(sc, TI_GCR_PAR0, (m[0] << 8) | m[1]); 2508 CSR_WRITE_4(sc, TI_GCR_PAR1, (m[2] << 24) | (m[3] << 16) 2509 | (m[4] << 8) | m[5]); 2510 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2511 2512 /* Enable or disable promiscuous mode as needed. */ 2513 if (ifp->if_flags & IFF_PROMISC) { 2514 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2515 } else { 2516 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2517 } 2518 2519 /* Program multicast filter. */ 2520 ti_setmulti(sc); 2521 2522 /* 2523 * If this is a Tigon 1, we should tell the 2524 * firmware to use software packet filtering. 2525 */ 2526 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2527 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2528 } 2529 2530 /* Init RX ring. */ 2531 ti_init_rx_ring_std(sc); 2532 2533 /* Init jumbo RX ring. */ 2534 if (ifp->if_mtu > (MCLBYTES - ETHER_HDR_LEN - ETHER_CRC_LEN)) 2535 ti_init_rx_ring_jumbo(sc); 2536 2537 /* 2538 * If this is a Tigon 2, we can also configure the 2539 * mini ring. 2540 */ 2541 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2542 ti_init_rx_ring_mini(sc); 2543 2544 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2545 sc->ti_rx_saved_considx = 0; 2546 2547 /* Init TX ring. */ 2548 ti_init_tx_ring(sc); 2549 2550 /* Tell firmware we're alive. */ 2551 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2552 2553 /* Enable host interrupts. */ 2554 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2555 2556 ifp->if_flags |= IFF_RUNNING; 2557 ifp->if_flags &= ~IFF_OACTIVE; 2558 2559 /* 2560 * Make sure to set media properly. We have to do this 2561 * here since we have to issue commands in order to set 2562 * the link negotiation and we can't issue commands until 2563 * the firmware is running. 2564 */ 2565 ifm = &sc->ifmedia; 2566 tmp = ifm->ifm_media; 2567 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2568 ti_ifmedia_upd(ifp); 2569 ifm->ifm_media = tmp; 2570 } 2571 2572 /* 2573 * Set media options. 2574 */ 2575 static int 2576 ti_ifmedia_upd(struct ifnet *ifp) 2577 { 2578 struct ti_softc *sc; 2579 struct ifmedia *ifm; 2580 struct ti_cmd_desc cmd; 2581 2582 sc = ifp->if_softc; 2583 ifm = &sc->ifmedia; 2584 2585 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2586 return (EINVAL); 2587 2588 switch (IFM_SUBTYPE(ifm->ifm_media)) { 2589 case IFM_AUTO: 2590 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2591 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 2592 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2593 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2594 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 2595 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2596 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2597 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2598 break; 2599 case IFM_1000_SX: 2600 case IFM_1000_T: 2601 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2602 CSR_WRITE_4(sc, TI_GCR_GLINK, 2603 TI_GLNK_PREF|TI_GLNK_1000MB|TI_GLNK_FULL_DUPLEX| 2604 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2605 } else { 2606 CSR_WRITE_4(sc, TI_GCR_GLINK, 2607 TI_GLNK_PREF|TI_GLNK_1000MB| 2608 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2609 } 2610 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2611 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2612 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2613 break; 2614 case IFM_100_FX: 2615 case IFM_10_FL: 2616 case IFM_100_TX: 2617 case IFM_10_T: 2618 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2619 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 2620 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2621 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 2622 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2623 } else { 2624 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2625 } 2626 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2627 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2628 } else { 2629 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2630 } 2631 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2632 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2633 break; 2634 } 2635 2636 sc->ethercom.ec_if.if_baudrate = 2637 ifmedia_baudrate(ifm->ifm_media); 2638 2639 return (0); 2640 } 2641 2642 /* 2643 * Report current media status. 2644 */ 2645 static void 2646 ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2647 { 2648 struct ti_softc *sc; 2649 u_int32_t media = 0; 2650 2651 sc = ifp->if_softc; 2652 2653 ifmr->ifm_status = IFM_AVALID; 2654 ifmr->ifm_active = IFM_ETHER; 2655 2656 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2657 return; 2658 2659 ifmr->ifm_status |= IFM_ACTIVE; 2660 2661 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2662 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2663 if (sc->ti_copper) 2664 ifmr->ifm_active |= IFM_1000_T; 2665 else 2666 ifmr->ifm_active |= IFM_1000_SX; 2667 if (media & TI_GLNK_FULL_DUPLEX) 2668 ifmr->ifm_active |= IFM_FDX; 2669 else 2670 ifmr->ifm_active |= IFM_HDX; 2671 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2672 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2673 if (sc->ti_copper) { 2674 if (media & TI_LNK_100MB) 2675 ifmr->ifm_active |= IFM_100_TX; 2676 if (media & TI_LNK_10MB) 2677 ifmr->ifm_active |= IFM_10_T; 2678 } else { 2679 if (media & TI_LNK_100MB) 2680 ifmr->ifm_active |= IFM_100_FX; 2681 if (media & TI_LNK_10MB) 2682 ifmr->ifm_active |= IFM_10_FL; 2683 } 2684 if (media & TI_LNK_FULL_DUPLEX) 2685 ifmr->ifm_active |= IFM_FDX; 2686 if (media & TI_LNK_HALF_DUPLEX) 2687 ifmr->ifm_active |= IFM_HDX; 2688 } 2689 2690 sc->ethercom.ec_if.if_baudrate = 2691 ifmedia_baudrate(sc->ifmedia.ifm_media); 2692 } 2693 2694 static int 2695 ti_ether_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2696 { 2697 struct ifaddr *ifa = (struct ifaddr *) data; 2698 struct ti_softc *sc = ifp->if_softc; 2699 2700 if ((ifp->if_flags & IFF_UP) == 0) { 2701 ifp->if_flags |= IFF_UP; 2702 ti_init(sc); 2703 } 2704 2705 switch (cmd) { 2706 case SIOCINITIFADDR: 2707 2708 switch (ifa->ifa_addr->sa_family) { 2709 #ifdef INET 2710 case AF_INET: 2711 arp_ifinit(ifp, ifa); 2712 break; 2713 #endif 2714 default: 2715 break; 2716 } 2717 break; 2718 2719 default: 2720 return (EINVAL); 2721 } 2722 2723 return (0); 2724 } 2725 2726 static int 2727 ti_ioctl(struct ifnet *ifp, u_long command, void *data) 2728 { 2729 struct ti_softc *sc = ifp->if_softc; 2730 struct ifreq *ifr = (struct ifreq *) data; 2731 int s, error = 0; 2732 struct ti_cmd_desc cmd; 2733 2734 s = splnet(); 2735 2736 switch (command) { 2737 case SIOCINITIFADDR: 2738 error = ti_ether_ioctl(ifp, command, data); 2739 break; 2740 case SIOCSIFMTU: 2741 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU_JUMBO) 2742 error = EINVAL; 2743 else if ((error = ifioctl_common(ifp, command, data)) == ENETRESET){ 2744 ti_init(sc); 2745 error = 0; 2746 } 2747 break; 2748 case SIOCSIFFLAGS: 2749 if ((error = ifioctl_common(ifp, command, data)) != 0) 2750 break; 2751 if (ifp->if_flags & IFF_UP) { 2752 /* 2753 * If only the state of the PROMISC flag changed, 2754 * then just use the 'set promisc mode' command 2755 * instead of reinitializing the entire NIC. Doing 2756 * a full re-init means reloading the firmware and 2757 * waiting for it to start up, which may take a 2758 * second or two. 2759 */ 2760 if (ifp->if_flags & IFF_RUNNING && 2761 ifp->if_flags & IFF_PROMISC && 2762 !(sc->ti_if_flags & IFF_PROMISC)) { 2763 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2764 TI_CMD_CODE_PROMISC_ENB, 0); 2765 } else if (ifp->if_flags & IFF_RUNNING && 2766 !(ifp->if_flags & IFF_PROMISC) && 2767 sc->ti_if_flags & IFF_PROMISC) { 2768 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2769 TI_CMD_CODE_PROMISC_DIS, 0); 2770 } else 2771 ti_init(sc); 2772 } else { 2773 if (ifp->if_flags & IFF_RUNNING) { 2774 ti_stop(sc); 2775 } 2776 } 2777 sc->ti_if_flags = ifp->if_flags; 2778 error = 0; 2779 break; 2780 case SIOCSIFMEDIA: 2781 case SIOCGIFMEDIA: 2782 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2783 break; 2784 default: 2785 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 2786 break; 2787 2788 error = 0; 2789 2790 if (command == SIOCSIFCAP) 2791 ti_init(sc); 2792 else if (command != SIOCADDMULTI && command != SIOCDELMULTI) 2793 ; 2794 else if (ifp->if_flags & IFF_RUNNING) 2795 ti_setmulti(sc); 2796 break; 2797 } 2798 2799 (void)splx(s); 2800 2801 return (error); 2802 } 2803 2804 static void 2805 ti_watchdog(struct ifnet *ifp) 2806 { 2807 struct ti_softc *sc; 2808 2809 sc = ifp->if_softc; 2810 2811 aprint_error_dev(&sc->sc_dev, "watchdog timeout -- resetting\n"); 2812 ti_stop(sc); 2813 ti_init(sc); 2814 2815 ifp->if_oerrors++; 2816 } 2817 2818 /* 2819 * Stop the adapter and free any mbufs allocated to the 2820 * RX and TX lists. 2821 */ 2822 static void 2823 ti_stop(struct ti_softc *sc) 2824 { 2825 struct ifnet *ifp; 2826 struct ti_cmd_desc cmd; 2827 2828 ifp = &sc->ethercom.ec_if; 2829 2830 /* Disable host interrupts. */ 2831 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2832 /* 2833 * Tell firmware we're shutting down. 2834 */ 2835 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2836 2837 /* Halt and reinitialize. */ 2838 ti_chipinit(sc); 2839 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2840 ti_chipinit(sc); 2841 2842 /* Free the RX lists. */ 2843 ti_free_rx_ring_std(sc); 2844 2845 /* Free jumbo RX list. */ 2846 ti_free_rx_ring_jumbo(sc); 2847 2848 /* Free mini RX list. */ 2849 ti_free_rx_ring_mini(sc); 2850 2851 /* Free TX buffers. */ 2852 ti_free_tx_ring(sc); 2853 2854 sc->ti_ev_prodidx.ti_idx = 0; 2855 sc->ti_return_prodidx.ti_idx = 0; 2856 sc->ti_tx_considx.ti_idx = 0; 2857 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2858 2859 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2860 } 2861 2862 /* 2863 * Stop all chip I/O so that the kernel's probe routines don't 2864 * get confused by errant DMAs when rebooting. 2865 */ 2866 static bool 2867 ti_shutdown(device_t self, int howto) 2868 { 2869 struct ti_softc *sc; 2870 2871 sc = device_private(self); 2872 ti_chipinit(sc); 2873 2874 return true; 2875 } 2876