1 /* $NetBSD: if_ti.c,v 1.120 2020/03/05 15:45:48 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_ti.c,v 1.15 1999/08/14 15:45:03 wpaul Exp 35 */ 36 37 /* 38 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 39 * Manuals, sample driver and firmware source kits are available 40 * from http://www.alteon.com/support/openkits. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 49 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 50 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 51 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 52 * filtering and jumbo (9014 byte) frames. The hardware is largely 53 * controlled by firmware, which must be loaded into the NIC during 54 * initialization. 55 * 56 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 57 * revision, which supports new features such as extended commands, 58 * extended jumbo receive ring desciptors and a mini receive ring. 59 * 60 * Alteon Networks is to be commended for releasing such a vast amount 61 * of development material for the Tigon NIC without requiring an NDA 62 * (although they really should have done it a long time ago). With 63 * any luck, the other vendors will finally wise up and follow Alteon's 64 * stellar example. 65 * 66 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 67 * this driver by #including it as a C header file. This bloats the 68 * driver somewhat, but it's the easiest method considering that the 69 * driver code and firmware code need to be kept in sync. The source 70 * for the firmware is not provided with the FreeBSD distribution since 71 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 72 * 73 * The following people deserve special thanks: 74 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 75 * for testing 76 * - Raymond Lee of Netgear, for providing a pair of Netgear 77 * GA620 Tigon 2 boards for testing 78 * - Ulf Zimmermann, for bringing the GA620 to my attention and 79 * convincing me to write this driver. 80 * - Andrew Gallatin for providing FreeBSD/Alpha support. 81 */ 82 83 #include <sys/cdefs.h> 84 __KERNEL_RCSID(0, "$NetBSD: if_ti.c,v 1.120 2020/03/05 15:45:48 msaitoh Exp $"); 85 86 #include "opt_inet.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/queue.h> 96 #include <sys/device.h> 97 #include <sys/reboot.h> 98 99 #include <net/if.h> 100 #include <net/if_arp.h> 101 #include <net/if_ether.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 105 #include <net/bpf.h> 106 107 #ifdef INET 108 #include <netinet/in.h> 109 #include <netinet/if_inarp.h> 110 #include <netinet/in_systm.h> 111 #include <netinet/ip.h> 112 #endif 113 114 115 #include <sys/bus.h> 116 117 #include <dev/pci/pcireg.h> 118 #include <dev/pci/pcivar.h> 119 #include <dev/pci/pcidevs.h> 120 121 #include <dev/pci/if_tireg.h> 122 123 #include <dev/microcode/tigon/ti_fw.h> 124 #include <dev/microcode/tigon/ti_fw2.h> 125 126 #define TI_HOSTADDR(x, y) \ 127 do { \ 128 (x).ti_addr_lo = (uint32_t)(y); \ 129 if (sizeof(bus_addr_t) == 8) \ 130 (x).ti_addr_hi = \ 131 (uint32_t)(((uint64_t)(y) >> 32)); \ 132 else \ 133 (x).ti_addr_hi = 0; \ 134 } while (/*CONSTCOND*/0) 135 136 /* 137 * Various supported device vendors/types and their names. 138 */ 139 140 static const struct ti_type ti_devs[] = { 141 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC, 142 "Alteon AceNIC 1000BASE-SX Ethernet" }, 143 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC_COPPER, 144 "Alteon AceNIC 1000BASE-T Ethernet" }, 145 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C985, 146 "3Com 3c985-SX Gigabit Ethernet" }, 147 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620, 148 "Netgear GA620 1000BASE-SX Ethernet" }, 149 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620T, 150 "Netgear GA620 1000BASE-T Ethernet" }, 151 { PCI_VENDOR_SGI, PCI_PRODUCT_SGI_TIGON, 152 "Silicon Graphics Gigabit Ethernet" }, 153 { PCI_VENDOR_DEC, PCI_PRODUCT_DEC_PN9000SX, 154 "Farallon PN9000SX Gigabit Ethernet" }, 155 { 0, 0, NULL } 156 }; 157 158 static const struct ti_type *ti_type_match(struct pci_attach_args *); 159 static int ti_probe(device_t, cfdata_t, void *); 160 static void ti_attach(device_t, device_t, void *); 161 static bool ti_shutdown(device_t, int); 162 static void ti_txeof_tigon1(struct ti_softc *); 163 static void ti_txeof_tigon2(struct ti_softc *); 164 static void ti_rxeof(struct ti_softc *); 165 166 static void ti_stats_update(struct ti_softc *); 167 static int ti_encap_tigon1(struct ti_softc *, struct mbuf *, uint32_t *); 168 static int ti_encap_tigon2(struct ti_softc *, struct mbuf *, uint32_t *); 169 170 static int ti_intr(void *); 171 static void ti_start(struct ifnet *); 172 static int ti_ioctl(struct ifnet *, u_long, void *); 173 static void ti_init(void *); 174 static void ti_init2(struct ti_softc *); 175 static void ti_stop(struct ti_softc *); 176 static void ti_watchdog(struct ifnet *); 177 static int ti_ifmedia_upd(struct ifnet *); 178 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 179 180 static uint32_t ti_eeprom_putbyte(struct ti_softc *, int); 181 static uint8_t ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *); 182 static int ti_read_eeprom(struct ti_softc *, void *, int, int); 183 184 static void ti_add_mcast(struct ti_softc *, struct ether_addr *); 185 static void ti_del_mcast(struct ti_softc *, struct ether_addr *); 186 static void ti_setmulti(struct ti_softc *); 187 188 static void ti_mem(struct ti_softc *, uint32_t, uint32_t, const void *); 189 static void ti_loadfw(struct ti_softc *); 190 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 191 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, void *, int); 192 static void ti_handle_events(struct ti_softc *); 193 static int ti_alloc_jumbo_mem(struct ti_softc *); 194 static void *ti_jalloc(struct ti_softc *); 195 static void ti_jfree(struct mbuf *, void *, size_t, void *); 196 static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *, bus_dmamap_t); 197 static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *, bus_dmamap_t); 198 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 199 static int ti_init_rx_ring_std(struct ti_softc *); 200 static void ti_free_rx_ring_std(struct ti_softc *); 201 static int ti_init_rx_ring_jumbo(struct ti_softc *); 202 static void ti_free_rx_ring_jumbo(struct ti_softc *); 203 static int ti_init_rx_ring_mini(struct ti_softc *); 204 static void ti_free_rx_ring_mini(struct ti_softc *); 205 static void ti_free_tx_ring(struct ti_softc *); 206 static int ti_init_tx_ring(struct ti_softc *); 207 208 static int ti_64bitslot_war(struct ti_softc *); 209 static int ti_chipinit(struct ti_softc *); 210 static int ti_gibinit(struct ti_softc *); 211 212 static int ti_ether_ioctl(struct ifnet *, u_long, void *); 213 214 CFATTACH_DECL_NEW(ti, sizeof(struct ti_softc), 215 ti_probe, ti_attach, NULL, NULL); 216 217 /* 218 * Send an instruction or address to the EEPROM, check for ACK. 219 */ 220 static uint32_t 221 ti_eeprom_putbyte(struct ti_softc *sc, int byte) 222 { 223 int i, ack = 0; 224 225 /* 226 * Make sure we're in TX mode. 227 */ 228 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 229 230 /* 231 * Feed in each bit and strobe the clock. 232 */ 233 for (i = 0x80; i; i >>= 1) { 234 if (byte & i) { 235 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 236 } else { 237 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 238 } 239 DELAY(1); 240 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 241 DELAY(1); 242 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 243 } 244 245 /* 246 * Turn off TX mode. 247 */ 248 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 249 250 /* 251 * Check for ack. 252 */ 253 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 254 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 255 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 256 257 return (ack); 258 } 259 260 /* 261 * Read a byte of data stored in the EEPROM at address 'addr.' 262 * We have to send two address bytes since the EEPROM can hold 263 * more than 256 bytes of data. 264 */ 265 static uint8_t 266 ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest) 267 { 268 int i; 269 uint8_t byte = 0; 270 271 EEPROM_START(); 272 273 /* 274 * Send write control code to EEPROM. 275 */ 276 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 277 printf("%s: failed to send write command, status: %x\n", 278 device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 279 return (1); 280 } 281 282 /* 283 * Send first byte of address of byte we want to read. 284 */ 285 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 286 printf("%s: failed to send address, status: %x\n", 287 device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 288 return (1); 289 } 290 /* 291 * Send second byte address of byte we want to read. 292 */ 293 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 294 printf("%s: failed to send address, status: %x\n", 295 device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 296 return (1); 297 } 298 299 EEPROM_STOP(); 300 EEPROM_START(); 301 /* 302 * Send read control code to EEPROM. 303 */ 304 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 305 printf("%s: failed to send read command, status: %x\n", 306 device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 307 return (1); 308 } 309 310 /* 311 * Start reading bits from EEPROM. 312 */ 313 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 314 for (i = 0x80; i; i >>= 1) { 315 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 316 DELAY(1); 317 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 318 byte |= i; 319 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 320 DELAY(1); 321 } 322 323 EEPROM_STOP(); 324 325 /* 326 * No ACK generated for read, so just return byte. 327 */ 328 329 *dest = byte; 330 331 return (0); 332 } 333 334 /* 335 * Read a sequence of bytes from the EEPROM. 336 */ 337 static int 338 ti_read_eeprom(struct ti_softc *sc, void *destv, int off, int cnt) 339 { 340 char *dest = destv; 341 int err = 0, i; 342 uint8_t byte = 0; 343 344 for (i = 0; i < cnt; i++) { 345 err = ti_eeprom_getbyte(sc, off + i, &byte); 346 if (err) 347 break; 348 *(dest + i) = byte; 349 } 350 351 return (err ? 1 : 0); 352 } 353 354 /* 355 * NIC memory access function. Can be used to either clear a section 356 * of NIC local memory or (if tbuf is non-NULL) copy data into it. 357 */ 358 static void 359 ti_mem(struct ti_softc *sc, uint32_t addr, uint32_t len, const void *xbuf) 360 { 361 int segptr, segsize, cnt; 362 const void *ptr; 363 364 segptr = addr; 365 cnt = len; 366 ptr = xbuf; 367 368 while (cnt) { 369 if (cnt < TI_WINLEN) 370 segsize = cnt; 371 else 372 segsize = TI_WINLEN - (segptr % TI_WINLEN); 373 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 374 if (xbuf == NULL) { 375 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 376 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, 377 segsize / 4); 378 } else { 379 #ifdef __BUS_SPACE_HAS_STREAM_METHODS 380 bus_space_write_region_stream_4(sc->ti_btag, 381 sc->ti_bhandle, 382 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 383 (const uint32_t *)ptr, segsize / 4); 384 #else 385 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 386 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 387 (const uint32_t *)ptr, segsize / 4); 388 #endif 389 ptr = (const char *)ptr + segsize; 390 } 391 segptr += segsize; 392 cnt -= segsize; 393 } 394 395 return; 396 } 397 398 /* 399 * Load firmware image into the NIC. Check that the firmware revision 400 * is acceptable and see if we want the firmware for the Tigon 1 or 401 * Tigon 2. 402 */ 403 static void 404 ti_loadfw(struct ti_softc *sc) 405 { 406 switch (sc->ti_hwrev) { 407 case TI_HWREV_TIGON: 408 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 409 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 410 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 411 printf("%s: firmware revision mismatch; want " 412 "%d.%d.%d, got %d.%d.%d\n", device_xname(sc->sc_dev), 413 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 414 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 415 tigonFwReleaseMinor, tigonFwReleaseFix); 416 return; 417 } 418 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText); 419 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData); 420 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, tigonFwRodata); 421 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 422 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 423 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 424 break; 425 case TI_HWREV_TIGON_II: 426 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 427 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 428 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 429 printf("%s: firmware revision mismatch; want " 430 "%d.%d.%d, got %d.%d.%d\n", device_xname(sc->sc_dev), 431 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 432 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 433 tigon2FwReleaseMinor, tigon2FwReleaseFix); 434 return; 435 } 436 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, tigon2FwText); 437 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, tigon2FwData); 438 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 439 tigon2FwRodata); 440 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 441 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 442 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 443 break; 444 default: 445 printf("%s: can't load firmware: unknown hardware rev\n", 446 device_xname(sc->sc_dev)); 447 break; 448 } 449 450 return; 451 } 452 453 /* 454 * Send the NIC a command via the command ring. 455 */ 456 static void 457 ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd) 458 { 459 uint32_t index; 460 461 index = sc->ti_cmd_saved_prodidx; 462 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 463 TI_INC(index, TI_CMD_RING_CNT); 464 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 465 sc->ti_cmd_saved_prodidx = index; 466 } 467 468 /* 469 * Send the NIC an extended command. The 'len' parameter specifies the 470 * number of command slots to include after the initial command. 471 */ 472 static void 473 ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, void *argv, int len) 474 { 475 char *arg = argv; 476 uint32_t index; 477 int i; 478 479 index = sc->ti_cmd_saved_prodidx; 480 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 481 TI_INC(index, TI_CMD_RING_CNT); 482 for (i = 0; i < len; i++) { 483 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 484 *(uint32_t *)(&arg[i * 4])); 485 TI_INC(index, TI_CMD_RING_CNT); 486 } 487 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 488 sc->ti_cmd_saved_prodidx = index; 489 } 490 491 /* 492 * Handle events that have triggered interrupts. 493 */ 494 static void 495 ti_handle_events(struct ti_softc *sc) 496 { 497 struct ti_event_desc *e; 498 499 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 500 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 501 switch (TI_EVENT_EVENT(e)) { 502 case TI_EV_LINKSTAT_CHANGED: 503 sc->ti_linkstat = TI_EVENT_CODE(e); 504 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) 505 printf("%s: 10/100 link up\n", 506 device_xname(sc->sc_dev)); 507 else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) 508 printf("%s: gigabit link up\n", 509 device_xname(sc->sc_dev)); 510 else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 511 printf("%s: link down\n", 512 device_xname(sc->sc_dev)); 513 break; 514 case TI_EV_ERROR: 515 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD) 516 printf("%s: invalid command\n", 517 device_xname(sc->sc_dev)); 518 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD) 519 printf("%s: unknown command\n", 520 device_xname(sc->sc_dev)); 521 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG) 522 printf("%s: bad config data\n", 523 device_xname(sc->sc_dev)); 524 break; 525 case TI_EV_FIRMWARE_UP: 526 ti_init2(sc); 527 break; 528 case TI_EV_STATS_UPDATED: 529 ti_stats_update(sc); 530 break; 531 case TI_EV_RESET_JUMBO_RING: 532 case TI_EV_MCAST_UPDATED: 533 /* Who cares. */ 534 break; 535 default: 536 printf("%s: unknown event: %d\n", 537 device_xname(sc->sc_dev), TI_EVENT_EVENT(e)); 538 break; 539 } 540 /* Advance the consumer index. */ 541 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 542 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 543 } 544 545 return; 546 } 547 548 /* 549 * Memory management for the jumbo receive ring is a pain in the 550 * butt. We need to allocate at least 9018 bytes of space per frame, 551 * _and_ it has to be contiguous (unless you use the extended 552 * jumbo descriptor format). Using malloc() all the time won't 553 * work: malloc() allocates memory in powers of two, which means we 554 * would end up wasting a considerable amount of space by allocating 555 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 556 * to do our own memory management. 557 * 558 * The driver needs to allocate a contiguous chunk of memory at boot 559 * time. We then chop this up ourselves into 9K pieces and use them 560 * as external mbuf storage. 561 * 562 * One issue here is how much memory to allocate. The jumbo ring has 563 * 256 slots in it, but at 9K per slot than can consume over 2MB of 564 * RAM. This is a bit much, especially considering we also need 565 * RAM for the standard ring and mini ring (on the Tigon 2). To 566 * save space, we only actually allocate enough memory for 64 slots 567 * by default, which works out to between 500 and 600K. This can 568 * be tuned by changing a #define in if_tireg.h. 569 */ 570 571 static int 572 ti_alloc_jumbo_mem(struct ti_softc *sc) 573 { 574 char *ptr; 575 int i; 576 struct ti_jpool_entry *entry; 577 bus_dma_segment_t dmaseg; 578 int error, dmanseg; 579 580 /* Grab a big chunk o' storage. */ 581 if ((error = bus_dmamem_alloc(sc->sc_dmat, 582 TI_JMEM, PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 583 BUS_DMA_NOWAIT)) != 0) { 584 aprint_error_dev(sc->sc_dev, 585 "can't allocate jumbo buffer, error = %d\n", error); 586 return (error); 587 } 588 589 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 590 TI_JMEM, (void **)&sc->ti_cdata.ti_jumbo_buf, 591 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 592 aprint_error_dev(sc->sc_dev, 593 "can't map jumbo buffer, error = %d\n", error); 594 return (error); 595 } 596 597 if ((error = bus_dmamap_create(sc->sc_dmat, 598 TI_JMEM, 1, 599 TI_JMEM, 0, BUS_DMA_NOWAIT, 600 &sc->jumbo_dmamap)) != 0) { 601 aprint_error_dev(sc->sc_dev, 602 "can't create jumbo buffer DMA map, error = %d\n", error); 603 return (error); 604 } 605 606 if ((error = bus_dmamap_load(sc->sc_dmat, sc->jumbo_dmamap, 607 sc->ti_cdata.ti_jumbo_buf, TI_JMEM, NULL, 608 BUS_DMA_NOWAIT)) != 0) { 609 aprint_error_dev(sc->sc_dev, 610 "can't load jumbo buffer DMA map, error = %d\n", error); 611 return (error); 612 } 613 sc->jumbo_dmaaddr = sc->jumbo_dmamap->dm_segs[0].ds_addr; 614 615 SIMPLEQ_INIT(&sc->ti_jfree_listhead); 616 SIMPLEQ_INIT(&sc->ti_jinuse_listhead); 617 618 /* 619 * Now divide it up into 9K pieces and save the addresses 620 * in an array. 621 */ 622 ptr = sc->ti_cdata.ti_jumbo_buf; 623 for (i = 0; i < TI_JSLOTS; i++) { 624 sc->ti_cdata.ti_jslots[i] = ptr; 625 ptr += TI_JLEN; 626 entry = malloc(sizeof(struct ti_jpool_entry), 627 M_DEVBUF, M_WAITOK); 628 entry->slot = i; 629 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, 630 jpool_entries); 631 } 632 633 return (0); 634 } 635 636 /* 637 * Allocate a jumbo buffer. 638 */ 639 static void * 640 ti_jalloc(struct ti_softc *sc) 641 { 642 struct ti_jpool_entry *entry; 643 644 entry = SIMPLEQ_FIRST(&sc->ti_jfree_listhead); 645 646 if (entry == NULL) { 647 printf("%s: no free jumbo buffers\n", device_xname(sc->sc_dev)); 648 return (NULL); 649 } 650 651 SIMPLEQ_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 652 SIMPLEQ_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 653 654 return (sc->ti_cdata.ti_jslots[entry->slot]); 655 } 656 657 /* 658 * Release a jumbo buffer. 659 */ 660 static void 661 ti_jfree(struct mbuf *m, void *tbuf, size_t size, void *arg) 662 { 663 struct ti_softc *sc; 664 int i, s; 665 struct ti_jpool_entry *entry; 666 667 /* Extract the softc struct pointer. */ 668 sc = (struct ti_softc *)arg; 669 670 if (sc == NULL) 671 panic("ti_jfree: didn't get softc pointer!"); 672 673 /* calculate the slot this buffer belongs to */ 674 675 i = ((char *)tbuf 676 - (char *)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 677 678 if ((i < 0) || (i >= TI_JSLOTS)) 679 panic("ti_jfree: asked to free buffer that we don't manage!"); 680 681 s = splvm(); 682 entry = SIMPLEQ_FIRST(&sc->ti_jinuse_listhead); 683 if (entry == NULL) 684 panic("ti_jfree: buffer not in use!"); 685 entry->slot = i; 686 SIMPLEQ_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 687 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 688 689 if (__predict_true(m != NULL)) 690 pool_cache_put(mb_cache, m); 691 splx(s); 692 } 693 694 695 /* 696 * Initialize a standard receive ring descriptor. 697 */ 698 static int 699 ti_newbuf_std(struct ti_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap) 700 { 701 struct mbuf *m_new = NULL; 702 struct ti_rx_desc *r; 703 int error; 704 705 if (dmamap == NULL) { 706 /* if (m) panic() */ 707 708 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 709 MCLBYTES, 0, BUS_DMA_NOWAIT, 710 &dmamap)) != 0) { 711 aprint_error_dev(sc->sc_dev, 712 "can't create recv map, error = %d\n", error); 713 return (ENOMEM); 714 } 715 } 716 sc->std_dmamap[i] = dmamap; 717 718 if (m == NULL) { 719 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 720 if (m_new == NULL) { 721 aprint_error_dev(sc->sc_dev, 722 "mbuf allocation failed -- packet dropped!\n"); 723 return (ENOBUFS); 724 } 725 726 MCLGET(m_new, M_DONTWAIT); 727 if (!(m_new->m_flags & M_EXT)) { 728 aprint_error_dev(sc->sc_dev, 729 "cluster allocation failed -- packet dropped!\n"); 730 m_freem(m_new); 731 return (ENOBUFS); 732 } 733 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 734 m_adj(m_new, ETHER_ALIGN); 735 736 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 737 mtod(m_new, void *), m_new->m_len, NULL, 738 BUS_DMA_READ | BUS_DMA_NOWAIT)) != 0) { 739 aprint_error_dev(sc->sc_dev, 740 "can't load recv map, error = %d\n", error); 741 m_freem(m_new); 742 return (ENOMEM); 743 } 744 } else { 745 m_new = m; 746 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 747 m_new->m_data = m_new->m_ext.ext_buf; 748 m_adj(m_new, ETHER_ALIGN); 749 750 /* reuse the dmamap */ 751 } 752 753 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 754 r = &sc->ti_rdata->ti_rx_std_ring[i]; 755 TI_HOSTADDR(r->ti_addr, dmamap->dm_segs[0].ds_addr); 756 r->ti_type = TI_BDTYPE_RECV_BD; 757 r->ti_flags = 0; 758 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx) 759 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 760 if (sc->ethercom.ec_if.if_capenable & 761 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 762 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 763 r->ti_len = m_new->m_len; /* == ds_len */ 764 r->ti_idx = i; 765 766 return (0); 767 } 768 769 /* 770 * Initialize a mini receive ring descriptor. This only applies to 771 * the Tigon 2. 772 */ 773 static int 774 ti_newbuf_mini(struct ti_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap) 775 { 776 struct mbuf *m_new = NULL; 777 struct ti_rx_desc *r; 778 int error; 779 780 if (dmamap == NULL) { 781 /* if (m) panic() */ 782 783 if ((error = bus_dmamap_create(sc->sc_dmat, MHLEN, 1, 784 MHLEN, 0, BUS_DMA_NOWAIT, 785 &dmamap)) != 0) { 786 aprint_error_dev(sc->sc_dev, 787 "can't create recv map, error = %d\n", error); 788 return (ENOMEM); 789 } 790 } 791 sc->mini_dmamap[i] = dmamap; 792 793 if (m == NULL) { 794 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 795 if (m_new == NULL) { 796 aprint_error_dev(sc->sc_dev, 797 "mbuf allocation failed -- packet dropped!\n"); 798 return (ENOBUFS); 799 } 800 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 801 m_adj(m_new, ETHER_ALIGN); 802 803 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 804 mtod(m_new, void *), m_new->m_len, NULL, 805 BUS_DMA_READ | BUS_DMA_NOWAIT)) != 0) { 806 aprint_error_dev(sc->sc_dev, 807 "can't load recv map, error = %d\n", error); 808 m_freem(m_new); 809 return (ENOMEM); 810 } 811 } else { 812 m_new = m; 813 m_new->m_data = m_new->m_pktdat; 814 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 815 m_adj(m_new, ETHER_ALIGN); 816 817 /* reuse the dmamap */ 818 } 819 820 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 821 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 822 TI_HOSTADDR(r->ti_addr, dmamap->dm_segs[0].ds_addr); 823 r->ti_type = TI_BDTYPE_RECV_BD; 824 r->ti_flags = TI_BDFLAG_MINI_RING; 825 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx) 826 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 827 if (sc->ethercom.ec_if.if_capenable & 828 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 829 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 830 r->ti_len = m_new->m_len; /* == ds_len */ 831 r->ti_idx = i; 832 833 return (0); 834 } 835 836 /* 837 * Initialize a jumbo receive ring descriptor. This allocates 838 * a jumbo buffer from the pool managed internally by the driver. 839 */ 840 static int 841 ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *m) 842 { 843 struct mbuf *m_new = NULL; 844 struct ti_rx_desc *r; 845 846 if (m == NULL) { 847 void * tbuf = NULL; 848 849 /* Allocate the mbuf. */ 850 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 851 if (m_new == NULL) { 852 aprint_error_dev(sc->sc_dev, 853 "mbuf allocation failed -- packet dropped!\n"); 854 return (ENOBUFS); 855 } 856 857 /* Allocate the jumbo buffer */ 858 tbuf = ti_jalloc(sc); 859 if (tbuf == NULL) { 860 m_freem(m_new); 861 aprint_error_dev(sc->sc_dev, 862 "jumbo allocation failed -- packet dropped!\n"); 863 return (ENOBUFS); 864 } 865 866 /* Attach the buffer to the mbuf. */ 867 MEXTADD(m_new, tbuf, ETHER_MAX_LEN_JUMBO, 868 M_DEVBUF, ti_jfree, sc); 869 m_new->m_flags |= M_EXT_RW; 870 m_new->m_len = m_new->m_pkthdr.len = ETHER_MAX_LEN_JUMBO; 871 } else { 872 m_new = m; 873 m_new->m_data = m_new->m_ext.ext_buf; 874 m_new->m_ext.ext_size = ETHER_MAX_LEN_JUMBO; 875 } 876 877 m_adj(m_new, ETHER_ALIGN); 878 /* Set up the descriptor. */ 879 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 880 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 881 TI_HOSTADDR(r->ti_addr, sc->jumbo_dmaaddr + 882 (mtod(m_new, char *) - (char *)sc->ti_cdata.ti_jumbo_buf)); 883 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 884 r->ti_flags = TI_BDFLAG_JUMBO_RING; 885 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx) 886 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 887 if (sc->ethercom.ec_if.if_capenable & 888 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 889 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 890 r->ti_len = m_new->m_len; 891 r->ti_idx = i; 892 893 return (0); 894 } 895 896 /* 897 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 898 * that's 1MB or memory, which is a lot. For now, we fill only the first 899 * 256 ring entries and hope that our CPU is fast enough to keep up with 900 * the NIC. 901 */ 902 static int 903 ti_init_rx_ring_std(struct ti_softc *sc) 904 { 905 int i; 906 struct ti_cmd_desc cmd; 907 908 for (i = 0; i < TI_SSLOTS; i++) { 909 if (ti_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 910 return (ENOBUFS); 911 } 912 913 TI_UPDATE_STDPROD(sc, i - 1); 914 sc->ti_std = i - 1; 915 916 return (0); 917 } 918 919 static void 920 ti_free_rx_ring_std(struct ti_softc *sc) 921 { 922 int i; 923 924 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 925 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 926 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 927 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 928 929 /* if (sc->std_dmamap[i] == 0) panic() */ 930 bus_dmamap_destroy(sc->sc_dmat, sc->std_dmamap[i]); 931 sc->std_dmamap[i] = 0; 932 } 933 memset((char *)&sc->ti_rdata->ti_rx_std_ring[i], 0, 934 sizeof(struct ti_rx_desc)); 935 } 936 937 return; 938 } 939 940 static int 941 ti_init_rx_ring_jumbo(struct ti_softc *sc) 942 { 943 int i; 944 struct ti_cmd_desc cmd; 945 946 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 947 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 948 return (ENOBUFS); 949 } 950 951 TI_UPDATE_JUMBOPROD(sc, i - 1); 952 sc->ti_jumbo = i - 1; 953 954 return (0); 955 } 956 957 static void 958 ti_free_rx_ring_jumbo(struct ti_softc *sc) 959 { 960 int i; 961 962 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 963 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 964 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 965 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 966 } 967 memset((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 0, 968 sizeof(struct ti_rx_desc)); 969 } 970 971 return; 972 } 973 974 static int 975 ti_init_rx_ring_mini(struct ti_softc *sc) 976 { 977 int i; 978 979 for (i = 0; i < TI_MSLOTS; i++) { 980 if (ti_newbuf_mini(sc, i, NULL, 0) == ENOBUFS) 981 return (ENOBUFS); 982 } 983 984 TI_UPDATE_MINIPROD(sc, i - 1); 985 sc->ti_mini = i - 1; 986 987 return (0); 988 } 989 990 static void 991 ti_free_rx_ring_mini(struct ti_softc *sc) 992 { 993 int i; 994 995 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 996 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 997 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 998 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 999 1000 /* if (sc->mini_dmamap[i] == 0) panic() */ 1001 bus_dmamap_destroy(sc->sc_dmat, sc->mini_dmamap[i]); 1002 sc->mini_dmamap[i] = 0; 1003 } 1004 memset((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 0, 1005 sizeof(struct ti_rx_desc)); 1006 } 1007 1008 return; 1009 } 1010 1011 static void 1012 ti_free_tx_ring(struct ti_softc *sc) 1013 { 1014 int i; 1015 struct txdmamap_pool_entry *dma; 1016 1017 for (i = 0; i < TI_TX_RING_CNT; i++) { 1018 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1019 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1020 sc->ti_cdata.ti_tx_chain[i] = NULL; 1021 1022 /* if (sc->txdma[i] == 0) panic() */ 1023 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1024 link); 1025 sc->txdma[i] = 0; 1026 } 1027 memset((char *)&sc->ti_rdata->ti_tx_ring[i], 0, 1028 sizeof(struct ti_tx_desc)); 1029 } 1030 1031 while ((dma = SIMPLEQ_FIRST(&sc->txdma_list))) { 1032 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 1033 bus_dmamap_destroy(sc->sc_dmat, dma->dmamap); 1034 free(dma, M_DEVBUF); 1035 } 1036 1037 return; 1038 } 1039 1040 static int 1041 ti_init_tx_ring(struct ti_softc *sc) 1042 { 1043 int i, error; 1044 bus_dmamap_t dmamap; 1045 struct txdmamap_pool_entry *dma; 1046 1047 sc->ti_txcnt = 0; 1048 sc->ti_tx_saved_considx = 0; 1049 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1050 1051 SIMPLEQ_INIT(&sc->txdma_list); 1052 for (i = 0; i < TI_RSLOTS; i++) { 1053 /* I've seen mbufs with 30 fragments. */ 1054 if ((error = bus_dmamap_create(sc->sc_dmat, 1055 ETHER_MAX_LEN_JUMBO, 40, ETHER_MAX_LEN_JUMBO, 0, 1056 BUS_DMA_NOWAIT, &dmamap)) != 0) { 1057 aprint_error_dev(sc->sc_dev, 1058 "can't create tx map, error = %d\n", error); 1059 return (ENOMEM); 1060 } 1061 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1062 if (!dma) { 1063 aprint_error_dev(sc->sc_dev, 1064 "can't alloc txdmamap_pool_entry\n"); 1065 bus_dmamap_destroy(sc->sc_dmat, dmamap); 1066 return (ENOMEM); 1067 } 1068 dma->dmamap = dmamap; 1069 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 1070 } 1071 1072 return (0); 1073 } 1074 1075 /* 1076 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1077 * but we have to support the old way too so that Tigon 1 cards will 1078 * work. 1079 */ 1080 static void 1081 ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr) 1082 { 1083 struct ti_cmd_desc cmd; 1084 uint16_t *m; 1085 uint32_t ext[2] = {0, 0}; 1086 1087 m = (uint16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1088 1089 switch (sc->ti_hwrev) { 1090 case TI_HWREV_TIGON: 1091 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1092 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1093 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1094 break; 1095 case TI_HWREV_TIGON_II: 1096 ext[0] = htons(m[0]); 1097 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1098 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (void *)&ext, 2); 1099 break; 1100 default: 1101 printf("%s: unknown hwrev\n", device_xname(sc->sc_dev)); 1102 break; 1103 } 1104 1105 return; 1106 } 1107 1108 static void 1109 ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr) 1110 { 1111 struct ti_cmd_desc cmd; 1112 uint16_t *m; 1113 uint32_t ext[2] = {0, 0}; 1114 1115 m = (uint16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1116 1117 switch (sc->ti_hwrev) { 1118 case TI_HWREV_TIGON: 1119 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1120 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1121 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1122 break; 1123 case TI_HWREV_TIGON_II: 1124 ext[0] = htons(m[0]); 1125 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1126 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (void *)&ext, 2); 1127 break; 1128 default: 1129 printf("%s: unknown hwrev\n", device_xname(sc->sc_dev)); 1130 break; 1131 } 1132 1133 return; 1134 } 1135 1136 /* 1137 * Configure the Tigon's multicast address filter. 1138 * 1139 * The actual multicast table management is a bit of a pain, thanks to 1140 * slight brain damage on the part of both Alteon and us. With our 1141 * multicast code, we are only alerted when the multicast address table 1142 * changes and at that point we only have the current list of addresses: 1143 * we only know the current state, not the previous state, so we don't 1144 * actually know what addresses were removed or added. The firmware has 1145 * state, but we can't get our grubby mits on it, and there is no 'delete 1146 * all multicast addresses' command. Hence, we have to maintain our own 1147 * state so we know what addresses have been programmed into the NIC at 1148 * any given time. 1149 */ 1150 static void 1151 ti_setmulti(struct ti_softc *sc) 1152 { 1153 struct ethercom *ec = &sc->ethercom; 1154 struct ifnet *ifp = &ec->ec_if; 1155 struct ti_cmd_desc cmd; 1156 struct ti_mc_entry *mc; 1157 uint32_t intrs; 1158 struct ether_multi *enm; 1159 struct ether_multistep step; 1160 1161 /* Disable interrupts. */ 1162 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1163 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1164 1165 /* First, zot all the existing filters. */ 1166 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1167 ti_del_mcast(sc, &mc->mc_addr); 1168 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1169 free(mc, M_DEVBUF); 1170 } 1171 1172 /* 1173 * Remember all multicast addresses so that we can delete them 1174 * later. Punt if there is a range of addresses or memory shortage. 1175 */ 1176 ETHER_LOCK(ec); 1177 ETHER_FIRST_MULTI(step, ec, enm); 1178 while (enm != NULL) { 1179 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1180 ETHER_ADDR_LEN) != 0) { 1181 ETHER_UNLOCK(ec); 1182 goto allmulti; 1183 } 1184 if ((mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, 1185 M_NOWAIT)) == NULL) { 1186 ETHER_UNLOCK(ec); 1187 goto allmulti; 1188 } 1189 memcpy(&mc->mc_addr, enm->enm_addrlo, ETHER_ADDR_LEN); 1190 SIMPLEQ_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1191 ETHER_NEXT_MULTI(step, enm); 1192 } 1193 ETHER_UNLOCK(ec); 1194 1195 /* Accept only programmed multicast addresses */ 1196 ifp->if_flags &= ~IFF_ALLMULTI; 1197 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1198 1199 /* Now program new ones. */ 1200 SIMPLEQ_FOREACH(mc, &sc->ti_mc_listhead, mc_entries) 1201 ti_add_mcast(sc, &mc->mc_addr); 1202 1203 /* Re-enable interrupts. */ 1204 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1205 1206 return; 1207 1208 allmulti: 1209 /* No need to keep individual multicast addresses */ 1210 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1211 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1212 free(mc, M_DEVBUF); 1213 } 1214 1215 /* Accept all multicast addresses */ 1216 ifp->if_flags |= IFF_ALLMULTI; 1217 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1218 1219 /* Re-enable interrupts. */ 1220 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1221 } 1222 1223 /* 1224 * Check to see if the BIOS has configured us for a 64 bit slot when 1225 * we aren't actually in one. If we detect this condition, we can work 1226 * around it on the Tigon 2 by setting a bit in the PCI state register, 1227 * but for the Tigon 1 we must give up and abort the interface attach. 1228 */ 1229 static int 1230 ti_64bitslot_war(struct ti_softc *sc) 1231 { 1232 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1233 CSR_WRITE_4(sc, 0x600, 0); 1234 CSR_WRITE_4(sc, 0x604, 0); 1235 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1236 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1237 if (sc->ti_hwrev == TI_HWREV_TIGON) 1238 return (EINVAL); 1239 else { 1240 TI_SETBIT(sc, TI_PCI_STATE, 1241 TI_PCISTATE_32BIT_BUS); 1242 return (0); 1243 } 1244 } 1245 } 1246 1247 return (0); 1248 } 1249 1250 /* 1251 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1252 * self-test results. 1253 */ 1254 static int 1255 ti_chipinit(struct ti_softc *sc) 1256 { 1257 uint32_t cacheline; 1258 uint32_t pci_writemax = 0; 1259 uint32_t rev; 1260 1261 /* Initialize link to down state. */ 1262 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1263 1264 /* Set endianness before we access any non-PCI registers. */ 1265 #if BYTE_ORDER == BIG_ENDIAN 1266 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1267 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1268 #else 1269 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1270 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1271 #endif 1272 1273 /* Check the ROM failed bit to see if self-tests passed. */ 1274 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1275 printf("%s: board self-diagnostics failed!\n", 1276 device_xname(sc->sc_dev)); 1277 return (ENODEV); 1278 } 1279 1280 /* Halt the CPU. */ 1281 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1282 1283 /* Figure out the hardware revision. */ 1284 rev = CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK; 1285 switch (rev) { 1286 case TI_REV_TIGON_I: 1287 sc->ti_hwrev = TI_HWREV_TIGON; 1288 break; 1289 case TI_REV_TIGON_II: 1290 sc->ti_hwrev = TI_HWREV_TIGON_II; 1291 break; 1292 default: 1293 printf("%s: unsupported chip revision 0x%x\n", 1294 device_xname(sc->sc_dev), rev); 1295 return (ENODEV); 1296 } 1297 1298 /* Do special setup for Tigon 2. */ 1299 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1300 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1301 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 1302 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1303 } 1304 1305 /* Set up the PCI state register. */ 1306 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD | TI_PCI_WRITE_CMD); 1307 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1308 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1309 } 1310 1311 /* Clear the read/write max DMA parameters. */ 1312 TI_CLRBIT(sc, TI_PCI_STATE, 1313 (TI_PCISTATE_WRITE_MAXDMA | TI_PCISTATE_READ_MAXDMA)); 1314 1315 /* Get cache line size. */ 1316 cacheline = PCI_CACHELINE(CSR_READ_4(sc, PCI_BHLC_REG)); 1317 1318 /* 1319 * If the system has set enabled the PCI memory write 1320 * and invalidate command in the command register, set 1321 * the write max parameter accordingly. This is necessary 1322 * to use MWI with the Tigon 2. 1323 */ 1324 if (CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1325 & PCI_COMMAND_INVALIDATE_ENABLE) { 1326 switch (cacheline) { 1327 case 1: 1328 case 4: 1329 case 8: 1330 case 16: 1331 case 32: 1332 case 64: 1333 break; 1334 default: 1335 /* Disable PCI memory write and invalidate. */ 1336 if (bootverbose) 1337 printf("%s: cache line size %d not " 1338 "supported; disabling PCI MWI\n", 1339 device_xname(sc->sc_dev), cacheline); 1340 CSR_WRITE_4(sc, PCI_COMMAND_STATUS_REG, 1341 CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1342 & ~PCI_COMMAND_INVALIDATE_ENABLE); 1343 break; 1344 } 1345 } 1346 1347 #ifdef __brokenalpha__ 1348 /* 1349 * From the Alteon sample driver: 1350 * Must insure that we do not cross an 8K (bytes) boundary 1351 * for DMA reads. Our highest limit is 1K bytes. This is a 1352 * restriction on some ALPHA platforms with early revision 1353 * 21174 PCI chipsets, such as the AlphaPC 164lx 1354 */ 1355 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax | TI_PCI_READMAX_1024); 1356 #else 1357 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1358 #endif 1359 1360 /* This sets the min dma param all the way up (0xff). */ 1361 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1362 1363 /* Configure DMA variables. */ 1364 #if BYTE_ORDER == BIG_ENDIAN 1365 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1366 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1367 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1368 TI_OPMODE_DONT_FRAG_JUMBO); 1369 #else 1370 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA | 1371 TI_OPMODE_WORDSWAP_BD | TI_OPMODE_DONT_FRAG_JUMBO | 1372 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB); 1373 #endif 1374 1375 /* 1376 * Only allow 1 DMA channel to be active at a time. 1377 * I don't think this is a good idea, but without it 1378 * the firmware racks up lots of nicDmaReadRingFull 1379 * errors. 1380 * Incompatible with hardware assisted checksums. 1381 */ 1382 if ((sc->ethercom.ec_if.if_capenable & 1383 (IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1384 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 1385 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx)) == 0) 1386 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1387 1388 /* Recommended settings from Tigon manual. */ 1389 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1390 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1391 1392 if (ti_64bitslot_war(sc)) { 1393 printf("%s: bios thinks we're in a 64 bit slot, " 1394 "but we aren't", device_xname(sc->sc_dev)); 1395 return (EINVAL); 1396 } 1397 1398 return (0); 1399 } 1400 1401 /* 1402 * Initialize the general information block and firmware, and 1403 * start the CPU(s) running. 1404 */ 1405 static int 1406 ti_gibinit(struct ti_softc *sc) 1407 { 1408 struct ti_rcb *rcb; 1409 int i; 1410 struct ifnet *ifp; 1411 1412 ifp = &sc->ethercom.ec_if; 1413 1414 /* Disable interrupts for now. */ 1415 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1416 1417 /* Tell the chip where to find the general information block. */ 1418 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1419 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, TI_CDGIBADDR(sc)); 1420 1421 /* Load the firmware into SRAM. */ 1422 ti_loadfw(sc); 1423 1424 /* Set up the contents of the general info and ring control blocks. */ 1425 1426 /* Set up the event ring and producer pointer. */ 1427 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1428 1429 TI_HOSTADDR(rcb->ti_hostaddr, TI_CDEVENTADDR(sc, 0)); 1430 rcb->ti_flags = 0; 1431 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr, 1432 TI_CDEVPRODADDR(sc)); 1433 1434 sc->ti_ev_prodidx.ti_idx = 0; 1435 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1436 sc->ti_ev_saved_considx = 0; 1437 1438 /* Set up the command ring and producer mailbox. */ 1439 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1440 1441 TI_HOSTADDR(rcb->ti_hostaddr, TI_GCR_NIC_ADDR(TI_GCR_CMDRING)); 1442 rcb->ti_flags = 0; 1443 rcb->ti_max_len = 0; 1444 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1445 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1446 } 1447 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1448 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1449 sc->ti_cmd_saved_prodidx = 0; 1450 1451 /* 1452 * Assign the address of the stats refresh buffer. 1453 * We re-use the current stats buffer for this to 1454 * conserve memory. 1455 */ 1456 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr, 1457 TI_CDSTATSADDR(sc)); 1458 1459 /* Set up the standard receive ring. */ 1460 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1461 TI_HOSTADDR(rcb->ti_hostaddr, TI_CDRXSTDADDR(sc, 0)); 1462 rcb->ti_max_len = ETHER_MAX_LEN; 1463 rcb->ti_flags = 0; 1464 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1465 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1466 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 1467 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1468 if (VLAN_ATTACHED(&sc->ethercom)) 1469 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1470 1471 /* Set up the jumbo receive ring. */ 1472 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1473 TI_HOSTADDR(rcb->ti_hostaddr, TI_CDRXJUMBOADDR(sc, 0)); 1474 rcb->ti_max_len = ETHER_MAX_LEN_JUMBO; 1475 rcb->ti_flags = 0; 1476 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1477 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1478 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 1479 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1480 if (VLAN_ATTACHED(&sc->ethercom)) 1481 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1482 1483 /* 1484 * Set up the mini ring. Only activated on the 1485 * Tigon 2 but the slot in the config block is 1486 * still there on the Tigon 1. 1487 */ 1488 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1489 TI_HOSTADDR(rcb->ti_hostaddr, TI_CDRXMINIADDR(sc, 0)); 1490 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1491 if (sc->ti_hwrev == TI_HWREV_TIGON) 1492 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1493 else 1494 rcb->ti_flags = 0; 1495 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1496 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1497 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 1498 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1499 if (VLAN_ATTACHED(&sc->ethercom)) 1500 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1501 1502 /* 1503 * Set up the receive return ring. 1504 */ 1505 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1506 TI_HOSTADDR(rcb->ti_hostaddr, TI_CDRXRTNADDR(sc, 0)); 1507 rcb->ti_flags = 0; 1508 rcb->ti_max_len = TI_RETURN_RING_CNT; 1509 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr, 1510 TI_CDRTNPRODADDR(sc)); 1511 1512 /* 1513 * Set up the tx ring. Note: for the Tigon 2, we have the option 1514 * of putting the transmit ring in the host's address space and 1515 * letting the chip DMA it instead of leaving the ring in the NIC's 1516 * memory and accessing it through the shared memory region. We 1517 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1518 * so we have to revert to the shared memory scheme if we detect 1519 * a Tigon 1 chip. 1520 */ 1521 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1522 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1523 sc->ti_tx_ring_nic = 1524 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1525 } 1526 memset((char *)sc->ti_rdata->ti_tx_ring, 0, 1527 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1528 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1529 if (sc->ti_hwrev == TI_HWREV_TIGON) 1530 rcb->ti_flags = 0; 1531 else 1532 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1533 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) 1534 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1535 /* 1536 * When we get the packet, there is a pseudo-header seed already 1537 * in the th_sum or uh_sum field. Make sure the firmware doesn't 1538 * compute the pseudo-header checksum again! 1539 */ 1540 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx)) 1541 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1542 TI_RCB_FLAG_NO_PHDR_CKSUM; 1543 if (VLAN_ATTACHED(&sc->ethercom)) 1544 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1545 rcb->ti_max_len = TI_TX_RING_CNT; 1546 if (sc->ti_hwrev == TI_HWREV_TIGON) 1547 TI_HOSTADDR(rcb->ti_hostaddr, TI_TX_RING_BASE); 1548 else 1549 TI_HOSTADDR(rcb->ti_hostaddr, TI_CDTXADDR(sc, 0)); 1550 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr, 1551 TI_CDTXCONSADDR(sc)); 1552 1553 /* 1554 * We're done frobbing the General Information Block. Sync 1555 * it. Note we take care of the first stats sync here, as 1556 * well. 1557 */ 1558 TI_CDGIBSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1559 1560 /* Set up tuneables */ 1561 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN) || 1562 (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 1563 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1564 (sc->ti_rx_coal_ticks / 10)); 1565 else 1566 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1567 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1568 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1569 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1570 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1571 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1572 1573 /* Turn interrupts on. */ 1574 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1575 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1576 1577 /* Start CPU. */ 1578 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT | TI_CPUSTATE_STEP)); 1579 1580 return (0); 1581 } 1582 1583 /* 1584 * look for id in the device list, returning the first match 1585 */ 1586 static const struct ti_type * 1587 ti_type_match(struct pci_attach_args *pa) 1588 { 1589 const struct ti_type *t; 1590 1591 t = ti_devs; 1592 while (t->ti_name != NULL) { 1593 if ((PCI_VENDOR(pa->pa_id) == t->ti_vid) && 1594 (PCI_PRODUCT(pa->pa_id) == t->ti_did)) { 1595 return (t); 1596 } 1597 t++; 1598 } 1599 1600 return (NULL); 1601 } 1602 1603 /* 1604 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1605 * against our list and return its name if we find a match. 1606 */ 1607 static int 1608 ti_probe(device_t parent, cfdata_t match, void *aux) 1609 { 1610 struct pci_attach_args *pa = aux; 1611 const struct ti_type *t; 1612 1613 t = ti_type_match(pa); 1614 1615 return ((t == NULL) ? 0 : 1); 1616 } 1617 1618 static void 1619 ti_attach(device_t parent, device_t self, void *aux) 1620 { 1621 uint32_t command; 1622 struct ifnet *ifp; 1623 struct ti_softc *sc; 1624 uint8_t eaddr[ETHER_ADDR_LEN]; 1625 struct pci_attach_args *pa = aux; 1626 pci_chipset_tag_t pc = pa->pa_pc; 1627 pci_intr_handle_t ih; 1628 const char *intrstr = NULL; 1629 bus_dma_segment_t dmaseg; 1630 int error, dmanseg, nolinear; 1631 const struct ti_type *t; 1632 char intrbuf[PCI_INTRSTR_LEN]; 1633 1634 t = ti_type_match(pa); 1635 if (t == NULL) { 1636 aprint_error("ti_attach: were did the card go ?\n"); 1637 return; 1638 } 1639 1640 aprint_normal(": %s (rev. 0x%02x)\n", t->ti_name, 1641 PCI_REVISION(pa->pa_class)); 1642 1643 sc = device_private(self); 1644 sc->sc_dev = self; 1645 1646 /* 1647 * Map control/status registers. 1648 */ 1649 nolinear = 0; 1650 if (pci_mapreg_map(pa, 0x10, 1651 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1652 BUS_SPACE_MAP_LINEAR , &sc->ti_btag, &sc->ti_bhandle, 1653 NULL, NULL)) { 1654 nolinear = 1; 1655 if (pci_mapreg_map(pa, 0x10, 1656 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1657 0 , &sc->ti_btag, &sc->ti_bhandle, NULL, NULL)) { 1658 aprint_error_dev(self, "can't map memory space\n"); 1659 return; 1660 } 1661 } 1662 if (nolinear == 0) 1663 sc->ti_vhandle = bus_space_vaddr(sc->ti_btag, sc->ti_bhandle); 1664 else 1665 sc->ti_vhandle = NULL; 1666 1667 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1668 command |= PCI_COMMAND_MASTER_ENABLE; 1669 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1670 1671 /* Allocate interrupt */ 1672 if (pci_intr_map(pa, &ih)) { 1673 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 1674 return; 1675 } 1676 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1677 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, ti_intr, sc, 1678 device_xname(self)); 1679 if (sc->sc_ih == NULL) { 1680 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 1681 if (intrstr != NULL) 1682 aprint_error(" at %s", intrstr); 1683 aprint_error("\n"); 1684 return; 1685 } 1686 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1687 1688 if (ti_chipinit(sc)) { 1689 aprint_error_dev(self, "chip initialization failed\n"); 1690 goto fail2; 1691 } 1692 1693 /* 1694 * Deal with some chip diffrences. 1695 */ 1696 switch (sc->ti_hwrev) { 1697 case TI_HWREV_TIGON: 1698 sc->sc_tx_encap = ti_encap_tigon1; 1699 sc->sc_tx_eof = ti_txeof_tigon1; 1700 if (nolinear == 1) 1701 aprint_error_dev(self, 1702 "memory space not mapped linear\n"); 1703 break; 1704 1705 case TI_HWREV_TIGON_II: 1706 sc->sc_tx_encap = ti_encap_tigon2; 1707 sc->sc_tx_eof = ti_txeof_tigon2; 1708 break; 1709 1710 default: 1711 aprint_error_dev(self, "Unknown chip version: %d\n", 1712 sc->ti_hwrev); 1713 goto fail2; 1714 } 1715 1716 /* Zero out the NIC's on-board SRAM. */ 1717 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1718 1719 /* Init again -- zeroing memory may have clobbered some registers. */ 1720 if (ti_chipinit(sc)) { 1721 aprint_error_dev(self, "chip initialization failed\n"); 1722 goto fail2; 1723 } 1724 1725 /* 1726 * Get station address from the EEPROM. Note: the manual states 1727 * that the MAC address is at offset 0x8c, however the data is 1728 * stored as two longwords (since that's how it's loaded into 1729 * the NIC). This means the MAC address is actually preceded 1730 * by two zero bytes. We need to skip over those. 1731 */ 1732 if (ti_read_eeprom(sc, (void *)&eaddr, 1733 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1734 aprint_error_dev(self, "failed to read station address\n"); 1735 goto fail2; 1736 } 1737 1738 /* 1739 * A Tigon chip was detected. Inform the world. 1740 */ 1741 aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(eaddr)); 1742 1743 if (pci_dma64_available(pa)) 1744 sc->sc_dmat = pa->pa_dmat64; 1745 else 1746 sc->sc_dmat = pa->pa_dmat; 1747 1748 /* Allocate the general information block and ring buffers. */ 1749 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1750 sizeof(struct ti_ring_data), PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 1751 BUS_DMA_NOWAIT)) != 0) { 1752 aprint_error_dev(self, 1753 "can't allocate ring buffer, error = %d\n", error); 1754 goto fail2; 1755 } 1756 1757 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 1758 sizeof(struct ti_ring_data), (void **)&sc->ti_rdata, 1759 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 1760 aprint_error_dev(self, 1761 "can't map ring buffer, error = %d\n", error); 1762 goto fail2; 1763 } 1764 1765 if ((error = bus_dmamap_create(sc->sc_dmat, 1766 sizeof(struct ti_ring_data), 1, 1767 sizeof(struct ti_ring_data), 0, BUS_DMA_NOWAIT, 1768 &sc->info_dmamap)) != 0) { 1769 aprint_error_dev(self, 1770 "can't create ring buffer DMA map, error = %d\n", error); 1771 goto fail2; 1772 } 1773 1774 if ((error = bus_dmamap_load(sc->sc_dmat, sc->info_dmamap, 1775 sc->ti_rdata, sizeof(struct ti_ring_data), NULL, 1776 BUS_DMA_NOWAIT)) != 0) { 1777 aprint_error_dev(self, 1778 "can't load ring buffer DMA map, error = %d\n", error); 1779 goto fail2; 1780 } 1781 1782 sc->info_dmaaddr = sc->info_dmamap->dm_segs[0].ds_addr; 1783 1784 memset(sc->ti_rdata, 0, sizeof(struct ti_ring_data)); 1785 1786 /* Try to allocate memory for jumbo buffers. */ 1787 if (ti_alloc_jumbo_mem(sc)) { 1788 aprint_error_dev(self, "jumbo buffer allocation failed\n"); 1789 goto fail2; 1790 } 1791 1792 SIMPLEQ_INIT(&sc->ti_mc_listhead); 1793 1794 /* 1795 * We really need a better way to tell a 1000baseT card 1796 * from a 1000baseSX one, since in theory there could be 1797 * OEMed 1000baseT cards from lame vendors who aren't 1798 * clever enough to change the PCI ID. For the moment 1799 * though, the AceNIC is the only copper card available. 1800 */ 1801 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALTEON && 1802 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALTEON_ACENIC_COPPER) || 1803 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NETGEAR && 1804 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NETGEAR_GA620T)) 1805 sc->ti_copper = 1; 1806 else 1807 sc->ti_copper = 0; 1808 1809 /* Set default tuneable values. */ 1810 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1811 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1812 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1813 sc->ti_rx_max_coal_bds = 64; 1814 sc->ti_tx_max_coal_bds = 128; 1815 sc->ti_tx_buf_ratio = 21; 1816 1817 /* Set up ifnet structure */ 1818 ifp = &sc->ethercom.ec_if; 1819 ifp->if_softc = sc; 1820 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 1821 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1822 ifp->if_ioctl = ti_ioctl; 1823 ifp->if_start = ti_start; 1824 ifp->if_watchdog = ti_watchdog; 1825 IFQ_SET_READY(&ifp->if_snd); 1826 1827 #if 0 1828 /* 1829 * XXX This is not really correct -- we don't necessarily 1830 * XXX want to queue up as many as we can transmit at the 1831 * XXX upper layer like that. Someone with a board should 1832 * XXX check to see how this affects performance. 1833 */ 1834 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1835 #endif 1836 1837 /* 1838 * We can support 802.1Q VLAN-sized frames. 1839 */ 1840 sc->ethercom.ec_capabilities |= 1841 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 1842 sc->ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 1843 1844 /* 1845 * We can do IPv4, TCPv4, and UDPv4 checksums in hardware. 1846 */ 1847 ifp->if_capabilities |= 1848 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1849 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1850 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1851 1852 /* Set up ifmedia support. */ 1853 sc->ethercom.ec_ifmedia = &sc->ifmedia; 1854 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1855 if (sc->ti_copper) { 1856 /* 1857 * Copper cards allow manual 10/100 mode selection, 1858 * but not manual 1000baseT mode selection. Why? 1859 * Because currently there's no way to specify the 1860 * master/slave setting through the firmware interface, 1861 * so Alteon decided to just bag it and handle it 1862 * via autonegotiation. 1863 */ 1864 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 1865 ifmedia_add(&sc->ifmedia, 1866 IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 1867 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 1868 ifmedia_add(&sc->ifmedia, 1869 IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 1870 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL); 1871 ifmedia_add(&sc->ifmedia, 1872 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 1873 } else { 1874 /* Fiber cards don't support 10/100 modes. */ 1875 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); 1876 ifmedia_add(&sc->ifmedia, 1877 IFM_ETHER | IFM_1000_SX | IFM_FDX, 0, NULL); 1878 } 1879 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 1880 ifmedia_set(&sc->ifmedia, IFM_ETHER | IFM_AUTO); 1881 1882 /* 1883 * Call MI attach routines. 1884 */ 1885 if_attach(ifp); 1886 if_deferred_start_init(ifp, NULL); 1887 ether_ifattach(ifp, eaddr); 1888 1889 /* 1890 * Add shutdown hook so that DMA is disabled prior to reboot. Not 1891 * doing do could allow DMA to corrupt kernel memory during the 1892 * reboot before the driver initializes. 1893 */ 1894 if (pmf_device_register1(self, NULL, NULL, ti_shutdown)) 1895 pmf_class_network_register(self, ifp); 1896 else 1897 aprint_error_dev(self, "couldn't establish power handler\n"); 1898 1899 return; 1900 fail2: 1901 pci_intr_disestablish(pc, sc->sc_ih); 1902 return; 1903 } 1904 1905 /* 1906 * Frame reception handling. This is called if there's a frame 1907 * on the receive return list. 1908 * 1909 * Note: we have to be able to handle three possibilities here: 1910 * 1) the frame is from the mini receive ring (can only happen) 1911 * on Tigon 2 boards) 1912 * 2) the frame is from the jumbo receive ring 1913 * 3) the frame is from the standard receive ring 1914 */ 1915 1916 static void 1917 ti_rxeof(struct ti_softc *sc) 1918 { 1919 struct ifnet *ifp; 1920 struct ti_cmd_desc cmd; 1921 1922 ifp = &sc->ethercom.ec_if; 1923 1924 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1925 struct ti_rx_desc *cur_rx; 1926 uint32_t rxidx; 1927 struct mbuf *m = NULL; 1928 struct ether_header *eh; 1929 bus_dmamap_t dmamap; 1930 1931 cur_rx = 1932 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1933 rxidx = cur_rx->ti_idx; 1934 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1935 1936 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1937 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1938 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1939 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1940 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1941 if_statinc(ifp, if_ierrors); 1942 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1943 continue; 1944 } 1945 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) 1946 == ENOBUFS) { 1947 if_statinc(ifp, if_ierrors); 1948 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1949 continue; 1950 } 1951 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1952 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1953 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1954 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1955 dmamap = sc->mini_dmamap[rxidx]; 1956 sc->mini_dmamap[rxidx] = 0; 1957 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1958 if_statinc(ifp, if_ierrors); 1959 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1960 continue; 1961 } 1962 if (ti_newbuf_mini(sc, sc->ti_mini, NULL, dmamap) 1963 == ENOBUFS) { 1964 if_statinc(ifp, if_ierrors); 1965 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1966 continue; 1967 } 1968 } else { 1969 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1970 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1971 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1972 dmamap = sc->std_dmamap[rxidx]; 1973 sc->std_dmamap[rxidx] = 0; 1974 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1975 if_statinc(ifp, if_ierrors); 1976 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 1977 continue; 1978 } 1979 if (ti_newbuf_std(sc, sc->ti_std, NULL, dmamap) 1980 == ENOBUFS) { 1981 if_statinc(ifp, if_ierrors); 1982 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 1983 continue; 1984 } 1985 } 1986 1987 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 1988 m_set_rcvif(m, ifp); 1989 1990 eh = mtod(m, struct ether_header *); 1991 switch (ntohs(eh->ether_type)) { 1992 #ifdef INET 1993 case ETHERTYPE_IP: 1994 { 1995 struct ip *ip = (struct ip *) (eh + 1); 1996 1997 /* 1998 * Note the Tigon firmware does not invert 1999 * the checksum for us, hence the XOR. 2000 */ 2001 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2002 if ((cur_rx->ti_ip_cksum ^ 0xffff) != 0) 2003 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2004 /* 2005 * ntohs() the constant so the compiler can 2006 * optimize... 2007 * 2008 * XXX Figure out a sane way to deal with 2009 * fragmented packets. 2010 */ 2011 if ((ip->ip_off & htons(IP_MF | IP_OFFMASK)) == 0) { 2012 switch (ip->ip_p) { 2013 case IPPROTO_TCP: 2014 m->m_pkthdr.csum_data = 2015 cur_rx->ti_tcp_udp_cksum; 2016 m->m_pkthdr.csum_flags |= 2017 M_CSUM_TCPv4 | M_CSUM_DATA; 2018 break; 2019 case IPPROTO_UDP: 2020 m->m_pkthdr.csum_data = 2021 cur_rx->ti_tcp_udp_cksum; 2022 m->m_pkthdr.csum_flags |= 2023 M_CSUM_UDPv4 | M_CSUM_DATA; 2024 break; 2025 default: 2026 /* Nothing */; 2027 } 2028 } 2029 break; 2030 } 2031 #endif 2032 default: 2033 /* Nothing. */ 2034 break; 2035 } 2036 2037 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) 2038 vlan_set_tag(m, cur_rx->ti_vlan_tag); 2039 2040 if_percpuq_enqueue(ifp->if_percpuq, m); 2041 } 2042 2043 /* Only necessary on the Tigon 1. */ 2044 if (sc->ti_hwrev == TI_HWREV_TIGON) 2045 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2046 sc->ti_rx_saved_considx); 2047 2048 TI_UPDATE_STDPROD(sc, sc->ti_std); 2049 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2050 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2051 } 2052 2053 static void 2054 ti_txeof_tigon1(struct ti_softc *sc) 2055 { 2056 struct ti_tx_desc *cur_tx = NULL; 2057 struct ifnet *ifp; 2058 struct txdmamap_pool_entry *dma; 2059 2060 ifp = &sc->ethercom.ec_if; 2061 2062 /* 2063 * Go through our tx ring and free mbufs for those 2064 * frames that have been sent. 2065 */ 2066 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2067 uint32_t idx = 0; 2068 2069 idx = sc->ti_tx_saved_considx; 2070 if (idx > 383) 2071 CSR_WRITE_4(sc, TI_WINBASE, 2072 TI_TX_RING_BASE + 6144); 2073 else if (idx > 255) 2074 CSR_WRITE_4(sc, TI_WINBASE, 2075 TI_TX_RING_BASE + 4096); 2076 else if (idx > 127) 2077 CSR_WRITE_4(sc, TI_WINBASE, 2078 TI_TX_RING_BASE + 2048); 2079 else 2080 CSR_WRITE_4(sc, TI_WINBASE, 2081 TI_TX_RING_BASE); 2082 cur_tx = &sc->ti_tx_ring_nic[idx % 128]; 2083 if (cur_tx->ti_flags & TI_BDFLAG_END) 2084 if_statinc(ifp, if_opackets); 2085 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2086 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2087 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2088 2089 dma = sc->txdma[idx]; 2090 KDASSERT(dma != NULL); 2091 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2092 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2093 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2094 2095 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2096 sc->txdma[idx] = NULL; 2097 } 2098 sc->ti_txcnt--; 2099 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2100 ifp->if_timer = 0; 2101 } 2102 2103 if (cur_tx != NULL) 2104 ifp->if_flags &= ~IFF_OACTIVE; 2105 } 2106 2107 static void 2108 ti_txeof_tigon2(struct ti_softc *sc) 2109 { 2110 struct ti_tx_desc *cur_tx = NULL; 2111 struct ifnet *ifp; 2112 struct txdmamap_pool_entry *dma; 2113 int firstidx, cnt; 2114 2115 ifp = &sc->ethercom.ec_if; 2116 2117 /* 2118 * Go through our tx ring and free mbufs for those 2119 * frames that have been sent. 2120 */ 2121 firstidx = sc->ti_tx_saved_considx; 2122 cnt = 0; 2123 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2124 uint32_t idx = 0; 2125 2126 idx = sc->ti_tx_saved_considx; 2127 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2128 if (cur_tx->ti_flags & TI_BDFLAG_END) 2129 if_statinc(ifp, if_opackets); 2130 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2131 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2132 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2133 2134 dma = sc->txdma[idx]; 2135 KDASSERT(dma != NULL); 2136 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2137 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2138 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2139 2140 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2141 sc->txdma[idx] = NULL; 2142 } 2143 cnt++; 2144 sc->ti_txcnt--; 2145 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2146 ifp->if_timer = 0; 2147 } 2148 2149 if (cnt != 0) 2150 TI_CDTXSYNC(sc, firstidx, cnt, BUS_DMASYNC_POSTWRITE); 2151 2152 if (cur_tx != NULL) 2153 ifp->if_flags &= ~IFF_OACTIVE; 2154 } 2155 2156 static int 2157 ti_intr(void *xsc) 2158 { 2159 struct ti_softc *sc; 2160 struct ifnet *ifp; 2161 2162 sc = xsc; 2163 ifp = &sc->ethercom.ec_if; 2164 2165 #ifdef notdef 2166 /* Avoid this for now -- checking this register is expensive. */ 2167 /* Make sure this is really our interrupt. */ 2168 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 2169 return (0); 2170 #endif 2171 2172 /* Ack interrupt and stop others from occurring. */ 2173 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2174 2175 if (ifp->if_flags & IFF_RUNNING) { 2176 /* Check RX return ring producer/consumer */ 2177 ti_rxeof(sc); 2178 2179 /* Check TX ring producer/consumer */ 2180 (*sc->sc_tx_eof)(sc); 2181 } 2182 2183 ti_handle_events(sc); 2184 2185 /* Re-enable interrupts. */ 2186 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2187 2188 if ((ifp->if_flags & IFF_RUNNING) != 0) 2189 if_schedule_deferred_start(ifp); 2190 2191 return (1); 2192 } 2193 2194 static void 2195 ti_stats_update(struct ti_softc *sc) 2196 { 2197 struct ifnet *ifp = &sc->ethercom.ec_if; 2198 2199 TI_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 2200 2201 uint64_t collisions = 2202 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2203 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2204 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2205 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions); 2206 if_statadd(ifp, if_collisions, collisions - sc->ti_if_collisions); 2207 sc->ti_if_collisions = collisions; 2208 2209 TI_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 2210 } 2211 2212 /* 2213 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2214 * pointers to descriptors. 2215 */ 2216 static int 2217 ti_encap_tigon1(struct ti_softc *sc, struct mbuf *m_head, uint32_t *txidx) 2218 { 2219 struct ti_tx_desc *f = NULL; 2220 uint32_t frag, cur, cnt = 0; 2221 struct txdmamap_pool_entry *dma; 2222 bus_dmamap_t dmamap; 2223 int error, i; 2224 uint16_t csum_flags = 0; 2225 2226 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2227 if (dma == NULL) { 2228 return ENOMEM; 2229 } 2230 dmamap = dma->dmamap; 2231 2232 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2233 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2234 if (error) { 2235 struct mbuf *m; 2236 int j = 0; 2237 for (m = m_head; m; m = m->m_next) 2238 j++; 2239 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2240 "error %d\n", m_head->m_pkthdr.len, j, error); 2241 return (ENOMEM); 2242 } 2243 2244 cur = frag = *txidx; 2245 2246 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2247 /* IP header checksum field must be 0! */ 2248 csum_flags |= TI_BDFLAG_IP_CKSUM; 2249 } 2250 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 2251 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2252 2253 /* XXX fragmented packet checksum capability? */ 2254 2255 /* 2256 * Start packing the mbufs in this chain into 2257 * the fragment pointers. Stop when we run out 2258 * of fragments or hit the end of the mbuf chain. 2259 */ 2260 for (i = 0; i < dmamap->dm_nsegs; i++) { 2261 if (frag > 383) 2262 CSR_WRITE_4(sc, TI_WINBASE, 2263 TI_TX_RING_BASE + 6144); 2264 else if (frag > 255) 2265 CSR_WRITE_4(sc, TI_WINBASE, 2266 TI_TX_RING_BASE + 4096); 2267 else if (frag > 127) 2268 CSR_WRITE_4(sc, TI_WINBASE, 2269 TI_TX_RING_BASE + 2048); 2270 else 2271 CSR_WRITE_4(sc, TI_WINBASE, 2272 TI_TX_RING_BASE); 2273 f = &sc->ti_tx_ring_nic[frag % 128]; 2274 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2275 break; 2276 TI_HOSTADDR(f->ti_addr, dmamap->dm_segs[i].ds_addr); 2277 f->ti_len = dmamap->dm_segs[i].ds_len; 2278 f->ti_flags = csum_flags; 2279 if (vlan_has_tag(m_head)) { 2280 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2281 f->ti_vlan_tag = vlan_get_tag(m_head); 2282 } else { 2283 f->ti_vlan_tag = 0; 2284 } 2285 /* 2286 * Sanity check: avoid coming within 16 descriptors 2287 * of the end of the ring. 2288 */ 2289 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2290 return (ENOBUFS); 2291 cur = frag; 2292 TI_INC(frag, TI_TX_RING_CNT); 2293 cnt++; 2294 } 2295 2296 if (i < dmamap->dm_nsegs) 2297 return (ENOBUFS); 2298 2299 if (frag == sc->ti_tx_saved_considx) 2300 return (ENOBUFS); 2301 2302 sc->ti_tx_ring_nic[cur % 128].ti_flags |= 2303 TI_BDFLAG_END; 2304 2305 /* Sync the packet's DMA map. */ 2306 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2307 BUS_DMASYNC_PREWRITE); 2308 2309 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2310 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 2311 sc->txdma[cur] = dma; 2312 sc->ti_txcnt += cnt; 2313 2314 *txidx = frag; 2315 2316 return (0); 2317 } 2318 2319 static int 2320 ti_encap_tigon2(struct ti_softc *sc, struct mbuf *m_head, uint32_t *txidx) 2321 { 2322 struct ti_tx_desc *f = NULL; 2323 uint32_t frag, firstfrag, cur, cnt = 0; 2324 struct txdmamap_pool_entry *dma; 2325 bus_dmamap_t dmamap; 2326 int error, i; 2327 uint16_t csum_flags = 0; 2328 2329 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2330 if (dma == NULL) { 2331 return ENOMEM; 2332 } 2333 dmamap = dma->dmamap; 2334 2335 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2336 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2337 if (error) { 2338 struct mbuf *m; 2339 int j = 0; 2340 for (m = m_head; m; m = m->m_next) 2341 j++; 2342 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2343 "error %d\n", m_head->m_pkthdr.len, j, error); 2344 return (ENOMEM); 2345 } 2346 2347 cur = firstfrag = frag = *txidx; 2348 2349 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2350 /* IP header checksum field must be 0! */ 2351 csum_flags |= TI_BDFLAG_IP_CKSUM; 2352 } 2353 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 2354 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2355 2356 /* XXX fragmented packet checksum capability? */ 2357 2358 /* 2359 * Start packing the mbufs in this chain into 2360 * the fragment pointers. Stop when we run out 2361 * of fragments or hit the end of the mbuf chain. 2362 */ 2363 for (i = 0; i < dmamap->dm_nsegs; i++) { 2364 f = &sc->ti_rdata->ti_tx_ring[frag]; 2365 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2366 break; 2367 TI_HOSTADDR(f->ti_addr, dmamap->dm_segs[i].ds_addr); 2368 f->ti_len = dmamap->dm_segs[i].ds_len; 2369 f->ti_flags = csum_flags; 2370 if (vlan_has_tag(m_head)) { 2371 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2372 f->ti_vlan_tag = vlan_get_tag(m_head); 2373 } else { 2374 f->ti_vlan_tag = 0; 2375 } 2376 /* 2377 * Sanity check: avoid coming within 16 descriptors 2378 * of the end of the ring. 2379 */ 2380 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2381 return (ENOBUFS); 2382 cur = frag; 2383 TI_INC(frag, TI_TX_RING_CNT); 2384 cnt++; 2385 } 2386 2387 if (i < dmamap->dm_nsegs) 2388 return (ENOBUFS); 2389 2390 if (frag == sc->ti_tx_saved_considx) 2391 return (ENOBUFS); 2392 2393 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2394 2395 /* Sync the packet's DMA map. */ 2396 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2397 BUS_DMASYNC_PREWRITE); 2398 2399 /* Sync the descriptors we are using. */ 2400 TI_CDTXSYNC(sc, firstfrag, cnt, BUS_DMASYNC_PREWRITE); 2401 2402 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2403 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 2404 sc->txdma[cur] = dma; 2405 sc->ti_txcnt += cnt; 2406 2407 *txidx = frag; 2408 2409 return (0); 2410 } 2411 2412 /* 2413 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2414 * to the mbuf data regions directly in the transmit descriptors. 2415 */ 2416 static void 2417 ti_start(struct ifnet *ifp) 2418 { 2419 struct ti_softc *sc; 2420 struct mbuf *m_head = NULL; 2421 uint32_t prodidx = 0; 2422 2423 sc = ifp->if_softc; 2424 2425 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2426 2427 while (sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2428 IFQ_POLL(&ifp->if_snd, m_head); 2429 if (m_head == NULL) 2430 break; 2431 2432 /* 2433 * Pack the data into the transmit ring. If we 2434 * don't have room, set the OACTIVE flag and wait 2435 * for the NIC to drain the ring. 2436 */ 2437 if ((*sc->sc_tx_encap)(sc, m_head, &prodidx)) { 2438 ifp->if_flags |= IFF_OACTIVE; 2439 break; 2440 } 2441 2442 IFQ_DEQUEUE(&ifp->if_snd, m_head); 2443 2444 /* 2445 * If there's a BPF listener, bounce a copy of this frame 2446 * to him. 2447 */ 2448 bpf_mtap(ifp, m_head, BPF_D_OUT); 2449 } 2450 2451 /* Transmit */ 2452 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2453 2454 /* Set a timeout in case the chip goes out to lunch. */ 2455 ifp->if_timer = 5; 2456 } 2457 2458 static void 2459 ti_init(void *xsc) 2460 { 2461 struct ti_softc *sc = xsc; 2462 int s; 2463 2464 s = splnet(); 2465 2466 /* Cancel pending I/O and flush buffers. */ 2467 ti_stop(sc); 2468 2469 /* Init the gen info block, ring control blocks and firmware. */ 2470 if (ti_gibinit(sc)) { 2471 aprint_error_dev(sc->sc_dev, "initialization failure\n"); 2472 splx(s); 2473 return; 2474 } 2475 2476 splx(s); 2477 } 2478 2479 static void 2480 ti_init2(struct ti_softc *sc) 2481 { 2482 struct ti_cmd_desc cmd; 2483 struct ifnet *ifp; 2484 const uint8_t *m; 2485 struct ifmedia *ifm; 2486 int tmp; 2487 2488 ifp = &sc->ethercom.ec_if; 2489 2490 /* Specify MTU and interface index. */ 2491 CSR_WRITE_4(sc, TI_GCR_IFINDEX, device_unit(sc->sc_dev)); /* ??? */ 2492 2493 tmp = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 2494 if (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2495 tmp += ETHER_VLAN_ENCAP_LEN; 2496 CSR_WRITE_4(sc, TI_GCR_IFMTU, tmp); 2497 2498 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2499 2500 /* Load our MAC address. */ 2501 m = (const uint8_t *)CLLADDR(ifp->if_sadl); 2502 CSR_WRITE_4(sc, TI_GCR_PAR0, (m[0] << 8) | m[1]); 2503 CSR_WRITE_4(sc, TI_GCR_PAR1, (m[2] << 24) | (m[3] << 16) 2504 | (m[4] << 8) | m[5]); 2505 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2506 2507 /* Enable or disable promiscuous mode as needed. */ 2508 if (ifp->if_flags & IFF_PROMISC) { 2509 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2510 } else { 2511 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2512 } 2513 2514 /* Program multicast filter. */ 2515 ti_setmulti(sc); 2516 2517 /* 2518 * If this is a Tigon 1, we should tell the 2519 * firmware to use software packet filtering. 2520 */ 2521 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2522 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2523 } 2524 2525 /* Init RX ring. */ 2526 ti_init_rx_ring_std(sc); 2527 2528 /* Init jumbo RX ring. */ 2529 if (ifp->if_mtu > (MCLBYTES - ETHER_HDR_LEN - ETHER_CRC_LEN)) 2530 ti_init_rx_ring_jumbo(sc); 2531 2532 /* 2533 * If this is a Tigon 2, we can also configure the 2534 * mini ring. 2535 */ 2536 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2537 ti_init_rx_ring_mini(sc); 2538 2539 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2540 sc->ti_rx_saved_considx = 0; 2541 2542 /* Init TX ring. */ 2543 ti_init_tx_ring(sc); 2544 2545 /* Tell firmware we're alive. */ 2546 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2547 2548 /* Enable host interrupts. */ 2549 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2550 2551 ifp->if_flags |= IFF_RUNNING; 2552 ifp->if_flags &= ~IFF_OACTIVE; 2553 2554 /* 2555 * Make sure to set media properly. We have to do this 2556 * here since we have to issue commands in order to set 2557 * the link negotiation and we can't issue commands until 2558 * the firmware is running. 2559 */ 2560 ifm = &sc->ifmedia; 2561 tmp = ifm->ifm_media; 2562 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2563 ti_ifmedia_upd(ifp); 2564 ifm->ifm_media = tmp; 2565 } 2566 2567 /* 2568 * Set media options. 2569 */ 2570 static int 2571 ti_ifmedia_upd(struct ifnet *ifp) 2572 { 2573 struct ti_softc *sc; 2574 struct ifmedia *ifm; 2575 struct ti_cmd_desc cmd; 2576 2577 sc = ifp->if_softc; 2578 ifm = &sc->ifmedia; 2579 2580 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2581 return (EINVAL); 2582 2583 switch (IFM_SUBTYPE(ifm->ifm_media)) { 2584 case IFM_AUTO: 2585 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF | TI_GLNK_1000MB | 2586 TI_GLNK_FULL_DUPLEX | TI_GLNK_RX_FLOWCTL_Y | 2587 TI_GLNK_AUTONEGENB | TI_GLNK_ENB); 2588 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB | TI_LNK_10MB | 2589 TI_LNK_FULL_DUPLEX | TI_LNK_HALF_DUPLEX | 2590 TI_LNK_AUTONEGENB | TI_LNK_ENB); 2591 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2592 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2593 break; 2594 case IFM_1000_SX: 2595 case IFM_1000_T: 2596 if ((ifm->ifm_media & IFM_FDX) != 0) { 2597 CSR_WRITE_4(sc, TI_GCR_GLINK, 2598 TI_GLNK_PREF | TI_GLNK_1000MB | TI_GLNK_FULL_DUPLEX 2599 | TI_GLNK_RX_FLOWCTL_Y | TI_GLNK_ENB); 2600 } else { 2601 CSR_WRITE_4(sc, TI_GCR_GLINK, 2602 TI_GLNK_PREF | TI_GLNK_1000MB | 2603 TI_GLNK_RX_FLOWCTL_Y | TI_GLNK_ENB); 2604 } 2605 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2606 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2607 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2608 break; 2609 case IFM_100_FX: 2610 case IFM_10_FL: 2611 case IFM_100_TX: 2612 case IFM_10_T: 2613 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2614 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB | TI_LNK_PREF); 2615 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2616 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 2617 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2618 } else { 2619 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2620 } 2621 if ((ifm->ifm_media & IFM_FDX) != 0) { 2622 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2623 } else { 2624 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2625 } 2626 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2627 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2628 break; 2629 } 2630 2631 sc->ethercom.ec_if.if_baudrate = 2632 ifmedia_baudrate(ifm->ifm_media); 2633 2634 return (0); 2635 } 2636 2637 /* 2638 * Report current media status. 2639 */ 2640 static void 2641 ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2642 { 2643 struct ti_softc *sc; 2644 uint32_t media = 0; 2645 2646 sc = ifp->if_softc; 2647 2648 ifmr->ifm_status = IFM_AVALID; 2649 ifmr->ifm_active = IFM_ETHER; 2650 2651 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2652 return; 2653 2654 ifmr->ifm_status |= IFM_ACTIVE; 2655 2656 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2657 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2658 if (sc->ti_copper) 2659 ifmr->ifm_active |= IFM_1000_T; 2660 else 2661 ifmr->ifm_active |= IFM_1000_SX; 2662 if (media & TI_GLNK_FULL_DUPLEX) 2663 ifmr->ifm_active |= IFM_FDX; 2664 else 2665 ifmr->ifm_active |= IFM_HDX; 2666 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2667 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2668 if (sc->ti_copper) { 2669 if (media & TI_LNK_100MB) 2670 ifmr->ifm_active |= IFM_100_TX; 2671 if (media & TI_LNK_10MB) 2672 ifmr->ifm_active |= IFM_10_T; 2673 } else { 2674 if (media & TI_LNK_100MB) 2675 ifmr->ifm_active |= IFM_100_FX; 2676 if (media & TI_LNK_10MB) 2677 ifmr->ifm_active |= IFM_10_FL; 2678 } 2679 if (media & TI_LNK_FULL_DUPLEX) 2680 ifmr->ifm_active |= IFM_FDX; 2681 if (media & TI_LNK_HALF_DUPLEX) 2682 ifmr->ifm_active |= IFM_HDX; 2683 } 2684 2685 sc->ethercom.ec_if.if_baudrate = 2686 ifmedia_baudrate(sc->ifmedia.ifm_media); 2687 } 2688 2689 static int 2690 ti_ether_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2691 { 2692 struct ifaddr *ifa = (struct ifaddr *)data; 2693 struct ti_softc *sc = ifp->if_softc; 2694 2695 if ((ifp->if_flags & IFF_UP) == 0) { 2696 ifp->if_flags |= IFF_UP; 2697 ti_init(sc); 2698 } 2699 2700 switch (cmd) { 2701 case SIOCINITIFADDR: 2702 2703 switch (ifa->ifa_addr->sa_family) { 2704 #ifdef INET 2705 case AF_INET: 2706 arp_ifinit(ifp, ifa); 2707 break; 2708 #endif 2709 default: 2710 break; 2711 } 2712 break; 2713 2714 default: 2715 return (EINVAL); 2716 } 2717 2718 return (0); 2719 } 2720 2721 static int 2722 ti_ioctl(struct ifnet *ifp, u_long command, void *data) 2723 { 2724 struct ti_softc *sc = ifp->if_softc; 2725 struct ifreq *ifr = (struct ifreq *)data; 2726 int s, error = 0; 2727 struct ti_cmd_desc cmd; 2728 2729 s = splnet(); 2730 2731 switch (command) { 2732 case SIOCINITIFADDR: 2733 error = ti_ether_ioctl(ifp, command, data); 2734 break; 2735 case SIOCSIFMTU: 2736 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU_JUMBO) 2737 error = EINVAL; 2738 else if ((error = ifioctl_common(ifp, command, data)) 2739 == ENETRESET) { 2740 ti_init(sc); 2741 error = 0; 2742 } 2743 break; 2744 case SIOCSIFFLAGS: 2745 if ((error = ifioctl_common(ifp, command, data)) != 0) 2746 break; 2747 if (ifp->if_flags & IFF_UP) { 2748 /* 2749 * If only the state of the PROMISC flag changed, 2750 * then just use the 'set promisc mode' command 2751 * instead of reinitializing the entire NIC. Doing 2752 * a full re-init means reloading the firmware and 2753 * waiting for it to start up, which may take a 2754 * second or two. 2755 */ 2756 if (ifp->if_flags & IFF_RUNNING && 2757 ifp->if_flags & IFF_PROMISC && 2758 !(sc->ti_if_flags & IFF_PROMISC)) { 2759 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2760 TI_CMD_CODE_PROMISC_ENB, 0); 2761 } else if (ifp->if_flags & IFF_RUNNING && 2762 !(ifp->if_flags & IFF_PROMISC) && 2763 sc->ti_if_flags & IFF_PROMISC) { 2764 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2765 TI_CMD_CODE_PROMISC_DIS, 0); 2766 } else 2767 ti_init(sc); 2768 } else { 2769 if (ifp->if_flags & IFF_RUNNING) { 2770 ti_stop(sc); 2771 } 2772 } 2773 sc->ti_if_flags = ifp->if_flags; 2774 error = 0; 2775 break; 2776 default: 2777 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 2778 break; 2779 2780 error = 0; 2781 2782 if (command == SIOCSIFCAP) 2783 ti_init(sc); 2784 else if (command != SIOCADDMULTI && command != SIOCDELMULTI) 2785 ; 2786 else if (ifp->if_flags & IFF_RUNNING) 2787 ti_setmulti(sc); 2788 break; 2789 } 2790 2791 (void)splx(s); 2792 2793 return (error); 2794 } 2795 2796 static void 2797 ti_watchdog(struct ifnet *ifp) 2798 { 2799 struct ti_softc *sc; 2800 2801 sc = ifp->if_softc; 2802 2803 aprint_error_dev(sc->sc_dev, "watchdog timeout -- resetting\n"); 2804 ti_stop(sc); 2805 ti_init(sc); 2806 2807 if_statinc(ifp, if_oerrors); 2808 } 2809 2810 /* 2811 * Stop the adapter and free any mbufs allocated to the 2812 * RX and TX lists. 2813 */ 2814 static void 2815 ti_stop(struct ti_softc *sc) 2816 { 2817 struct ifnet *ifp; 2818 struct ti_cmd_desc cmd; 2819 2820 ifp = &sc->ethercom.ec_if; 2821 2822 /* Disable host interrupts. */ 2823 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2824 /* 2825 * Tell firmware we're shutting down. 2826 */ 2827 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2828 2829 /* Halt and reinitialize. */ 2830 ti_chipinit(sc); 2831 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2832 ti_chipinit(sc); 2833 2834 /* Free the RX lists. */ 2835 ti_free_rx_ring_std(sc); 2836 2837 /* Free jumbo RX list. */ 2838 ti_free_rx_ring_jumbo(sc); 2839 2840 /* Free mini RX list. */ 2841 ti_free_rx_ring_mini(sc); 2842 2843 /* Free TX buffers. */ 2844 ti_free_tx_ring(sc); 2845 2846 sc->ti_ev_prodidx.ti_idx = 0; 2847 sc->ti_return_prodidx.ti_idx = 0; 2848 sc->ti_tx_considx.ti_idx = 0; 2849 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2850 2851 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2852 } 2853 2854 /* 2855 * Stop all chip I/O so that the kernel's probe routines don't 2856 * get confused by errant DMAs when rebooting. 2857 */ 2858 static bool 2859 ti_shutdown(device_t self, int howto) 2860 { 2861 struct ti_softc *sc; 2862 2863 sc = device_private(self); 2864 ti_chipinit(sc); 2865 2866 return true; 2867 } 2868