1 /* $NetBSD: if_ti.c,v 1.122 2021/11/10 16:17:34 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_ti.c,v 1.15 1999/08/14 15:45:03 wpaul Exp 35 */ 36 37 /* 38 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 39 * Manuals, sample driver and firmware source kits are available 40 * from http://www.alteon.com/support/openkits. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 49 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 50 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 51 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 52 * filtering and jumbo (9014 byte) frames. The hardware is largely 53 * controlled by firmware, which must be loaded into the NIC during 54 * initialization. 55 * 56 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 57 * revision, which supports new features such as extended commands, 58 * extended jumbo receive ring descriptors and a mini receive ring. 59 * 60 * Alteon Networks is to be commended for releasing such a vast amount 61 * of development material for the Tigon NIC without requiring an NDA 62 * (although they really should have done it a long time ago). With 63 * any luck, the other vendors will finally wise up and follow Alteon's 64 * stellar example. 65 * 66 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 67 * this driver by #including it as a C header file. This bloats the 68 * driver somewhat, but it's the easiest method considering that the 69 * driver code and firmware code need to be kept in sync. The source 70 * for the firmware is not provided with the FreeBSD distribution since 71 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 72 * 73 * The following people deserve special thanks: 74 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 75 * for testing 76 * - Raymond Lee of Netgear, for providing a pair of Netgear 77 * GA620 Tigon 2 boards for testing 78 * - Ulf Zimmermann, for bringing the GA620 to my attention and 79 * convincing me to write this driver. 80 * - Andrew Gallatin for providing FreeBSD/Alpha support. 81 */ 82 83 #include <sys/cdefs.h> 84 __KERNEL_RCSID(0, "$NetBSD: if_ti.c,v 1.122 2021/11/10 16:17:34 msaitoh Exp $"); 85 86 #include "opt_inet.h" 87 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/socket.h> 95 #include <sys/queue.h> 96 #include <sys/device.h> 97 #include <sys/reboot.h> 98 99 #include <net/if.h> 100 #include <net/if_arp.h> 101 #include <net/if_ether.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 105 #include <net/bpf.h> 106 107 #ifdef INET 108 #include <netinet/in.h> 109 #include <netinet/if_inarp.h> 110 #include <netinet/in_systm.h> 111 #include <netinet/ip.h> 112 #endif 113 114 115 #include <sys/bus.h> 116 117 #include <dev/pci/pcireg.h> 118 #include <dev/pci/pcivar.h> 119 #include <dev/pci/pcidevs.h> 120 121 #include <dev/pci/if_tireg.h> 122 123 #include <dev/microcode/tigon/ti_fw.h> 124 #include <dev/microcode/tigon/ti_fw2.h> 125 126 /* 127 * Various supported device vendors/types and their names. 128 */ 129 130 static const struct ti_type ti_devs[] = { 131 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC, 132 "Alteon AceNIC 1000BASE-SX Ethernet" }, 133 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC_COPPER, 134 "Alteon AceNIC 1000BASE-T Ethernet" }, 135 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C985, 136 "3Com 3c985-SX Gigabit Ethernet" }, 137 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620, 138 "Netgear GA620 1000BASE-SX Ethernet" }, 139 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620T, 140 "Netgear GA620 1000BASE-T Ethernet" }, 141 { PCI_VENDOR_SGI, PCI_PRODUCT_SGI_TIGON, 142 "Silicon Graphics Gigabit Ethernet" }, 143 { PCI_VENDOR_DEC, PCI_PRODUCT_DEC_PN9000SX, 144 "Farallon PN9000SX Gigabit Ethernet" }, 145 { 0, 0, NULL } 146 }; 147 148 static const struct ti_type *ti_type_match(struct pci_attach_args *); 149 static int ti_probe(device_t, cfdata_t, void *); 150 static void ti_attach(device_t, device_t, void *); 151 static bool ti_shutdown(device_t, int); 152 static void ti_txeof_tigon1(struct ti_softc *); 153 static void ti_txeof_tigon2(struct ti_softc *); 154 static void ti_rxeof(struct ti_softc *); 155 156 static void ti_stats_update(struct ti_softc *); 157 static int ti_encap_tigon1(struct ti_softc *, struct mbuf *, uint32_t *); 158 static int ti_encap_tigon2(struct ti_softc *, struct mbuf *, uint32_t *); 159 160 static int ti_intr(void *); 161 static void ti_start(struct ifnet *); 162 static int ti_ioctl(struct ifnet *, u_long, void *); 163 static void ti_init(void *); 164 static void ti_init2(struct ti_softc *); 165 static void ti_stop(struct ti_softc *); 166 static void ti_watchdog(struct ifnet *); 167 static int ti_ifmedia_upd(struct ifnet *); 168 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *); 169 170 static uint32_t ti_eeprom_putbyte(struct ti_softc *, int); 171 static uint8_t ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *); 172 static int ti_read_eeprom(struct ti_softc *, void *, int, int); 173 174 static void ti_add_mcast(struct ti_softc *, struct ether_addr *); 175 static void ti_del_mcast(struct ti_softc *, struct ether_addr *); 176 static void ti_setmulti(struct ti_softc *); 177 178 static void ti_mem(struct ti_softc *, uint32_t, uint32_t, const void *); 179 static void ti_loadfw(struct ti_softc *); 180 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *); 181 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, void *, int); 182 static void ti_handle_events(struct ti_softc *); 183 static int ti_alloc_jumbo_mem(struct ti_softc *); 184 static void *ti_jalloc(struct ti_softc *); 185 static void ti_jfree(struct mbuf *, void *, size_t, void *); 186 static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *, bus_dmamap_t); 187 static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *, bus_dmamap_t); 188 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *); 189 static int ti_init_rx_ring_std(struct ti_softc *); 190 static void ti_free_rx_ring_std(struct ti_softc *); 191 static int ti_init_rx_ring_jumbo(struct ti_softc *); 192 static void ti_free_rx_ring_jumbo(struct ti_softc *); 193 static int ti_init_rx_ring_mini(struct ti_softc *); 194 static void ti_free_rx_ring_mini(struct ti_softc *); 195 static void ti_free_tx_ring(struct ti_softc *); 196 static int ti_init_tx_ring(struct ti_softc *); 197 198 static int ti_64bitslot_war(struct ti_softc *); 199 static int ti_chipinit(struct ti_softc *); 200 static int ti_gibinit(struct ti_softc *); 201 202 static int ti_ether_ioctl(struct ifnet *, u_long, void *); 203 204 CFATTACH_DECL_NEW(ti, sizeof(struct ti_softc), 205 ti_probe, ti_attach, NULL, NULL); 206 207 /* 208 * Send an instruction or address to the EEPROM, check for ACK. 209 */ 210 static uint32_t 211 ti_eeprom_putbyte(struct ti_softc *sc, int byte) 212 { 213 int i, ack = 0; 214 215 /* 216 * Make sure we're in TX mode. 217 */ 218 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 219 220 /* 221 * Feed in each bit and strobe the clock. 222 */ 223 for (i = 0x80; i; i >>= 1) { 224 if (byte & i) { 225 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 226 } else { 227 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 228 } 229 DELAY(1); 230 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 231 DELAY(1); 232 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 233 } 234 235 /* 236 * Turn off TX mode. 237 */ 238 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 239 240 /* 241 * Check for ack. 242 */ 243 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 244 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 245 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 246 247 return (ack); 248 } 249 250 /* 251 * Read a byte of data stored in the EEPROM at address 'addr.' 252 * We have to send two address bytes since the EEPROM can hold 253 * more than 256 bytes of data. 254 */ 255 static uint8_t 256 ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest) 257 { 258 int i; 259 uint8_t byte = 0; 260 261 EEPROM_START(); 262 263 /* 264 * Send write control code to EEPROM. 265 */ 266 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 267 printf("%s: failed to send write command, status: %x\n", 268 device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 269 return (1); 270 } 271 272 /* 273 * Send first byte of address of byte we want to read. 274 */ 275 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 276 printf("%s: failed to send address, status: %x\n", 277 device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 278 return (1); 279 } 280 /* 281 * Send second byte address of byte we want to read. 282 */ 283 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 284 printf("%s: failed to send address, status: %x\n", 285 device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 286 return (1); 287 } 288 289 EEPROM_STOP(); 290 EEPROM_START(); 291 /* 292 * Send read control code to EEPROM. 293 */ 294 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 295 printf("%s: failed to send read command, status: %x\n", 296 device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 297 return (1); 298 } 299 300 /* 301 * Start reading bits from EEPROM. 302 */ 303 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 304 for (i = 0x80; i; i >>= 1) { 305 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 306 DELAY(1); 307 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 308 byte |= i; 309 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 310 DELAY(1); 311 } 312 313 EEPROM_STOP(); 314 315 /* 316 * No ACK generated for read, so just return byte. 317 */ 318 319 *dest = byte; 320 321 return (0); 322 } 323 324 /* 325 * Read a sequence of bytes from the EEPROM. 326 */ 327 static int 328 ti_read_eeprom(struct ti_softc *sc, void *destv, int off, int cnt) 329 { 330 char *dest = destv; 331 int err = 0, i; 332 uint8_t byte = 0; 333 334 for (i = 0; i < cnt; i++) { 335 err = ti_eeprom_getbyte(sc, off + i, &byte); 336 if (err) 337 break; 338 *(dest + i) = byte; 339 } 340 341 return (err ? 1 : 0); 342 } 343 344 /* 345 * NIC memory access function. Can be used to either clear a section 346 * of NIC local memory or (if tbuf is non-NULL) copy data into it. 347 */ 348 static void 349 ti_mem(struct ti_softc *sc, uint32_t addr, uint32_t len, const void *xbuf) 350 { 351 int segptr, segsize, cnt; 352 const void *ptr; 353 354 segptr = addr; 355 cnt = len; 356 ptr = xbuf; 357 358 while (cnt) { 359 if (cnt < TI_WINLEN) 360 segsize = cnt; 361 else 362 segsize = TI_WINLEN - (segptr % TI_WINLEN); 363 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 364 if (xbuf == NULL) { 365 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 366 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, 367 segsize / 4); 368 } else { 369 #ifdef __BUS_SPACE_HAS_STREAM_METHODS 370 bus_space_write_region_stream_4(sc->ti_btag, 371 sc->ti_bhandle, 372 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 373 (const uint32_t *)ptr, segsize / 4); 374 #else 375 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 376 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 377 (const uint32_t *)ptr, segsize / 4); 378 #endif 379 ptr = (const char *)ptr + segsize; 380 } 381 segptr += segsize; 382 cnt -= segsize; 383 } 384 385 return; 386 } 387 388 /* 389 * Load firmware image into the NIC. Check that the firmware revision 390 * is acceptable and see if we want the firmware for the Tigon 1 or 391 * Tigon 2. 392 */ 393 static void 394 ti_loadfw(struct ti_softc *sc) 395 { 396 switch (sc->ti_hwrev) { 397 case TI_HWREV_TIGON: 398 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 399 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 400 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 401 printf("%s: firmware revision mismatch; want " 402 "%d.%d.%d, got %d.%d.%d\n", device_xname(sc->sc_dev), 403 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 404 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 405 tigonFwReleaseMinor, tigonFwReleaseFix); 406 return; 407 } 408 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText); 409 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData); 410 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, tigonFwRodata); 411 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 412 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 413 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 414 break; 415 case TI_HWREV_TIGON_II: 416 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 417 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 418 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 419 printf("%s: firmware revision mismatch; want " 420 "%d.%d.%d, got %d.%d.%d\n", device_xname(sc->sc_dev), 421 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 422 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 423 tigon2FwReleaseMinor, tigon2FwReleaseFix); 424 return; 425 } 426 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, tigon2FwText); 427 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, tigon2FwData); 428 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 429 tigon2FwRodata); 430 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 431 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 432 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 433 break; 434 default: 435 printf("%s: can't load firmware: unknown hardware rev\n", 436 device_xname(sc->sc_dev)); 437 break; 438 } 439 440 return; 441 } 442 443 /* 444 * Send the NIC a command via the command ring. 445 */ 446 static void 447 ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd) 448 { 449 uint32_t index; 450 451 index = sc->ti_cmd_saved_prodidx; 452 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 453 TI_INC(index, TI_CMD_RING_CNT); 454 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 455 sc->ti_cmd_saved_prodidx = index; 456 } 457 458 /* 459 * Send the NIC an extended command. The 'len' parameter specifies the 460 * number of command slots to include after the initial command. 461 */ 462 static void 463 ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, void *argv, int len) 464 { 465 char *arg = argv; 466 uint32_t index; 467 int i; 468 469 index = sc->ti_cmd_saved_prodidx; 470 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd)); 471 TI_INC(index, TI_CMD_RING_CNT); 472 for (i = 0; i < len; i++) { 473 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 474 *(uint32_t *)(&arg[i * 4])); 475 TI_INC(index, TI_CMD_RING_CNT); 476 } 477 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 478 sc->ti_cmd_saved_prodidx = index; 479 } 480 481 /* 482 * Handle events that have triggered interrupts. 483 */ 484 static void 485 ti_handle_events(struct ti_softc *sc) 486 { 487 struct ti_event_desc *e; 488 489 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 490 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 491 switch (TI_EVENT_EVENT(e)) { 492 case TI_EV_LINKSTAT_CHANGED: 493 sc->ti_linkstat = TI_EVENT_CODE(e); 494 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) 495 printf("%s: 10/100 link up\n", 496 device_xname(sc->sc_dev)); 497 else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) 498 printf("%s: gigabit link up\n", 499 device_xname(sc->sc_dev)); 500 else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 501 printf("%s: link down\n", 502 device_xname(sc->sc_dev)); 503 break; 504 case TI_EV_ERROR: 505 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD) 506 printf("%s: invalid command\n", 507 device_xname(sc->sc_dev)); 508 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD) 509 printf("%s: unknown command\n", 510 device_xname(sc->sc_dev)); 511 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG) 512 printf("%s: bad config data\n", 513 device_xname(sc->sc_dev)); 514 break; 515 case TI_EV_FIRMWARE_UP: 516 ti_init2(sc); 517 break; 518 case TI_EV_STATS_UPDATED: 519 ti_stats_update(sc); 520 break; 521 case TI_EV_RESET_JUMBO_RING: 522 case TI_EV_MCAST_UPDATED: 523 /* Who cares. */ 524 break; 525 default: 526 printf("%s: unknown event: %d\n", 527 device_xname(sc->sc_dev), TI_EVENT_EVENT(e)); 528 break; 529 } 530 /* Advance the consumer index. */ 531 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 532 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 533 } 534 535 return; 536 } 537 538 /* 539 * Memory management for the jumbo receive ring is a pain in the 540 * butt. We need to allocate at least 9018 bytes of space per frame, 541 * _and_ it has to be contiguous (unless you use the extended 542 * jumbo descriptor format). Using malloc() all the time won't 543 * work: malloc() allocates memory in powers of two, which means we 544 * would end up wasting a considerable amount of space by allocating 545 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 546 * to do our own memory management. 547 * 548 * The driver needs to allocate a contiguous chunk of memory at boot 549 * time. We then chop this up ourselves into 9K pieces and use them 550 * as external mbuf storage. 551 * 552 * One issue here is how much memory to allocate. The jumbo ring has 553 * 256 slots in it, but at 9K per slot than can consume over 2MB of 554 * RAM. This is a bit much, especially considering we also need 555 * RAM for the standard ring and mini ring (on the Tigon 2). To 556 * save space, we only actually allocate enough memory for 64 slots 557 * by default, which works out to between 500 and 600K. This can 558 * be tuned by changing a #define in if_tireg.h. 559 */ 560 561 static int 562 ti_alloc_jumbo_mem(struct ti_softc *sc) 563 { 564 char *ptr; 565 int i; 566 struct ti_jpool_entry *entry; 567 bus_dma_segment_t dmaseg; 568 int error, dmanseg; 569 570 /* Grab a big chunk o' storage. */ 571 if ((error = bus_dmamem_alloc(sc->sc_dmat, 572 TI_JMEM, PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 573 BUS_DMA_NOWAIT)) != 0) { 574 aprint_error_dev(sc->sc_dev, 575 "can't allocate jumbo buffer, error = %d\n", error); 576 return (error); 577 } 578 579 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 580 TI_JMEM, (void **)&sc->ti_cdata.ti_jumbo_buf, 581 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 582 aprint_error_dev(sc->sc_dev, 583 "can't map jumbo buffer, error = %d\n", error); 584 return (error); 585 } 586 587 if ((error = bus_dmamap_create(sc->sc_dmat, 588 TI_JMEM, 1, 589 TI_JMEM, 0, BUS_DMA_NOWAIT, 590 &sc->jumbo_dmamap)) != 0) { 591 aprint_error_dev(sc->sc_dev, 592 "can't create jumbo buffer DMA map, error = %d\n", error); 593 return (error); 594 } 595 596 if ((error = bus_dmamap_load(sc->sc_dmat, sc->jumbo_dmamap, 597 sc->ti_cdata.ti_jumbo_buf, TI_JMEM, NULL, 598 BUS_DMA_NOWAIT)) != 0) { 599 aprint_error_dev(sc->sc_dev, 600 "can't load jumbo buffer DMA map, error = %d\n", error); 601 return (error); 602 } 603 sc->jumbo_dmaaddr = sc->jumbo_dmamap->dm_segs[0].ds_addr; 604 605 SIMPLEQ_INIT(&sc->ti_jfree_listhead); 606 SIMPLEQ_INIT(&sc->ti_jinuse_listhead); 607 608 /* 609 * Now divide it up into 9K pieces and save the addresses 610 * in an array. 611 */ 612 ptr = sc->ti_cdata.ti_jumbo_buf; 613 for (i = 0; i < TI_JSLOTS; i++) { 614 sc->ti_cdata.ti_jslots[i] = ptr; 615 ptr += TI_JLEN; 616 entry = malloc(sizeof(struct ti_jpool_entry), 617 M_DEVBUF, M_WAITOK); 618 entry->slot = i; 619 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, 620 jpool_entries); 621 } 622 623 return (0); 624 } 625 626 /* 627 * Allocate a jumbo buffer. 628 */ 629 static void * 630 ti_jalloc(struct ti_softc *sc) 631 { 632 struct ti_jpool_entry *entry; 633 634 entry = SIMPLEQ_FIRST(&sc->ti_jfree_listhead); 635 636 if (entry == NULL) { 637 printf("%s: no free jumbo buffers\n", device_xname(sc->sc_dev)); 638 return (NULL); 639 } 640 641 SIMPLEQ_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries); 642 SIMPLEQ_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 643 644 return (sc->ti_cdata.ti_jslots[entry->slot]); 645 } 646 647 /* 648 * Release a jumbo buffer. 649 */ 650 static void 651 ti_jfree(struct mbuf *m, void *tbuf, size_t size, void *arg) 652 { 653 struct ti_softc *sc; 654 int i, s; 655 struct ti_jpool_entry *entry; 656 657 /* Extract the softc struct pointer. */ 658 sc = (struct ti_softc *)arg; 659 660 if (sc == NULL) 661 panic("ti_jfree: didn't get softc pointer!"); 662 663 /* calculate the slot this buffer belongs to */ 664 665 i = ((char *)tbuf 666 - (char *)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 667 668 if ((i < 0) || (i >= TI_JSLOTS)) 669 panic("ti_jfree: asked to free buffer that we don't manage!"); 670 671 s = splvm(); 672 entry = SIMPLEQ_FIRST(&sc->ti_jinuse_listhead); 673 if (entry == NULL) 674 panic("ti_jfree: buffer not in use!"); 675 entry->slot = i; 676 SIMPLEQ_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries); 677 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 678 679 if (__predict_true(m != NULL)) 680 pool_cache_put(mb_cache, m); 681 splx(s); 682 } 683 684 685 /* 686 * Initialize a standard receive ring descriptor. 687 */ 688 static int 689 ti_newbuf_std(struct ti_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap) 690 { 691 struct mbuf *m_new = NULL; 692 struct ti_rx_desc *r; 693 int error; 694 695 if (dmamap == NULL) { 696 /* if (m) panic() */ 697 698 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 699 MCLBYTES, 0, BUS_DMA_NOWAIT, 700 &dmamap)) != 0) { 701 aprint_error_dev(sc->sc_dev, 702 "can't create recv map, error = %d\n", error); 703 return (ENOMEM); 704 } 705 } 706 sc->std_dmamap[i] = dmamap; 707 708 if (m == NULL) { 709 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 710 if (m_new == NULL) { 711 aprint_error_dev(sc->sc_dev, 712 "mbuf allocation failed -- packet dropped!\n"); 713 return (ENOBUFS); 714 } 715 716 MCLGET(m_new, M_DONTWAIT); 717 if (!(m_new->m_flags & M_EXT)) { 718 aprint_error_dev(sc->sc_dev, 719 "cluster allocation failed -- packet dropped!\n"); 720 m_freem(m_new); 721 return (ENOBUFS); 722 } 723 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 724 m_adj(m_new, ETHER_ALIGN); 725 726 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 727 mtod(m_new, void *), m_new->m_len, NULL, 728 BUS_DMA_READ | BUS_DMA_NOWAIT)) != 0) { 729 aprint_error_dev(sc->sc_dev, 730 "can't load recv map, error = %d\n", error); 731 m_freem(m_new); 732 return (ENOMEM); 733 } 734 } else { 735 m_new = m; 736 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 737 m_new->m_data = m_new->m_ext.ext_buf; 738 m_adj(m_new, ETHER_ALIGN); 739 740 /* reuse the dmamap */ 741 } 742 743 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 744 r = &sc->ti_rdata->ti_rx_std_ring[i]; 745 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 746 r->ti_type = TI_BDTYPE_RECV_BD; 747 r->ti_flags = 0; 748 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx) 749 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 750 if (sc->ethercom.ec_if.if_capenable & 751 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 752 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 753 r->ti_len = m_new->m_len; /* == ds_len */ 754 r->ti_idx = i; 755 756 return (0); 757 } 758 759 /* 760 * Initialize a mini receive ring descriptor. This only applies to 761 * the Tigon 2. 762 */ 763 static int 764 ti_newbuf_mini(struct ti_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap) 765 { 766 struct mbuf *m_new = NULL; 767 struct ti_rx_desc *r; 768 int error; 769 770 if (dmamap == NULL) { 771 /* if (m) panic() */ 772 773 if ((error = bus_dmamap_create(sc->sc_dmat, MHLEN, 1, 774 MHLEN, 0, BUS_DMA_NOWAIT, 775 &dmamap)) != 0) { 776 aprint_error_dev(sc->sc_dev, 777 "can't create recv map, error = %d\n", error); 778 return (ENOMEM); 779 } 780 } 781 sc->mini_dmamap[i] = dmamap; 782 783 if (m == NULL) { 784 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 785 if (m_new == NULL) { 786 aprint_error_dev(sc->sc_dev, 787 "mbuf allocation failed -- packet dropped!\n"); 788 return (ENOBUFS); 789 } 790 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 791 m_adj(m_new, ETHER_ALIGN); 792 793 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 794 mtod(m_new, void *), m_new->m_len, NULL, 795 BUS_DMA_READ | BUS_DMA_NOWAIT)) != 0) { 796 aprint_error_dev(sc->sc_dev, 797 "can't load recv map, error = %d\n", error); 798 m_freem(m_new); 799 return (ENOMEM); 800 } 801 } else { 802 m_new = m; 803 m_new->m_data = m_new->m_pktdat; 804 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 805 m_adj(m_new, ETHER_ALIGN); 806 807 /* reuse the dmamap */ 808 } 809 810 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 811 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 812 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 813 r->ti_type = TI_BDTYPE_RECV_BD; 814 r->ti_flags = TI_BDFLAG_MINI_RING; 815 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx) 816 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 817 if (sc->ethercom.ec_if.if_capenable & 818 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 819 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 820 r->ti_len = m_new->m_len; /* == ds_len */ 821 r->ti_idx = i; 822 823 return (0); 824 } 825 826 /* 827 * Initialize a jumbo receive ring descriptor. This allocates 828 * a jumbo buffer from the pool managed internally by the driver. 829 */ 830 static int 831 ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *m) 832 { 833 struct mbuf *m_new = NULL; 834 struct ti_rx_desc *r; 835 836 if (m == NULL) { 837 void * tbuf = NULL; 838 839 /* Allocate the mbuf. */ 840 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 841 if (m_new == NULL) { 842 aprint_error_dev(sc->sc_dev, 843 "mbuf allocation failed -- packet dropped!\n"); 844 return (ENOBUFS); 845 } 846 847 /* Allocate the jumbo buffer */ 848 tbuf = ti_jalloc(sc); 849 if (tbuf == NULL) { 850 m_freem(m_new); 851 aprint_error_dev(sc->sc_dev, 852 "jumbo allocation failed -- packet dropped!\n"); 853 return (ENOBUFS); 854 } 855 856 /* Attach the buffer to the mbuf. */ 857 MEXTADD(m_new, tbuf, ETHER_MAX_LEN_JUMBO, 858 M_DEVBUF, ti_jfree, sc); 859 m_new->m_flags |= M_EXT_RW; 860 m_new->m_len = m_new->m_pkthdr.len = ETHER_MAX_LEN_JUMBO; 861 } else { 862 m_new = m; 863 m_new->m_data = m_new->m_ext.ext_buf; 864 m_new->m_ext.ext_size = ETHER_MAX_LEN_JUMBO; 865 } 866 867 m_adj(m_new, ETHER_ALIGN); 868 /* Set up the descriptor. */ 869 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 870 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 871 TI_HOSTADDR(r->ti_addr) = sc->jumbo_dmaaddr + 872 (mtod(m_new, char *) - (char *)sc->ti_cdata.ti_jumbo_buf); 873 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 874 r->ti_flags = TI_BDFLAG_JUMBO_RING; 875 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx) 876 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 877 if (sc->ethercom.ec_if.if_capenable & 878 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 879 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 880 r->ti_len = m_new->m_len; 881 r->ti_idx = i; 882 883 return (0); 884 } 885 886 /* 887 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 888 * that's 1MB or memory, which is a lot. For now, we fill only the first 889 * 256 ring entries and hope that our CPU is fast enough to keep up with 890 * the NIC. 891 */ 892 static int 893 ti_init_rx_ring_std(struct ti_softc *sc) 894 { 895 int i; 896 struct ti_cmd_desc cmd; 897 898 for (i = 0; i < TI_SSLOTS; i++) { 899 if (ti_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 900 return (ENOBUFS); 901 } 902 903 TI_UPDATE_STDPROD(sc, i - 1); 904 sc->ti_std = i - 1; 905 906 return (0); 907 } 908 909 static void 910 ti_free_rx_ring_std(struct ti_softc *sc) 911 { 912 int i; 913 914 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 915 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 916 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 917 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 918 919 /* if (sc->std_dmamap[i] == 0) panic() */ 920 bus_dmamap_destroy(sc->sc_dmat, sc->std_dmamap[i]); 921 sc->std_dmamap[i] = 0; 922 } 923 memset((char *)&sc->ti_rdata->ti_rx_std_ring[i], 0, 924 sizeof(struct ti_rx_desc)); 925 } 926 927 return; 928 } 929 930 static int 931 ti_init_rx_ring_jumbo(struct ti_softc *sc) 932 { 933 int i; 934 struct ti_cmd_desc cmd; 935 936 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 937 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 938 return (ENOBUFS); 939 } 940 941 TI_UPDATE_JUMBOPROD(sc, i - 1); 942 sc->ti_jumbo = i - 1; 943 944 return (0); 945 } 946 947 static void 948 ti_free_rx_ring_jumbo(struct ti_softc *sc) 949 { 950 int i; 951 952 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 953 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 954 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 955 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 956 } 957 memset((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 0, 958 sizeof(struct ti_rx_desc)); 959 } 960 961 return; 962 } 963 964 static int 965 ti_init_rx_ring_mini(struct ti_softc *sc) 966 { 967 int i; 968 969 for (i = 0; i < TI_MSLOTS; i++) { 970 if (ti_newbuf_mini(sc, i, NULL, 0) == ENOBUFS) 971 return (ENOBUFS); 972 } 973 974 TI_UPDATE_MINIPROD(sc, i - 1); 975 sc->ti_mini = i - 1; 976 977 return (0); 978 } 979 980 static void 981 ti_free_rx_ring_mini(struct ti_softc *sc) 982 { 983 int i; 984 985 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 986 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 987 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 988 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 989 990 /* if (sc->mini_dmamap[i] == 0) panic() */ 991 bus_dmamap_destroy(sc->sc_dmat, sc->mini_dmamap[i]); 992 sc->mini_dmamap[i] = 0; 993 } 994 memset((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 0, 995 sizeof(struct ti_rx_desc)); 996 } 997 998 return; 999 } 1000 1001 static void 1002 ti_free_tx_ring(struct ti_softc *sc) 1003 { 1004 int i; 1005 struct txdmamap_pool_entry *dma; 1006 1007 for (i = 0; i < TI_TX_RING_CNT; i++) { 1008 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1009 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1010 sc->ti_cdata.ti_tx_chain[i] = NULL; 1011 1012 /* if (sc->txdma[i] == 0) panic() */ 1013 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1014 link); 1015 sc->txdma[i] = 0; 1016 } 1017 memset((char *)&sc->ti_rdata->ti_tx_ring[i], 0, 1018 sizeof(struct ti_tx_desc)); 1019 } 1020 1021 while ((dma = SIMPLEQ_FIRST(&sc->txdma_list))) { 1022 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 1023 bus_dmamap_destroy(sc->sc_dmat, dma->dmamap); 1024 free(dma, M_DEVBUF); 1025 } 1026 1027 return; 1028 } 1029 1030 static int 1031 ti_init_tx_ring(struct ti_softc *sc) 1032 { 1033 int i, error; 1034 bus_dmamap_t dmamap; 1035 struct txdmamap_pool_entry *dma; 1036 1037 sc->ti_txcnt = 0; 1038 sc->ti_tx_saved_considx = 0; 1039 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1040 1041 SIMPLEQ_INIT(&sc->txdma_list); 1042 for (i = 0; i < TI_RSLOTS; i++) { 1043 /* I've seen mbufs with 30 fragments. */ 1044 if ((error = bus_dmamap_create(sc->sc_dmat, 1045 ETHER_MAX_LEN_JUMBO, 40, ETHER_MAX_LEN_JUMBO, 0, 1046 BUS_DMA_NOWAIT, &dmamap)) != 0) { 1047 aprint_error_dev(sc->sc_dev, 1048 "can't create tx map, error = %d\n", error); 1049 return (ENOMEM); 1050 } 1051 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1052 if (!dma) { 1053 aprint_error_dev(sc->sc_dev, 1054 "can't alloc txdmamap_pool_entry\n"); 1055 bus_dmamap_destroy(sc->sc_dmat, dmamap); 1056 return (ENOMEM); 1057 } 1058 dma->dmamap = dmamap; 1059 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 1060 } 1061 1062 return (0); 1063 } 1064 1065 /* 1066 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1067 * but we have to support the old way too so that Tigon 1 cards will 1068 * work. 1069 */ 1070 static void 1071 ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr) 1072 { 1073 struct ti_cmd_desc cmd; 1074 uint16_t *m; 1075 uint32_t ext[2] = {0, 0}; 1076 1077 m = (uint16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1078 1079 switch (sc->ti_hwrev) { 1080 case TI_HWREV_TIGON: 1081 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1082 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1083 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1084 break; 1085 case TI_HWREV_TIGON_II: 1086 ext[0] = htons(m[0]); 1087 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1088 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (void *)&ext, 2); 1089 break; 1090 default: 1091 printf("%s: unknown hwrev\n", device_xname(sc->sc_dev)); 1092 break; 1093 } 1094 1095 return; 1096 } 1097 1098 static void 1099 ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr) 1100 { 1101 struct ti_cmd_desc cmd; 1102 uint16_t *m; 1103 uint32_t ext[2] = {0, 0}; 1104 1105 m = (uint16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1106 1107 switch (sc->ti_hwrev) { 1108 case TI_HWREV_TIGON: 1109 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1110 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1111 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1112 break; 1113 case TI_HWREV_TIGON_II: 1114 ext[0] = htons(m[0]); 1115 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1116 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (void *)&ext, 2); 1117 break; 1118 default: 1119 printf("%s: unknown hwrev\n", device_xname(sc->sc_dev)); 1120 break; 1121 } 1122 1123 return; 1124 } 1125 1126 /* 1127 * Configure the Tigon's multicast address filter. 1128 * 1129 * The actual multicast table management is a bit of a pain, thanks to 1130 * slight brain damage on the part of both Alteon and us. With our 1131 * multicast code, we are only alerted when the multicast address table 1132 * changes and at that point we only have the current list of addresses: 1133 * we only know the current state, not the previous state, so we don't 1134 * actually know what addresses were removed or added. The firmware has 1135 * state, but we can't get our grubby mits on it, and there is no 'delete 1136 * all multicast addresses' command. Hence, we have to maintain our own 1137 * state so we know what addresses have been programmed into the NIC at 1138 * any given time. 1139 */ 1140 static void 1141 ti_setmulti(struct ti_softc *sc) 1142 { 1143 struct ethercom *ec = &sc->ethercom; 1144 struct ifnet *ifp = &ec->ec_if; 1145 struct ti_cmd_desc cmd; 1146 struct ti_mc_entry *mc; 1147 uint32_t intrs; 1148 struct ether_multi *enm; 1149 struct ether_multistep step; 1150 1151 /* Disable interrupts. */ 1152 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1153 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1154 1155 /* First, zot all the existing filters. */ 1156 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1157 ti_del_mcast(sc, &mc->mc_addr); 1158 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1159 free(mc, M_DEVBUF); 1160 } 1161 1162 /* 1163 * Remember all multicast addresses so that we can delete them 1164 * later. Punt if there is a range of addresses or memory shortage. 1165 */ 1166 ETHER_LOCK(ec); 1167 ETHER_FIRST_MULTI(step, ec, enm); 1168 while (enm != NULL) { 1169 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1170 ETHER_ADDR_LEN) != 0) { 1171 ETHER_UNLOCK(ec); 1172 goto allmulti; 1173 } 1174 if ((mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, 1175 M_NOWAIT)) == NULL) { 1176 ETHER_UNLOCK(ec); 1177 goto allmulti; 1178 } 1179 memcpy(&mc->mc_addr, enm->enm_addrlo, ETHER_ADDR_LEN); 1180 SIMPLEQ_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1181 ETHER_NEXT_MULTI(step, enm); 1182 } 1183 ETHER_UNLOCK(ec); 1184 1185 /* Accept only programmed multicast addresses */ 1186 ifp->if_flags &= ~IFF_ALLMULTI; 1187 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1188 1189 /* Now program new ones. */ 1190 SIMPLEQ_FOREACH(mc, &sc->ti_mc_listhead, mc_entries) 1191 ti_add_mcast(sc, &mc->mc_addr); 1192 1193 /* Re-enable interrupts. */ 1194 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1195 1196 return; 1197 1198 allmulti: 1199 /* No need to keep individual multicast addresses */ 1200 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1201 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries); 1202 free(mc, M_DEVBUF); 1203 } 1204 1205 /* Accept all multicast addresses */ 1206 ifp->if_flags |= IFF_ALLMULTI; 1207 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1208 1209 /* Re-enable interrupts. */ 1210 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1211 } 1212 1213 /* 1214 * Check to see if the BIOS has configured us for a 64 bit slot when 1215 * we aren't actually in one. If we detect this condition, we can work 1216 * around it on the Tigon 2 by setting a bit in the PCI state register, 1217 * but for the Tigon 1 we must give up and abort the interface attach. 1218 */ 1219 static int 1220 ti_64bitslot_war(struct ti_softc *sc) 1221 { 1222 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1223 CSR_WRITE_4(sc, 0x600, 0); 1224 CSR_WRITE_4(sc, 0x604, 0); 1225 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1226 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1227 if (sc->ti_hwrev == TI_HWREV_TIGON) 1228 return (EINVAL); 1229 else { 1230 TI_SETBIT(sc, TI_PCI_STATE, 1231 TI_PCISTATE_32BIT_BUS); 1232 return (0); 1233 } 1234 } 1235 } 1236 1237 return (0); 1238 } 1239 1240 /* 1241 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1242 * self-test results. 1243 */ 1244 static int 1245 ti_chipinit(struct ti_softc *sc) 1246 { 1247 uint32_t cacheline; 1248 uint32_t pci_writemax = 0; 1249 uint32_t rev; 1250 1251 /* Initialize link to down state. */ 1252 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1253 1254 /* Set endianness before we access any non-PCI registers. */ 1255 #if BYTE_ORDER == BIG_ENDIAN 1256 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1257 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1258 #else 1259 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1260 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1261 #endif 1262 1263 /* Check the ROM failed bit to see if self-tests passed. */ 1264 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1265 printf("%s: board self-diagnostics failed!\n", 1266 device_xname(sc->sc_dev)); 1267 return (ENODEV); 1268 } 1269 1270 /* Halt the CPU. */ 1271 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1272 1273 /* Figure out the hardware revision. */ 1274 rev = CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK; 1275 switch (rev) { 1276 case TI_REV_TIGON_I: 1277 sc->ti_hwrev = TI_HWREV_TIGON; 1278 break; 1279 case TI_REV_TIGON_II: 1280 sc->ti_hwrev = TI_HWREV_TIGON_II; 1281 break; 1282 default: 1283 printf("%s: unsupported chip revision 0x%x\n", 1284 device_xname(sc->sc_dev), rev); 1285 return (ENODEV); 1286 } 1287 1288 /* Do special setup for Tigon 2. */ 1289 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1290 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1291 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 1292 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1293 } 1294 1295 /* Set up the PCI state register. */ 1296 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD | TI_PCI_WRITE_CMD); 1297 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1298 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1299 } 1300 1301 /* Clear the read/write max DMA parameters. */ 1302 TI_CLRBIT(sc, TI_PCI_STATE, 1303 (TI_PCISTATE_WRITE_MAXDMA | TI_PCISTATE_READ_MAXDMA)); 1304 1305 /* Get cache line size. */ 1306 cacheline = PCI_CACHELINE(CSR_READ_4(sc, PCI_BHLC_REG)); 1307 1308 /* 1309 * If the system has set enabled the PCI memory write 1310 * and invalidate command in the command register, set 1311 * the write max parameter accordingly. This is necessary 1312 * to use MWI with the Tigon 2. 1313 */ 1314 if (CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1315 & PCI_COMMAND_INVALIDATE_ENABLE) { 1316 switch (cacheline) { 1317 case 1: 1318 case 4: 1319 case 8: 1320 case 16: 1321 case 32: 1322 case 64: 1323 break; 1324 default: 1325 /* Disable PCI memory write and invalidate. */ 1326 if (bootverbose) 1327 printf("%s: cache line size %d not " 1328 "supported; disabling PCI MWI\n", 1329 device_xname(sc->sc_dev), cacheline); 1330 CSR_WRITE_4(sc, PCI_COMMAND_STATUS_REG, 1331 CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1332 & ~PCI_COMMAND_INVALIDATE_ENABLE); 1333 break; 1334 } 1335 } 1336 1337 #ifdef __brokenalpha__ 1338 /* 1339 * From the Alteon sample driver: 1340 * Must insure that we do not cross an 8K (bytes) boundary 1341 * for DMA reads. Our highest limit is 1K bytes. This is a 1342 * restriction on some ALPHA platforms with early revision 1343 * 21174 PCI chipsets, such as the AlphaPC 164lx 1344 */ 1345 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax | TI_PCI_READMAX_1024); 1346 #else 1347 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1348 #endif 1349 1350 /* This sets the min dma param all the way up (0xff). */ 1351 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1352 1353 /* Configure DMA variables. */ 1354 #if BYTE_ORDER == BIG_ENDIAN 1355 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1356 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1357 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1358 TI_OPMODE_DONT_FRAG_JUMBO); 1359 #else 1360 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA | 1361 TI_OPMODE_WORDSWAP_BD | TI_OPMODE_DONT_FRAG_JUMBO | 1362 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB); 1363 #endif 1364 1365 /* 1366 * Only allow 1 DMA channel to be active at a time. 1367 * I don't think this is a good idea, but without it 1368 * the firmware racks up lots of nicDmaReadRingFull 1369 * errors. 1370 * Incompatible with hardware assisted checksums. 1371 */ 1372 if ((sc->ethercom.ec_if.if_capenable & 1373 (IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1374 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 1375 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx)) == 0) 1376 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1377 1378 /* Recommended settings from Tigon manual. */ 1379 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1380 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1381 1382 if (ti_64bitslot_war(sc)) { 1383 printf("%s: bios thinks we're in a 64 bit slot, " 1384 "but we aren't", device_xname(sc->sc_dev)); 1385 return (EINVAL); 1386 } 1387 1388 return (0); 1389 } 1390 1391 /* 1392 * Initialize the general information block and firmware, and 1393 * start the CPU(s) running. 1394 */ 1395 static int 1396 ti_gibinit(struct ti_softc *sc) 1397 { 1398 struct ti_rcb *rcb; 1399 int i; 1400 struct ifnet *ifp; 1401 1402 ifp = &sc->ethercom.ec_if; 1403 1404 /* Disable interrupts for now. */ 1405 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1406 1407 /* Tell the chip where to find the general information block. */ 1408 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1409 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, TI_CDGIBADDR(sc)); 1410 1411 /* Load the firmware into SRAM. */ 1412 ti_loadfw(sc); 1413 1414 /* Set up the contents of the general info and ring control blocks. */ 1415 1416 /* Set up the event ring and producer pointer. */ 1417 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1418 1419 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDEVENTADDR(sc, 0); 1420 rcb->ti_flags = 0; 1421 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1422 TI_CDEVPRODADDR(sc); 1423 1424 sc->ti_ev_prodidx.ti_idx = 0; 1425 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1426 sc->ti_ev_saved_considx = 0; 1427 1428 /* Set up the command ring and producer mailbox. */ 1429 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1430 1431 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1432 rcb->ti_flags = 0; 1433 rcb->ti_max_len = 0; 1434 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1435 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1436 } 1437 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1438 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1439 sc->ti_cmd_saved_prodidx = 0; 1440 1441 /* 1442 * Assign the address of the stats refresh buffer. 1443 * We re-use the current stats buffer for this to 1444 * conserve memory. 1445 */ 1446 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1447 TI_CDSTATSADDR(sc); 1448 1449 /* Set up the standard receive ring. */ 1450 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1451 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXSTDADDR(sc, 0); 1452 rcb->ti_max_len = ETHER_MAX_LEN; 1453 rcb->ti_flags = 0; 1454 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1455 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1456 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 1457 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1458 if (VLAN_ATTACHED(&sc->ethercom)) 1459 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1460 1461 /* Set up the jumbo receive ring. */ 1462 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1463 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXJUMBOADDR(sc, 0); 1464 rcb->ti_max_len = ETHER_MAX_LEN_JUMBO; 1465 rcb->ti_flags = 0; 1466 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1467 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1468 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 1469 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1470 if (VLAN_ATTACHED(&sc->ethercom)) 1471 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1472 1473 /* 1474 * Set up the mini ring. Only activated on the 1475 * Tigon 2 but the slot in the config block is 1476 * still there on the Tigon 1. 1477 */ 1478 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1479 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXMINIADDR(sc, 0); 1480 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1481 if (sc->ti_hwrev == TI_HWREV_TIGON) 1482 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1483 else 1484 rcb->ti_flags = 0; 1485 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) 1486 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1487 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) 1488 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1489 if (VLAN_ATTACHED(&sc->ethercom)) 1490 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1491 1492 /* 1493 * Set up the receive return ring. 1494 */ 1495 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1496 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXRTNADDR(sc, 0); 1497 rcb->ti_flags = 0; 1498 rcb->ti_max_len = TI_RETURN_RING_CNT; 1499 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1500 TI_CDRTNPRODADDR(sc); 1501 1502 /* 1503 * Set up the tx ring. Note: for the Tigon 2, we have the option 1504 * of putting the transmit ring in the host's address space and 1505 * letting the chip DMA it instead of leaving the ring in the NIC's 1506 * memory and accessing it through the shared memory region. We 1507 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1508 * so we have to revert to the shared memory scheme if we detect 1509 * a Tigon 1 chip. 1510 */ 1511 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1512 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1513 sc->ti_tx_ring_nic = 1514 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1515 } 1516 memset((char *)sc->ti_rdata->ti_tx_ring, 0, 1517 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1518 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1519 if (sc->ti_hwrev == TI_HWREV_TIGON) 1520 rcb->ti_flags = 0; 1521 else 1522 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1523 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Tx) 1524 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1525 /* 1526 * When we get the packet, there is a pseudo-header seed already 1527 * in the th_sum or uh_sum field. Make sure the firmware doesn't 1528 * compute the pseudo-header checksum again! 1529 */ 1530 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx)) 1531 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM | 1532 TI_RCB_FLAG_NO_PHDR_CKSUM; 1533 if (VLAN_ATTACHED(&sc->ethercom)) 1534 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1535 rcb->ti_max_len = TI_TX_RING_CNT; 1536 if (sc->ti_hwrev == TI_HWREV_TIGON) 1537 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1538 else 1539 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDTXADDR(sc, 0); 1540 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1541 TI_CDTXCONSADDR(sc); 1542 1543 /* 1544 * We're done frobbing the General Information Block. Sync 1545 * it. Note we take care of the first stats sync here, as 1546 * well. 1547 */ 1548 TI_CDGIBSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1549 1550 /* Set up tuneables */ 1551 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN) || 1552 (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 1553 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1554 (sc->ti_rx_coal_ticks / 10)); 1555 else 1556 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1557 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1558 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1559 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1560 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1561 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1562 1563 /* Turn interrupts on. */ 1564 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1565 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1566 1567 /* Start CPU. */ 1568 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT | TI_CPUSTATE_STEP)); 1569 1570 return (0); 1571 } 1572 1573 /* 1574 * look for id in the device list, returning the first match 1575 */ 1576 static const struct ti_type * 1577 ti_type_match(struct pci_attach_args *pa) 1578 { 1579 const struct ti_type *t; 1580 1581 t = ti_devs; 1582 while (t->ti_name != NULL) { 1583 if ((PCI_VENDOR(pa->pa_id) == t->ti_vid) && 1584 (PCI_PRODUCT(pa->pa_id) == t->ti_did)) { 1585 return (t); 1586 } 1587 t++; 1588 } 1589 1590 return (NULL); 1591 } 1592 1593 /* 1594 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1595 * against our list and return its name if we find a match. 1596 */ 1597 static int 1598 ti_probe(device_t parent, cfdata_t match, void *aux) 1599 { 1600 struct pci_attach_args *pa = aux; 1601 const struct ti_type *t; 1602 1603 t = ti_type_match(pa); 1604 1605 return ((t == NULL) ? 0 : 1); 1606 } 1607 1608 static void 1609 ti_attach(device_t parent, device_t self, void *aux) 1610 { 1611 uint32_t command; 1612 struct ifnet *ifp; 1613 struct ti_softc *sc; 1614 uint8_t eaddr[ETHER_ADDR_LEN]; 1615 struct pci_attach_args *pa = aux; 1616 pci_chipset_tag_t pc = pa->pa_pc; 1617 pci_intr_handle_t ih; 1618 const char *intrstr = NULL; 1619 bus_dma_segment_t dmaseg; 1620 int error, dmanseg, nolinear; 1621 const struct ti_type *t; 1622 char intrbuf[PCI_INTRSTR_LEN]; 1623 1624 t = ti_type_match(pa); 1625 if (t == NULL) { 1626 aprint_error("ti_attach: were did the card go ?\n"); 1627 return; 1628 } 1629 1630 aprint_normal(": %s (rev. 0x%02x)\n", t->ti_name, 1631 PCI_REVISION(pa->pa_class)); 1632 1633 sc = device_private(self); 1634 sc->sc_dev = self; 1635 1636 /* 1637 * Map control/status registers. 1638 */ 1639 nolinear = 0; 1640 if (pci_mapreg_map(pa, 0x10, 1641 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1642 BUS_SPACE_MAP_LINEAR , &sc->ti_btag, &sc->ti_bhandle, 1643 NULL, NULL)) { 1644 nolinear = 1; 1645 if (pci_mapreg_map(pa, 0x10, 1646 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1647 0 , &sc->ti_btag, &sc->ti_bhandle, NULL, NULL)) { 1648 aprint_error_dev(self, "can't map memory space\n"); 1649 return; 1650 } 1651 } 1652 if (nolinear == 0) 1653 sc->ti_vhandle = bus_space_vaddr(sc->ti_btag, sc->ti_bhandle); 1654 else 1655 sc->ti_vhandle = NULL; 1656 1657 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1658 command |= PCI_COMMAND_MASTER_ENABLE; 1659 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1660 1661 /* Allocate interrupt */ 1662 if (pci_intr_map(pa, &ih)) { 1663 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n"); 1664 return; 1665 } 1666 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 1667 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, ti_intr, sc, 1668 device_xname(self)); 1669 if (sc->sc_ih == NULL) { 1670 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt"); 1671 if (intrstr != NULL) 1672 aprint_error(" at %s", intrstr); 1673 aprint_error("\n"); 1674 return; 1675 } 1676 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr); 1677 1678 if (ti_chipinit(sc)) { 1679 aprint_error_dev(self, "chip initialization failed\n"); 1680 goto fail2; 1681 } 1682 1683 /* 1684 * Deal with some chip diffrences. 1685 */ 1686 switch (sc->ti_hwrev) { 1687 case TI_HWREV_TIGON: 1688 sc->sc_tx_encap = ti_encap_tigon1; 1689 sc->sc_tx_eof = ti_txeof_tigon1; 1690 if (nolinear == 1) 1691 aprint_error_dev(self, 1692 "memory space not mapped linear\n"); 1693 break; 1694 1695 case TI_HWREV_TIGON_II: 1696 sc->sc_tx_encap = ti_encap_tigon2; 1697 sc->sc_tx_eof = ti_txeof_tigon2; 1698 break; 1699 1700 default: 1701 aprint_error_dev(self, "Unknown chip version: %d\n", 1702 sc->ti_hwrev); 1703 goto fail2; 1704 } 1705 1706 /* Zero out the NIC's on-board SRAM. */ 1707 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1708 1709 /* Init again -- zeroing memory may have clobbered some registers. */ 1710 if (ti_chipinit(sc)) { 1711 aprint_error_dev(self, "chip initialization failed\n"); 1712 goto fail2; 1713 } 1714 1715 /* 1716 * Get station address from the EEPROM. Note: the manual states 1717 * that the MAC address is at offset 0x8c, however the data is 1718 * stored as two longwords (since that's how it's loaded into 1719 * the NIC). This means the MAC address is actually preceded 1720 * by two zero bytes. We need to skip over those. 1721 */ 1722 if (ti_read_eeprom(sc, (void *)&eaddr, 1723 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1724 aprint_error_dev(self, "failed to read station address\n"); 1725 goto fail2; 1726 } 1727 1728 /* 1729 * A Tigon chip was detected. Inform the world. 1730 */ 1731 aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(eaddr)); 1732 1733 sc->sc_dmat = pa->pa_dmat; 1734 1735 /* Allocate the general information block and ring buffers. */ 1736 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1737 sizeof(struct ti_ring_data), PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 1738 BUS_DMA_NOWAIT)) != 0) { 1739 aprint_error_dev(self, 1740 "can't allocate ring buffer, error = %d\n", error); 1741 goto fail2; 1742 } 1743 1744 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 1745 sizeof(struct ti_ring_data), (void **)&sc->ti_rdata, 1746 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 1747 aprint_error_dev(self, 1748 "can't map ring buffer, error = %d\n", error); 1749 goto fail2; 1750 } 1751 1752 if ((error = bus_dmamap_create(sc->sc_dmat, 1753 sizeof(struct ti_ring_data), 1, 1754 sizeof(struct ti_ring_data), 0, BUS_DMA_NOWAIT, 1755 &sc->info_dmamap)) != 0) { 1756 aprint_error_dev(self, 1757 "can't create ring buffer DMA map, error = %d\n", error); 1758 goto fail2; 1759 } 1760 1761 if ((error = bus_dmamap_load(sc->sc_dmat, sc->info_dmamap, 1762 sc->ti_rdata, sizeof(struct ti_ring_data), NULL, 1763 BUS_DMA_NOWAIT)) != 0) { 1764 aprint_error_dev(self, 1765 "can't load ring buffer DMA map, error = %d\n", error); 1766 goto fail2; 1767 } 1768 1769 sc->info_dmaaddr = sc->info_dmamap->dm_segs[0].ds_addr; 1770 1771 memset(sc->ti_rdata, 0, sizeof(struct ti_ring_data)); 1772 1773 /* Try to allocate memory for jumbo buffers. */ 1774 if (ti_alloc_jumbo_mem(sc)) { 1775 aprint_error_dev(self, "jumbo buffer allocation failed\n"); 1776 goto fail2; 1777 } 1778 1779 SIMPLEQ_INIT(&sc->ti_mc_listhead); 1780 1781 /* 1782 * We really need a better way to tell a 1000baseT card 1783 * from a 1000baseSX one, since in theory there could be 1784 * OEMed 1000baseT cards from lame vendors who aren't 1785 * clever enough to change the PCI ID. For the moment 1786 * though, the AceNIC is the only copper card available. 1787 */ 1788 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALTEON && 1789 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALTEON_ACENIC_COPPER) || 1790 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NETGEAR && 1791 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NETGEAR_GA620T)) 1792 sc->ti_copper = 1; 1793 else 1794 sc->ti_copper = 0; 1795 1796 /* Set default tuneable values. */ 1797 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1798 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1799 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1800 sc->ti_rx_max_coal_bds = 64; 1801 sc->ti_tx_max_coal_bds = 128; 1802 sc->ti_tx_buf_ratio = 21; 1803 1804 /* Set up ifnet structure */ 1805 ifp = &sc->ethercom.ec_if; 1806 ifp->if_softc = sc; 1807 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 1808 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1809 ifp->if_ioctl = ti_ioctl; 1810 ifp->if_start = ti_start; 1811 ifp->if_watchdog = ti_watchdog; 1812 IFQ_SET_READY(&ifp->if_snd); 1813 1814 #if 0 1815 /* 1816 * XXX This is not really correct -- we don't necessarily 1817 * XXX want to queue up as many as we can transmit at the 1818 * XXX upper layer like that. Someone with a board should 1819 * XXX check to see how this affects performance. 1820 */ 1821 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1822 #endif 1823 1824 /* 1825 * We can support 802.1Q VLAN-sized frames. 1826 */ 1827 sc->ethercom.ec_capabilities |= 1828 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 1829 sc->ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING; 1830 1831 /* 1832 * We can do IPv4, TCPv4, and UDPv4 checksums in hardware. 1833 */ 1834 ifp->if_capabilities |= 1835 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 1836 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 1837 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 1838 1839 /* Set up ifmedia support. */ 1840 sc->ethercom.ec_ifmedia = &sc->ifmedia; 1841 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1842 if (sc->ti_copper) { 1843 /* 1844 * Copper cards allow manual 10/100 mode selection, 1845 * but not manual 1000baseT mode selection. Why? 1846 * Because currently there's no way to specify the 1847 * master/slave setting through the firmware interface, 1848 * so Alteon decided to just bag it and handle it 1849 * via autonegotiation. 1850 */ 1851 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 1852 ifmedia_add(&sc->ifmedia, 1853 IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 1854 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 1855 ifmedia_add(&sc->ifmedia, 1856 IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 1857 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL); 1858 ifmedia_add(&sc->ifmedia, 1859 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 1860 } else { 1861 /* Fiber cards don't support 10/100 modes. */ 1862 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); 1863 ifmedia_add(&sc->ifmedia, 1864 IFM_ETHER | IFM_1000_SX | IFM_FDX, 0, NULL); 1865 } 1866 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 1867 ifmedia_set(&sc->ifmedia, IFM_ETHER | IFM_AUTO); 1868 1869 /* 1870 * Call MI attach routines. 1871 */ 1872 if_attach(ifp); 1873 if_deferred_start_init(ifp, NULL); 1874 ether_ifattach(ifp, eaddr); 1875 1876 /* 1877 * Add shutdown hook so that DMA is disabled prior to reboot. Not 1878 * doing do could allow DMA to corrupt kernel memory during the 1879 * reboot before the driver initializes. 1880 */ 1881 if (pmf_device_register1(self, NULL, NULL, ti_shutdown)) 1882 pmf_class_network_register(self, ifp); 1883 else 1884 aprint_error_dev(self, "couldn't establish power handler\n"); 1885 1886 return; 1887 fail2: 1888 pci_intr_disestablish(pc, sc->sc_ih); 1889 return; 1890 } 1891 1892 /* 1893 * Frame reception handling. This is called if there's a frame 1894 * on the receive return list. 1895 * 1896 * Note: we have to be able to handle three possibilities here: 1897 * 1) the frame is from the mini receive ring (can only happen) 1898 * on Tigon 2 boards) 1899 * 2) the frame is from the jumbo receive ring 1900 * 3) the frame is from the standard receive ring 1901 */ 1902 1903 static void 1904 ti_rxeof(struct ti_softc *sc) 1905 { 1906 struct ifnet *ifp; 1907 struct ti_cmd_desc cmd; 1908 1909 ifp = &sc->ethercom.ec_if; 1910 1911 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1912 struct ti_rx_desc *cur_rx; 1913 uint32_t rxidx; 1914 struct mbuf *m = NULL; 1915 struct ether_header *eh; 1916 bus_dmamap_t dmamap; 1917 1918 cur_rx = 1919 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1920 rxidx = cur_rx->ti_idx; 1921 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1922 1923 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1924 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1925 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1926 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1927 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1928 if_statinc(ifp, if_ierrors); 1929 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1930 continue; 1931 } 1932 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) 1933 == ENOBUFS) { 1934 if_statinc(ifp, if_ierrors); 1935 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1936 continue; 1937 } 1938 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1939 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1940 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1941 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1942 dmamap = sc->mini_dmamap[rxidx]; 1943 sc->mini_dmamap[rxidx] = 0; 1944 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1945 if_statinc(ifp, if_ierrors); 1946 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1947 continue; 1948 } 1949 if (ti_newbuf_mini(sc, sc->ti_mini, NULL, dmamap) 1950 == ENOBUFS) { 1951 if_statinc(ifp, if_ierrors); 1952 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1953 continue; 1954 } 1955 } else { 1956 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1957 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1958 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1959 dmamap = sc->std_dmamap[rxidx]; 1960 sc->std_dmamap[rxidx] = 0; 1961 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1962 if_statinc(ifp, if_ierrors); 1963 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 1964 continue; 1965 } 1966 if (ti_newbuf_std(sc, sc->ti_std, NULL, dmamap) 1967 == ENOBUFS) { 1968 if_statinc(ifp, if_ierrors); 1969 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 1970 continue; 1971 } 1972 } 1973 1974 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 1975 m_set_rcvif(m, ifp); 1976 1977 eh = mtod(m, struct ether_header *); 1978 switch (ntohs(eh->ether_type)) { 1979 #ifdef INET 1980 case ETHERTYPE_IP: 1981 { 1982 struct ip *ip = (struct ip *) (eh + 1); 1983 1984 /* 1985 * Note the Tigon firmware does not invert 1986 * the checksum for us, hence the XOR. 1987 */ 1988 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1989 if ((cur_rx->ti_ip_cksum ^ 0xffff) != 0) 1990 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1991 /* 1992 * ntohs() the constant so the compiler can 1993 * optimize... 1994 * 1995 * XXX Figure out a sane way to deal with 1996 * fragmented packets. 1997 */ 1998 if ((ip->ip_off & htons(IP_MF | IP_OFFMASK)) == 0) { 1999 switch (ip->ip_p) { 2000 case IPPROTO_TCP: 2001 m->m_pkthdr.csum_data = 2002 cur_rx->ti_tcp_udp_cksum; 2003 m->m_pkthdr.csum_flags |= 2004 M_CSUM_TCPv4 | M_CSUM_DATA; 2005 break; 2006 case IPPROTO_UDP: 2007 m->m_pkthdr.csum_data = 2008 cur_rx->ti_tcp_udp_cksum; 2009 m->m_pkthdr.csum_flags |= 2010 M_CSUM_UDPv4 | M_CSUM_DATA; 2011 break; 2012 default: 2013 /* Nothing */; 2014 } 2015 } 2016 break; 2017 } 2018 #endif 2019 default: 2020 /* Nothing. */ 2021 break; 2022 } 2023 2024 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) 2025 vlan_set_tag(m, cur_rx->ti_vlan_tag); 2026 2027 if_percpuq_enqueue(ifp->if_percpuq, m); 2028 } 2029 2030 /* Only necessary on the Tigon 1. */ 2031 if (sc->ti_hwrev == TI_HWREV_TIGON) 2032 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2033 sc->ti_rx_saved_considx); 2034 2035 TI_UPDATE_STDPROD(sc, sc->ti_std); 2036 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2037 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2038 } 2039 2040 static void 2041 ti_txeof_tigon1(struct ti_softc *sc) 2042 { 2043 struct ti_tx_desc *cur_tx = NULL; 2044 struct ifnet *ifp; 2045 struct txdmamap_pool_entry *dma; 2046 2047 ifp = &sc->ethercom.ec_if; 2048 2049 /* 2050 * Go through our tx ring and free mbufs for those 2051 * frames that have been sent. 2052 */ 2053 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2054 uint32_t idx = 0; 2055 2056 idx = sc->ti_tx_saved_considx; 2057 if (idx > 383) 2058 CSR_WRITE_4(sc, TI_WINBASE, 2059 TI_TX_RING_BASE + 6144); 2060 else if (idx > 255) 2061 CSR_WRITE_4(sc, TI_WINBASE, 2062 TI_TX_RING_BASE + 4096); 2063 else if (idx > 127) 2064 CSR_WRITE_4(sc, TI_WINBASE, 2065 TI_TX_RING_BASE + 2048); 2066 else 2067 CSR_WRITE_4(sc, TI_WINBASE, 2068 TI_TX_RING_BASE); 2069 cur_tx = &sc->ti_tx_ring_nic[idx % 128]; 2070 if (cur_tx->ti_flags & TI_BDFLAG_END) 2071 if_statinc(ifp, if_opackets); 2072 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2073 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2074 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2075 2076 dma = sc->txdma[idx]; 2077 KDASSERT(dma != NULL); 2078 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2079 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2080 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2081 2082 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2083 sc->txdma[idx] = NULL; 2084 } 2085 sc->ti_txcnt--; 2086 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2087 ifp->if_timer = 0; 2088 } 2089 2090 if (cur_tx != NULL) 2091 ifp->if_flags &= ~IFF_OACTIVE; 2092 } 2093 2094 static void 2095 ti_txeof_tigon2(struct ti_softc *sc) 2096 { 2097 struct ti_tx_desc *cur_tx = NULL; 2098 struct ifnet *ifp; 2099 struct txdmamap_pool_entry *dma; 2100 int firstidx, cnt; 2101 2102 ifp = &sc->ethercom.ec_if; 2103 2104 /* 2105 * Go through our tx ring and free mbufs for those 2106 * frames that have been sent. 2107 */ 2108 firstidx = sc->ti_tx_saved_considx; 2109 cnt = 0; 2110 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2111 uint32_t idx = 0; 2112 2113 idx = sc->ti_tx_saved_considx; 2114 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2115 if (cur_tx->ti_flags & TI_BDFLAG_END) 2116 if_statinc(ifp, if_opackets); 2117 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2118 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2119 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2120 2121 dma = sc->txdma[idx]; 2122 KDASSERT(dma != NULL); 2123 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2124 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2125 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2126 2127 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2128 sc->txdma[idx] = NULL; 2129 } 2130 cnt++; 2131 sc->ti_txcnt--; 2132 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2133 ifp->if_timer = 0; 2134 } 2135 2136 if (cnt != 0) 2137 TI_CDTXSYNC(sc, firstidx, cnt, BUS_DMASYNC_POSTWRITE); 2138 2139 if (cur_tx != NULL) 2140 ifp->if_flags &= ~IFF_OACTIVE; 2141 } 2142 2143 static int 2144 ti_intr(void *xsc) 2145 { 2146 struct ti_softc *sc; 2147 struct ifnet *ifp; 2148 2149 sc = xsc; 2150 ifp = &sc->ethercom.ec_if; 2151 2152 #ifdef notdef 2153 /* Avoid this for now -- checking this register is expensive. */ 2154 /* Make sure this is really our interrupt. */ 2155 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 2156 return (0); 2157 #endif 2158 2159 /* Ack interrupt and stop others from occurring. */ 2160 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2161 2162 if (ifp->if_flags & IFF_RUNNING) { 2163 /* Check RX return ring producer/consumer */ 2164 ti_rxeof(sc); 2165 2166 /* Check TX ring producer/consumer */ 2167 (*sc->sc_tx_eof)(sc); 2168 } 2169 2170 ti_handle_events(sc); 2171 2172 /* Re-enable interrupts. */ 2173 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2174 2175 if ((ifp->if_flags & IFF_RUNNING) != 0) 2176 if_schedule_deferred_start(ifp); 2177 2178 return (1); 2179 } 2180 2181 static void 2182 ti_stats_update(struct ti_softc *sc) 2183 { 2184 struct ifnet *ifp = &sc->ethercom.ec_if; 2185 2186 TI_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 2187 2188 uint64_t collisions = 2189 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2190 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2191 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2192 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions); 2193 if_statadd(ifp, if_collisions, collisions - sc->ti_if_collisions); 2194 sc->ti_if_collisions = collisions; 2195 2196 TI_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 2197 } 2198 2199 /* 2200 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2201 * pointers to descriptors. 2202 */ 2203 static int 2204 ti_encap_tigon1(struct ti_softc *sc, struct mbuf *m_head, uint32_t *txidx) 2205 { 2206 struct ti_tx_desc *f = NULL; 2207 uint32_t frag, cur, cnt = 0; 2208 struct txdmamap_pool_entry *dma; 2209 bus_dmamap_t dmamap; 2210 int error, i; 2211 uint16_t csum_flags = 0; 2212 2213 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2214 if (dma == NULL) { 2215 return ENOMEM; 2216 } 2217 dmamap = dma->dmamap; 2218 2219 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2220 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2221 if (error) { 2222 struct mbuf *m; 2223 int j = 0; 2224 for (m = m_head; m; m = m->m_next) 2225 j++; 2226 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2227 "error %d\n", m_head->m_pkthdr.len, j, error); 2228 return (ENOMEM); 2229 } 2230 2231 cur = frag = *txidx; 2232 2233 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2234 /* IP header checksum field must be 0! */ 2235 csum_flags |= TI_BDFLAG_IP_CKSUM; 2236 } 2237 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 2238 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2239 2240 /* XXX fragmented packet checksum capability? */ 2241 2242 /* 2243 * Start packing the mbufs in this chain into 2244 * the fragment pointers. Stop when we run out 2245 * of fragments or hit the end of the mbuf chain. 2246 */ 2247 for (i = 0; i < dmamap->dm_nsegs; i++) { 2248 if (frag > 383) 2249 CSR_WRITE_4(sc, TI_WINBASE, 2250 TI_TX_RING_BASE + 6144); 2251 else if (frag > 255) 2252 CSR_WRITE_4(sc, TI_WINBASE, 2253 TI_TX_RING_BASE + 4096); 2254 else if (frag > 127) 2255 CSR_WRITE_4(sc, TI_WINBASE, 2256 TI_TX_RING_BASE + 2048); 2257 else 2258 CSR_WRITE_4(sc, TI_WINBASE, 2259 TI_TX_RING_BASE); 2260 f = &sc->ti_tx_ring_nic[frag % 128]; 2261 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2262 break; 2263 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2264 f->ti_len = dmamap->dm_segs[i].ds_len; 2265 f->ti_flags = csum_flags; 2266 if (vlan_has_tag(m_head)) { 2267 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2268 f->ti_vlan_tag = vlan_get_tag(m_head); 2269 } else { 2270 f->ti_vlan_tag = 0; 2271 } 2272 /* 2273 * Sanity check: avoid coming within 16 descriptors 2274 * of the end of the ring. 2275 */ 2276 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2277 return (ENOBUFS); 2278 cur = frag; 2279 TI_INC(frag, TI_TX_RING_CNT); 2280 cnt++; 2281 } 2282 2283 if (i < dmamap->dm_nsegs) 2284 return (ENOBUFS); 2285 2286 if (frag == sc->ti_tx_saved_considx) 2287 return (ENOBUFS); 2288 2289 sc->ti_tx_ring_nic[cur % 128].ti_flags |= 2290 TI_BDFLAG_END; 2291 2292 /* Sync the packet's DMA map. */ 2293 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2294 BUS_DMASYNC_PREWRITE); 2295 2296 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2297 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 2298 sc->txdma[cur] = dma; 2299 sc->ti_txcnt += cnt; 2300 2301 *txidx = frag; 2302 2303 return (0); 2304 } 2305 2306 static int 2307 ti_encap_tigon2(struct ti_softc *sc, struct mbuf *m_head, uint32_t *txidx) 2308 { 2309 struct ti_tx_desc *f = NULL; 2310 uint32_t frag, firstfrag, cur, cnt = 0; 2311 struct txdmamap_pool_entry *dma; 2312 bus_dmamap_t dmamap; 2313 int error, i; 2314 uint16_t csum_flags = 0; 2315 2316 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2317 if (dma == NULL) { 2318 return ENOMEM; 2319 } 2320 dmamap = dma->dmamap; 2321 2322 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2323 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 2324 if (error) { 2325 struct mbuf *m; 2326 int j = 0; 2327 for (m = m_head; m; m = m->m_next) 2328 j++; 2329 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2330 "error %d\n", m_head->m_pkthdr.len, j, error); 2331 return (ENOMEM); 2332 } 2333 2334 cur = firstfrag = frag = *txidx; 2335 2336 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2337 /* IP header checksum field must be 0! */ 2338 csum_flags |= TI_BDFLAG_IP_CKSUM; 2339 } 2340 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) 2341 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2342 2343 /* XXX fragmented packet checksum capability? */ 2344 2345 /* 2346 * Start packing the mbufs in this chain into 2347 * the fragment pointers. Stop when we run out 2348 * of fragments or hit the end of the mbuf chain. 2349 */ 2350 for (i = 0; i < dmamap->dm_nsegs; i++) { 2351 f = &sc->ti_rdata->ti_tx_ring[frag]; 2352 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2353 break; 2354 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2355 f->ti_len = dmamap->dm_segs[i].ds_len; 2356 f->ti_flags = csum_flags; 2357 if (vlan_has_tag(m_head)) { 2358 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2359 f->ti_vlan_tag = vlan_get_tag(m_head); 2360 } else { 2361 f->ti_vlan_tag = 0; 2362 } 2363 /* 2364 * Sanity check: avoid coming within 16 descriptors 2365 * of the end of the ring. 2366 */ 2367 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2368 return (ENOBUFS); 2369 cur = frag; 2370 TI_INC(frag, TI_TX_RING_CNT); 2371 cnt++; 2372 } 2373 2374 if (i < dmamap->dm_nsegs) 2375 return (ENOBUFS); 2376 2377 if (frag == sc->ti_tx_saved_considx) 2378 return (ENOBUFS); 2379 2380 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2381 2382 /* Sync the packet's DMA map. */ 2383 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2384 BUS_DMASYNC_PREWRITE); 2385 2386 /* Sync the descriptors we are using. */ 2387 TI_CDTXSYNC(sc, firstfrag, cnt, BUS_DMASYNC_PREWRITE); 2388 2389 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2390 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link); 2391 sc->txdma[cur] = dma; 2392 sc->ti_txcnt += cnt; 2393 2394 *txidx = frag; 2395 2396 return (0); 2397 } 2398 2399 /* 2400 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2401 * to the mbuf data regions directly in the transmit descriptors. 2402 */ 2403 static void 2404 ti_start(struct ifnet *ifp) 2405 { 2406 struct ti_softc *sc; 2407 struct mbuf *m_head = NULL; 2408 uint32_t prodidx = 0; 2409 2410 sc = ifp->if_softc; 2411 2412 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2413 2414 while (sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2415 IFQ_POLL(&ifp->if_snd, m_head); 2416 if (m_head == NULL) 2417 break; 2418 2419 /* 2420 * Pack the data into the transmit ring. If we 2421 * don't have room, set the OACTIVE flag and wait 2422 * for the NIC to drain the ring. 2423 */ 2424 if ((*sc->sc_tx_encap)(sc, m_head, &prodidx)) { 2425 ifp->if_flags |= IFF_OACTIVE; 2426 break; 2427 } 2428 2429 IFQ_DEQUEUE(&ifp->if_snd, m_head); 2430 2431 /* 2432 * If there's a BPF listener, bounce a copy of this frame 2433 * to him. 2434 */ 2435 bpf_mtap(ifp, m_head, BPF_D_OUT); 2436 } 2437 2438 /* Transmit */ 2439 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2440 2441 /* Set a timeout in case the chip goes out to lunch. */ 2442 ifp->if_timer = 5; 2443 } 2444 2445 static void 2446 ti_init(void *xsc) 2447 { 2448 struct ti_softc *sc = xsc; 2449 int s; 2450 2451 s = splnet(); 2452 2453 /* Cancel pending I/O and flush buffers. */ 2454 ti_stop(sc); 2455 2456 /* Init the gen info block, ring control blocks and firmware. */ 2457 if (ti_gibinit(sc)) { 2458 aprint_error_dev(sc->sc_dev, "initialization failure\n"); 2459 splx(s); 2460 return; 2461 } 2462 2463 splx(s); 2464 } 2465 2466 static void 2467 ti_init2(struct ti_softc *sc) 2468 { 2469 struct ti_cmd_desc cmd; 2470 struct ifnet *ifp; 2471 const uint8_t *m; 2472 struct ifmedia *ifm; 2473 int tmp; 2474 2475 ifp = &sc->ethercom.ec_if; 2476 2477 /* Specify MTU and interface index. */ 2478 CSR_WRITE_4(sc, TI_GCR_IFINDEX, device_unit(sc->sc_dev)); /* ??? */ 2479 2480 tmp = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 2481 if (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2482 tmp += ETHER_VLAN_ENCAP_LEN; 2483 CSR_WRITE_4(sc, TI_GCR_IFMTU, tmp); 2484 2485 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2486 2487 /* Load our MAC address. */ 2488 m = (const uint8_t *)CLLADDR(ifp->if_sadl); 2489 CSR_WRITE_4(sc, TI_GCR_PAR0, (m[0] << 8) | m[1]); 2490 CSR_WRITE_4(sc, TI_GCR_PAR1, (m[2] << 24) | (m[3] << 16) 2491 | (m[4] << 8) | m[5]); 2492 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2493 2494 /* Enable or disable promiscuous mode as needed. */ 2495 if (ifp->if_flags & IFF_PROMISC) { 2496 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2497 } else { 2498 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2499 } 2500 2501 /* Program multicast filter. */ 2502 ti_setmulti(sc); 2503 2504 /* 2505 * If this is a Tigon 1, we should tell the 2506 * firmware to use software packet filtering. 2507 */ 2508 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2509 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2510 } 2511 2512 /* Init RX ring. */ 2513 ti_init_rx_ring_std(sc); 2514 2515 /* Init jumbo RX ring. */ 2516 if (ifp->if_mtu > (MCLBYTES - ETHER_HDR_LEN - ETHER_CRC_LEN)) 2517 ti_init_rx_ring_jumbo(sc); 2518 2519 /* 2520 * If this is a Tigon 2, we can also configure the 2521 * mini ring. 2522 */ 2523 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2524 ti_init_rx_ring_mini(sc); 2525 2526 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2527 sc->ti_rx_saved_considx = 0; 2528 2529 /* Init TX ring. */ 2530 ti_init_tx_ring(sc); 2531 2532 /* Tell firmware we're alive. */ 2533 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2534 2535 /* Enable host interrupts. */ 2536 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2537 2538 ifp->if_flags |= IFF_RUNNING; 2539 ifp->if_flags &= ~IFF_OACTIVE; 2540 2541 /* 2542 * Make sure to set media properly. We have to do this 2543 * here since we have to issue commands in order to set 2544 * the link negotiation and we can't issue commands until 2545 * the firmware is running. 2546 */ 2547 ifm = &sc->ifmedia; 2548 tmp = ifm->ifm_media; 2549 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2550 ti_ifmedia_upd(ifp); 2551 ifm->ifm_media = tmp; 2552 } 2553 2554 /* 2555 * Set media options. 2556 */ 2557 static int 2558 ti_ifmedia_upd(struct ifnet *ifp) 2559 { 2560 struct ti_softc *sc; 2561 struct ifmedia *ifm; 2562 struct ti_cmd_desc cmd; 2563 2564 sc = ifp->if_softc; 2565 ifm = &sc->ifmedia; 2566 2567 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2568 return (EINVAL); 2569 2570 switch (IFM_SUBTYPE(ifm->ifm_media)) { 2571 case IFM_AUTO: 2572 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF | TI_GLNK_1000MB | 2573 TI_GLNK_FULL_DUPLEX | TI_GLNK_RX_FLOWCTL_Y | 2574 TI_GLNK_AUTONEGENB | TI_GLNK_ENB); 2575 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB | TI_LNK_10MB | 2576 TI_LNK_FULL_DUPLEX | TI_LNK_HALF_DUPLEX | 2577 TI_LNK_AUTONEGENB | TI_LNK_ENB); 2578 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2579 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2580 break; 2581 case IFM_1000_SX: 2582 case IFM_1000_T: 2583 if ((ifm->ifm_media & IFM_FDX) != 0) { 2584 CSR_WRITE_4(sc, TI_GCR_GLINK, 2585 TI_GLNK_PREF | TI_GLNK_1000MB | TI_GLNK_FULL_DUPLEX 2586 | TI_GLNK_RX_FLOWCTL_Y | TI_GLNK_ENB); 2587 } else { 2588 CSR_WRITE_4(sc, TI_GCR_GLINK, 2589 TI_GLNK_PREF | TI_GLNK_1000MB | 2590 TI_GLNK_RX_FLOWCTL_Y | TI_GLNK_ENB); 2591 } 2592 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2593 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2594 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2595 break; 2596 case IFM_100_FX: 2597 case IFM_10_FL: 2598 case IFM_100_TX: 2599 case IFM_10_T: 2600 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2601 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB | TI_LNK_PREF); 2602 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2603 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 2604 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2605 } else { 2606 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2607 } 2608 if ((ifm->ifm_media & IFM_FDX) != 0) { 2609 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2610 } else { 2611 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2612 } 2613 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2614 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2615 break; 2616 } 2617 2618 sc->ethercom.ec_if.if_baudrate = 2619 ifmedia_baudrate(ifm->ifm_media); 2620 2621 return (0); 2622 } 2623 2624 /* 2625 * Report current media status. 2626 */ 2627 static void 2628 ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2629 { 2630 struct ti_softc *sc; 2631 uint32_t media = 0; 2632 2633 sc = ifp->if_softc; 2634 2635 ifmr->ifm_status = IFM_AVALID; 2636 ifmr->ifm_active = IFM_ETHER; 2637 2638 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2639 return; 2640 2641 ifmr->ifm_status |= IFM_ACTIVE; 2642 2643 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2644 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2645 if (sc->ti_copper) 2646 ifmr->ifm_active |= IFM_1000_T; 2647 else 2648 ifmr->ifm_active |= IFM_1000_SX; 2649 if (media & TI_GLNK_FULL_DUPLEX) 2650 ifmr->ifm_active |= IFM_FDX; 2651 else 2652 ifmr->ifm_active |= IFM_HDX; 2653 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2654 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2655 if (sc->ti_copper) { 2656 if (media & TI_LNK_100MB) 2657 ifmr->ifm_active |= IFM_100_TX; 2658 if (media & TI_LNK_10MB) 2659 ifmr->ifm_active |= IFM_10_T; 2660 } else { 2661 if (media & TI_LNK_100MB) 2662 ifmr->ifm_active |= IFM_100_FX; 2663 if (media & TI_LNK_10MB) 2664 ifmr->ifm_active |= IFM_10_FL; 2665 } 2666 if (media & TI_LNK_FULL_DUPLEX) 2667 ifmr->ifm_active |= IFM_FDX; 2668 if (media & TI_LNK_HALF_DUPLEX) 2669 ifmr->ifm_active |= IFM_HDX; 2670 } 2671 2672 sc->ethercom.ec_if.if_baudrate = 2673 ifmedia_baudrate(sc->ifmedia.ifm_media); 2674 } 2675 2676 static int 2677 ti_ether_ioctl(struct ifnet *ifp, u_long cmd, void *data) 2678 { 2679 struct ifaddr *ifa = (struct ifaddr *)data; 2680 struct ti_softc *sc = ifp->if_softc; 2681 2682 if ((ifp->if_flags & IFF_UP) == 0) { 2683 ifp->if_flags |= IFF_UP; 2684 ti_init(sc); 2685 } 2686 2687 switch (cmd) { 2688 case SIOCINITIFADDR: 2689 2690 switch (ifa->ifa_addr->sa_family) { 2691 #ifdef INET 2692 case AF_INET: 2693 arp_ifinit(ifp, ifa); 2694 break; 2695 #endif 2696 default: 2697 break; 2698 } 2699 break; 2700 2701 default: 2702 return (EINVAL); 2703 } 2704 2705 return (0); 2706 } 2707 2708 static int 2709 ti_ioctl(struct ifnet *ifp, u_long command, void *data) 2710 { 2711 struct ti_softc *sc = ifp->if_softc; 2712 struct ifreq *ifr = (struct ifreq *)data; 2713 int s, error = 0; 2714 struct ti_cmd_desc cmd; 2715 2716 s = splnet(); 2717 2718 switch (command) { 2719 case SIOCINITIFADDR: 2720 error = ti_ether_ioctl(ifp, command, data); 2721 break; 2722 case SIOCSIFMTU: 2723 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU_JUMBO) 2724 error = EINVAL; 2725 else if ((error = ifioctl_common(ifp, command, data)) 2726 == ENETRESET) { 2727 ti_init(sc); 2728 error = 0; 2729 } 2730 break; 2731 case SIOCSIFFLAGS: 2732 if ((error = ifioctl_common(ifp, command, data)) != 0) 2733 break; 2734 if (ifp->if_flags & IFF_UP) { 2735 /* 2736 * If only the state of the PROMISC flag changed, 2737 * then just use the 'set promisc mode' command 2738 * instead of reinitializing the entire NIC. Doing 2739 * a full re-init means reloading the firmware and 2740 * waiting for it to start up, which may take a 2741 * second or two. 2742 */ 2743 if (ifp->if_flags & IFF_RUNNING && 2744 ifp->if_flags & IFF_PROMISC && 2745 !(sc->ti_if_flags & IFF_PROMISC)) { 2746 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2747 TI_CMD_CODE_PROMISC_ENB, 0); 2748 } else if (ifp->if_flags & IFF_RUNNING && 2749 !(ifp->if_flags & IFF_PROMISC) && 2750 sc->ti_if_flags & IFF_PROMISC) { 2751 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2752 TI_CMD_CODE_PROMISC_DIS, 0); 2753 } else 2754 ti_init(sc); 2755 } else { 2756 if (ifp->if_flags & IFF_RUNNING) { 2757 ti_stop(sc); 2758 } 2759 } 2760 sc->ti_if_flags = ifp->if_flags; 2761 error = 0; 2762 break; 2763 default: 2764 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 2765 break; 2766 2767 error = 0; 2768 2769 if (command == SIOCSIFCAP) 2770 ti_init(sc); 2771 else if (command != SIOCADDMULTI && command != SIOCDELMULTI) 2772 ; 2773 else if (ifp->if_flags & IFF_RUNNING) 2774 ti_setmulti(sc); 2775 break; 2776 } 2777 2778 (void)splx(s); 2779 2780 return (error); 2781 } 2782 2783 static void 2784 ti_watchdog(struct ifnet *ifp) 2785 { 2786 struct ti_softc *sc; 2787 2788 sc = ifp->if_softc; 2789 2790 aprint_error_dev(sc->sc_dev, "watchdog timeout -- resetting\n"); 2791 ti_stop(sc); 2792 ti_init(sc); 2793 2794 if_statinc(ifp, if_oerrors); 2795 } 2796 2797 /* 2798 * Stop the adapter and free any mbufs allocated to the 2799 * RX and TX lists. 2800 */ 2801 static void 2802 ti_stop(struct ti_softc *sc) 2803 { 2804 struct ifnet *ifp; 2805 struct ti_cmd_desc cmd; 2806 2807 ifp = &sc->ethercom.ec_if; 2808 2809 /* Disable host interrupts. */ 2810 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2811 /* 2812 * Tell firmware we're shutting down. 2813 */ 2814 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2815 2816 /* Halt and reinitialize. */ 2817 ti_chipinit(sc); 2818 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2819 ti_chipinit(sc); 2820 2821 /* Free the RX lists. */ 2822 ti_free_rx_ring_std(sc); 2823 2824 /* Free jumbo RX list. */ 2825 ti_free_rx_ring_jumbo(sc); 2826 2827 /* Free mini RX list. */ 2828 ti_free_rx_ring_mini(sc); 2829 2830 /* Free TX buffers. */ 2831 ti_free_tx_ring(sc); 2832 2833 sc->ti_ev_prodidx.ti_idx = 0; 2834 sc->ti_return_prodidx.ti_idx = 0; 2835 sc->ti_tx_considx.ti_idx = 0; 2836 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2837 2838 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2839 } 2840 2841 /* 2842 * Stop all chip I/O so that the kernel's probe routines don't 2843 * get confused by errant DMAs when rebooting. 2844 */ 2845 static bool 2846 ti_shutdown(device_t self, int howto) 2847 { 2848 struct ti_softc *sc; 2849 2850 sc = device_private(self); 2851 ti_chipinit(sc); 2852 2853 return true; 2854 } 2855