1 /* $NetBSD: if_ti.c,v 1.8 2000/03/30 12:45:35 augustss Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_ti.c,v 1.15 1999/08/14 15:45:03 wpaul Exp 35 */ 36 37 /* 38 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 39 * Manuals, sample driver and firmware source kits are available 40 * from http://www.alteon.com/support/openkits. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 49 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 50 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 51 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 52 * filtering and jumbo (9014 byte) frames. The hardware is largely 53 * controlled by firmware, which must be loaded into the NIC during 54 * initialization. 55 * 56 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 57 * revision, which supports new features such as extended commands, 58 * extended jumbo receive ring desciptors and a mini receive ring. 59 * 60 * Alteon Networks is to be commended for releasing such a vast amount 61 * of development material for the Tigon NIC without requiring an NDA 62 * (although they really should have done it a long time ago). With 63 * any luck, the other vendors will finally wise up and follow Alteon's 64 * stellar example. 65 * 66 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 67 * this driver by #including it as a C header file. This bloats the 68 * driver somewhat, but it's the easiest method considering that the 69 * driver code and firmware code need to be kept in sync. The source 70 * for the firmware is not provided with the FreeBSD distribution since 71 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 72 * 73 * The following people deserve special thanks: 74 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 75 * for testing 76 * - Raymond Lee of Netgear, for providing a pair of Netgear 77 * GA620 Tigon 2 boards for testing 78 * - Ulf Zimmermann, for bringing the GA620 to my attention and 79 * convincing me to write this driver. 80 * - Andrew Gallatin for providing FreeBSD/Alpha support. 81 */ 82 83 #include "bpfilter.h" 84 #include "opt_inet.h" 85 #include "opt_ns.h" 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/sockio.h> 90 #include <sys/mbuf.h> 91 #include <sys/malloc.h> 92 #include <sys/kernel.h> 93 #include <sys/socket.h> 94 #include <sys/queue.h> 95 #include <sys/device.h> 96 97 #include <net/if.h> 98 #include <net/if_arp.h> 99 #include <net/if_ether.h> 100 #include <net/if_dl.h> 101 #include <net/if_media.h> 102 103 #if NBPFILTER > 0 104 #include <net/bpf.h> 105 #endif 106 107 #ifdef INET 108 #include <netinet/in.h> 109 #include <netinet/if_inarp.h> 110 #endif 111 112 #ifdef NS 113 #include <netns/ns.h> 114 #include <netns/ns_if.h> 115 #endif 116 117 #include <machine/bus.h> 118 119 #include <dev/pci/pcireg.h> 120 #include <dev/pci/pcivar.h> 121 #include <dev/pci/pcidevs.h> 122 123 #include <dev/pci/if_tireg.h> 124 #include <dev/pci/ti_fw.h> 125 #include <dev/pci/ti_fw2.h> 126 127 #ifdef M_HWCKSUM 128 /*#define TI_CSUM_OFFLOAD*/ 129 #endif 130 131 #define bootverbose 1 132 133 /* 134 * Various supported device vendors/types and their names. 135 */ 136 137 static struct ti_type ti_devs[] = { 138 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC, 139 "Alteon AceNIC Gigabit Ethernet" }, 140 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C985, 141 "3Com 3c985-SX Gigabit Ethernet" }, 142 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620, 143 "Netgear GA620 Gigabit Ethernet" }, 144 { PCI_VENDOR_SGI, PCI_PRODUCT_SGI_TIGON, 145 "Silicon Graphics Gigabit Ethernet" }, 146 { 0, 0, NULL } 147 }; 148 149 static struct ti_type *ti_type_match __P((struct pci_attach_args *)); 150 static int ti_probe __P((struct device *, struct cfdata *, void *)); 151 static void ti_attach __P((struct device *, struct device *, void *)); 152 static void ti_shutdown __P((void *)); 153 static void ti_txeof __P((struct ti_softc *)); 154 static void ti_rxeof __P((struct ti_softc *)); 155 156 static void ti_stats_update __P((struct ti_softc *)); 157 static int ti_encap __P((struct ti_softc *, struct mbuf *, 158 u_int32_t *)); 159 160 static int ti_intr __P((void *)); 161 static void ti_start __P((struct ifnet *)); 162 static int ti_ioctl __P((struct ifnet *, u_long, caddr_t)); 163 static void ti_init __P((void *)); 164 static void ti_init2 __P((struct ti_softc *)); 165 static void ti_stop __P((struct ti_softc *)); 166 static void ti_watchdog __P((struct ifnet *)); 167 static int ti_ifmedia_upd __P((struct ifnet *)); 168 static void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 169 170 static u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int)); 171 static u_int8_t ti_eeprom_getbyte __P((struct ti_softc *, 172 int, u_int8_t *)); 173 static int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int)); 174 175 static void ti_add_mcast __P((struct ti_softc *, struct ether_addr *)); 176 static void ti_del_mcast __P((struct ti_softc *, struct ether_addr *)); 177 static void ti_setmulti __P((struct ti_softc *)); 178 179 static void ti_mem __P((struct ti_softc *, u_int32_t, 180 u_int32_t, caddr_t)); 181 static void ti_loadfw __P((struct ti_softc *)); 182 static void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *)); 183 static void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *, 184 caddr_t, int)); 185 static void ti_handle_events __P((struct ti_softc *)); 186 static int ti_alloc_jumbo_mem __P((struct ti_softc *)); 187 static void *ti_jalloc __P((struct ti_softc *)); 188 static void ti_jfree __P((caddr_t, u_int, void *)); 189 static int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *, bus_dmamap_t)); 190 static int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *, bus_dmamap_t)); 191 static int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *)); 192 static int ti_init_rx_ring_std __P((struct ti_softc *)); 193 static void ti_free_rx_ring_std __P((struct ti_softc *)); 194 static int ti_init_rx_ring_jumbo __P((struct ti_softc *)); 195 static void ti_free_rx_ring_jumbo __P((struct ti_softc *)); 196 static int ti_init_rx_ring_mini __P((struct ti_softc *)); 197 static void ti_free_rx_ring_mini __P((struct ti_softc *)); 198 static void ti_free_tx_ring __P((struct ti_softc *)); 199 static int ti_init_tx_ring __P((struct ti_softc *)); 200 201 static int ti_64bitslot_war __P((struct ti_softc *)); 202 static int ti_chipinit __P((struct ti_softc *)); 203 static int ti_gibinit __P((struct ti_softc *)); 204 205 static int ti_ether_ioctl __P((struct ifnet *, u_long, caddr_t)); 206 207 struct cfattach ti_ca = { 208 sizeof(struct ti_softc), ti_probe, ti_attach 209 }; 210 211 /* 212 * Send an instruction or address to the EEPROM, check for ACK. 213 */ 214 static u_int32_t ti_eeprom_putbyte(sc, byte) 215 struct ti_softc *sc; 216 int byte; 217 { 218 int i, ack = 0; 219 220 /* 221 * Make sure we're in TX mode. 222 */ 223 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 224 225 /* 226 * Feed in each bit and stobe the clock. 227 */ 228 for (i = 0x80; i; i >>= 1) { 229 if (byte & i) { 230 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 231 } else { 232 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 233 } 234 DELAY(1); 235 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 236 DELAY(1); 237 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 238 } 239 240 /* 241 * Turn off TX mode. 242 */ 243 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 244 245 /* 246 * Check for ack. 247 */ 248 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 249 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 250 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 251 252 return(ack); 253 } 254 255 /* 256 * Read a byte of data stored in the EEPROM at address 'addr.' 257 * We have to send two address bytes since the EEPROM can hold 258 * more than 256 bytes of data. 259 */ 260 static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 261 struct ti_softc *sc; 262 int addr; 263 u_int8_t *dest; 264 { 265 int i; 266 u_int8_t byte = 0; 267 268 EEPROM_START; 269 270 /* 271 * Send write control code to EEPROM. 272 */ 273 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 274 printf("%s: failed to send write command, status: %x\n", 275 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 276 return(1); 277 } 278 279 /* 280 * Send first byte of address of byte we want to read. 281 */ 282 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 283 printf("%s: failed to send address, status: %x\n", 284 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 285 return(1); 286 } 287 /* 288 * Send second byte address of byte we want to read. 289 */ 290 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 291 printf("%s: failed to send address, status: %x\n", 292 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 293 return(1); 294 } 295 296 EEPROM_STOP; 297 EEPROM_START; 298 /* 299 * Send read control code to EEPROM. 300 */ 301 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 302 printf("%s: failed to send read command, status: %x\n", 303 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 304 return(1); 305 } 306 307 /* 308 * Start reading bits from EEPROM. 309 */ 310 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 311 for (i = 0x80; i; i >>= 1) { 312 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 313 DELAY(1); 314 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 315 byte |= i; 316 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 317 DELAY(1); 318 } 319 320 EEPROM_STOP; 321 322 /* 323 * No ACK generated for read, so just return byte. 324 */ 325 326 *dest = byte; 327 328 return(0); 329 } 330 331 /* 332 * Read a sequence of bytes from the EEPROM. 333 */ 334 static int ti_read_eeprom(sc, dest, off, cnt) 335 struct ti_softc *sc; 336 caddr_t dest; 337 int off; 338 int cnt; 339 { 340 int err = 0, i; 341 u_int8_t byte = 0; 342 343 for (i = 0; i < cnt; i++) { 344 err = ti_eeprom_getbyte(sc, off + i, &byte); 345 if (err) 346 break; 347 *(dest + i) = byte; 348 } 349 350 return(err ? 1 : 0); 351 } 352 353 /* 354 * NIC memory access function. Can be used to either clear a section 355 * of NIC local memory or (if buf is non-NULL) copy data into it. 356 */ 357 static void ti_mem(sc, addr, len, buf) 358 struct ti_softc *sc; 359 u_int32_t addr, len; 360 caddr_t buf; 361 { 362 int segptr, segsize, cnt; 363 caddr_t ptr; 364 365 segptr = addr; 366 cnt = len; 367 ptr = buf; 368 369 while(cnt) { 370 if (cnt < TI_WINLEN) 371 segsize = cnt; 372 else 373 segsize = TI_WINLEN - (segptr % TI_WINLEN); 374 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 375 if (buf == NULL) { 376 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 377 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, 378 segsize / 4); 379 } else { 380 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 381 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 382 (u_int32_t *)ptr, segsize / 4); 383 ptr += segsize; 384 } 385 segptr += segsize; 386 cnt -= segsize; 387 } 388 389 return; 390 } 391 392 /* 393 * Load firmware image into the NIC. Check that the firmware revision 394 * is acceptable and see if we want the firmware for the Tigon 1 or 395 * Tigon 2. 396 */ 397 static void ti_loadfw(sc) 398 struct ti_softc *sc; 399 { 400 switch(sc->ti_hwrev) { 401 case TI_HWREV_TIGON: 402 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 403 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 404 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 405 printf("%s: firmware revision mismatch; want " 406 "%d.%d.%d, got %d.%d.%d\n", sc->sc_dev.dv_xname, 407 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 408 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 409 tigonFwReleaseMinor, tigonFwReleaseFix); 410 return; 411 } 412 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 413 (caddr_t)tigonFwText); 414 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 415 (caddr_t)tigonFwData); 416 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 417 (caddr_t)tigonFwRodata); 418 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 419 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 420 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 421 break; 422 case TI_HWREV_TIGON_II: 423 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 424 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 425 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 426 printf("%s: firmware revision mismatch; want " 427 "%d.%d.%d, got %d.%d.%d\n", sc->sc_dev.dv_xname, 428 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 429 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 430 tigon2FwReleaseMinor, tigon2FwReleaseFix); 431 return; 432 } 433 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 434 (caddr_t)tigon2FwText); 435 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 436 (caddr_t)tigon2FwData); 437 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 438 (caddr_t)tigon2FwRodata); 439 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 440 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 441 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 442 break; 443 default: 444 printf("%s: can't load firmware: unknown hardware rev\n", 445 sc->sc_dev.dv_xname); 446 break; 447 } 448 449 return; 450 } 451 452 /* 453 * Send the NIC a command via the command ring. 454 */ 455 static void ti_cmd(sc, cmd) 456 struct ti_softc *sc; 457 struct ti_cmd_desc *cmd; 458 { 459 u_int32_t index; 460 461 index = sc->ti_cmd_saved_prodidx; 462 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 463 TI_INC(index, TI_CMD_RING_CNT); 464 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 465 sc->ti_cmd_saved_prodidx = index; 466 467 return; 468 } 469 470 /* 471 * Send the NIC an extended command. The 'len' parameter specifies the 472 * number of command slots to include after the initial command. 473 */ 474 static void ti_cmd_ext(sc, cmd, arg, len) 475 struct ti_softc *sc; 476 struct ti_cmd_desc *cmd; 477 caddr_t arg; 478 int len; 479 { 480 u_int32_t index; 481 int i; 482 483 index = sc->ti_cmd_saved_prodidx; 484 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 485 TI_INC(index, TI_CMD_RING_CNT); 486 for (i = 0; i < len; i++) { 487 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 488 *(u_int32_t *)(&arg[i * 4])); 489 TI_INC(index, TI_CMD_RING_CNT); 490 } 491 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 492 sc->ti_cmd_saved_prodidx = index; 493 494 return; 495 } 496 497 /* 498 * Handle events that have triggered interrupts. 499 */ 500 static void ti_handle_events(sc) 501 struct ti_softc *sc; 502 { 503 struct ti_event_desc *e; 504 505 if (sc->ti_rdata->ti_event_ring == NULL) 506 return; 507 508 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 509 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 510 switch(e->ti_event) { 511 case TI_EV_LINKSTAT_CHANGED: 512 sc->ti_linkstat = e->ti_code; 513 if (e->ti_code == TI_EV_CODE_LINK_UP) 514 printf("%s: 10/100 link up\n", 515 sc->sc_dev.dv_xname); 516 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 517 printf("%s: gigabit link up\n", 518 sc->sc_dev.dv_xname); 519 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 520 printf("%s: link down\n", 521 sc->sc_dev.dv_xname); 522 break; 523 case TI_EV_ERROR: 524 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 525 printf("%s: invalid command\n", 526 sc->sc_dev.dv_xname); 527 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 528 printf("%s: unknown command\n", 529 sc->sc_dev.dv_xname); 530 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 531 printf("%s: bad config data\n", 532 sc->sc_dev.dv_xname); 533 break; 534 case TI_EV_FIRMWARE_UP: 535 ti_init2(sc); 536 break; 537 case TI_EV_STATS_UPDATED: 538 ti_stats_update(sc); 539 break; 540 case TI_EV_RESET_JUMBO_RING: 541 case TI_EV_MCAST_UPDATED: 542 /* Who cares. */ 543 break; 544 default: 545 printf("%s: unknown event: %d\n", 546 sc->sc_dev.dv_xname, e->ti_event); 547 break; 548 } 549 /* Advance the consumer index. */ 550 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 551 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 552 } 553 554 return; 555 } 556 557 /* 558 * Memory management for the jumbo receive ring is a pain in the 559 * butt. We need to allocate at least 9018 bytes of space per frame, 560 * _and_ it has to be contiguous (unless you use the extended 561 * jumbo descriptor format). Using malloc() all the time won't 562 * work: malloc() allocates memory in powers of two, which means we 563 * would end up wasting a considerable amount of space by allocating 564 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 565 * to do our own memory management. 566 * 567 * The driver needs to allocate a contiguous chunk of memory at boot 568 * time. We then chop this up ourselves into 9K pieces and use them 569 * as external mbuf storage. 570 * 571 * One issue here is how much memory to allocate. The jumbo ring has 572 * 256 slots in it, but at 9K per slot than can consume over 2MB of 573 * RAM. This is a bit much, especially considering we also need 574 * RAM for the standard ring and mini ring (on the Tigon 2). To 575 * save space, we only actually allocate enough memory for 64 slots 576 * by default, which works out to between 500 and 600K. This can 577 * be tuned by changing a #define in if_tireg.h. 578 */ 579 580 static int ti_alloc_jumbo_mem(sc) 581 struct ti_softc *sc; 582 { 583 caddr_t ptr; 584 int i; 585 struct ti_jpool_entry *entry; 586 bus_dma_segment_t dmaseg; 587 int error, dmanseg; 588 589 /* Grab a big chunk o' storage. */ 590 if ((error = bus_dmamem_alloc(sc->sc_dmat, 591 TI_JMEM, NBPG, 0, &dmaseg, 1, &dmanseg, 592 BUS_DMA_NOWAIT)) != 0) { 593 printf("%s: can't allocate jumbo buffer, error = %d\n", 594 sc->sc_dev.dv_xname, error); 595 return (error); 596 } 597 598 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 599 TI_JMEM, (caddr_t *)&sc->ti_cdata.ti_jumbo_buf, 600 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 601 printf("%s: can't map jumbo buffer, error = %d\n", 602 sc->sc_dev.dv_xname, error); 603 return (error); 604 } 605 606 if ((error = bus_dmamap_create(sc->sc_dmat, 607 TI_JMEM, 1, 608 TI_JMEM, 0, BUS_DMA_NOWAIT, 609 &sc->jumbo_dmamap)) != 0) { 610 printf("%s: can't create jumbo buffer DMA map, error = %d\n", 611 sc->sc_dev.dv_xname, error); 612 return (error); 613 } 614 615 if ((error = bus_dmamap_load(sc->sc_dmat, sc->jumbo_dmamap, 616 sc->ti_cdata.ti_jumbo_buf, TI_JMEM, NULL, 617 BUS_DMA_NOWAIT)) != 0) { 618 printf("%s: can't load jumbo buffer DMA map, error = %d\n", 619 sc->sc_dev.dv_xname, error); 620 return (error); 621 } 622 sc->jumbo_dmaaddr = sc->jumbo_dmamap->dm_segs[0].ds_addr; 623 624 SIMPLEQ_INIT(&sc->ti_jfree_listhead); 625 SIMPLEQ_INIT(&sc->ti_jinuse_listhead); 626 627 /* 628 * Now divide it up into 9K pieces and save the addresses 629 * in an array. Note that we play an evil trick here by using 630 * the first few bytes in the buffer to hold the address 631 * of the softc structure for this interface. This is because 632 * ti_jfree() needs it, but it is called by the mbuf management 633 * code which will not pass it to us explicitly. 634 */ 635 ptr = sc->ti_cdata.ti_jumbo_buf; 636 for (i = 0; i < TI_JSLOTS; i++) { 637 u_int64_t **aptr; 638 aptr = (u_int64_t **)ptr; 639 aptr[0] = (u_int64_t *)sc; 640 ptr += sizeof(u_int64_t); 641 sc->ti_cdata.ti_jslots[i].ti_buf = ptr; 642 sc->ti_cdata.ti_jslots[i].ti_inuse = 0; 643 ptr += (TI_JLEN - sizeof(u_int64_t)); 644 entry = malloc(sizeof(struct ti_jpool_entry), 645 M_DEVBUF, M_NOWAIT); 646 if (entry == NULL) { 647 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF); 648 sc->ti_cdata.ti_jumbo_buf = NULL; 649 printf("%s: no memory for jumbo " 650 "buffer queue!\n", sc->sc_dev.dv_xname); 651 return(ENOBUFS); 652 } 653 entry->slot = i; 654 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, 655 jpool_entries); 656 } 657 658 return(0); 659 } 660 661 /* 662 * Allocate a jumbo buffer. 663 */ 664 static void *ti_jalloc(sc) 665 struct ti_softc *sc; 666 { 667 struct ti_jpool_entry *entry; 668 669 entry = SIMPLEQ_FIRST(&sc->ti_jfree_listhead); 670 671 if (entry == NULL) { 672 printf("%s: no free jumbo buffers\n", sc->sc_dev.dv_xname); 673 return(NULL); 674 } 675 676 SIMPLEQ_REMOVE_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 677 SIMPLEQ_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 678 sc->ti_cdata.ti_jslots[entry->slot].ti_inuse = 1; 679 return(sc->ti_cdata.ti_jslots[entry->slot].ti_buf); 680 } 681 682 /* 683 * Release a jumbo buffer. 684 */ 685 static void ti_jfree(buf, size, arg) 686 caddr_t buf; 687 u_int size; 688 void *arg; /* XXX NetBSD: we should really use it */ 689 { 690 struct ti_softc *sc; 691 u_int64_t **aptr; 692 int i; 693 struct ti_jpool_entry *entry; 694 695 /* Extract the softc struct pointer. */ 696 aptr = (u_int64_t **)(buf - sizeof(u_int64_t)); 697 sc = (struct ti_softc *)(aptr[0]); 698 699 if (sc == NULL) 700 panic("ti_jfree: can't find softc pointer!"); 701 702 if (size != TI_JUMBO_FRAMELEN) 703 panic("ti_jfree: freeing buffer of wrong size!"); 704 705 /* calculate the slot this buffer belongs to */ 706 707 i = ((caddr_t)aptr 708 - (caddr_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 709 710 if ((i < 0) || (i >= TI_JSLOTS)) 711 panic("ti_jfree: asked to free buffer that we don't manage!"); 712 else if (sc->ti_cdata.ti_jslots[i].ti_inuse == 0) 713 panic("ti_jfree: buffer already free!"); 714 else { 715 sc->ti_cdata.ti_jslots[i].ti_inuse--; 716 if(sc->ti_cdata.ti_jslots[i].ti_inuse == 0) { 717 entry = SIMPLEQ_FIRST(&sc->ti_jinuse_listhead); 718 if (entry == NULL) 719 panic("ti_jfree: buffer not in use!"); 720 entry->slot = i; 721 SIMPLEQ_REMOVE_HEAD(&sc->ti_jinuse_listhead, 722 entry, jpool_entries); 723 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, 724 entry, jpool_entries); 725 } 726 } 727 728 return; 729 } 730 731 732 /* 733 * Intialize a standard receive ring descriptor. 734 */ 735 static int ti_newbuf_std(sc, i, m, dmamap) 736 struct ti_softc *sc; 737 int i; 738 struct mbuf *m; 739 bus_dmamap_t dmamap; /* required if (m != NULL) */ 740 { 741 struct mbuf *m_new = NULL; 742 struct ti_rx_desc *r; 743 int error; 744 745 if (dmamap == NULL) { 746 /* if (m) panic() */ 747 748 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 749 MCLBYTES, 0, BUS_DMA_NOWAIT, 750 &dmamap)) != 0) { 751 printf("%s: can't create recv map, error = %d\n", 752 sc->sc_dev.dv_xname, error); 753 return(ENOMEM); 754 } 755 } 756 sc->std_dmamap[i] = dmamap; 757 758 if (m == NULL) { 759 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 760 if (m_new == NULL) { 761 printf("%s: mbuf allocation failed " 762 "-- packet dropped!\n", sc->sc_dev.dv_xname); 763 return(ENOBUFS); 764 } 765 766 MCLGET(m_new, M_DONTWAIT); 767 if (!(m_new->m_flags & M_EXT)) { 768 printf("%s: cluster allocation failed " 769 "-- packet dropped!\n", sc->sc_dev.dv_xname); 770 m_freem(m_new); 771 return(ENOBUFS); 772 } 773 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 774 m_adj(m_new, ETHER_ALIGN); 775 776 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 777 mtod(m_new, caddr_t), m_new->m_len, NULL, 778 BUS_DMA_NOWAIT)) != 0) { 779 printf("%s: can't load recv map, error = %d\n", 780 sc->sc_dev.dv_xname, error); 781 return (ENOMEM); 782 } 783 } else { 784 m_new = m; 785 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 786 m_new->m_data = m_new->m_ext.ext_buf; 787 m_adj(m_new, ETHER_ALIGN); 788 789 /* reuse the dmamap */ 790 } 791 792 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 793 r = &sc->ti_rdata->ti_rx_std_ring[i]; 794 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 795 r->ti_type = TI_BDTYPE_RECV_BD; 796 #ifdef TI_CSUM_OFFLOAD 797 r->ti_flags = TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 798 #else 799 r->ti_flags = 0; 800 #endif 801 r->ti_len = m_new->m_len; /* == ds_len */ 802 r->ti_idx = i; 803 804 return(0); 805 } 806 807 /* 808 * Intialize a mini receive ring descriptor. This only applies to 809 * the Tigon 2. 810 */ 811 static int ti_newbuf_mini(sc, i, m, dmamap) 812 struct ti_softc *sc; 813 int i; 814 struct mbuf *m; 815 bus_dmamap_t dmamap; /* required if (m != NULL) */ 816 { 817 struct mbuf *m_new = NULL; 818 struct ti_rx_desc *r; 819 int error; 820 821 if (dmamap == NULL) { 822 /* if (m) panic() */ 823 824 if ((error = bus_dmamap_create(sc->sc_dmat, MHLEN, 1, 825 MHLEN, 0, BUS_DMA_NOWAIT, 826 &dmamap)) != 0) { 827 printf("%s: can't create recv map, error = %d\n", 828 sc->sc_dev.dv_xname, error); 829 return(ENOMEM); 830 } 831 } 832 sc->mini_dmamap[i] = dmamap; 833 834 if (m == NULL) { 835 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 836 if (m_new == NULL) { 837 printf("%s: mbuf allocation failed " 838 "-- packet dropped!\n", sc->sc_dev.dv_xname); 839 return(ENOBUFS); 840 } 841 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 842 m_adj(m_new, ETHER_ALIGN); 843 844 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 845 mtod(m_new, caddr_t), m_new->m_len, NULL, 846 BUS_DMA_NOWAIT)) != 0) { 847 printf("%s: can't load recv map, error = %d\n", 848 sc->sc_dev.dv_xname, error); 849 return (ENOMEM); 850 } 851 } else { 852 m_new = m; 853 m_new->m_data = m_new->m_pktdat; 854 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 855 m_adj(m_new, ETHER_ALIGN); 856 857 /* reuse the dmamap */ 858 } 859 860 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 861 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 862 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 863 r->ti_type = TI_BDTYPE_RECV_BD; 864 r->ti_flags = TI_BDFLAG_MINI_RING; 865 #ifdef TI_CSUM_OFFLOAD 866 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 867 #endif 868 r->ti_len = m_new->m_len; /* == ds_len */ 869 r->ti_idx = i; 870 871 return(0); 872 } 873 874 /* 875 * Initialize a jumbo receive ring descriptor. This allocates 876 * a jumbo buffer from the pool managed internally by the driver. 877 */ 878 static int ti_newbuf_jumbo(sc, i, m) 879 struct ti_softc *sc; 880 int i; 881 struct mbuf *m; 882 { 883 struct mbuf *m_new = NULL; 884 struct ti_rx_desc *r; 885 886 if (m == NULL) { 887 caddr_t *buf = NULL; 888 889 /* Allocate the mbuf. */ 890 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 891 if (m_new == NULL) { 892 printf("%s: mbuf allocation failed " 893 "-- packet dropped!\n", sc->sc_dev.dv_xname); 894 return(ENOBUFS); 895 } 896 897 /* Allocate the jumbo buffer */ 898 buf = ti_jalloc(sc); 899 if (buf == NULL) { 900 m_freem(m_new); 901 printf("%s: jumbo allocation failed " 902 "-- packet dropped!\n", sc->sc_dev.dv_xname); 903 return(ENOBUFS); 904 } 905 906 /* Attach the buffer to the mbuf. */ 907 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 908 m_new->m_flags |= M_EXT; 909 m_new->m_len = m_new->m_pkthdr.len = 910 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 911 m_new->m_ext.ext_free = ti_jfree; 912 m_new->m_ext.ext_arg = sc; 913 MCLINITREFERENCE(m_new); 914 } else { 915 m_new = m; 916 m_new->m_data = m_new->m_ext.ext_buf; 917 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN; 918 } 919 920 m_adj(m_new, ETHER_ALIGN); 921 /* Set up the descriptor. */ 922 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 923 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 924 TI_HOSTADDR(r->ti_addr) = sc->jumbo_dmaaddr + 925 ((caddr_t)mtod(m_new, caddr_t) 926 - (caddr_t)sc->ti_cdata.ti_jumbo_buf); 927 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 928 r->ti_flags = TI_BDFLAG_JUMBO_RING; 929 #ifdef TI_CSUM_OFFLOAD 930 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM|TI_BDFLAG_IP_CKSUM; 931 #endif 932 r->ti_len = m_new->m_len; 933 r->ti_idx = i; 934 935 return(0); 936 } 937 938 /* 939 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 940 * that's 1MB or memory, which is a lot. For now, we fill only the first 941 * 256 ring entries and hope that our CPU is fast enough to keep up with 942 * the NIC. 943 */ 944 static int ti_init_rx_ring_std(sc) 945 struct ti_softc *sc; 946 { 947 int i; 948 struct ti_cmd_desc cmd; 949 950 for (i = 0; i < TI_SSLOTS; i++) { 951 if (ti_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 952 return(ENOBUFS); 953 }; 954 955 TI_UPDATE_STDPROD(sc, i - 1); 956 sc->ti_std = i - 1; 957 958 return(0); 959 } 960 961 static void ti_free_rx_ring_std(sc) 962 struct ti_softc *sc; 963 { 964 int i; 965 966 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 967 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 968 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 969 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 970 971 /* if (sc->std_dmamap[i] == 0) panic() */ 972 bus_dmamap_destroy(sc->sc_dmat, sc->std_dmamap[i]); 973 sc->std_dmamap[i] = 0; 974 } 975 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i], 976 sizeof(struct ti_rx_desc)); 977 } 978 979 return; 980 } 981 982 static int ti_init_rx_ring_jumbo(sc) 983 struct ti_softc *sc; 984 { 985 int i; 986 struct ti_cmd_desc cmd; 987 988 for (i = 0; i < (TI_JSLOTS - 20); i++) { 989 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 990 return(ENOBUFS); 991 }; 992 993 TI_UPDATE_JUMBOPROD(sc, i - 1); 994 sc->ti_jumbo = i - 1; 995 996 return(0); 997 } 998 999 static void ti_free_rx_ring_jumbo(sc) 1000 struct ti_softc *sc; 1001 { 1002 int i; 1003 1004 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 1005 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 1006 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 1007 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 1008 } 1009 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 1010 sizeof(struct ti_rx_desc)); 1011 } 1012 1013 return; 1014 } 1015 1016 static int ti_init_rx_ring_mini(sc) 1017 struct ti_softc *sc; 1018 { 1019 int i; 1020 1021 for (i = 0; i < TI_MSLOTS; i++) { 1022 if (ti_newbuf_mini(sc, i, NULL, 0) == ENOBUFS) 1023 return(ENOBUFS); 1024 }; 1025 1026 TI_UPDATE_MINIPROD(sc, i - 1); 1027 sc->ti_mini = i - 1; 1028 1029 return(0); 1030 } 1031 1032 static void ti_free_rx_ring_mini(sc) 1033 struct ti_softc *sc; 1034 { 1035 int i; 1036 1037 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1038 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1039 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1040 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1041 1042 /* if (sc->mini_dmamap[i] == 0) panic() */ 1043 bus_dmamap_destroy(sc->sc_dmat, sc->mini_dmamap[i]); 1044 sc->mini_dmamap[i] = 0; 1045 } 1046 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 1047 sizeof(struct ti_rx_desc)); 1048 } 1049 1050 return; 1051 } 1052 1053 static void ti_free_tx_ring(sc) 1054 struct ti_softc *sc; 1055 { 1056 int i; 1057 struct txdmamap_pool_entry *dma; 1058 1059 if (sc->ti_rdata->ti_tx_ring == NULL) 1060 return; 1061 1062 for (i = 0; i < TI_TX_RING_CNT; i++) { 1063 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1064 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1065 sc->ti_cdata.ti_tx_chain[i] = NULL; 1066 1067 /* if (sc->txdma[i] == 0) panic() */ 1068 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1069 link); 1070 sc->txdma[i] = 0; 1071 } 1072 bzero((char *)&sc->ti_rdata->ti_tx_ring[i], 1073 sizeof(struct ti_tx_desc)); 1074 } 1075 1076 while ((dma = SIMPLEQ_FIRST(&sc->txdma_list))) { 1077 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, dma, link); 1078 bus_dmamap_destroy(sc->sc_dmat, dma->dmamap); 1079 free(dma, M_DEVBUF); 1080 } 1081 1082 return; 1083 } 1084 1085 static int ti_init_tx_ring(sc) 1086 struct ti_softc *sc; 1087 { 1088 int i, error; 1089 bus_dmamap_t dmamap; 1090 struct txdmamap_pool_entry *dma; 1091 1092 sc->ti_txcnt = 0; 1093 sc->ti_tx_saved_considx = 0; 1094 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1095 1096 SIMPLEQ_INIT(&sc->txdma_list); 1097 for (i = 0; i < TI_RSLOTS; i++) { 1098 /* I've seen mbufs with 30 fragments. */ 1099 if ((error = bus_dmamap_create(sc->sc_dmat, TI_JUMBO_FRAMELEN, 1100 40, TI_JUMBO_FRAMELEN, 0, 1101 BUS_DMA_NOWAIT, &dmamap)) != 0) { 1102 printf("%s: can't create tx map, error = %d\n", 1103 sc->sc_dev.dv_xname, error); 1104 return(ENOMEM); 1105 } 1106 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1107 if (!dma) { 1108 printf("%s: can't alloc txdmamap_pool_entry\n", 1109 sc->sc_dev.dv_xname); 1110 bus_dmamap_destroy(sc->sc_dmat, dmamap); 1111 return (ENOMEM); 1112 } 1113 dma->dmamap = dmamap; 1114 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 1115 } 1116 1117 return(0); 1118 } 1119 1120 /* 1121 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1122 * but we have to support the old way too so that Tigon 1 cards will 1123 * work. 1124 */ 1125 void ti_add_mcast(sc, addr) 1126 struct ti_softc *sc; 1127 struct ether_addr *addr; 1128 { 1129 struct ti_cmd_desc cmd; 1130 u_int16_t *m; 1131 u_int32_t ext[2] = {0, 0}; 1132 1133 m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1134 1135 switch(sc->ti_hwrev) { 1136 case TI_HWREV_TIGON: 1137 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1138 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1139 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1140 break; 1141 case TI_HWREV_TIGON_II: 1142 ext[0] = htons(m[0]); 1143 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1144 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1145 break; 1146 default: 1147 printf("%s: unknown hwrev\n", sc->sc_dev.dv_xname); 1148 break; 1149 } 1150 1151 return; 1152 } 1153 1154 void ti_del_mcast(sc, addr) 1155 struct ti_softc *sc; 1156 struct ether_addr *addr; 1157 { 1158 struct ti_cmd_desc cmd; 1159 u_int16_t *m; 1160 u_int32_t ext[2] = {0, 0}; 1161 1162 m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1163 1164 switch(sc->ti_hwrev) { 1165 case TI_HWREV_TIGON: 1166 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1167 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1168 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1169 break; 1170 case TI_HWREV_TIGON_II: 1171 ext[0] = htons(m[0]); 1172 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1173 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1174 break; 1175 default: 1176 printf("%s: unknown hwrev\n", sc->sc_dev.dv_xname); 1177 break; 1178 } 1179 1180 return; 1181 } 1182 1183 /* 1184 * Configure the Tigon's multicast address filter. 1185 * 1186 * The actual multicast table management is a bit of a pain, thanks to 1187 * slight brain damage on the part of both Alteon and us. With our 1188 * multicast code, we are only alerted when the multicast address table 1189 * changes and at that point we only have the current list of addresses: 1190 * we only know the current state, not the previous state, so we don't 1191 * actually know what addresses were removed or added. The firmware has 1192 * state, but we can't get our grubby mits on it, and there is no 'delete 1193 * all multicast addresses' command. Hence, we have to maintain our own 1194 * state so we know what addresses have been programmed into the NIC at 1195 * any given time. 1196 */ 1197 static void ti_setmulti(sc) 1198 struct ti_softc *sc; 1199 { 1200 struct ifnet *ifp; 1201 struct ti_cmd_desc cmd; 1202 struct ti_mc_entry *mc; 1203 u_int32_t intrs; 1204 struct ether_multi *enm; 1205 struct ether_multistep step; 1206 1207 ifp = &sc->ethercom.ec_if; 1208 1209 if (ifp->if_flags & IFF_ALLMULTI) { 1210 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1211 return; 1212 } else { 1213 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1214 } 1215 1216 /* Disable interrupts. */ 1217 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1218 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1219 1220 /* First, zot all the existing filters. */ 1221 while (SIMPLEQ_FIRST(&sc->ti_mc_listhead) != NULL) { 1222 mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead); 1223 ti_del_mcast(sc, &mc->mc_addr); 1224 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1225 free(mc, M_DEVBUF); 1226 } 1227 1228 /* Now program new ones. */ 1229 ETHER_FIRST_MULTI(step, &sc->ethercom, enm); 1230 while (enm != NULL) { 1231 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT); 1232 bcopy(enm->enm_addrlo, 1233 (char *)&mc->mc_addr, ETHER_ADDR_LEN); 1234 SIMPLEQ_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1235 ti_add_mcast(sc, &mc->mc_addr); 1236 ETHER_NEXT_MULTI(step, enm); 1237 } 1238 1239 /* Re-enable interrupts. */ 1240 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1241 1242 return; 1243 } 1244 1245 /* 1246 * Check to see if the BIOS has configured us for a 64 bit slot when 1247 * we aren't actually in one. If we detect this condition, we can work 1248 * around it on the Tigon 2 by setting a bit in the PCI state register, 1249 * but for the Tigon 1 we must give up and abort the interface attach. 1250 */ 1251 static int ti_64bitslot_war(sc) 1252 struct ti_softc *sc; 1253 { 1254 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1255 CSR_WRITE_4(sc, 0x600, 0); 1256 CSR_WRITE_4(sc, 0x604, 0); 1257 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1258 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1259 if (sc->ti_hwrev == TI_HWREV_TIGON) 1260 return(EINVAL); 1261 else { 1262 TI_SETBIT(sc, TI_PCI_STATE, 1263 TI_PCISTATE_32BIT_BUS); 1264 return(0); 1265 } 1266 } 1267 } 1268 1269 return(0); 1270 } 1271 1272 /* 1273 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1274 * self-test results. 1275 */ 1276 static int ti_chipinit(sc) 1277 struct ti_softc *sc; 1278 { 1279 u_int32_t cacheline; 1280 u_int32_t pci_writemax = 0; 1281 1282 /* Initialize link to down state. */ 1283 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1284 1285 /* Set endianness before we access any non-PCI registers. */ 1286 #if BYTE_ORDER == BIG_ENDIAN 1287 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1288 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1289 #else 1290 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1291 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1292 #endif 1293 1294 /* Check the ROM failed bit to see if self-tests passed. */ 1295 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1296 printf("%s: board self-diagnostics failed!\n", 1297 sc->sc_dev.dv_xname); 1298 return(ENODEV); 1299 } 1300 1301 /* Halt the CPU. */ 1302 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1303 1304 /* Figure out the hardware revision. */ 1305 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1306 case TI_REV_TIGON_I: 1307 sc->ti_hwrev = TI_HWREV_TIGON; 1308 break; 1309 case TI_REV_TIGON_II: 1310 sc->ti_hwrev = TI_HWREV_TIGON_II; 1311 break; 1312 default: 1313 printf("%s: unsupported chip revision\n", sc->sc_dev.dv_xname); 1314 return(ENODEV); 1315 } 1316 1317 /* Do special setup for Tigon 2. */ 1318 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1319 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1320 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 1321 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1322 } 1323 1324 /* Set up the PCI state register. */ 1325 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1326 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1327 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1328 } 1329 1330 /* Clear the read/write max DMA parameters. */ 1331 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1332 TI_PCISTATE_READ_MAXDMA)); 1333 1334 /* Get cache line size. */ 1335 cacheline = PCI_CACHELINE(CSR_READ_4(sc, PCI_BHLC_REG)); 1336 1337 /* 1338 * If the system has set enabled the PCI memory write 1339 * and invalidate command in the command register, set 1340 * the write max parameter accordingly. This is necessary 1341 * to use MWI with the Tigon 2. 1342 */ 1343 if (CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1344 & PCI_COMMAND_INVALIDATE_ENABLE) { 1345 switch(cacheline) { 1346 case 1: 1347 case 4: 1348 case 8: 1349 case 16: 1350 case 32: 1351 case 64: 1352 break; 1353 default: 1354 /* Disable PCI memory write and invalidate. */ 1355 if (bootverbose) 1356 printf("%s: cache line size %d not " 1357 "supported; disabling PCI MWI\n", 1358 sc->sc_dev.dv_xname, cacheline); 1359 CSR_WRITE_4(sc, PCI_COMMAND_STATUS_REG, 1360 CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1361 & ~PCI_COMMAND_INVALIDATE_ENABLE); 1362 break; 1363 } 1364 } 1365 1366 #ifdef __brokenalpha__ 1367 /* 1368 * From the Alteon sample driver: 1369 * Must insure that we do not cross an 8K (bytes) boundary 1370 * for DMA reads. Our highest limit is 1K bytes. This is a 1371 * restriction on some ALPHA platforms with early revision 1372 * 21174 PCI chipsets, such as the AlphaPC 164lx 1373 */ 1374 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1375 #else 1376 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1377 #endif 1378 1379 /* This sets the min dma param all the way up (0xff). */ 1380 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1381 1382 /* Configure DMA variables. */ 1383 #if BYTE_ORDER == BIG_ENDIAN 1384 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1385 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1386 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1387 TI_OPMODE_DONT_FRAG_JUMBO); 1388 #else 1389 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1390 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1391 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1392 #endif 1393 1394 /* 1395 * Only allow 1 DMA channel to be active at a time. 1396 * I don't think this is a good idea, but without it 1397 * the firmware racks up lots of nicDmaReadRingFull 1398 * errors. 1399 */ 1400 #ifndef TI_CSUM_OFFLOAD 1401 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1402 #endif 1403 1404 /* Recommended settings from Tigon manual. */ 1405 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1406 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1407 1408 if (ti_64bitslot_war(sc)) { 1409 printf("%s: bios thinks we're in a 64 bit slot, " 1410 "but we aren't", sc->sc_dev.dv_xname); 1411 return(EINVAL); 1412 } 1413 1414 return(0); 1415 } 1416 1417 /* 1418 * Initialize the general information block and firmware, and 1419 * start the CPU(s) running. 1420 */ 1421 static int ti_gibinit(sc) 1422 struct ti_softc *sc; 1423 { 1424 struct ti_rcb *rcb; 1425 int i; 1426 struct ifnet *ifp; 1427 1428 ifp = &sc->ethercom.ec_if; 1429 1430 /* Disable interrupts for now. */ 1431 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1432 1433 /* Tell the chip where to find the general information block. */ 1434 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1435 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, sc->info_dmaaddr + 1436 ((caddr_t)&sc->ti_rdata->ti_info - (caddr_t)sc->ti_rdata)); 1437 1438 /* Load the firmware into SRAM. */ 1439 ti_loadfw(sc); 1440 1441 /* Set up the contents of the general info and ring control blocks. */ 1442 1443 /* Set up the event ring and producer pointer. */ 1444 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1445 1446 TI_HOSTADDR(rcb->ti_hostaddr) = sc->info_dmaaddr + 1447 ((caddr_t)&sc->ti_rdata->ti_event_ring - (caddr_t)sc->ti_rdata); 1448 rcb->ti_flags = 0; 1449 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1450 sc->info_dmaaddr + ((caddr_t)&sc->ti_rdata->ti_ev_prodidx_r 1451 - (caddr_t)sc->ti_rdata); 1452 sc->ti_ev_prodidx.ti_idx = 0; 1453 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1454 sc->ti_ev_saved_considx = 0; 1455 1456 /* Set up the command ring and producer mailbox. */ 1457 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1458 1459 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1460 rcb->ti_flags = 0; 1461 rcb->ti_max_len = 0; 1462 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1463 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1464 } 1465 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1466 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1467 sc->ti_cmd_saved_prodidx = 0; 1468 1469 /* 1470 * Assign the address of the stats refresh buffer. 1471 * We re-use the current stats buffer for this to 1472 * conserve memory. 1473 */ 1474 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1475 sc->info_dmaaddr + ((caddr_t)&sc->ti_rdata->ti_info.ti_stats 1476 - (caddr_t)sc->ti_rdata); 1477 1478 /* Set up the standard receive ring. */ 1479 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1480 TI_HOSTADDR(rcb->ti_hostaddr) = sc->info_dmaaddr + 1481 ((caddr_t)&sc->ti_rdata->ti_rx_std_ring 1482 - (caddr_t)sc->ti_rdata); 1483 rcb->ti_max_len = TI_FRAMELEN; 1484 rcb->ti_flags = 0; 1485 #ifdef TI_CSUM_OFFLOAD 1486 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM; 1487 #endif 1488 #if NVLAN > 0 1489 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1490 #endif 1491 1492 /* Set up the jumbo receive ring. */ 1493 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1494 TI_HOSTADDR(rcb->ti_hostaddr) = sc->info_dmaaddr + 1495 ((caddr_t)&sc->ti_rdata->ti_rx_jumbo_ring - (caddr_t)sc->ti_rdata); 1496 rcb->ti_max_len = TI_JUMBO_FRAMELEN; 1497 rcb->ti_flags = 0; 1498 #ifdef TI_CSUM_OFFLOAD 1499 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM; 1500 #endif 1501 #if NVLAN > 0 1502 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1503 #endif 1504 1505 /* 1506 * Set up the mini ring. Only activated on the 1507 * Tigon 2 but the slot in the config block is 1508 * still there on the Tigon 1. 1509 */ 1510 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1511 TI_HOSTADDR(rcb->ti_hostaddr) = sc->info_dmaaddr + 1512 ((caddr_t)&sc->ti_rdata->ti_rx_mini_ring - (caddr_t)sc->ti_rdata); 1513 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1514 if (sc->ti_hwrev == TI_HWREV_TIGON) 1515 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1516 else 1517 rcb->ti_flags = 0; 1518 #ifdef TI_CSUM_OFFLOAD 1519 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM|TI_RCB_FLAG_IP_CKSUM; 1520 #endif 1521 #if NVLAN > 0 1522 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1523 #endif 1524 1525 /* 1526 * Set up the receive return ring. 1527 */ 1528 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1529 TI_HOSTADDR(rcb->ti_hostaddr) = sc->info_dmaaddr + 1530 ((caddr_t)&sc->ti_rdata->ti_rx_return_ring - (caddr_t)sc->ti_rdata); 1531 rcb->ti_flags = 0; 1532 rcb->ti_max_len = TI_RETURN_RING_CNT; 1533 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1534 sc->info_dmaaddr + ((caddr_t)&sc->ti_rdata->ti_return_prodidx_r 1535 - (caddr_t)sc->ti_rdata); 1536 1537 /* 1538 * Set up the tx ring. Note: for the Tigon 2, we have the option 1539 * of putting the transmit ring in the host's address space and 1540 * letting the chip DMA it instead of leaving the ring in the NIC's 1541 * memory and accessing it through the shared memory region. We 1542 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1543 * so we have to revert to the shared memory scheme if we detect 1544 * a Tigon 1 chip. 1545 */ 1546 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1547 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1548 sc->ti_rdata->ti_tx_ring_nic = 1549 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1550 } 1551 bzero((char *)sc->ti_rdata->ti_tx_ring, 1552 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1553 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1554 if (sc->ti_hwrev == TI_HWREV_TIGON) 1555 rcb->ti_flags = 0; 1556 else 1557 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1558 #if NVLAN > 0 1559 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1560 #endif 1561 rcb->ti_max_len = TI_TX_RING_CNT; 1562 if (sc->ti_hwrev == TI_HWREV_TIGON) 1563 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1564 else 1565 TI_HOSTADDR(rcb->ti_hostaddr) = sc->info_dmaaddr + 1566 ((caddr_t)&sc->ti_rdata->ti_tx_ring 1567 - (caddr_t)sc->ti_rdata); 1568 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1569 sc->info_dmaaddr + ((caddr_t)&sc->ti_rdata->ti_tx_considx_r 1570 - (caddr_t)sc->ti_rdata); 1571 1572 /* Set up tuneables */ 1573 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 1574 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1575 (sc->ti_rx_coal_ticks / 10)); 1576 else 1577 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1578 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1579 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1580 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1581 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1582 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1583 1584 /* Turn interrupts on. */ 1585 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1586 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1587 1588 /* Start CPU. */ 1589 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1590 1591 return(0); 1592 } 1593 1594 /* 1595 * look for id in the device list, returning the first match 1596 */ 1597 static struct ti_type * ti_type_match(pa) 1598 struct pci_attach_args *pa; 1599 { 1600 struct ti_type *t; 1601 1602 t = ti_devs; 1603 while(t->ti_name != NULL) { 1604 if ((PCI_VENDOR(pa->pa_id) == t->ti_vid) && 1605 (PCI_PRODUCT(pa->pa_id) == t->ti_did)) { 1606 return (t); 1607 } 1608 t++; 1609 } 1610 1611 return(NULL); 1612 } 1613 1614 /* 1615 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1616 * against our list and return its name if we find a match. 1617 */ 1618 static int ti_probe(parent, match, aux) 1619 struct device *parent; 1620 struct cfdata *match; 1621 void *aux; 1622 { 1623 struct pci_attach_args *pa = aux; 1624 struct ti_type *t; 1625 1626 t = ti_type_match(pa); 1627 1628 return((t == NULL) ? 0 : 1); 1629 } 1630 1631 static void ti_attach(parent, self, aux) 1632 struct device *parent, *self; 1633 void *aux; 1634 { 1635 u_int32_t command; 1636 struct ifnet *ifp; 1637 struct ti_softc *sc; 1638 u_char eaddr[ETHER_ADDR_LEN]; 1639 struct pci_attach_args *pa = aux; 1640 pci_chipset_tag_t pc = pa->pa_pc; 1641 pci_intr_handle_t ih; 1642 const char *intrstr = NULL; 1643 bus_dma_segment_t dmaseg; 1644 int error, dmanseg, nolinear; 1645 struct ti_type *t; 1646 1647 t = ti_type_match(pa); 1648 if (t == NULL) { 1649 printf("ti_attach: were did the card go ?\n"); 1650 return; 1651 } 1652 1653 printf(": %s (rev. 0x%02x)\n", t->ti_name, PCI_REVISION(pa->pa_class)); 1654 1655 sc = (struct ti_softc *)self; 1656 1657 /* 1658 * Map control/status registers. 1659 */ 1660 nolinear = 0; 1661 if (pci_mapreg_map(pa, 0x10, 1662 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1663 BUS_SPACE_MAP_LINEAR , &sc->ti_btag, &sc->ti_bhandle, 1664 NULL, NULL)) { 1665 nolinear = 1; 1666 if (pci_mapreg_map(pa, 0x10, 1667 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1668 0 , &sc->ti_btag, &sc->ti_bhandle, NULL, NULL)) { 1669 printf(": can't map memory space\n"); 1670 return; 1671 } 1672 } 1673 if (nolinear == 0) 1674 sc->ti_vhandle = (void *)(sc->ti_bhandle); /* XXX XXX XXX */ 1675 else 1676 sc->ti_vhandle = NULL; 1677 1678 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1679 command |= PCI_COMMAND_MASTER_ENABLE; 1680 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1681 1682 /* Allocate interrupt */ 1683 if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin, 1684 pa->pa_intrline, &ih)) { 1685 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 1686 return;; 1687 } 1688 intrstr = pci_intr_string(pc, ih); 1689 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ti_intr, sc); 1690 if (sc->sc_ih == NULL) { 1691 printf("%s: couldn't establish interrupt", 1692 sc->sc_dev.dv_xname); 1693 if (intrstr != NULL) 1694 printf(" at %s", intrstr); 1695 printf("\n"); 1696 return;; 1697 } 1698 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 1699 /* 1700 * Add shutdown hook so that DMA is disabled prior to reboot. Not 1701 * doing do could allow DMA to corrupt kernel memory during the 1702 * reboot before the driver initializes. 1703 */ 1704 (void) shutdownhook_establish(ti_shutdown, sc); 1705 1706 if (ti_chipinit(sc)) { 1707 printf("%s: chip initialization failed\n", self->dv_xname); 1708 goto fail2; 1709 } 1710 if (sc->ti_hwrev == TI_HWREV_TIGON && nolinear == 1) { 1711 printf("%s: memory space not mapped linear\n", self->dv_xname); 1712 } 1713 1714 /* Zero out the NIC's on-board SRAM. */ 1715 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1716 1717 /* Init again -- zeroing memory may have clobbered some registers. */ 1718 if (ti_chipinit(sc)) { 1719 printf("%s: chip initialization failed\n", self->dv_xname); 1720 goto fail2; 1721 } 1722 1723 /* 1724 * Get station address from the EEPROM. Note: the manual states 1725 * that the MAC address is at offset 0x8c, however the data is 1726 * stored as two longwords (since that's how it's loaded into 1727 * the NIC). This means the MAC address is actually preceeded 1728 * by two zero bytes. We need to skip over those. 1729 */ 1730 if (ti_read_eeprom(sc, (caddr_t)&eaddr, 1731 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1732 printf("%s: failed to read station address\n", self->dv_xname); 1733 goto fail2; 1734 } 1735 1736 /* 1737 * A Tigon chip was detected. Inform the world. 1738 */ 1739 printf("%s: Ethernet address: %s\n", self->dv_xname, 1740 ether_sprintf(eaddr)); 1741 1742 sc->sc_dmat = pa->pa_dmat; 1743 1744 /* Allocate the general information block and ring buffers. */ 1745 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1746 sizeof(struct ti_ring_data), NBPG, 0, &dmaseg, 1, &dmanseg, 1747 BUS_DMA_NOWAIT)) != 0) { 1748 printf("%s: can't allocate ring buffer, error = %d\n", 1749 sc->sc_dev.dv_xname, error); 1750 goto fail2; 1751 } 1752 1753 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 1754 sizeof(struct ti_ring_data), (caddr_t *)&sc->ti_rdata, 1755 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1756 printf("%s: can't map ring buffer, error = %d\n", 1757 sc->sc_dev.dv_xname, error); 1758 goto fail2; 1759 } 1760 1761 if ((error = bus_dmamap_create(sc->sc_dmat, 1762 sizeof(struct ti_ring_data), 1, 1763 sizeof(struct ti_ring_data), 0, BUS_DMA_NOWAIT, 1764 &sc->info_dmamap)) != 0) { 1765 printf("%s: can't create ring buffer DMA map, error = %d\n", 1766 sc->sc_dev.dv_xname, error); 1767 goto fail2; 1768 } 1769 1770 if ((error = bus_dmamap_load(sc->sc_dmat, sc->info_dmamap, 1771 sc->ti_rdata, sizeof(struct ti_ring_data), NULL, 1772 BUS_DMA_NOWAIT)) != 0) { 1773 printf("%s: can't load ring buffer DMA map, error = %d\n", 1774 sc->sc_dev.dv_xname, error); 1775 goto fail2; 1776 } 1777 1778 sc->info_dmaaddr = sc->info_dmamap->dm_segs[0].ds_addr; 1779 1780 bzero(sc->ti_rdata, sizeof(struct ti_ring_data)); 1781 1782 /* Try to allocate memory for jumbo buffers. */ 1783 if (ti_alloc_jumbo_mem(sc)) { 1784 printf("%s: jumbo buffer allocation failed\n", self->dv_xname); 1785 goto fail2; 1786 } 1787 1788 /* Set default tuneable values. */ 1789 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1790 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1791 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1792 sc->ti_rx_max_coal_bds = 64; 1793 sc->ti_tx_max_coal_bds = 128; 1794 sc->ti_tx_buf_ratio = 21; 1795 1796 /* Set up ifnet structure */ 1797 ifp = &sc->ethercom.ec_if; 1798 ifp->if_softc = sc; 1799 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 1800 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1801 ifp->if_ioctl = ti_ioctl; 1802 ifp->if_start = ti_start; 1803 ifp->if_watchdog = ti_watchdog; 1804 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1805 1806 /* Set up ifmedia support. */ 1807 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1808 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1809 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1810 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1811 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX|IFM_FDX, 0, NULL); 1812 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1813 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1814 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1815 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1816 1817 /* 1818 * Call MI attach routines. 1819 */ 1820 if_attach(ifp); 1821 ether_ifattach(ifp, eaddr); 1822 1823 #if NBPFILTER > 0 1824 bpfattach(&sc->ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 1825 sizeof(struct ether_header)); 1826 #endif 1827 1828 return; 1829 fail2: 1830 pci_intr_disestablish(pc, sc->sc_ih); 1831 return; 1832 } 1833 1834 /* 1835 * Frame reception handling. This is called if there's a frame 1836 * on the receive return list. 1837 * 1838 * Note: we have to be able to handle three possibilities here: 1839 * 1) the frame is from the mini receive ring (can only happen) 1840 * on Tigon 2 boards) 1841 * 2) the frame is from the jumbo recieve ring 1842 * 3) the frame is from the standard receive ring 1843 */ 1844 1845 static void ti_rxeof(sc) 1846 struct ti_softc *sc; 1847 { 1848 struct ifnet *ifp; 1849 struct ti_cmd_desc cmd; 1850 1851 ifp = &sc->ethercom.ec_if; 1852 1853 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1854 struct ti_rx_desc *cur_rx; 1855 u_int32_t rxidx; 1856 struct ether_header *eh; 1857 struct mbuf *m = NULL; 1858 #if NVLAN > 0 1859 u_int16_t vlan_tag = 0; 1860 int have_tag = 0; 1861 #endif 1862 #ifdef TI_CSUM_OFFLOAD 1863 struct ip *ip; 1864 #endif 1865 bus_dmamap_t dmamap; 1866 1867 cur_rx = 1868 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1869 rxidx = cur_rx->ti_idx; 1870 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1871 1872 #if NVLAN > 0 1873 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 1874 have_tag = 1; 1875 vlan_tag = cur_rx->ti_vlan_tag; 1876 } 1877 #endif 1878 1879 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1880 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1881 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1882 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1883 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1884 ifp->if_ierrors++; 1885 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1886 continue; 1887 } 1888 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) 1889 == ENOBUFS) { 1890 ifp->if_ierrors++; 1891 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1892 continue; 1893 } 1894 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1895 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1896 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1897 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1898 dmamap = sc->mini_dmamap[rxidx]; 1899 sc->mini_dmamap[rxidx] = 0; 1900 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1901 ifp->if_ierrors++; 1902 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1903 continue; 1904 } 1905 if (ti_newbuf_mini(sc, sc->ti_mini, NULL, dmamap) 1906 == ENOBUFS) { 1907 ifp->if_ierrors++; 1908 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1909 continue; 1910 } 1911 } else { 1912 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1913 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1914 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 1915 dmamap = sc->std_dmamap[rxidx]; 1916 sc->std_dmamap[rxidx] = 0; 1917 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1918 ifp->if_ierrors++; 1919 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 1920 continue; 1921 } 1922 if (ti_newbuf_std(sc, sc->ti_std, NULL, dmamap) 1923 == ENOBUFS) { 1924 ifp->if_ierrors++; 1925 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 1926 continue; 1927 } 1928 } 1929 1930 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 1931 ifp->if_ipackets++; 1932 eh = mtod(m, struct ether_header *); 1933 m->m_pkthdr.rcvif = ifp; 1934 1935 #if NBPFILTER > 0 1936 /* 1937 * Handle BPF listeners. Let the BPF user see the packet, but 1938 * don't pass it up to the ether_input() layer unless it's 1939 * a broadcast packet, multicast packet, matches our ethernet 1940 * address or the interface is in promiscuous mode. 1941 */ 1942 if (ifp->if_bpf) { 1943 bpf_mtap(ifp->if_bpf, m); 1944 if (ifp->if_flags & IFF_PROMISC && 1945 (bcmp(eh->ether_dhost, LLADDR(ifp->if_sadl), 1946 ETHER_ADDR_LEN) && 1947 (eh->ether_dhost[0] & 1) == 0)) { 1948 m_freem(m); 1949 continue; 1950 } 1951 } 1952 #endif 1953 1954 #ifdef TI_CSUM_OFFLOAD /* XXX NetBSD: broken because m points to ether pkt */ 1955 ip = mtod(m, struct ip *); 1956 if (!(cur_rx->ti_tcp_udp_cksum ^ 0xFFFF) && 1957 !(ip->ip_off & htons(IP_MF | IP_OFFMASK | IP_RF))) 1958 m->m_flags |= M_HWCKSUM; 1959 #endif 1960 1961 #if NVLAN > 0 /* XXX NetBSD: broken because m points to ether pkt */ 1962 /* 1963 * If we received a packet with a vlan tag, pass it 1964 * to vlan_input() instead of ether_input(). 1965 */ 1966 if (have_tag) { 1967 vlan_input_tag(eh, m, vlan_tag); 1968 have_tag = vlan_tag = 0; 1969 continue; 1970 } 1971 #endif 1972 (*ifp->if_input)(ifp, m); 1973 } 1974 1975 /* Only necessary on the Tigon 1. */ 1976 if (sc->ti_hwrev == TI_HWREV_TIGON) 1977 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 1978 sc->ti_rx_saved_considx); 1979 1980 TI_UPDATE_STDPROD(sc, sc->ti_std); 1981 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 1982 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 1983 1984 return; 1985 } 1986 1987 static void ti_txeof(sc) 1988 struct ti_softc *sc; 1989 { 1990 struct ti_tx_desc *cur_tx = NULL; 1991 struct ifnet *ifp; 1992 1993 ifp = &sc->ethercom.ec_if; 1994 1995 /* 1996 * Go through our tx ring and free mbufs for those 1997 * frames that have been sent. 1998 */ 1999 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2000 u_int32_t idx = 0; 2001 2002 idx = sc->ti_tx_saved_considx; 2003 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2004 if (idx > 383) 2005 CSR_WRITE_4(sc, TI_WINBASE, 2006 TI_TX_RING_BASE + 6144); 2007 else if (idx > 255) 2008 CSR_WRITE_4(sc, TI_WINBASE, 2009 TI_TX_RING_BASE + 4096); 2010 else if (idx > 127) 2011 CSR_WRITE_4(sc, TI_WINBASE, 2012 TI_TX_RING_BASE + 2048); 2013 else 2014 CSR_WRITE_4(sc, TI_WINBASE, 2015 TI_TX_RING_BASE); 2016 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128]; 2017 } else 2018 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2019 if (cur_tx->ti_flags & TI_BDFLAG_END) 2020 ifp->if_opackets++; 2021 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2022 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2023 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2024 2025 /* if (sc->txdma[idx] == 0) panic() */ 2026 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, sc->txdma[idx], 2027 link); 2028 sc->txdma[idx] = 0; 2029 } 2030 sc->ti_txcnt--; 2031 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2032 ifp->if_timer = 0; 2033 } 2034 2035 if (cur_tx != NULL) 2036 ifp->if_flags &= ~IFF_OACTIVE; 2037 2038 return; 2039 } 2040 2041 static int ti_intr(xsc) 2042 void *xsc; 2043 { 2044 struct ti_softc *sc; 2045 struct ifnet *ifp; 2046 2047 sc = xsc; 2048 ifp = &sc->ethercom.ec_if; 2049 2050 #ifdef notdef 2051 /* Avoid this for now -- checking this register is expensive. */ 2052 /* Make sure this is really our interrupt. */ 2053 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 2054 return (0); 2055 #endif 2056 2057 /* Ack interrupt and stop others from occuring. */ 2058 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2059 2060 if (ifp->if_flags & IFF_RUNNING) { 2061 /* Check RX return ring producer/consumer */ 2062 ti_rxeof(sc); 2063 2064 /* Check TX ring producer/consumer */ 2065 ti_txeof(sc); 2066 } 2067 2068 ti_handle_events(sc); 2069 2070 /* Re-enable interrupts. */ 2071 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2072 2073 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 2074 ti_start(ifp); 2075 2076 return (1); 2077 } 2078 2079 static void ti_stats_update(sc) 2080 struct ti_softc *sc; 2081 { 2082 struct ifnet *ifp; 2083 2084 ifp = &sc->ethercom.ec_if; 2085 2086 ifp->if_collisions += 2087 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2088 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2089 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2090 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2091 ifp->if_collisions; 2092 2093 return; 2094 } 2095 2096 /* 2097 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2098 * pointers to descriptors. 2099 */ 2100 static int ti_encap(sc, m_head, txidx) 2101 struct ti_softc *sc; 2102 struct mbuf *m_head; 2103 u_int32_t *txidx; 2104 { 2105 struct ti_tx_desc *f = NULL; 2106 u_int32_t frag, cur, cnt = 0; 2107 struct txdmamap_pool_entry *dma; 2108 bus_dmamap_t dmamap; 2109 int error, i; 2110 #if NVLAN > 0 2111 struct ifvlan *ifv = NULL; 2112 2113 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 2114 m_head->m_pkthdr.rcvif != NULL && 2115 m_head->m_pkthdr.rcvif->if_type == IFT_8021_VLAN) 2116 ifv = m_head->m_pkthdr.rcvif->if_softc; 2117 #endif 2118 2119 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2120 if (dma == NULL) { 2121 return ENOMEM; 2122 } 2123 dmamap = dma->dmamap; 2124 2125 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 0); 2126 if (error) { 2127 struct mbuf *m; 2128 int i = 0; 2129 for (m = m_head; m; m = m->m_next) 2130 i++; 2131 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2132 "error %d\n", m_head->m_pkthdr.len, i, error); 2133 return (ENOMEM); 2134 } 2135 2136 cur = frag = *txidx; 2137 2138 /* 2139 * Start packing the mbufs in this chain into 2140 * the fragment pointers. Stop when we run out 2141 * of fragments or hit the end of the mbuf chain. 2142 */ 2143 for (i = 0; i < dmamap->dm_nsegs; i++) { 2144 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2145 if (frag > 383) 2146 CSR_WRITE_4(sc, TI_WINBASE, 2147 TI_TX_RING_BASE + 6144); 2148 else if (frag > 255) 2149 CSR_WRITE_4(sc, TI_WINBASE, 2150 TI_TX_RING_BASE + 4096); 2151 else if (frag > 127) 2152 CSR_WRITE_4(sc, TI_WINBASE, 2153 TI_TX_RING_BASE + 2048); 2154 else 2155 CSR_WRITE_4(sc, TI_WINBASE, 2156 TI_TX_RING_BASE); 2157 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128]; 2158 } else 2159 f = &sc->ti_rdata->ti_tx_ring[frag]; 2160 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2161 break; 2162 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2163 f->ti_len = dmamap->dm_segs[i].ds_len; 2164 f->ti_flags = 0; 2165 #if NVLAN > 0 2166 if (ifv != NULL) { 2167 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2168 f->ti_vlan_tag = ifv->ifv_tag; 2169 } else { 2170 f->ti_vlan_tag = 0; 2171 } 2172 #endif 2173 /* 2174 * Sanity check: avoid coming within 16 descriptors 2175 * of the end of the ring. 2176 */ 2177 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2178 return(ENOBUFS); 2179 cur = frag; 2180 TI_INC(frag, TI_TX_RING_CNT); 2181 cnt++; 2182 } 2183 2184 if (i < dmamap->dm_nsegs) 2185 return(ENOBUFS); 2186 2187 if (frag == sc->ti_tx_saved_considx) 2188 return(ENOBUFS); 2189 2190 if (sc->ti_hwrev == TI_HWREV_TIGON) 2191 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |= 2192 TI_BDFLAG_END; 2193 else 2194 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2195 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2196 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, dma, link); 2197 sc->txdma[cur] = dma; 2198 sc->ti_txcnt += cnt; 2199 2200 *txidx = frag; 2201 2202 return(0); 2203 } 2204 2205 /* 2206 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2207 * to the mbuf data regions directly in the transmit descriptors. 2208 */ 2209 static void ti_start(ifp) 2210 struct ifnet *ifp; 2211 { 2212 struct ti_softc *sc; 2213 struct mbuf *m_head = NULL; 2214 u_int32_t prodidx = 0; 2215 2216 sc = ifp->if_softc; 2217 2218 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2219 2220 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2221 IF_DEQUEUE(&ifp->if_snd, m_head); 2222 if (m_head == NULL) 2223 break; 2224 2225 /* 2226 * Pack the data into the transmit ring. If we 2227 * don't have room, set the OACTIVE flag and wait 2228 * for the NIC to drain the ring. 2229 */ 2230 if (ti_encap(sc, m_head, &prodidx)) { 2231 IF_PREPEND(&ifp->if_snd, m_head); 2232 ifp->if_flags |= IFF_OACTIVE; 2233 break; 2234 } 2235 2236 /* 2237 * If there's a BPF listener, bounce a copy of this frame 2238 * to him. 2239 */ 2240 #if NBPFILTER > 0 2241 if (ifp->if_bpf) 2242 bpf_mtap(ifp->if_bpf, m_head); 2243 #endif 2244 } 2245 2246 /* Transmit */ 2247 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2248 2249 /* 2250 * Set a timeout in case the chip goes out to lunch. 2251 */ 2252 ifp->if_timer = 5; 2253 2254 return; 2255 } 2256 2257 static void ti_init(xsc) 2258 void *xsc; 2259 { 2260 struct ti_softc *sc = xsc; 2261 int s; 2262 2263 s = splimp(); 2264 2265 /* Cancel pending I/O and flush buffers. */ 2266 ti_stop(sc); 2267 2268 /* Init the gen info block, ring control blocks and firmware. */ 2269 if (ti_gibinit(sc)) { 2270 printf("%s: initialization failure\n", sc->sc_dev.dv_xname); 2271 splx(s); 2272 return; 2273 } 2274 2275 splx(s); 2276 2277 return; 2278 } 2279 2280 static void ti_init2(sc) 2281 struct ti_softc *sc; 2282 { 2283 struct ti_cmd_desc cmd; 2284 struct ifnet *ifp; 2285 u_int8_t *m; 2286 struct ifmedia *ifm; 2287 int tmp; 2288 2289 ifp = &sc->ethercom.ec_if; 2290 2291 /* Specify MTU and interface index. */ 2292 CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->sc_dev.dv_unit); /* ??? */ 2293 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu + 2294 ETHER_HDR_LEN + ETHER_CRC_LEN); 2295 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2296 2297 /* Load our MAC address. */ 2298 m = (u_int8_t *)LLADDR(ifp->if_sadl); 2299 CSR_WRITE_4(sc, TI_GCR_PAR0, (m[0] << 8) | m[1]); 2300 CSR_WRITE_4(sc, TI_GCR_PAR1, (m[2] << 24) | (m[3] << 16) 2301 | (m[4] << 8) | m[5]); 2302 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2303 2304 /* Enable or disable promiscuous mode as needed. */ 2305 if (ifp->if_flags & IFF_PROMISC) { 2306 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2307 } else { 2308 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2309 } 2310 2311 /* Program multicast filter. */ 2312 ti_setmulti(sc); 2313 2314 /* 2315 * If this is a Tigon 1, we should tell the 2316 * firmware to use software packet filtering. 2317 */ 2318 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2319 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2320 } 2321 2322 /* Init RX ring. */ 2323 ti_init_rx_ring_std(sc); 2324 2325 /* Init jumbo RX ring. */ 2326 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2327 ti_init_rx_ring_jumbo(sc); 2328 2329 /* 2330 * If this is a Tigon 2, we can also configure the 2331 * mini ring. 2332 */ 2333 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2334 ti_init_rx_ring_mini(sc); 2335 2336 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2337 sc->ti_rx_saved_considx = 0; 2338 2339 /* Init TX ring. */ 2340 ti_init_tx_ring(sc); 2341 2342 /* Tell firmware we're alive. */ 2343 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2344 2345 /* Enable host interrupts. */ 2346 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2347 2348 ifp->if_flags |= IFF_RUNNING; 2349 ifp->if_flags &= ~IFF_OACTIVE; 2350 2351 /* 2352 * Make sure to set media properly. We have to do this 2353 * here since we have to issue commands in order to set 2354 * the link negotiation and we can't issue commands until 2355 * the firmware is running. 2356 */ 2357 ifm = &sc->ifmedia; 2358 tmp = ifm->ifm_media; 2359 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2360 ti_ifmedia_upd(ifp); 2361 ifm->ifm_media = tmp; 2362 2363 return; 2364 } 2365 2366 /* 2367 * Set media options. 2368 */ 2369 static int ti_ifmedia_upd(ifp) 2370 struct ifnet *ifp; 2371 { 2372 struct ti_softc *sc; 2373 struct ifmedia *ifm; 2374 struct ti_cmd_desc cmd; 2375 2376 sc = ifp->if_softc; 2377 ifm = &sc->ifmedia; 2378 2379 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2380 return(EINVAL); 2381 2382 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2383 case IFM_AUTO: 2384 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2385 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 2386 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2387 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2388 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 2389 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2390 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2391 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2392 break; 2393 case IFM_1000_SX: 2394 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2395 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2396 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2397 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2398 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2399 break; 2400 case IFM_100_FX: 2401 case IFM_10_FL: 2402 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2403 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 2404 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX) { 2405 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2406 } else { 2407 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2408 } 2409 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2410 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2411 } else { 2412 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2413 } 2414 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2415 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2416 break; 2417 } 2418 2419 sc->ethercom.ec_if.if_baudrate = 2420 ifmedia_baudrate(ifm->ifm_media); 2421 2422 return(0); 2423 } 2424 2425 /* 2426 * Report current media status. 2427 */ 2428 static void ti_ifmedia_sts(ifp, ifmr) 2429 struct ifnet *ifp; 2430 struct ifmediareq *ifmr; 2431 { 2432 struct ti_softc *sc; 2433 2434 sc = ifp->if_softc; 2435 2436 ifmr->ifm_status = IFM_AVALID; 2437 ifmr->ifm_active = IFM_ETHER; 2438 2439 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2440 return; 2441 2442 ifmr->ifm_status |= IFM_ACTIVE; 2443 2444 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) 2445 ifmr->ifm_active |= IFM_1000_SX|IFM_FDX; 2446 else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2447 u_int32_t media; 2448 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2449 if (media & TI_LNK_100MB) 2450 ifmr->ifm_active |= IFM_100_FX; 2451 if (media & TI_LNK_10MB) 2452 ifmr->ifm_active |= IFM_10_FL; 2453 if (media & TI_LNK_FULL_DUPLEX) 2454 ifmr->ifm_active |= IFM_FDX; 2455 if (media & TI_LNK_HALF_DUPLEX) 2456 ifmr->ifm_active |= IFM_HDX; 2457 } 2458 2459 sc->ethercom.ec_if.if_baudrate = 2460 ifmedia_baudrate(sc->ifmedia.ifm_media); 2461 2462 return; 2463 } 2464 2465 static int 2466 ti_ether_ioctl(ifp, cmd, data) 2467 struct ifnet *ifp; 2468 u_long cmd; 2469 caddr_t data; 2470 { 2471 struct ifaddr *ifa = (struct ifaddr *) data; 2472 struct ti_softc *sc = ifp->if_softc; 2473 2474 switch (cmd) { 2475 case SIOCSIFADDR: 2476 ifp->if_flags |= IFF_UP; 2477 2478 switch (ifa->ifa_addr->sa_family) { 2479 #ifdef INET 2480 case AF_INET: 2481 ti_init(sc); 2482 arp_ifinit(ifp, ifa); 2483 break; 2484 #endif 2485 #ifdef NS 2486 case AF_NS: 2487 { 2488 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 2489 2490 if (ns_nullhost(*ina)) 2491 ina->x_host = *(union ns_host *) 2492 LLADDR(ifp->if_sadl); 2493 else 2494 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 2495 ifp->if_addrlen); 2496 /* Set new address. */ 2497 ti_init(sc); 2498 break; 2499 } 2500 #endif 2501 default: 2502 ti_init(sc); 2503 break; 2504 } 2505 break; 2506 2507 default: 2508 return (EINVAL); 2509 } 2510 2511 return (0); 2512 } 2513 2514 static int ti_ioctl(ifp, command, data) 2515 struct ifnet *ifp; 2516 u_long command; 2517 caddr_t data; 2518 { 2519 struct ti_softc *sc = ifp->if_softc; 2520 struct ifreq *ifr = (struct ifreq *) data; 2521 int s, error = 0; 2522 struct ti_cmd_desc cmd; 2523 2524 s = splimp(); 2525 2526 switch(command) { 2527 case SIOCSIFADDR: 2528 case SIOCGIFADDR: 2529 error = ti_ether_ioctl(ifp, command, data); 2530 break; 2531 case SIOCSIFMTU: 2532 if (ifr->ifr_mtu > TI_JUMBO_MTU) 2533 error = EINVAL; 2534 else { 2535 ifp->if_mtu = ifr->ifr_mtu; 2536 ti_init(sc); 2537 } 2538 break; 2539 case SIOCSIFFLAGS: 2540 if (ifp->if_flags & IFF_UP) { 2541 /* 2542 * If only the state of the PROMISC flag changed, 2543 * then just use the 'set promisc mode' command 2544 * instead of reinitializing the entire NIC. Doing 2545 * a full re-init means reloading the firmware and 2546 * waiting for it to start up, which may take a 2547 * second or two. 2548 */ 2549 if (ifp->if_flags & IFF_RUNNING && 2550 ifp->if_flags & IFF_PROMISC && 2551 !(sc->ti_if_flags & IFF_PROMISC)) { 2552 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2553 TI_CMD_CODE_PROMISC_ENB, 0); 2554 } else if (ifp->if_flags & IFF_RUNNING && 2555 !(ifp->if_flags & IFF_PROMISC) && 2556 sc->ti_if_flags & IFF_PROMISC) { 2557 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2558 TI_CMD_CODE_PROMISC_DIS, 0); 2559 } else 2560 ti_init(sc); 2561 } else { 2562 if (ifp->if_flags & IFF_RUNNING) { 2563 ti_stop(sc); 2564 } 2565 } 2566 sc->ti_if_flags = ifp->if_flags; 2567 error = 0; 2568 break; 2569 case SIOCADDMULTI: 2570 case SIOCDELMULTI: 2571 if (ifp->if_flags & IFF_RUNNING) { 2572 ti_setmulti(sc); 2573 error = 0; 2574 } 2575 break; 2576 case SIOCSIFMEDIA: 2577 case SIOCGIFMEDIA: 2578 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2579 break; 2580 default: 2581 error = EINVAL; 2582 break; 2583 } 2584 2585 (void)splx(s); 2586 2587 return(error); 2588 } 2589 2590 static void ti_watchdog(ifp) 2591 struct ifnet *ifp; 2592 { 2593 struct ti_softc *sc; 2594 2595 sc = ifp->if_softc; 2596 2597 printf("%s: watchdog timeout -- resetting\n", sc->sc_dev.dv_xname); 2598 ti_stop(sc); 2599 ti_init(sc); 2600 2601 ifp->if_oerrors++; 2602 2603 return; 2604 } 2605 2606 /* 2607 * Stop the adapter and free any mbufs allocated to the 2608 * RX and TX lists. 2609 */ 2610 static void ti_stop(sc) 2611 struct ti_softc *sc; 2612 { 2613 struct ifnet *ifp; 2614 struct ti_cmd_desc cmd; 2615 2616 ifp = &sc->ethercom.ec_if; 2617 2618 /* Disable host interrupts. */ 2619 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2620 /* 2621 * Tell firmware we're shutting down. 2622 */ 2623 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2624 2625 /* Halt and reinitialize. */ 2626 ti_chipinit(sc); 2627 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2628 ti_chipinit(sc); 2629 2630 /* Free the RX lists. */ 2631 ti_free_rx_ring_std(sc); 2632 2633 /* Free jumbo RX list. */ 2634 ti_free_rx_ring_jumbo(sc); 2635 2636 /* Free mini RX list. */ 2637 ti_free_rx_ring_mini(sc); 2638 2639 /* Free TX buffers. */ 2640 ti_free_tx_ring(sc); 2641 2642 sc->ti_ev_prodidx.ti_idx = 0; 2643 sc->ti_return_prodidx.ti_idx = 0; 2644 sc->ti_tx_considx.ti_idx = 0; 2645 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2646 2647 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2648 2649 return; 2650 } 2651 2652 /* 2653 * Stop all chip I/O so that the kernel's probe routines don't 2654 * get confused by errant DMAs when rebooting. 2655 */ 2656 static void ti_shutdown(v) 2657 void *v; 2658 { 2659 struct ti_softc *sc = v; 2660 2661 ti_chipinit(sc); 2662 2663 return; 2664 } 2665