1 /* $NetBSD: if_ti.c,v 1.43 2001/11/13 07:48:45 lukem Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_ti.c,v 1.15 1999/08/14 15:45:03 wpaul Exp 35 */ 36 37 /* 38 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD. 39 * Manuals, sample driver and firmware source kits are available 40 * from http://www.alteon.com/support/openkits. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The Alteon Networks Tigon chip contains an embedded R4000 CPU, 49 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs 50 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The 51 * Tigon supports hardware IP, TCP and UCP checksumming, multicast 52 * filtering and jumbo (9014 byte) frames. The hardware is largely 53 * controlled by firmware, which must be loaded into the NIC during 54 * initialization. 55 * 56 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware 57 * revision, which supports new features such as extended commands, 58 * extended jumbo receive ring desciptors and a mini receive ring. 59 * 60 * Alteon Networks is to be commended for releasing such a vast amount 61 * of development material for the Tigon NIC without requiring an NDA 62 * (although they really should have done it a long time ago). With 63 * any luck, the other vendors will finally wise up and follow Alteon's 64 * stellar example. 65 * 66 * The firmware for the Tigon 1 and 2 NICs is compiled directly into 67 * this driver by #including it as a C header file. This bloats the 68 * driver somewhat, but it's the easiest method considering that the 69 * driver code and firmware code need to be kept in sync. The source 70 * for the firmware is not provided with the FreeBSD distribution since 71 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3. 72 * 73 * The following people deserve special thanks: 74 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board 75 * for testing 76 * - Raymond Lee of Netgear, for providing a pair of Netgear 77 * GA620 Tigon 2 boards for testing 78 * - Ulf Zimmermann, for bringing the GA620 to my attention and 79 * convincing me to write this driver. 80 * - Andrew Gallatin for providing FreeBSD/Alpha support. 81 */ 82 83 #include <sys/cdefs.h> 84 __KERNEL_RCSID(0, "$NetBSD: if_ti.c,v 1.43 2001/11/13 07:48:45 lukem Exp $"); 85 86 #include "bpfilter.h" 87 #include "opt_inet.h" 88 #include "opt_ns.h" 89 90 #include <sys/param.h> 91 #include <sys/systm.h> 92 #include <sys/sockio.h> 93 #include <sys/mbuf.h> 94 #include <sys/malloc.h> 95 #include <sys/kernel.h> 96 #include <sys/socket.h> 97 #include <sys/queue.h> 98 #include <sys/device.h> 99 #include <sys/reboot.h> 100 101 #include <uvm/uvm_extern.h> 102 103 #include <net/if.h> 104 #include <net/if_arp.h> 105 #include <net/if_ether.h> 106 #include <net/if_dl.h> 107 #include <net/if_media.h> 108 109 #if NBPFILTER > 0 110 #include <net/bpf.h> 111 #endif 112 113 #ifdef INET 114 #include <netinet/in.h> 115 #include <netinet/if_inarp.h> 116 #include <netinet/in_systm.h> 117 #include <netinet/ip.h> 118 #endif 119 120 #ifdef NS 121 #include <netns/ns.h> 122 #include <netns/ns_if.h> 123 #endif 124 125 #include <machine/bus.h> 126 127 #include <dev/pci/pcireg.h> 128 #include <dev/pci/pcivar.h> 129 #include <dev/pci/pcidevs.h> 130 131 #include <dev/pci/if_tireg.h> 132 133 #include <dev/microcode/tigon/ti_fw.h> 134 #include <dev/microcode/tigon/ti_fw2.h> 135 136 /* 137 * Various supported device vendors/types and their names. 138 */ 139 140 static const struct ti_type ti_devs[] = { 141 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC, 142 "Alteon AceNIC 1000BASE-SX Ethernet" }, 143 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC_COPPER, 144 "Alteon AceNIC 1000BASE-T Ethernet" }, 145 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C985, 146 "3Com 3c985-SX Gigabit Ethernet" }, 147 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620, 148 "Netgear GA620 1000BASE-SX Ethernet" }, 149 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620T, 150 "Netgear GA620 1000BASE-T Ethernet" }, 151 { PCI_VENDOR_SGI, PCI_PRODUCT_SGI_TIGON, 152 "Silicon Graphics Gigabit Ethernet" }, 153 { 0, 0, NULL } 154 }; 155 156 static const struct ti_type *ti_type_match __P((struct pci_attach_args *)); 157 static int ti_probe __P((struct device *, struct cfdata *, void *)); 158 static void ti_attach __P((struct device *, struct device *, void *)); 159 static void ti_shutdown __P((void *)); 160 static void ti_txeof_tigon1 __P((struct ti_softc *)); 161 static void ti_txeof_tigon2 __P((struct ti_softc *)); 162 static void ti_rxeof __P((struct ti_softc *)); 163 164 static void ti_stats_update __P((struct ti_softc *)); 165 static int ti_encap_tigon1 __P((struct ti_softc *, struct mbuf *, 166 u_int32_t *)); 167 static int ti_encap_tigon2 __P((struct ti_softc *, struct mbuf *, 168 u_int32_t *)); 169 170 static int ti_intr __P((void *)); 171 static void ti_start __P((struct ifnet *)); 172 static int ti_ioctl __P((struct ifnet *, u_long, caddr_t)); 173 static void ti_init __P((void *)); 174 static void ti_init2 __P((struct ti_softc *)); 175 static void ti_stop __P((struct ti_softc *)); 176 static void ti_watchdog __P((struct ifnet *)); 177 static int ti_ifmedia_upd __P((struct ifnet *)); 178 static void ti_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 179 180 static u_int32_t ti_eeprom_putbyte __P((struct ti_softc *, int)); 181 static u_int8_t ti_eeprom_getbyte __P((struct ti_softc *, 182 int, u_int8_t *)); 183 static int ti_read_eeprom __P((struct ti_softc *, caddr_t, int, int)); 184 185 static void ti_add_mcast __P((struct ti_softc *, struct ether_addr *)); 186 static void ti_del_mcast __P((struct ti_softc *, struct ether_addr *)); 187 static void ti_setmulti __P((struct ti_softc *)); 188 189 static void ti_mem __P((struct ti_softc *, u_int32_t, 190 u_int32_t, caddr_t)); 191 static void ti_loadfw __P((struct ti_softc *)); 192 static void ti_cmd __P((struct ti_softc *, struct ti_cmd_desc *)); 193 static void ti_cmd_ext __P((struct ti_softc *, struct ti_cmd_desc *, 194 caddr_t, int)); 195 static void ti_handle_events __P((struct ti_softc *)); 196 static int ti_alloc_jumbo_mem __P((struct ti_softc *)); 197 static void *ti_jalloc __P((struct ti_softc *)); 198 static void ti_jfree __P((caddr_t, u_int, void *)); 199 static int ti_newbuf_std __P((struct ti_softc *, int, struct mbuf *, bus_dmamap_t)); 200 static int ti_newbuf_mini __P((struct ti_softc *, int, struct mbuf *, bus_dmamap_t)); 201 static int ti_newbuf_jumbo __P((struct ti_softc *, int, struct mbuf *)); 202 static int ti_init_rx_ring_std __P((struct ti_softc *)); 203 static void ti_free_rx_ring_std __P((struct ti_softc *)); 204 static int ti_init_rx_ring_jumbo __P((struct ti_softc *)); 205 static void ti_free_rx_ring_jumbo __P((struct ti_softc *)); 206 static int ti_init_rx_ring_mini __P((struct ti_softc *)); 207 static void ti_free_rx_ring_mini __P((struct ti_softc *)); 208 static void ti_free_tx_ring __P((struct ti_softc *)); 209 static int ti_init_tx_ring __P((struct ti_softc *)); 210 211 static int ti_64bitslot_war __P((struct ti_softc *)); 212 static int ti_chipinit __P((struct ti_softc *)); 213 static int ti_gibinit __P((struct ti_softc *)); 214 215 static int ti_ether_ioctl __P((struct ifnet *, u_long, caddr_t)); 216 217 struct cfattach ti_ca = { 218 sizeof(struct ti_softc), ti_probe, ti_attach 219 }; 220 221 /* 222 * Send an instruction or address to the EEPROM, check for ACK. 223 */ 224 static u_int32_t ti_eeprom_putbyte(sc, byte) 225 struct ti_softc *sc; 226 int byte; 227 { 228 int i, ack = 0; 229 230 /* 231 * Make sure we're in TX mode. 232 */ 233 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 234 235 /* 236 * Feed in each bit and stobe the clock. 237 */ 238 for (i = 0x80; i; i >>= 1) { 239 if (byte & i) { 240 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 241 } else { 242 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT); 243 } 244 DELAY(1); 245 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 246 DELAY(1); 247 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 248 } 249 250 /* 251 * Turn off TX mode. 252 */ 253 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 254 255 /* 256 * Check for ack. 257 */ 258 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 259 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; 260 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 261 262 return(ack); 263 } 264 265 /* 266 * Read a byte of data stored in the EEPROM at address 'addr.' 267 * We have to send two address bytes since the EEPROM can hold 268 * more than 256 bytes of data. 269 */ 270 static u_int8_t ti_eeprom_getbyte(sc, addr, dest) 271 struct ti_softc *sc; 272 int addr; 273 u_int8_t *dest; 274 { 275 int i; 276 u_int8_t byte = 0; 277 278 EEPROM_START; 279 280 /* 281 * Send write control code to EEPROM. 282 */ 283 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 284 printf("%s: failed to send write command, status: %x\n", 285 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 286 return(1); 287 } 288 289 /* 290 * Send first byte of address of byte we want to read. 291 */ 292 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) { 293 printf("%s: failed to send address, status: %x\n", 294 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 295 return(1); 296 } 297 /* 298 * Send second byte address of byte we want to read. 299 */ 300 if (ti_eeprom_putbyte(sc, addr & 0xFF)) { 301 printf("%s: failed to send address, status: %x\n", 302 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 303 return(1); 304 } 305 306 EEPROM_STOP; 307 EEPROM_START; 308 /* 309 * Send read control code to EEPROM. 310 */ 311 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 312 printf("%s: failed to send read command, status: %x\n", 313 sc->sc_dev.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); 314 return(1); 315 } 316 317 /* 318 * Start reading bits from EEPROM. 319 */ 320 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN); 321 for (i = 0x80; i; i >>= 1) { 322 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 323 DELAY(1); 324 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) 325 byte |= i; 326 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK); 327 DELAY(1); 328 } 329 330 EEPROM_STOP; 331 332 /* 333 * No ACK generated for read, so just return byte. 334 */ 335 336 *dest = byte; 337 338 return(0); 339 } 340 341 /* 342 * Read a sequence of bytes from the EEPROM. 343 */ 344 static int ti_read_eeprom(sc, dest, off, cnt) 345 struct ti_softc *sc; 346 caddr_t dest; 347 int off; 348 int cnt; 349 { 350 int err = 0, i; 351 u_int8_t byte = 0; 352 353 for (i = 0; i < cnt; i++) { 354 err = ti_eeprom_getbyte(sc, off + i, &byte); 355 if (err) 356 break; 357 *(dest + i) = byte; 358 } 359 360 return(err ? 1 : 0); 361 } 362 363 /* 364 * NIC memory access function. Can be used to either clear a section 365 * of NIC local memory or (if buf is non-NULL) copy data into it. 366 */ 367 static void ti_mem(sc, addr, len, buf) 368 struct ti_softc *sc; 369 u_int32_t addr, len; 370 caddr_t buf; 371 { 372 int segptr, segsize, cnt; 373 caddr_t ptr; 374 375 segptr = addr; 376 cnt = len; 377 ptr = buf; 378 379 while(cnt) { 380 if (cnt < TI_WINLEN) 381 segsize = cnt; 382 else 383 segsize = TI_WINLEN - (segptr % TI_WINLEN); 384 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1))); 385 if (buf == NULL) { 386 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle, 387 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0, 388 segsize / 4); 389 } else { 390 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle, 391 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 392 (u_int32_t *)ptr, segsize / 4); 393 ptr += segsize; 394 } 395 segptr += segsize; 396 cnt -= segsize; 397 } 398 399 return; 400 } 401 402 /* 403 * Load firmware image into the NIC. Check that the firmware revision 404 * is acceptable and see if we want the firmware for the Tigon 1 or 405 * Tigon 2. 406 */ 407 static void ti_loadfw(sc) 408 struct ti_softc *sc; 409 { 410 switch(sc->ti_hwrev) { 411 case TI_HWREV_TIGON: 412 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR || 413 tigonFwReleaseMinor != TI_FIRMWARE_MINOR || 414 tigonFwReleaseFix != TI_FIRMWARE_FIX) { 415 printf("%s: firmware revision mismatch; want " 416 "%d.%d.%d, got %d.%d.%d\n", sc->sc_dev.dv_xname, 417 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 418 TI_FIRMWARE_FIX, tigonFwReleaseMajor, 419 tigonFwReleaseMinor, tigonFwReleaseFix); 420 return; 421 } 422 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, 423 (caddr_t)tigonFwText); 424 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, 425 (caddr_t)tigonFwData); 426 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, 427 (caddr_t)tigonFwRodata); 428 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL); 429 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL); 430 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr); 431 break; 432 case TI_HWREV_TIGON_II: 433 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR || 434 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR || 435 tigon2FwReleaseFix != TI_FIRMWARE_FIX) { 436 printf("%s: firmware revision mismatch; want " 437 "%d.%d.%d, got %d.%d.%d\n", sc->sc_dev.dv_xname, 438 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR, 439 TI_FIRMWARE_FIX, tigon2FwReleaseMajor, 440 tigon2FwReleaseMinor, tigon2FwReleaseFix); 441 return; 442 } 443 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, 444 (caddr_t)tigon2FwText); 445 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, 446 (caddr_t)tigon2FwData); 447 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen, 448 (caddr_t)tigon2FwRodata); 449 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL); 450 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL); 451 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr); 452 break; 453 default: 454 printf("%s: can't load firmware: unknown hardware rev\n", 455 sc->sc_dev.dv_xname); 456 break; 457 } 458 459 return; 460 } 461 462 /* 463 * Send the NIC a command via the command ring. 464 */ 465 static void ti_cmd(sc, cmd) 466 struct ti_softc *sc; 467 struct ti_cmd_desc *cmd; 468 { 469 u_int32_t index; 470 471 index = sc->ti_cmd_saved_prodidx; 472 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 473 TI_INC(index, TI_CMD_RING_CNT); 474 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 475 sc->ti_cmd_saved_prodidx = index; 476 477 return; 478 } 479 480 /* 481 * Send the NIC an extended command. The 'len' parameter specifies the 482 * number of command slots to include after the initial command. 483 */ 484 static void ti_cmd_ext(sc, cmd, arg, len) 485 struct ti_softc *sc; 486 struct ti_cmd_desc *cmd; 487 caddr_t arg; 488 int len; 489 { 490 u_int32_t index; 491 int i; 492 493 index = sc->ti_cmd_saved_prodidx; 494 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd)); 495 TI_INC(index, TI_CMD_RING_CNT); 496 for (i = 0; i < len; i++) { 497 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), 498 *(u_int32_t *)(&arg[i * 4])); 499 TI_INC(index, TI_CMD_RING_CNT); 500 } 501 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index); 502 sc->ti_cmd_saved_prodidx = index; 503 504 return; 505 } 506 507 /* 508 * Handle events that have triggered interrupts. 509 */ 510 static void ti_handle_events(sc) 511 struct ti_softc *sc; 512 { 513 struct ti_event_desc *e; 514 515 if (sc->ti_rdata->ti_event_ring == NULL) 516 return; 517 518 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) { 519 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx]; 520 switch(e->ti_event) { 521 case TI_EV_LINKSTAT_CHANGED: 522 sc->ti_linkstat = e->ti_code; 523 if (e->ti_code == TI_EV_CODE_LINK_UP) 524 printf("%s: 10/100 link up\n", 525 sc->sc_dev.dv_xname); 526 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP) 527 printf("%s: gigabit link up\n", 528 sc->sc_dev.dv_xname); 529 else if (e->ti_code == TI_EV_CODE_LINK_DOWN) 530 printf("%s: link down\n", 531 sc->sc_dev.dv_xname); 532 break; 533 case TI_EV_ERROR: 534 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD) 535 printf("%s: invalid command\n", 536 sc->sc_dev.dv_xname); 537 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD) 538 printf("%s: unknown command\n", 539 sc->sc_dev.dv_xname); 540 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG) 541 printf("%s: bad config data\n", 542 sc->sc_dev.dv_xname); 543 break; 544 case TI_EV_FIRMWARE_UP: 545 ti_init2(sc); 546 break; 547 case TI_EV_STATS_UPDATED: 548 ti_stats_update(sc); 549 break; 550 case TI_EV_RESET_JUMBO_RING: 551 case TI_EV_MCAST_UPDATED: 552 /* Who cares. */ 553 break; 554 default: 555 printf("%s: unknown event: %d\n", 556 sc->sc_dev.dv_xname, e->ti_event); 557 break; 558 } 559 /* Advance the consumer index. */ 560 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT); 561 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx); 562 } 563 564 return; 565 } 566 567 /* 568 * Memory management for the jumbo receive ring is a pain in the 569 * butt. We need to allocate at least 9018 bytes of space per frame, 570 * _and_ it has to be contiguous (unless you use the extended 571 * jumbo descriptor format). Using malloc() all the time won't 572 * work: malloc() allocates memory in powers of two, which means we 573 * would end up wasting a considerable amount of space by allocating 574 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have 575 * to do our own memory management. 576 * 577 * The driver needs to allocate a contiguous chunk of memory at boot 578 * time. We then chop this up ourselves into 9K pieces and use them 579 * as external mbuf storage. 580 * 581 * One issue here is how much memory to allocate. The jumbo ring has 582 * 256 slots in it, but at 9K per slot than can consume over 2MB of 583 * RAM. This is a bit much, especially considering we also need 584 * RAM for the standard ring and mini ring (on the Tigon 2). To 585 * save space, we only actually allocate enough memory for 64 slots 586 * by default, which works out to between 500 and 600K. This can 587 * be tuned by changing a #define in if_tireg.h. 588 */ 589 590 static int ti_alloc_jumbo_mem(sc) 591 struct ti_softc *sc; 592 { 593 caddr_t ptr; 594 int i; 595 struct ti_jpool_entry *entry; 596 bus_dma_segment_t dmaseg; 597 int error, dmanseg; 598 599 /* Grab a big chunk o' storage. */ 600 if ((error = bus_dmamem_alloc(sc->sc_dmat, 601 TI_JMEM, PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 602 BUS_DMA_NOWAIT)) != 0) { 603 printf("%s: can't allocate jumbo buffer, error = %d\n", 604 sc->sc_dev.dv_xname, error); 605 return (error); 606 } 607 608 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 609 TI_JMEM, (caddr_t *)&sc->ti_cdata.ti_jumbo_buf, 610 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 611 printf("%s: can't map jumbo buffer, error = %d\n", 612 sc->sc_dev.dv_xname, error); 613 return (error); 614 } 615 616 if ((error = bus_dmamap_create(sc->sc_dmat, 617 TI_JMEM, 1, 618 TI_JMEM, 0, BUS_DMA_NOWAIT, 619 &sc->jumbo_dmamap)) != 0) { 620 printf("%s: can't create jumbo buffer DMA map, error = %d\n", 621 sc->sc_dev.dv_xname, error); 622 return (error); 623 } 624 625 if ((error = bus_dmamap_load(sc->sc_dmat, sc->jumbo_dmamap, 626 sc->ti_cdata.ti_jumbo_buf, TI_JMEM, NULL, 627 BUS_DMA_NOWAIT)) != 0) { 628 printf("%s: can't load jumbo buffer DMA map, error = %d\n", 629 sc->sc_dev.dv_xname, error); 630 return (error); 631 } 632 sc->jumbo_dmaaddr = sc->jumbo_dmamap->dm_segs[0].ds_addr; 633 634 SIMPLEQ_INIT(&sc->ti_jfree_listhead); 635 SIMPLEQ_INIT(&sc->ti_jinuse_listhead); 636 637 /* 638 * Now divide it up into 9K pieces and save the addresses 639 * in an array. 640 */ 641 ptr = sc->ti_cdata.ti_jumbo_buf; 642 for (i = 0; i < TI_JSLOTS; i++) { 643 sc->ti_cdata.ti_jslots[i] = ptr; 644 ptr += TI_JLEN; 645 entry = malloc(sizeof(struct ti_jpool_entry), 646 M_DEVBUF, M_NOWAIT); 647 if (entry == NULL) { 648 free(sc->ti_cdata.ti_jumbo_buf, M_DEVBUF); 649 sc->ti_cdata.ti_jumbo_buf = NULL; 650 printf("%s: no memory for jumbo " 651 "buffer queue!\n", sc->sc_dev.dv_xname); 652 return(ENOBUFS); 653 } 654 entry->slot = i; 655 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, 656 jpool_entries); 657 } 658 659 return(0); 660 } 661 662 /* 663 * Allocate a jumbo buffer. 664 */ 665 static void *ti_jalloc(sc) 666 struct ti_softc *sc; 667 { 668 struct ti_jpool_entry *entry; 669 670 entry = SIMPLEQ_FIRST(&sc->ti_jfree_listhead); 671 672 if (entry == NULL) { 673 printf("%s: no free jumbo buffers\n", sc->sc_dev.dv_xname); 674 return(NULL); 675 } 676 677 SIMPLEQ_REMOVE_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries); 678 SIMPLEQ_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries); 679 return(sc->ti_cdata.ti_jslots[entry->slot]); 680 } 681 682 /* 683 * Release a jumbo buffer. 684 */ 685 static void ti_jfree(buf, size, arg) 686 caddr_t buf; 687 u_int size; 688 void *arg; 689 { 690 struct ti_softc *sc; 691 int i; 692 struct ti_jpool_entry *entry; 693 694 /* Extract the softc struct pointer. */ 695 sc = (struct ti_softc *)arg; 696 697 if (sc == NULL) 698 panic("ti_jfree: didn't get softc pointer!"); 699 700 /* calculate the slot this buffer belongs to */ 701 702 i = ((caddr_t)buf 703 - (caddr_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN; 704 705 if ((i < 0) || (i >= TI_JSLOTS)) 706 panic("ti_jfree: asked to free buffer that we don't manage!"); 707 entry = SIMPLEQ_FIRST(&sc->ti_jinuse_listhead); 708 if (entry == NULL) 709 panic("ti_jfree: buffer not in use!"); 710 entry->slot = i; 711 SIMPLEQ_REMOVE_HEAD(&sc->ti_jinuse_listhead, 712 entry, jpool_entries); 713 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, 714 entry, jpool_entries); 715 716 return; 717 } 718 719 720 /* 721 * Intialize a standard receive ring descriptor. 722 */ 723 static int ti_newbuf_std(sc, i, m, dmamap) 724 struct ti_softc *sc; 725 int i; 726 struct mbuf *m; 727 bus_dmamap_t dmamap; /* required if (m != NULL) */ 728 { 729 struct mbuf *m_new = NULL; 730 struct ti_rx_desc *r; 731 int error; 732 733 if (dmamap == NULL) { 734 /* if (m) panic() */ 735 736 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 737 MCLBYTES, 0, BUS_DMA_NOWAIT, 738 &dmamap)) != 0) { 739 printf("%s: can't create recv map, error = %d\n", 740 sc->sc_dev.dv_xname, error); 741 return(ENOMEM); 742 } 743 } 744 sc->std_dmamap[i] = dmamap; 745 746 if (m == NULL) { 747 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 748 if (m_new == NULL) { 749 printf("%s: mbuf allocation failed " 750 "-- packet dropped!\n", sc->sc_dev.dv_xname); 751 return(ENOBUFS); 752 } 753 754 MCLGET(m_new, M_DONTWAIT); 755 if (!(m_new->m_flags & M_EXT)) { 756 printf("%s: cluster allocation failed " 757 "-- packet dropped!\n", sc->sc_dev.dv_xname); 758 m_freem(m_new); 759 return(ENOBUFS); 760 } 761 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 762 m_adj(m_new, ETHER_ALIGN); 763 764 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 765 mtod(m_new, caddr_t), m_new->m_len, NULL, 766 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 767 printf("%s: can't load recv map, error = %d\n", 768 sc->sc_dev.dv_xname, error); 769 return (ENOMEM); 770 } 771 } else { 772 m_new = m; 773 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 774 m_new->m_data = m_new->m_ext.ext_buf; 775 m_adj(m_new, ETHER_ALIGN); 776 777 /* reuse the dmamap */ 778 } 779 780 sc->ti_cdata.ti_rx_std_chain[i] = m_new; 781 r = &sc->ti_rdata->ti_rx_std_ring[i]; 782 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 783 r->ti_type = TI_BDTYPE_RECV_BD; 784 r->ti_flags = 0; 785 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4) 786 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 787 if (sc->ethercom.ec_if.if_capenable & 788 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 789 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 790 r->ti_len = m_new->m_len; /* == ds_len */ 791 r->ti_idx = i; 792 793 return(0); 794 } 795 796 /* 797 * Intialize a mini receive ring descriptor. This only applies to 798 * the Tigon 2. 799 */ 800 static int ti_newbuf_mini(sc, i, m, dmamap) 801 struct ti_softc *sc; 802 int i; 803 struct mbuf *m; 804 bus_dmamap_t dmamap; /* required if (m != NULL) */ 805 { 806 struct mbuf *m_new = NULL; 807 struct ti_rx_desc *r; 808 int error; 809 810 if (dmamap == NULL) { 811 /* if (m) panic() */ 812 813 if ((error = bus_dmamap_create(sc->sc_dmat, MHLEN, 1, 814 MHLEN, 0, BUS_DMA_NOWAIT, 815 &dmamap)) != 0) { 816 printf("%s: can't create recv map, error = %d\n", 817 sc->sc_dev.dv_xname, error); 818 return(ENOMEM); 819 } 820 } 821 sc->mini_dmamap[i] = dmamap; 822 823 if (m == NULL) { 824 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 825 if (m_new == NULL) { 826 printf("%s: mbuf allocation failed " 827 "-- packet dropped!\n", sc->sc_dev.dv_xname); 828 return(ENOBUFS); 829 } 830 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 831 m_adj(m_new, ETHER_ALIGN); 832 833 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap, 834 mtod(m_new, caddr_t), m_new->m_len, NULL, 835 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 836 printf("%s: can't load recv map, error = %d\n", 837 sc->sc_dev.dv_xname, error); 838 return (ENOMEM); 839 } 840 } else { 841 m_new = m; 842 m_new->m_data = m_new->m_pktdat; 843 m_new->m_len = m_new->m_pkthdr.len = MHLEN; 844 m_adj(m_new, ETHER_ALIGN); 845 846 /* reuse the dmamap */ 847 } 848 849 r = &sc->ti_rdata->ti_rx_mini_ring[i]; 850 sc->ti_cdata.ti_rx_mini_chain[i] = m_new; 851 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr; 852 r->ti_type = TI_BDTYPE_RECV_BD; 853 r->ti_flags = TI_BDFLAG_MINI_RING; 854 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4) 855 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 856 if (sc->ethercom.ec_if.if_capenable & 857 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 858 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 859 r->ti_len = m_new->m_len; /* == ds_len */ 860 r->ti_idx = i; 861 862 return(0); 863 } 864 865 /* 866 * Initialize a jumbo receive ring descriptor. This allocates 867 * a jumbo buffer from the pool managed internally by the driver. 868 */ 869 static int ti_newbuf_jumbo(sc, i, m) 870 struct ti_softc *sc; 871 int i; 872 struct mbuf *m; 873 { 874 struct mbuf *m_new = NULL; 875 struct ti_rx_desc *r; 876 877 if (m == NULL) { 878 caddr_t *buf = NULL; 879 880 /* Allocate the mbuf. */ 881 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 882 if (m_new == NULL) { 883 printf("%s: mbuf allocation failed " 884 "-- packet dropped!\n", sc->sc_dev.dv_xname); 885 return(ENOBUFS); 886 } 887 888 /* Allocate the jumbo buffer */ 889 buf = ti_jalloc(sc); 890 if (buf == NULL) { 891 m_freem(m_new); 892 printf("%s: jumbo allocation failed " 893 "-- packet dropped!\n", sc->sc_dev.dv_xname); 894 return(ENOBUFS); 895 } 896 897 /* Attach the buffer to the mbuf. */ 898 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf; 899 m_new->m_flags |= M_EXT; 900 m_new->m_len = m_new->m_pkthdr.len = 901 m_new->m_ext.ext_size = ETHER_MAX_LEN_JUMBO; 902 m_new->m_ext.ext_free = ti_jfree; 903 m_new->m_ext.ext_arg = sc; 904 MCLINITREFERENCE(m_new); 905 } else { 906 m_new = m; 907 m_new->m_data = m_new->m_ext.ext_buf; 908 m_new->m_ext.ext_size = ETHER_MAX_LEN_JUMBO; 909 } 910 911 m_adj(m_new, ETHER_ALIGN); 912 /* Set up the descriptor. */ 913 r = &sc->ti_rdata->ti_rx_jumbo_ring[i]; 914 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new; 915 TI_HOSTADDR(r->ti_addr) = sc->jumbo_dmaaddr + 916 ((caddr_t)mtod(m_new, caddr_t) 917 - (caddr_t)sc->ti_cdata.ti_jumbo_buf); 918 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD; 919 r->ti_flags = TI_BDFLAG_JUMBO_RING; 920 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4) 921 r->ti_flags |= TI_BDFLAG_IP_CKSUM; 922 if (sc->ethercom.ec_if.if_capenable & 923 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 924 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 925 r->ti_len = m_new->m_len; 926 r->ti_idx = i; 927 928 return(0); 929 } 930 931 /* 932 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 933 * that's 1MB or memory, which is a lot. For now, we fill only the first 934 * 256 ring entries and hope that our CPU is fast enough to keep up with 935 * the NIC. 936 */ 937 static int ti_init_rx_ring_std(sc) 938 struct ti_softc *sc; 939 { 940 int i; 941 struct ti_cmd_desc cmd; 942 943 for (i = 0; i < TI_SSLOTS; i++) { 944 if (ti_newbuf_std(sc, i, NULL, 0) == ENOBUFS) 945 return(ENOBUFS); 946 }; 947 948 TI_UPDATE_STDPROD(sc, i - 1); 949 sc->ti_std = i - 1; 950 951 return(0); 952 } 953 954 static void ti_free_rx_ring_std(sc) 955 struct ti_softc *sc; 956 { 957 int i; 958 959 for (i = 0; i < TI_STD_RX_RING_CNT; i++) { 960 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) { 961 m_freem(sc->ti_cdata.ti_rx_std_chain[i]); 962 sc->ti_cdata.ti_rx_std_chain[i] = NULL; 963 964 /* if (sc->std_dmamap[i] == 0) panic() */ 965 bus_dmamap_destroy(sc->sc_dmat, sc->std_dmamap[i]); 966 sc->std_dmamap[i] = 0; 967 } 968 memset((char *)&sc->ti_rdata->ti_rx_std_ring[i], 0, 969 sizeof(struct ti_rx_desc)); 970 } 971 972 return; 973 } 974 975 static int ti_init_rx_ring_jumbo(sc) 976 struct ti_softc *sc; 977 { 978 int i; 979 struct ti_cmd_desc cmd; 980 981 for (i = 0; i < (TI_JSLOTS - 20); i++) { 982 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 983 return(ENOBUFS); 984 }; 985 986 TI_UPDATE_JUMBOPROD(sc, i - 1); 987 sc->ti_jumbo = i - 1; 988 989 return(0); 990 } 991 992 static void ti_free_rx_ring_jumbo(sc) 993 struct ti_softc *sc; 994 { 995 int i; 996 997 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) { 998 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) { 999 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]); 1000 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL; 1001 } 1002 memset((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 0, 1003 sizeof(struct ti_rx_desc)); 1004 } 1005 1006 return; 1007 } 1008 1009 static int ti_init_rx_ring_mini(sc) 1010 struct ti_softc *sc; 1011 { 1012 int i; 1013 1014 for (i = 0; i < TI_MSLOTS; i++) { 1015 if (ti_newbuf_mini(sc, i, NULL, 0) == ENOBUFS) 1016 return(ENOBUFS); 1017 }; 1018 1019 TI_UPDATE_MINIPROD(sc, i - 1); 1020 sc->ti_mini = i - 1; 1021 1022 return(0); 1023 } 1024 1025 static void ti_free_rx_ring_mini(sc) 1026 struct ti_softc *sc; 1027 { 1028 int i; 1029 1030 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) { 1031 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) { 1032 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]); 1033 sc->ti_cdata.ti_rx_mini_chain[i] = NULL; 1034 1035 /* if (sc->mini_dmamap[i] == 0) panic() */ 1036 bus_dmamap_destroy(sc->sc_dmat, sc->mini_dmamap[i]); 1037 sc->mini_dmamap[i] = 0; 1038 } 1039 memset((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 0, 1040 sizeof(struct ti_rx_desc)); 1041 } 1042 1043 return; 1044 } 1045 1046 static void ti_free_tx_ring(sc) 1047 struct ti_softc *sc; 1048 { 1049 int i; 1050 struct txdmamap_pool_entry *dma; 1051 1052 if (sc->ti_rdata->ti_tx_ring == NULL) 1053 return; 1054 1055 for (i = 0; i < TI_TX_RING_CNT; i++) { 1056 if (sc->ti_cdata.ti_tx_chain[i] != NULL) { 1057 m_freem(sc->ti_cdata.ti_tx_chain[i]); 1058 sc->ti_cdata.ti_tx_chain[i] = NULL; 1059 1060 /* if (sc->txdma[i] == 0) panic() */ 1061 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, sc->txdma[i], 1062 link); 1063 sc->txdma[i] = 0; 1064 } 1065 memset((char *)&sc->ti_rdata->ti_tx_ring[i], 0, 1066 sizeof(struct ti_tx_desc)); 1067 } 1068 1069 while ((dma = SIMPLEQ_FIRST(&sc->txdma_list))) { 1070 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, dma, link); 1071 bus_dmamap_destroy(sc->sc_dmat, dma->dmamap); 1072 free(dma, M_DEVBUF); 1073 } 1074 1075 return; 1076 } 1077 1078 static int ti_init_tx_ring(sc) 1079 struct ti_softc *sc; 1080 { 1081 int i, error; 1082 bus_dmamap_t dmamap; 1083 struct txdmamap_pool_entry *dma; 1084 1085 sc->ti_txcnt = 0; 1086 sc->ti_tx_saved_considx = 0; 1087 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0); 1088 1089 SIMPLEQ_INIT(&sc->txdma_list); 1090 for (i = 0; i < TI_RSLOTS; i++) { 1091 /* I've seen mbufs with 30 fragments. */ 1092 if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_MAX_LEN_JUMBO, 1093 40, ETHER_MAX_LEN_JUMBO, 0, 1094 BUS_DMA_NOWAIT, &dmamap)) != 0) { 1095 printf("%s: can't create tx map, error = %d\n", 1096 sc->sc_dev.dv_xname, error); 1097 return(ENOMEM); 1098 } 1099 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT); 1100 if (!dma) { 1101 printf("%s: can't alloc txdmamap_pool_entry\n", 1102 sc->sc_dev.dv_xname); 1103 bus_dmamap_destroy(sc->sc_dmat, dmamap); 1104 return (ENOMEM); 1105 } 1106 dma->dmamap = dmamap; 1107 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 1108 } 1109 1110 return(0); 1111 } 1112 1113 /* 1114 * The Tigon 2 firmware has a new way to add/delete multicast addresses, 1115 * but we have to support the old way too so that Tigon 1 cards will 1116 * work. 1117 */ 1118 void ti_add_mcast(sc, addr) 1119 struct ti_softc *sc; 1120 struct ether_addr *addr; 1121 { 1122 struct ti_cmd_desc cmd; 1123 u_int16_t *m; 1124 u_int32_t ext[2] = {0, 0}; 1125 1126 m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1127 1128 switch(sc->ti_hwrev) { 1129 case TI_HWREV_TIGON: 1130 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1131 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1132 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0); 1133 break; 1134 case TI_HWREV_TIGON_II: 1135 ext[0] = htons(m[0]); 1136 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1137 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2); 1138 break; 1139 default: 1140 printf("%s: unknown hwrev\n", sc->sc_dev.dv_xname); 1141 break; 1142 } 1143 1144 return; 1145 } 1146 1147 void ti_del_mcast(sc, addr) 1148 struct ti_softc *sc; 1149 struct ether_addr *addr; 1150 { 1151 struct ti_cmd_desc cmd; 1152 u_int16_t *m; 1153 u_int32_t ext[2] = {0, 0}; 1154 1155 m = (u_int16_t *)&addr->ether_addr_octet[0]; /* XXX */ 1156 1157 switch(sc->ti_hwrev) { 1158 case TI_HWREV_TIGON: 1159 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0])); 1160 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2])); 1161 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0); 1162 break; 1163 case TI_HWREV_TIGON_II: 1164 ext[0] = htons(m[0]); 1165 ext[1] = (htons(m[1]) << 16) | htons(m[2]); 1166 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2); 1167 break; 1168 default: 1169 printf("%s: unknown hwrev\n", sc->sc_dev.dv_xname); 1170 break; 1171 } 1172 1173 return; 1174 } 1175 1176 /* 1177 * Configure the Tigon's multicast address filter. 1178 * 1179 * The actual multicast table management is a bit of a pain, thanks to 1180 * slight brain damage on the part of both Alteon and us. With our 1181 * multicast code, we are only alerted when the multicast address table 1182 * changes and at that point we only have the current list of addresses: 1183 * we only know the current state, not the previous state, so we don't 1184 * actually know what addresses were removed or added. The firmware has 1185 * state, but we can't get our grubby mits on it, and there is no 'delete 1186 * all multicast addresses' command. Hence, we have to maintain our own 1187 * state so we know what addresses have been programmed into the NIC at 1188 * any given time. 1189 */ 1190 static void ti_setmulti(sc) 1191 struct ti_softc *sc; 1192 { 1193 struct ifnet *ifp; 1194 struct ti_cmd_desc cmd; 1195 struct ti_mc_entry *mc; 1196 u_int32_t intrs; 1197 struct ether_multi *enm; 1198 struct ether_multistep step; 1199 1200 ifp = &sc->ethercom.ec_if; 1201 1202 /* Disable interrupts. */ 1203 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); 1204 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1205 1206 /* First, zot all the existing filters. */ 1207 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1208 ti_del_mcast(sc, &mc->mc_addr); 1209 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1210 free(mc, M_DEVBUF); 1211 } 1212 1213 /* 1214 * Remember all multicast addresses so that we can delete them 1215 * later. Punt if there is a range of addresses or memory shortage. 1216 */ 1217 ETHER_FIRST_MULTI(step, &sc->ethercom, enm); 1218 while (enm != NULL) { 1219 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1220 ETHER_ADDR_LEN) != 0) 1221 goto allmulti; 1222 if ((mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, 1223 M_NOWAIT)) == NULL) 1224 goto allmulti; 1225 memcpy(&mc->mc_addr, enm->enm_addrlo, ETHER_ADDR_LEN); 1226 SIMPLEQ_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries); 1227 ETHER_NEXT_MULTI(step, enm); 1228 } 1229 1230 /* Accept only programmed multicast addresses */ 1231 ifp->if_flags &= ~IFF_ALLMULTI; 1232 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0); 1233 1234 /* Now program new ones. */ 1235 for (mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead); mc != NULL; 1236 mc = SIMPLEQ_NEXT(mc, mc_entries)) 1237 ti_add_mcast(sc, &mc->mc_addr); 1238 1239 /* Re-enable interrupts. */ 1240 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1241 1242 return; 1243 1244 allmulti: 1245 /* No need to keep individual multicast addresses */ 1246 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) { 1247 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc, 1248 mc_entries); 1249 free(mc, M_DEVBUF); 1250 } 1251 1252 /* Accept all multicast addresses */ 1253 ifp->if_flags |= IFF_ALLMULTI; 1254 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0); 1255 1256 /* Re-enable interrupts. */ 1257 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs); 1258 } 1259 1260 /* 1261 * Check to see if the BIOS has configured us for a 64 bit slot when 1262 * we aren't actually in one. If we detect this condition, we can work 1263 * around it on the Tigon 2 by setting a bit in the PCI state register, 1264 * but for the Tigon 1 we must give up and abort the interface attach. 1265 */ 1266 static int ti_64bitslot_war(sc) 1267 struct ti_softc *sc; 1268 { 1269 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { 1270 CSR_WRITE_4(sc, 0x600, 0); 1271 CSR_WRITE_4(sc, 0x604, 0); 1272 CSR_WRITE_4(sc, 0x600, 0x5555AAAA); 1273 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { 1274 if (sc->ti_hwrev == TI_HWREV_TIGON) 1275 return(EINVAL); 1276 else { 1277 TI_SETBIT(sc, TI_PCI_STATE, 1278 TI_PCISTATE_32BIT_BUS); 1279 return(0); 1280 } 1281 } 1282 } 1283 1284 return(0); 1285 } 1286 1287 /* 1288 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1289 * self-test results. 1290 */ 1291 static int ti_chipinit(sc) 1292 struct ti_softc *sc; 1293 { 1294 u_int32_t cacheline; 1295 u_int32_t pci_writemax = 0; 1296 1297 /* Initialize link to down state. */ 1298 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN; 1299 1300 /* Set endianness before we access any non-PCI registers. */ 1301 #if BYTE_ORDER == BIG_ENDIAN 1302 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1303 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24)); 1304 #else 1305 CSR_WRITE_4(sc, TI_MISC_HOST_CTL, 1306 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24)); 1307 #endif 1308 1309 /* Check the ROM failed bit to see if self-tests passed. */ 1310 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { 1311 printf("%s: board self-diagnostics failed!\n", 1312 sc->sc_dev.dv_xname); 1313 return(ENODEV); 1314 } 1315 1316 /* Halt the CPU. */ 1317 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT); 1318 1319 /* Figure out the hardware revision. */ 1320 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) { 1321 case TI_REV_TIGON_I: 1322 sc->ti_hwrev = TI_HWREV_TIGON; 1323 break; 1324 case TI_REV_TIGON_II: 1325 sc->ti_hwrev = TI_HWREV_TIGON_II; 1326 break; 1327 default: 1328 printf("%s: unsupported chip revision\n", sc->sc_dev.dv_xname); 1329 return(ENODEV); 1330 } 1331 1332 /* Do special setup for Tigon 2. */ 1333 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1334 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT); 1335 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K); 1336 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS); 1337 } 1338 1339 /* Set up the PCI state register. */ 1340 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD); 1341 if (sc->ti_hwrev == TI_HWREV_TIGON_II) { 1342 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT); 1343 } 1344 1345 /* Clear the read/write max DMA parameters. */ 1346 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA| 1347 TI_PCISTATE_READ_MAXDMA)); 1348 1349 /* Get cache line size. */ 1350 cacheline = PCI_CACHELINE(CSR_READ_4(sc, PCI_BHLC_REG)); 1351 1352 /* 1353 * If the system has set enabled the PCI memory write 1354 * and invalidate command in the command register, set 1355 * the write max parameter accordingly. This is necessary 1356 * to use MWI with the Tigon 2. 1357 */ 1358 if (CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1359 & PCI_COMMAND_INVALIDATE_ENABLE) { 1360 switch(cacheline) { 1361 case 1: 1362 case 4: 1363 case 8: 1364 case 16: 1365 case 32: 1366 case 64: 1367 break; 1368 default: 1369 /* Disable PCI memory write and invalidate. */ 1370 if (bootverbose) 1371 printf("%s: cache line size %d not " 1372 "supported; disabling PCI MWI\n", 1373 sc->sc_dev.dv_xname, cacheline); 1374 CSR_WRITE_4(sc, PCI_COMMAND_STATUS_REG, 1375 CSR_READ_4(sc, PCI_COMMAND_STATUS_REG) 1376 & ~PCI_COMMAND_INVALIDATE_ENABLE); 1377 break; 1378 } 1379 } 1380 1381 #ifdef __brokenalpha__ 1382 /* 1383 * From the Alteon sample driver: 1384 * Must insure that we do not cross an 8K (bytes) boundary 1385 * for DMA reads. Our highest limit is 1K bytes. This is a 1386 * restriction on some ALPHA platforms with early revision 1387 * 21174 PCI chipsets, such as the AlphaPC 164lx 1388 */ 1389 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024); 1390 #else 1391 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax); 1392 #endif 1393 1394 /* This sets the min dma param all the way up (0xff). */ 1395 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA); 1396 1397 /* Configure DMA variables. */ 1398 #if BYTE_ORDER == BIG_ENDIAN 1399 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD | 1400 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD | 1401 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB | 1402 TI_OPMODE_DONT_FRAG_JUMBO); 1403 #else 1404 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA| 1405 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO| 1406 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB); 1407 #endif 1408 1409 /* 1410 * Only allow 1 DMA channel to be active at a time. 1411 * I don't think this is a good idea, but without it 1412 * the firmware racks up lots of nicDmaReadRingFull 1413 * errors. 1414 * Incompatible with hardware assisted checksums. 1415 */ 1416 if ((sc->ethercom.ec_if.if_capenable & 1417 (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4|IFCAP_CSUM_IPv4)) == 0) 1418 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE); 1419 1420 /* Recommended settings from Tigon manual. */ 1421 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W); 1422 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W); 1423 1424 if (ti_64bitslot_war(sc)) { 1425 printf("%s: bios thinks we're in a 64 bit slot, " 1426 "but we aren't", sc->sc_dev.dv_xname); 1427 return(EINVAL); 1428 } 1429 1430 return(0); 1431 } 1432 1433 /* 1434 * Initialize the general information block and firmware, and 1435 * start the CPU(s) running. 1436 */ 1437 static int ti_gibinit(sc) 1438 struct ti_softc *sc; 1439 { 1440 struct ti_rcb *rcb; 1441 int i; 1442 struct ifnet *ifp; 1443 1444 ifp = &sc->ethercom.ec_if; 1445 1446 /* Disable interrupts for now. */ 1447 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 1448 1449 /* Tell the chip where to find the general information block. */ 1450 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0); 1451 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, TI_CDGIBADDR(sc)); 1452 1453 /* Load the firmware into SRAM. */ 1454 ti_loadfw(sc); 1455 1456 /* Set up the contents of the general info and ring control blocks. */ 1457 1458 /* Set up the event ring and producer pointer. */ 1459 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb; 1460 1461 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDEVENTADDR(sc, 0); 1462 rcb->ti_flags = 0; 1463 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) = 1464 TI_CDEVPRODADDR(sc); 1465 1466 sc->ti_ev_prodidx.ti_idx = 0; 1467 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0); 1468 sc->ti_ev_saved_considx = 0; 1469 1470 /* Set up the command ring and producer mailbox. */ 1471 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb; 1472 1473 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING); 1474 rcb->ti_flags = 0; 1475 rcb->ti_max_len = 0; 1476 for (i = 0; i < TI_CMD_RING_CNT; i++) { 1477 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0); 1478 } 1479 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0); 1480 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0); 1481 sc->ti_cmd_saved_prodidx = 0; 1482 1483 /* 1484 * Assign the address of the stats refresh buffer. 1485 * We re-use the current stats buffer for this to 1486 * conserve memory. 1487 */ 1488 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) = 1489 TI_CDSTATSADDR(sc); 1490 1491 /* Set up the standard receive ring. */ 1492 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb; 1493 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXSTDADDR(sc, 0); 1494 rcb->ti_max_len = ETHER_MAX_LEN; 1495 rcb->ti_flags = 0; 1496 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1497 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1498 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1499 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1500 if (sc->ethercom.ec_nvlans != 0) 1501 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1502 1503 /* Set up the jumbo receive ring. */ 1504 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb; 1505 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXJUMBOADDR(sc, 0); 1506 rcb->ti_max_len = ETHER_MAX_LEN_JUMBO; 1507 rcb->ti_flags = 0; 1508 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1509 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1510 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1511 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1512 if (sc->ethercom.ec_nvlans != 0) 1513 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1514 1515 /* 1516 * Set up the mini ring. Only activated on the 1517 * Tigon 2 but the slot in the config block is 1518 * still there on the Tigon 1. 1519 */ 1520 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb; 1521 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXMINIADDR(sc, 0); 1522 rcb->ti_max_len = MHLEN - ETHER_ALIGN; 1523 if (sc->ti_hwrev == TI_HWREV_TIGON) 1524 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED; 1525 else 1526 rcb->ti_flags = 0; 1527 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1528 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1529 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1530 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM; 1531 if (sc->ethercom.ec_nvlans != 0) 1532 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1533 1534 /* 1535 * Set up the receive return ring. 1536 */ 1537 rcb = &sc->ti_rdata->ti_info.ti_return_rcb; 1538 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXRTNADDR(sc, 0); 1539 rcb->ti_flags = 0; 1540 rcb->ti_max_len = TI_RETURN_RING_CNT; 1541 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) = 1542 TI_CDRTNPRODADDR(sc); 1543 1544 /* 1545 * Set up the tx ring. Note: for the Tigon 2, we have the option 1546 * of putting the transmit ring in the host's address space and 1547 * letting the chip DMA it instead of leaving the ring in the NIC's 1548 * memory and accessing it through the shared memory region. We 1549 * do this for the Tigon 2, but it doesn't work on the Tigon 1, 1550 * so we have to revert to the shared memory scheme if we detect 1551 * a Tigon 1 chip. 1552 */ 1553 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE); 1554 if (sc->ti_hwrev == TI_HWREV_TIGON) { 1555 sc->ti_tx_ring_nic = 1556 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW); 1557 } 1558 memset((char *)sc->ti_rdata->ti_tx_ring, 0, 1559 TI_TX_RING_CNT * sizeof(struct ti_tx_desc)); 1560 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb; 1561 if (sc->ti_hwrev == TI_HWREV_TIGON) 1562 rcb->ti_flags = 0; 1563 else 1564 rcb->ti_flags = TI_RCB_FLAG_HOST_RING; 1565 if (ifp->if_capenable & IFCAP_CSUM_IPv4) 1566 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM; 1567 /* 1568 * When we get the packet, there is a pseudo-header seed already 1569 * in the th_sum or uh_sum field. Make sure the firmware doesn't 1570 * compute the pseudo-header checksum again! 1571 */ 1572 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4)) 1573 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM| 1574 TI_RCB_FLAG_NO_PHDR_CKSUM; 1575 if (sc->ethercom.ec_nvlans != 0) 1576 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST; 1577 rcb->ti_max_len = TI_TX_RING_CNT; 1578 if (sc->ti_hwrev == TI_HWREV_TIGON) 1579 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE; 1580 else 1581 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDTXADDR(sc, 0); 1582 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) = 1583 TI_CDTXCONSADDR(sc); 1584 1585 /* 1586 * We're done frobbing the General Information Block. Sync 1587 * it. Note we take care of the first stats sync here, as 1588 * well. 1589 */ 1590 TI_CDGIBSYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1591 1592 /* Set up tuneables */ 1593 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN) || 1594 (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU)) 1595 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, 1596 (sc->ti_rx_coal_ticks / 10)); 1597 else 1598 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks); 1599 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks); 1600 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks); 1601 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds); 1602 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds); 1603 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio); 1604 1605 /* Turn interrupts on. */ 1606 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0); 1607 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 1608 1609 /* Start CPU. */ 1610 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP)); 1611 1612 return(0); 1613 } 1614 1615 /* 1616 * look for id in the device list, returning the first match 1617 */ 1618 static const struct ti_type * 1619 ti_type_match(pa) 1620 struct pci_attach_args *pa; 1621 { 1622 const struct ti_type *t; 1623 1624 t = ti_devs; 1625 while(t->ti_name != NULL) { 1626 if ((PCI_VENDOR(pa->pa_id) == t->ti_vid) && 1627 (PCI_PRODUCT(pa->pa_id) == t->ti_did)) { 1628 return (t); 1629 } 1630 t++; 1631 } 1632 1633 return(NULL); 1634 } 1635 1636 /* 1637 * Probe for a Tigon chip. Check the PCI vendor and device IDs 1638 * against our list and return its name if we find a match. 1639 */ 1640 static int ti_probe(parent, match, aux) 1641 struct device *parent; 1642 struct cfdata *match; 1643 void *aux; 1644 { 1645 struct pci_attach_args *pa = aux; 1646 const struct ti_type *t; 1647 1648 t = ti_type_match(pa); 1649 1650 return((t == NULL) ? 0 : 1); 1651 } 1652 1653 static void ti_attach(parent, self, aux) 1654 struct device *parent, *self; 1655 void *aux; 1656 { 1657 u_int32_t command; 1658 struct ifnet *ifp; 1659 struct ti_softc *sc; 1660 u_char eaddr[ETHER_ADDR_LEN]; 1661 struct pci_attach_args *pa = aux; 1662 pci_chipset_tag_t pc = pa->pa_pc; 1663 pci_intr_handle_t ih; 1664 const char *intrstr = NULL; 1665 bus_dma_segment_t dmaseg; 1666 int error, dmanseg, nolinear; 1667 const struct ti_type *t; 1668 1669 t = ti_type_match(pa); 1670 if (t == NULL) { 1671 printf("ti_attach: were did the card go ?\n"); 1672 return; 1673 } 1674 1675 printf(": %s (rev. 0x%02x)\n", t->ti_name, PCI_REVISION(pa->pa_class)); 1676 1677 sc = (struct ti_softc *)self; 1678 1679 /* 1680 * Map control/status registers. 1681 */ 1682 nolinear = 0; 1683 if (pci_mapreg_map(pa, 0x10, 1684 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1685 BUS_SPACE_MAP_LINEAR , &sc->ti_btag, &sc->ti_bhandle, 1686 NULL, NULL)) { 1687 nolinear = 1; 1688 if (pci_mapreg_map(pa, 0x10, 1689 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 1690 0 , &sc->ti_btag, &sc->ti_bhandle, NULL, NULL)) { 1691 printf(": can't map memory space\n"); 1692 return; 1693 } 1694 } 1695 if (nolinear == 0) 1696 sc->ti_vhandle = (void *)(u_long)(sc->ti_bhandle); /* XXX XXX XXX */ 1697 else 1698 sc->ti_vhandle = NULL; 1699 1700 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1701 command |= PCI_COMMAND_MASTER_ENABLE; 1702 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1703 1704 /* Allocate interrupt */ 1705 if (pci_intr_map(pa, &ih)) { 1706 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 1707 return;; 1708 } 1709 intrstr = pci_intr_string(pc, ih); 1710 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ti_intr, sc); 1711 if (sc->sc_ih == NULL) { 1712 printf("%s: couldn't establish interrupt", 1713 sc->sc_dev.dv_xname); 1714 if (intrstr != NULL) 1715 printf(" at %s", intrstr); 1716 printf("\n"); 1717 return;; 1718 } 1719 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 1720 /* 1721 * Add shutdown hook so that DMA is disabled prior to reboot. Not 1722 * doing do could allow DMA to corrupt kernel memory during the 1723 * reboot before the driver initializes. 1724 */ 1725 (void) shutdownhook_establish(ti_shutdown, sc); 1726 1727 if (ti_chipinit(sc)) { 1728 printf("%s: chip initialization failed\n", self->dv_xname); 1729 goto fail2; 1730 } 1731 1732 /* 1733 * Deal with some chip diffrences. 1734 */ 1735 switch (sc->ti_hwrev) { 1736 case TI_HWREV_TIGON: 1737 sc->sc_tx_encap = ti_encap_tigon1; 1738 sc->sc_tx_eof = ti_txeof_tigon1; 1739 if (nolinear == 1) 1740 printf("%s: memory space not mapped linear\n", 1741 self->dv_xname); 1742 break; 1743 1744 case TI_HWREV_TIGON_II: 1745 sc->sc_tx_encap = ti_encap_tigon2; 1746 sc->sc_tx_eof = ti_txeof_tigon2; 1747 break; 1748 1749 default: 1750 printf("%s: Unknown chip version: %d\n", self->dv_xname, 1751 sc->ti_hwrev); 1752 goto fail2; 1753 } 1754 1755 /* Zero out the NIC's on-board SRAM. */ 1756 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 1757 1758 /* Init again -- zeroing memory may have clobbered some registers. */ 1759 if (ti_chipinit(sc)) { 1760 printf("%s: chip initialization failed\n", self->dv_xname); 1761 goto fail2; 1762 } 1763 1764 /* 1765 * Get station address from the EEPROM. Note: the manual states 1766 * that the MAC address is at offset 0x8c, however the data is 1767 * stored as two longwords (since that's how it's loaded into 1768 * the NIC). This means the MAC address is actually preceded 1769 * by two zero bytes. We need to skip over those. 1770 */ 1771 if (ti_read_eeprom(sc, (caddr_t)&eaddr, 1772 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1773 printf("%s: failed to read station address\n", self->dv_xname); 1774 goto fail2; 1775 } 1776 1777 /* 1778 * A Tigon chip was detected. Inform the world. 1779 */ 1780 printf("%s: Ethernet address: %s\n", self->dv_xname, 1781 ether_sprintf(eaddr)); 1782 1783 sc->sc_dmat = pa->pa_dmat; 1784 1785 /* Allocate the general information block and ring buffers. */ 1786 if ((error = bus_dmamem_alloc(sc->sc_dmat, 1787 sizeof(struct ti_ring_data), PAGE_SIZE, 0, &dmaseg, 1, &dmanseg, 1788 BUS_DMA_NOWAIT)) != 0) { 1789 printf("%s: can't allocate ring buffer, error = %d\n", 1790 sc->sc_dev.dv_xname, error); 1791 goto fail2; 1792 } 1793 1794 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg, 1795 sizeof(struct ti_ring_data), (caddr_t *)&sc->ti_rdata, 1796 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1797 printf("%s: can't map ring buffer, error = %d\n", 1798 sc->sc_dev.dv_xname, error); 1799 goto fail2; 1800 } 1801 1802 if ((error = bus_dmamap_create(sc->sc_dmat, 1803 sizeof(struct ti_ring_data), 1, 1804 sizeof(struct ti_ring_data), 0, BUS_DMA_NOWAIT, 1805 &sc->info_dmamap)) != 0) { 1806 printf("%s: can't create ring buffer DMA map, error = %d\n", 1807 sc->sc_dev.dv_xname, error); 1808 goto fail2; 1809 } 1810 1811 if ((error = bus_dmamap_load(sc->sc_dmat, sc->info_dmamap, 1812 sc->ti_rdata, sizeof(struct ti_ring_data), NULL, 1813 BUS_DMA_NOWAIT)) != 0) { 1814 printf("%s: can't load ring buffer DMA map, error = %d\n", 1815 sc->sc_dev.dv_xname, error); 1816 goto fail2; 1817 } 1818 1819 sc->info_dmaaddr = sc->info_dmamap->dm_segs[0].ds_addr; 1820 1821 memset(sc->ti_rdata, 0, sizeof(struct ti_ring_data)); 1822 1823 /* Try to allocate memory for jumbo buffers. */ 1824 if (ti_alloc_jumbo_mem(sc)) { 1825 printf("%s: jumbo buffer allocation failed\n", self->dv_xname); 1826 goto fail2; 1827 } 1828 1829 SIMPLEQ_INIT(&sc->ti_mc_listhead); 1830 1831 /* 1832 * We really need a better way to tell a 1000baseT card 1833 * from a 1000baseSX one, since in theory there could be 1834 * OEMed 1000baseT cards from lame vendors who aren't 1835 * clever enough to change the PCI ID. For the moment 1836 * though, the AceNIC is the only copper card available. 1837 */ 1838 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALTEON && 1839 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALTEON_ACENIC_COPPER) || 1840 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NETGEAR && 1841 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NETGEAR_GA620T)) 1842 sc->ti_copper = 1; 1843 else 1844 sc->ti_copper = 0; 1845 1846 /* Set default tuneable values. */ 1847 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC; 1848 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000; 1849 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500; 1850 sc->ti_rx_max_coal_bds = 64; 1851 sc->ti_tx_max_coal_bds = 128; 1852 sc->ti_tx_buf_ratio = 21; 1853 1854 /* Set up ifnet structure */ 1855 ifp = &sc->ethercom.ec_if; 1856 ifp->if_softc = sc; 1857 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 1858 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1859 ifp->if_ioctl = ti_ioctl; 1860 ifp->if_start = ti_start; 1861 ifp->if_watchdog = ti_watchdog; 1862 IFQ_SET_READY(&ifp->if_snd); 1863 1864 #if 0 1865 /* 1866 * XXX This is not really correct -- we don't necessarily 1867 * XXX want to queue up as many as we can transmit at the 1868 * XXX upper layer like that. Someone with a board should 1869 * XXX check to see how this affects performance. 1870 */ 1871 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1; 1872 #endif 1873 1874 /* 1875 * We can support 802.1Q VLAN-sized frames. 1876 */ 1877 sc->ethercom.ec_capabilities |= 1878 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 1879 1880 /* 1881 * We can do IPv4, TCPv4, and UDPv4 checksums in hardware. 1882 */ 1883 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 1884 IFCAP_CSUM_UDPv4; 1885 1886 /* Set up ifmedia support. */ 1887 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts); 1888 if (sc->ti_copper) { 1889 /* 1890 * Copper cards allow manual 10/100 mode selection, 1891 * but not manual 1000baseT mode selection. Why? 1892 * Becuase currently there's no way to specify the 1893 * master/slave setting through the firmware interface, 1894 * so Alteon decided to just bag it and handle it 1895 * via autonegotiation. 1896 */ 1897 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1898 ifmedia_add(&sc->ifmedia, 1899 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1900 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 1901 ifmedia_add(&sc->ifmedia, 1902 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 1903 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL); 1904 ifmedia_add(&sc->ifmedia, 1905 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL); 1906 } else { 1907 /* Fiber cards don't support 10/100 modes. */ 1908 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1909 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1910 } 1911 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1912 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO); 1913 1914 /* 1915 * Call MI attach routines. 1916 */ 1917 if_attach(ifp); 1918 ether_ifattach(ifp, eaddr); 1919 1920 return; 1921 fail2: 1922 pci_intr_disestablish(pc, sc->sc_ih); 1923 return; 1924 } 1925 1926 /* 1927 * Frame reception handling. This is called if there's a frame 1928 * on the receive return list. 1929 * 1930 * Note: we have to be able to handle three possibilities here: 1931 * 1) the frame is from the mini receive ring (can only happen) 1932 * on Tigon 2 boards) 1933 * 2) the frame is from the jumbo receive ring 1934 * 3) the frame is from the standard receive ring 1935 */ 1936 1937 static void ti_rxeof(sc) 1938 struct ti_softc *sc; 1939 { 1940 struct ifnet *ifp; 1941 struct ti_cmd_desc cmd; 1942 1943 ifp = &sc->ethercom.ec_if; 1944 1945 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) { 1946 struct ti_rx_desc *cur_rx; 1947 u_int32_t rxidx; 1948 struct mbuf *m = NULL; 1949 u_int16_t vlan_tag = 0; 1950 int have_tag = 0; 1951 struct ether_header *eh; 1952 bus_dmamap_t dmamap; 1953 1954 cur_rx = 1955 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx]; 1956 rxidx = cur_rx->ti_idx; 1957 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT); 1958 1959 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) { 1960 have_tag = 1; 1961 vlan_tag = cur_rx->ti_vlan_tag; 1962 } 1963 1964 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) { 1965 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT); 1966 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx]; 1967 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL; 1968 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1969 ifp->if_ierrors++; 1970 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1971 continue; 1972 } 1973 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) 1974 == ENOBUFS) { 1975 ifp->if_ierrors++; 1976 ti_newbuf_jumbo(sc, sc->ti_jumbo, m); 1977 continue; 1978 } 1979 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) { 1980 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT); 1981 m = sc->ti_cdata.ti_rx_mini_chain[rxidx]; 1982 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL; 1983 dmamap = sc->mini_dmamap[rxidx]; 1984 sc->mini_dmamap[rxidx] = 0; 1985 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 1986 ifp->if_ierrors++; 1987 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1988 continue; 1989 } 1990 if (ti_newbuf_mini(sc, sc->ti_mini, NULL, dmamap) 1991 == ENOBUFS) { 1992 ifp->if_ierrors++; 1993 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap); 1994 continue; 1995 } 1996 } else { 1997 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT); 1998 m = sc->ti_cdata.ti_rx_std_chain[rxidx]; 1999 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL; 2000 dmamap = sc->std_dmamap[rxidx]; 2001 sc->std_dmamap[rxidx] = 0; 2002 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) { 2003 ifp->if_ierrors++; 2004 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 2005 continue; 2006 } 2007 if (ti_newbuf_std(sc, sc->ti_std, NULL, dmamap) 2008 == ENOBUFS) { 2009 ifp->if_ierrors++; 2010 ti_newbuf_std(sc, sc->ti_std, m, dmamap); 2011 continue; 2012 } 2013 } 2014 2015 m->m_pkthdr.len = m->m_len = cur_rx->ti_len; 2016 ifp->if_ipackets++; 2017 m->m_pkthdr.rcvif = ifp; 2018 2019 #if NBPFILTER > 0 2020 /* 2021 * Handle BPF listeners. Let the BPF user see the packet, but 2022 * don't pass it up to the ether_input() layer unless it's 2023 * a broadcast packet, multicast packet, matches our ethernet 2024 * address or the interface is in promiscuous mode. 2025 */ 2026 if (ifp->if_bpf) 2027 bpf_mtap(ifp->if_bpf, m); 2028 #endif 2029 2030 eh = mtod(m, struct ether_header *); 2031 switch (ntohs(eh->ether_type)) { 2032 case ETHERTYPE_IP: 2033 { 2034 struct ip *ip = (struct ip *) (eh + 1); 2035 2036 /* 2037 * Note the Tigon firmware does not invert 2038 * the checksum for us, hence the XOR. 2039 */ 2040 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 2041 if ((cur_rx->ti_ip_cksum ^ 0xffff) != 0) 2042 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 2043 /* 2044 * ntohs() the constant so the compiler can 2045 * optimize... 2046 * 2047 * XXX Figure out a sane way to deal with 2048 * fragmented packets. 2049 */ 2050 if ((ip->ip_off & htons(IP_MF|IP_OFFMASK)) == 0) { 2051 switch (ip->ip_p) { 2052 case IPPROTO_TCP: 2053 m->m_pkthdr.csum_data = 2054 cur_rx->ti_tcp_udp_cksum; 2055 m->m_pkthdr.csum_flags |= 2056 M_CSUM_TCPv4|M_CSUM_DATA; 2057 break; 2058 case IPPROTO_UDP: 2059 m->m_pkthdr.csum_data = 2060 cur_rx->ti_tcp_udp_cksum; 2061 m->m_pkthdr.csum_flags |= 2062 M_CSUM_UDPv4|M_CSUM_DATA; 2063 break; 2064 default: 2065 /* Nothing */; 2066 } 2067 } 2068 break; 2069 } 2070 default: 2071 /* Nothing. */ 2072 break; 2073 } 2074 2075 if (have_tag) { 2076 struct mbuf *n; 2077 n = m_aux_add(m, AF_LINK, ETHERTYPE_VLAN); 2078 if (n) { 2079 *mtod(n, int *) = vlan_tag; 2080 n->m_len = sizeof(int); 2081 } else { 2082 printf("%s: no mbuf for tag\n", ifp->if_xname); 2083 m_freem(m); 2084 continue; 2085 } 2086 have_tag = vlan_tag = 0; 2087 } 2088 (*ifp->if_input)(ifp, m); 2089 } 2090 2091 /* Only necessary on the Tigon 1. */ 2092 if (sc->ti_hwrev == TI_HWREV_TIGON) 2093 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 2094 sc->ti_rx_saved_considx); 2095 2096 TI_UPDATE_STDPROD(sc, sc->ti_std); 2097 TI_UPDATE_MINIPROD(sc, sc->ti_mini); 2098 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo); 2099 2100 return; 2101 } 2102 2103 static void ti_txeof_tigon1(sc) 2104 struct ti_softc *sc; 2105 { 2106 struct ti_tx_desc *cur_tx = NULL; 2107 struct ifnet *ifp; 2108 struct txdmamap_pool_entry *dma; 2109 2110 ifp = &sc->ethercom.ec_if; 2111 2112 /* 2113 * Go through our tx ring and free mbufs for those 2114 * frames that have been sent. 2115 */ 2116 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2117 u_int32_t idx = 0; 2118 2119 idx = sc->ti_tx_saved_considx; 2120 if (idx > 383) 2121 CSR_WRITE_4(sc, TI_WINBASE, 2122 TI_TX_RING_BASE + 6144); 2123 else if (idx > 255) 2124 CSR_WRITE_4(sc, TI_WINBASE, 2125 TI_TX_RING_BASE + 4096); 2126 else if (idx > 127) 2127 CSR_WRITE_4(sc, TI_WINBASE, 2128 TI_TX_RING_BASE + 2048); 2129 else 2130 CSR_WRITE_4(sc, TI_WINBASE, 2131 TI_TX_RING_BASE); 2132 cur_tx = &sc->ti_tx_ring_nic[idx % 128]; 2133 if (cur_tx->ti_flags & TI_BDFLAG_END) 2134 ifp->if_opackets++; 2135 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2136 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2137 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2138 2139 dma = sc->txdma[idx]; 2140 KDASSERT(dma != NULL); 2141 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2142 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2143 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2144 2145 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2146 sc->txdma[idx] = NULL; 2147 } 2148 sc->ti_txcnt--; 2149 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2150 ifp->if_timer = 0; 2151 } 2152 2153 if (cur_tx != NULL) 2154 ifp->if_flags &= ~IFF_OACTIVE; 2155 2156 return; 2157 } 2158 2159 static void ti_txeof_tigon2(sc) 2160 struct ti_softc *sc; 2161 { 2162 struct ti_tx_desc *cur_tx = NULL; 2163 struct ifnet *ifp; 2164 struct txdmamap_pool_entry *dma; 2165 int firstidx, cnt; 2166 2167 ifp = &sc->ethercom.ec_if; 2168 2169 /* 2170 * Go through our tx ring and free mbufs for those 2171 * frames that have been sent. 2172 */ 2173 firstidx = sc->ti_tx_saved_considx; 2174 cnt = 0; 2175 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) { 2176 u_int32_t idx = 0; 2177 2178 idx = sc->ti_tx_saved_considx; 2179 cur_tx = &sc->ti_rdata->ti_tx_ring[idx]; 2180 if (cur_tx->ti_flags & TI_BDFLAG_END) 2181 ifp->if_opackets++; 2182 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) { 2183 m_freem(sc->ti_cdata.ti_tx_chain[idx]); 2184 sc->ti_cdata.ti_tx_chain[idx] = NULL; 2185 2186 dma = sc->txdma[idx]; 2187 KDASSERT(dma != NULL); 2188 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0, 2189 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2190 bus_dmamap_unload(sc->sc_dmat, dma->dmamap); 2191 2192 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link); 2193 sc->txdma[idx] = NULL; 2194 } 2195 cnt++; 2196 sc->ti_txcnt--; 2197 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT); 2198 ifp->if_timer = 0; 2199 } 2200 2201 if (cnt != 0) 2202 TI_CDTXSYNC(sc, firstidx, cnt, BUS_DMASYNC_POSTWRITE); 2203 2204 if (cur_tx != NULL) 2205 ifp->if_flags &= ~IFF_OACTIVE; 2206 2207 return; 2208 } 2209 2210 static int ti_intr(xsc) 2211 void *xsc; 2212 { 2213 struct ti_softc *sc; 2214 struct ifnet *ifp; 2215 2216 sc = xsc; 2217 ifp = &sc->ethercom.ec_if; 2218 2219 #ifdef notdef 2220 /* Avoid this for now -- checking this register is expensive. */ 2221 /* Make sure this is really our interrupt. */ 2222 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) 2223 return (0); 2224 #endif 2225 2226 /* Ack interrupt and stop others from occuring. */ 2227 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2228 2229 if (ifp->if_flags & IFF_RUNNING) { 2230 /* Check RX return ring producer/consumer */ 2231 ti_rxeof(sc); 2232 2233 /* Check TX ring producer/consumer */ 2234 (*sc->sc_tx_eof)(sc); 2235 } 2236 2237 ti_handle_events(sc); 2238 2239 /* Re-enable interrupts. */ 2240 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2241 2242 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2243 IFQ_IS_EMPTY(&ifp->if_snd) == 0) 2244 ti_start(ifp); 2245 2246 return (1); 2247 } 2248 2249 static void ti_stats_update(sc) 2250 struct ti_softc *sc; 2251 { 2252 struct ifnet *ifp; 2253 2254 ifp = &sc->ethercom.ec_if; 2255 2256 TI_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD); 2257 2258 ifp->if_collisions += 2259 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames + 2260 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames + 2261 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions + 2262 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) - 2263 ifp->if_collisions; 2264 2265 TI_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD); 2266 } 2267 2268 /* 2269 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2270 * pointers to descriptors. 2271 */ 2272 static int ti_encap_tigon1(sc, m_head, txidx) 2273 struct ti_softc *sc; 2274 struct mbuf *m_head; 2275 u_int32_t *txidx; 2276 { 2277 struct ti_tx_desc *f = NULL; 2278 u_int32_t frag, cur, cnt = 0; 2279 struct txdmamap_pool_entry *dma; 2280 bus_dmamap_t dmamap; 2281 int error, i; 2282 struct mbuf *n; 2283 u_int16_t csum_flags = 0; 2284 2285 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2286 if (dma == NULL) { 2287 return ENOMEM; 2288 } 2289 dmamap = dma->dmamap; 2290 2291 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2292 BUS_DMA_WRITE); 2293 if (error) { 2294 struct mbuf *m; 2295 int i = 0; 2296 for (m = m_head; m; m = m->m_next) 2297 i++; 2298 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2299 "error %d\n", m_head->m_pkthdr.len, i, error); 2300 return (ENOMEM); 2301 } 2302 2303 cur = frag = *txidx; 2304 2305 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2306 /* IP header checksum field must be 0! */ 2307 csum_flags |= TI_BDFLAG_IP_CKSUM; 2308 } 2309 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2310 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2311 2312 /* XXX fragmented packet checksum capability? */ 2313 2314 /* 2315 * Start packing the mbufs in this chain into 2316 * the fragment pointers. Stop when we run out 2317 * of fragments or hit the end of the mbuf chain. 2318 */ 2319 for (i = 0; i < dmamap->dm_nsegs; i++) { 2320 if (frag > 383) 2321 CSR_WRITE_4(sc, TI_WINBASE, 2322 TI_TX_RING_BASE + 6144); 2323 else if (frag > 255) 2324 CSR_WRITE_4(sc, TI_WINBASE, 2325 TI_TX_RING_BASE + 4096); 2326 else if (frag > 127) 2327 CSR_WRITE_4(sc, TI_WINBASE, 2328 TI_TX_RING_BASE + 2048); 2329 else 2330 CSR_WRITE_4(sc, TI_WINBASE, 2331 TI_TX_RING_BASE); 2332 f = &sc->ti_tx_ring_nic[frag % 128]; 2333 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2334 break; 2335 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2336 f->ti_len = dmamap->dm_segs[i].ds_len; 2337 f->ti_flags = csum_flags; 2338 n = m_aux_find(m_head, AF_LINK, ETHERTYPE_VLAN); 2339 if (n) { 2340 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2341 f->ti_vlan_tag = *mtod(n, int *); 2342 } else { 2343 f->ti_vlan_tag = 0; 2344 } 2345 /* 2346 * Sanity check: avoid coming within 16 descriptors 2347 * of the end of the ring. 2348 */ 2349 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2350 return(ENOBUFS); 2351 cur = frag; 2352 TI_INC(frag, TI_TX_RING_CNT); 2353 cnt++; 2354 } 2355 2356 if (i < dmamap->dm_nsegs) 2357 return(ENOBUFS); 2358 2359 if (frag == sc->ti_tx_saved_considx) 2360 return(ENOBUFS); 2361 2362 sc->ti_tx_ring_nic[cur % 128].ti_flags |= 2363 TI_BDFLAG_END; 2364 2365 /* Sync the packet's DMA map. */ 2366 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2367 BUS_DMASYNC_PREWRITE); 2368 2369 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2370 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, dma, link); 2371 sc->txdma[cur] = dma; 2372 sc->ti_txcnt += cnt; 2373 2374 *txidx = frag; 2375 2376 return(0); 2377 } 2378 2379 static int ti_encap_tigon2(sc, m_head, txidx) 2380 struct ti_softc *sc; 2381 struct mbuf *m_head; 2382 u_int32_t *txidx; 2383 { 2384 struct ti_tx_desc *f = NULL; 2385 u_int32_t frag, firstfrag, cur, cnt = 0; 2386 struct txdmamap_pool_entry *dma; 2387 bus_dmamap_t dmamap; 2388 int error, i; 2389 struct mbuf *n; 2390 u_int16_t csum_flags = 0; 2391 2392 dma = SIMPLEQ_FIRST(&sc->txdma_list); 2393 if (dma == NULL) { 2394 return ENOMEM; 2395 } 2396 dmamap = dma->dmamap; 2397 2398 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head, 2399 BUS_DMA_WRITE); 2400 if (error) { 2401 struct mbuf *m; 2402 int i = 0; 2403 for (m = m_head; m; m = m->m_next) 2404 i++; 2405 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) " 2406 "error %d\n", m_head->m_pkthdr.len, i, error); 2407 return (ENOMEM); 2408 } 2409 2410 cur = firstfrag = frag = *txidx; 2411 2412 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) { 2413 /* IP header checksum field must be 0! */ 2414 csum_flags |= TI_BDFLAG_IP_CKSUM; 2415 } 2416 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4|M_CSUM_UDPv4)) 2417 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM; 2418 2419 /* XXX fragmented packet checksum capability? */ 2420 2421 /* 2422 * Start packing the mbufs in this chain into 2423 * the fragment pointers. Stop when we run out 2424 * of fragments or hit the end of the mbuf chain. 2425 */ 2426 for (i = 0; i < dmamap->dm_nsegs; i++) { 2427 f = &sc->ti_rdata->ti_tx_ring[frag]; 2428 if (sc->ti_cdata.ti_tx_chain[frag] != NULL) 2429 break; 2430 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr; 2431 f->ti_len = dmamap->dm_segs[i].ds_len; 2432 f->ti_flags = csum_flags; 2433 n = m_aux_find(m_head, AF_LINK, ETHERTYPE_VLAN); 2434 if (n) { 2435 f->ti_flags |= TI_BDFLAG_VLAN_TAG; 2436 f->ti_vlan_tag = *mtod(n, int *); 2437 } else { 2438 f->ti_vlan_tag = 0; 2439 } 2440 /* 2441 * Sanity check: avoid coming within 16 descriptors 2442 * of the end of the ring. 2443 */ 2444 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16) 2445 return(ENOBUFS); 2446 cur = frag; 2447 TI_INC(frag, TI_TX_RING_CNT); 2448 cnt++; 2449 } 2450 2451 if (i < dmamap->dm_nsegs) 2452 return(ENOBUFS); 2453 2454 if (frag == sc->ti_tx_saved_considx) 2455 return(ENOBUFS); 2456 2457 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END; 2458 2459 /* Sync the packet's DMA map. */ 2460 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 2461 BUS_DMASYNC_PREWRITE); 2462 2463 /* Sync the descriptors we are using. */ 2464 TI_CDTXSYNC(sc, firstfrag, cnt, BUS_DMASYNC_PREWRITE); 2465 2466 sc->ti_cdata.ti_tx_chain[cur] = m_head; 2467 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, dma, link); 2468 sc->txdma[cur] = dma; 2469 sc->ti_txcnt += cnt; 2470 2471 *txidx = frag; 2472 2473 return(0); 2474 } 2475 2476 /* 2477 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2478 * to the mbuf data regions directly in the transmit descriptors. 2479 */ 2480 static void ti_start(ifp) 2481 struct ifnet *ifp; 2482 { 2483 struct ti_softc *sc; 2484 struct mbuf *m_head = NULL; 2485 u_int32_t prodidx = 0; 2486 2487 sc = ifp->if_softc; 2488 2489 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX); 2490 2491 while (sc->ti_cdata.ti_tx_chain[prodidx] == NULL) { 2492 IFQ_POLL(&ifp->if_snd, m_head); 2493 if (m_head == NULL) 2494 break; 2495 2496 /* 2497 * Pack the data into the transmit ring. If we 2498 * don't have room, set the OACTIVE flag and wait 2499 * for the NIC to drain the ring. 2500 */ 2501 if ((*sc->sc_tx_encap)(sc, m_head, &prodidx)) { 2502 ifp->if_flags |= IFF_OACTIVE; 2503 break; 2504 } 2505 2506 IFQ_DEQUEUE(&ifp->if_snd, m_head); 2507 2508 /* 2509 * If there's a BPF listener, bounce a copy of this frame 2510 * to him. 2511 */ 2512 #if NBPFILTER > 0 2513 if (ifp->if_bpf) 2514 bpf_mtap(ifp->if_bpf, m_head); 2515 #endif 2516 } 2517 2518 /* Transmit */ 2519 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx); 2520 2521 /* 2522 * Set a timeout in case the chip goes out to lunch. 2523 */ 2524 ifp->if_timer = 5; 2525 2526 return; 2527 } 2528 2529 static void ti_init(xsc) 2530 void *xsc; 2531 { 2532 struct ti_softc *sc = xsc; 2533 int s; 2534 2535 s = splnet(); 2536 2537 /* Cancel pending I/O and flush buffers. */ 2538 ti_stop(sc); 2539 2540 /* Init the gen info block, ring control blocks and firmware. */ 2541 if (ti_gibinit(sc)) { 2542 printf("%s: initialization failure\n", sc->sc_dev.dv_xname); 2543 splx(s); 2544 return; 2545 } 2546 2547 splx(s); 2548 2549 return; 2550 } 2551 2552 static void ti_init2(sc) 2553 struct ti_softc *sc; 2554 { 2555 struct ti_cmd_desc cmd; 2556 struct ifnet *ifp; 2557 u_int8_t *m; 2558 struct ifmedia *ifm; 2559 int tmp; 2560 2561 ifp = &sc->ethercom.ec_if; 2562 2563 /* Specify MTU and interface index. */ 2564 CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->sc_dev.dv_unit); /* ??? */ 2565 2566 tmp = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 2567 if (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 2568 tmp += ETHER_VLAN_ENCAP_LEN; 2569 CSR_WRITE_4(sc, TI_GCR_IFMTU, tmp); 2570 2571 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0); 2572 2573 /* Load our MAC address. */ 2574 m = (u_int8_t *)LLADDR(ifp->if_sadl); 2575 CSR_WRITE_4(sc, TI_GCR_PAR0, (m[0] << 8) | m[1]); 2576 CSR_WRITE_4(sc, TI_GCR_PAR1, (m[2] << 24) | (m[3] << 16) 2577 | (m[4] << 8) | m[5]); 2578 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0); 2579 2580 /* Enable or disable promiscuous mode as needed. */ 2581 if (ifp->if_flags & IFF_PROMISC) { 2582 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0); 2583 } else { 2584 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0); 2585 } 2586 2587 /* Program multicast filter. */ 2588 ti_setmulti(sc); 2589 2590 /* 2591 * If this is a Tigon 1, we should tell the 2592 * firmware to use software packet filtering. 2593 */ 2594 if (sc->ti_hwrev == TI_HWREV_TIGON) { 2595 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0); 2596 } 2597 2598 /* Init RX ring. */ 2599 ti_init_rx_ring_std(sc); 2600 2601 /* Init jumbo RX ring. */ 2602 if (ifp->if_mtu > (MCLBYTES - ETHER_HDR_LEN - ETHER_CRC_LEN)) 2603 ti_init_rx_ring_jumbo(sc); 2604 2605 /* 2606 * If this is a Tigon 2, we can also configure the 2607 * mini ring. 2608 */ 2609 if (sc->ti_hwrev == TI_HWREV_TIGON_II) 2610 ti_init_rx_ring_mini(sc); 2611 2612 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0); 2613 sc->ti_rx_saved_considx = 0; 2614 2615 /* Init TX ring. */ 2616 ti_init_tx_ring(sc); 2617 2618 /* Tell firmware we're alive. */ 2619 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0); 2620 2621 /* Enable host interrupts. */ 2622 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0); 2623 2624 ifp->if_flags |= IFF_RUNNING; 2625 ifp->if_flags &= ~IFF_OACTIVE; 2626 2627 /* 2628 * Make sure to set media properly. We have to do this 2629 * here since we have to issue commands in order to set 2630 * the link negotiation and we can't issue commands until 2631 * the firmware is running. 2632 */ 2633 ifm = &sc->ifmedia; 2634 tmp = ifm->ifm_media; 2635 ifm->ifm_media = ifm->ifm_cur->ifm_media; 2636 ti_ifmedia_upd(ifp); 2637 ifm->ifm_media = tmp; 2638 2639 return; 2640 } 2641 2642 /* 2643 * Set media options. 2644 */ 2645 static int ti_ifmedia_upd(ifp) 2646 struct ifnet *ifp; 2647 { 2648 struct ti_softc *sc; 2649 struct ifmedia *ifm; 2650 struct ti_cmd_desc cmd; 2651 2652 sc = ifp->if_softc; 2653 ifm = &sc->ifmedia; 2654 2655 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2656 return(EINVAL); 2657 2658 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2659 case IFM_AUTO: 2660 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB| 2661 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y| 2662 TI_GLNK_AUTONEGENB|TI_GLNK_ENB); 2663 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB| 2664 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX| 2665 TI_LNK_AUTONEGENB|TI_LNK_ENB); 2666 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2667 TI_CMD_CODE_NEGOTIATE_BOTH, 0); 2668 break; 2669 case IFM_1000_SX: 2670 case IFM_1000_T: 2671 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2672 CSR_WRITE_4(sc, TI_GCR_GLINK, 2673 TI_GLNK_PREF|TI_GLNK_1000MB|TI_GLNK_FULL_DUPLEX| 2674 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2675 } else { 2676 CSR_WRITE_4(sc, TI_GCR_GLINK, 2677 TI_GLNK_PREF|TI_GLNK_1000MB| 2678 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB); 2679 } 2680 CSR_WRITE_4(sc, TI_GCR_LINK, 0); 2681 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2682 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0); 2683 break; 2684 case IFM_100_FX: 2685 case IFM_10_FL: 2686 case IFM_100_TX: 2687 case IFM_10_T: 2688 CSR_WRITE_4(sc, TI_GCR_GLINK, 0); 2689 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF); 2690 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX || 2691 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 2692 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB); 2693 } else { 2694 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB); 2695 } 2696 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2697 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX); 2698 } else { 2699 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX); 2700 } 2701 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION, 2702 TI_CMD_CODE_NEGOTIATE_10_100, 0); 2703 break; 2704 } 2705 2706 sc->ethercom.ec_if.if_baudrate = 2707 ifmedia_baudrate(ifm->ifm_media); 2708 2709 return(0); 2710 } 2711 2712 /* 2713 * Report current media status. 2714 */ 2715 static void ti_ifmedia_sts(ifp, ifmr) 2716 struct ifnet *ifp; 2717 struct ifmediareq *ifmr; 2718 { 2719 struct ti_softc *sc; 2720 u_int32_t media = 0; 2721 2722 sc = ifp->if_softc; 2723 2724 ifmr->ifm_status = IFM_AVALID; 2725 ifmr->ifm_active = IFM_ETHER; 2726 2727 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) 2728 return; 2729 2730 ifmr->ifm_status |= IFM_ACTIVE; 2731 2732 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) { 2733 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT); 2734 if (sc->ti_copper) 2735 ifmr->ifm_active |= IFM_1000_T; 2736 else 2737 ifmr->ifm_active |= IFM_1000_SX; 2738 if (media & TI_GLNK_FULL_DUPLEX) 2739 ifmr->ifm_active |= IFM_FDX; 2740 else 2741 ifmr->ifm_active |= IFM_HDX; 2742 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) { 2743 media = CSR_READ_4(sc, TI_GCR_LINK_STAT); 2744 if (sc->ti_copper) { 2745 if (media & TI_LNK_100MB) 2746 ifmr->ifm_active |= IFM_100_TX; 2747 if (media & TI_LNK_10MB) 2748 ifmr->ifm_active |= IFM_10_T; 2749 } else { 2750 if (media & TI_LNK_100MB) 2751 ifmr->ifm_active |= IFM_100_FX; 2752 if (media & TI_LNK_10MB) 2753 ifmr->ifm_active |= IFM_10_FL; 2754 } 2755 if (media & TI_LNK_FULL_DUPLEX) 2756 ifmr->ifm_active |= IFM_FDX; 2757 if (media & TI_LNK_HALF_DUPLEX) 2758 ifmr->ifm_active |= IFM_HDX; 2759 } 2760 2761 sc->ethercom.ec_if.if_baudrate = 2762 ifmedia_baudrate(sc->ifmedia.ifm_media); 2763 2764 return; 2765 } 2766 2767 static int 2768 ti_ether_ioctl(ifp, cmd, data) 2769 struct ifnet *ifp; 2770 u_long cmd; 2771 caddr_t data; 2772 { 2773 struct ifaddr *ifa = (struct ifaddr *) data; 2774 struct ti_softc *sc = ifp->if_softc; 2775 2776 if ((ifp->if_flags & IFF_UP) == 0) { 2777 ifp->if_flags |= IFF_UP; 2778 ti_init(sc); 2779 } 2780 2781 switch (cmd) { 2782 case SIOCSIFADDR: 2783 2784 switch (ifa->ifa_addr->sa_family) { 2785 #ifdef INET 2786 case AF_INET: 2787 arp_ifinit(ifp, ifa); 2788 break; 2789 #endif 2790 #ifdef NS 2791 case AF_NS: 2792 { 2793 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 2794 2795 if (ns_nullhost(*ina)) 2796 ina->x_host = *(union ns_host *) 2797 LLADDR(ifp->if_sadl); 2798 else 2799 memcpy(LLADDR(ifp->if_sadl), ina->x_host.c_host, 2800 ifp->if_addrlen); 2801 break; 2802 } 2803 #endif 2804 default: 2805 break; 2806 } 2807 break; 2808 2809 default: 2810 return (EINVAL); 2811 } 2812 2813 return (0); 2814 } 2815 2816 static int ti_ioctl(ifp, command, data) 2817 struct ifnet *ifp; 2818 u_long command; 2819 caddr_t data; 2820 { 2821 struct ti_softc *sc = ifp->if_softc; 2822 struct ifreq *ifr = (struct ifreq *) data; 2823 int s, error = 0; 2824 struct ti_cmd_desc cmd; 2825 2826 s = splnet(); 2827 2828 switch(command) { 2829 case SIOCSIFADDR: 2830 case SIOCGIFADDR: 2831 error = ti_ether_ioctl(ifp, command, data); 2832 break; 2833 case SIOCSIFMTU: 2834 if (ifr->ifr_mtu > ETHERMTU_JUMBO) 2835 error = EINVAL; 2836 else { 2837 ifp->if_mtu = ifr->ifr_mtu; 2838 ti_init(sc); 2839 } 2840 break; 2841 case SIOCSIFFLAGS: 2842 if (ifp->if_flags & IFF_UP) { 2843 /* 2844 * If only the state of the PROMISC flag changed, 2845 * then just use the 'set promisc mode' command 2846 * instead of reinitializing the entire NIC. Doing 2847 * a full re-init means reloading the firmware and 2848 * waiting for it to start up, which may take a 2849 * second or two. 2850 */ 2851 if (ifp->if_flags & IFF_RUNNING && 2852 ifp->if_flags & IFF_PROMISC && 2853 !(sc->ti_if_flags & IFF_PROMISC)) { 2854 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2855 TI_CMD_CODE_PROMISC_ENB, 0); 2856 } else if (ifp->if_flags & IFF_RUNNING && 2857 !(ifp->if_flags & IFF_PROMISC) && 2858 sc->ti_if_flags & IFF_PROMISC) { 2859 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, 2860 TI_CMD_CODE_PROMISC_DIS, 0); 2861 } else 2862 ti_init(sc); 2863 } else { 2864 if (ifp->if_flags & IFF_RUNNING) { 2865 ti_stop(sc); 2866 } 2867 } 2868 sc->ti_if_flags = ifp->if_flags; 2869 error = 0; 2870 break; 2871 case SIOCADDMULTI: 2872 case SIOCDELMULTI: 2873 error = (command == SIOCADDMULTI) ? 2874 ether_addmulti(ifr, &sc->ethercom) : 2875 ether_delmulti(ifr, &sc->ethercom); 2876 if (error == ENETRESET) { 2877 if (ifp->if_flags & IFF_RUNNING) 2878 ti_setmulti(sc); 2879 error = 0; 2880 } 2881 break; 2882 case SIOCSIFMEDIA: 2883 case SIOCGIFMEDIA: 2884 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2885 break; 2886 default: 2887 error = EINVAL; 2888 break; 2889 } 2890 2891 (void)splx(s); 2892 2893 return(error); 2894 } 2895 2896 static void ti_watchdog(ifp) 2897 struct ifnet *ifp; 2898 { 2899 struct ti_softc *sc; 2900 2901 sc = ifp->if_softc; 2902 2903 printf("%s: watchdog timeout -- resetting\n", sc->sc_dev.dv_xname); 2904 ti_stop(sc); 2905 ti_init(sc); 2906 2907 ifp->if_oerrors++; 2908 2909 return; 2910 } 2911 2912 /* 2913 * Stop the adapter and free any mbufs allocated to the 2914 * RX and TX lists. 2915 */ 2916 static void ti_stop(sc) 2917 struct ti_softc *sc; 2918 { 2919 struct ifnet *ifp; 2920 struct ti_cmd_desc cmd; 2921 2922 ifp = &sc->ethercom.ec_if; 2923 2924 /* Disable host interrupts. */ 2925 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1); 2926 /* 2927 * Tell firmware we're shutting down. 2928 */ 2929 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0); 2930 2931 /* Halt and reinitialize. */ 2932 ti_chipinit(sc); 2933 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL); 2934 ti_chipinit(sc); 2935 2936 /* Free the RX lists. */ 2937 ti_free_rx_ring_std(sc); 2938 2939 /* Free jumbo RX list. */ 2940 ti_free_rx_ring_jumbo(sc); 2941 2942 /* Free mini RX list. */ 2943 ti_free_rx_ring_mini(sc); 2944 2945 /* Free TX buffers. */ 2946 ti_free_tx_ring(sc); 2947 2948 sc->ti_ev_prodidx.ti_idx = 0; 2949 sc->ti_return_prodidx.ti_idx = 0; 2950 sc->ti_tx_considx.ti_idx = 0; 2951 sc->ti_tx_saved_considx = TI_TXCONS_UNSET; 2952 2953 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2954 2955 return; 2956 } 2957 2958 /* 2959 * Stop all chip I/O so that the kernel's probe routines don't 2960 * get confused by errant DMAs when rebooting. 2961 */ 2962 static void ti_shutdown(v) 2963 void *v; 2964 { 2965 struct ti_softc *sc = v; 2966 2967 ti_chipinit(sc); 2968 2969 return; 2970 } 2971